TPS62172QDSGRQ1 [TI]
采用 2x2 QFN 封装的 3-17V 0.5A 汽车类降压转换器 | DSG | 8 | -40 to 125;
| 型号： | TPS62172QDSGRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2x2 QFN 封装的 3-17V 0.5A 汽车类降压转换器 | DSG | 8 | -40 to 125 转换器 |
| 文件： | 总35页 (文件大小：3247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
TPS6217x-Q1 具有 DCS-Control™ 功能的 3V 到 17V 0.5A 降压转换器
1 特性
3 说明
1
•
•
•
DCS-Control™拓扑
TPS6217x-Q1 系列是一款简单易用的同步降压直流/直
流转换器，针对 高功率密度的应用 进行了优化。该器
件的开关频率典型值高达 2.25MHz，允许使用小型电
感，利用 DCS-Control™ 拓扑技术提供快速瞬态响应
并实现高输出电压精度。
适用于汽车电子 应用
具有符合 AEC-Q100 标准的下列结果：
–
–
–
器件温度等级：-40°C 至 125°C 的运行结温范
围
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
此器件具有 3V 至 17V 宽运行输入电压范围，非常适
用于由锂离子或其它电池以及 12V 中间电源轨供电的
系统。其输出电压为 0.9V 至 6V，支持高达 0.5A 的持
续输出电流（使用 100% 占空比模式）。
器件组件充电模式 (CDM) ESD 分类等级 C4B
•
•
•
•
•
•
•
•
•
•
•
•
•
输入电压范围：3V 至 17V
输出电流高达 500mA
可调输出电压范围为 0.9V 至 6V
固定输出电压版本
通过配置使能引脚和开漏电源正常状态引脚也可以实现
电源排序。
无缝省电模式转换
在节能模式下，器件可根据输入电压 (VIN) 生成约
17μA 的静态电流。负载较小时可自动且无缝进入节能
模式，同时该模式可保持整个负载范围内的高效率。在
关断模式下，此器件会关闭且关断期间的流耗少于
2μA。
静态电流典型值为 17µA
电源正常输出
100% 占空比模式
短路保护
过热保护
此器件分为可调和固定输出电压型号，采用 2mm ×
2mm (DSG) 8 引脚 WSON 封装。
与 TPS62160-Q1 引脚对引脚兼容
采用 2 × 2mm WSON-8 封装
借助 WEBENCH® 电源设计器并使用 TPS62170-
Q1 创建定制设计方案
器件信息(1)
器件型号
TPS62170-Q1
TPS62171-Q1
TPS62172-Q1
封装
WSON (8)
封装尺寸（标称值）
2.00mm x 2.00mm
2.00mm x 2.00mm
2.00mm x 2.00mm
2 应用
WSON (8)
WSON (8)
•
•
•
•
汽车类 12V 导轨式电源
同轴电缆供电 POL 电源
摄像机模块、视频模块
低压降稳压器 (LDO)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
典型应用电路原理图
效率与输出电流间的关系
空白
空白空白
VIN
2.2µH
3.3V / 0.5A
VIN
EN
SW
R1
470k
VOS
100k
C1
10uF
C2
22uF
TPS62170-Q1
AGND
PG
FB
R2
150k
PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCK7
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical TPS62170-Q1 Application ......................... 11
9.3 System Examples ................................................... 20
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
11.3 Thermal Considerations........................................ 24
12 器件和文档支持 ..................................................... 25
12.1 器件支持 ............................................................... 25
12.2 文档支持 ............................................................... 25
12.3 相关链接................................................................ 26
12.4 商标....................................................................... 26
12.5 静电放电警告......................................................... 26
12.6 接收文档更新通知 ................................................. 26
12.7 社区资源................................................................ 26
12.8 Glossary................................................................ 26
13 机械、封装和可订购信息....................................... 26
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (November 2016) to Revision D
Page
•
•
已添加 WEBENCH® 信息........................................................................................................................................................ 1
Changed TJ spec MAX value From 125°C To 150°C in the Absolute Maximum Ratings table............................................. 4
Changes from Revision B (October 2016) to Revision C
Page
•
•
•
•
已添加 引脚对引脚兼容特性.................................................................................................................................................... 1
Changed Thermal Information table....................................................................................................................................... 4
Added C1, C2, R1, R2, descriptors to Figure 5.................................................................................................................... 11
Added C1, C2 to Table 1 ..................................................................................................................................................... 11
Changes from Revision A (September 2016) to Revision B
Page
•
Added the Device Comparison Table..................................................................................................................................... 3
Changes from Original (December 2014) to Revision A
Page
•
•
•
•
•
•
•
在应用列表中将“同轴以太网供电 POL 电源”更改为“同轴电缆供电 POL 电源” ....................................................................... 1
已添加 数据表中增加了 TPS62171-Q1 器件。....................................................................................................................... 1
Changed Unit from mA to V for Pin voltage at FB, PG, and VOS in the Absolute Maximum Ratings table. ........................ 4
Changed Unit from °C to mA in the Absolute Maximum Ratings table for Power Good sink current. .................................. 4
Changed Unit from kV to °C in the Absolute Maximum Ratings table for the Operating junction temperature, TJ .............. 4
Added legal NOTE at Application and Implementation ....................................................................................................... 11
Added cross references to Third-Party Products disclaimer in Table 1 ............................................................................... 11
2
Copyright © 2014–2017, Texas Instruments Incorporated
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
www.ti.com.cn
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
5 Device Comparison Table
PART NUMBER(1)
TPS62170-Q1
TPS62171-Q1
TPS62172-Q1
OUTPUT VOLTAGE
adjustable
1.8 V
3.3 V
(1) For detailed ordering information please check the 机械、封装和可订购信息 section at the end of this
datasheet.
6 Pin Configuration and Functions
8-Pin WSON
DSG Package
(Top View)
1
2
3
4
8
7
6
5
PGND
VIN
PG
SW
VOS
FB
Exposed
Thermal
Pad
EN
AGND
space
Pin Functions
PIN(1)
I/O
DESCRIPTION
NAME
NUMBER
PGND
VIN
1
2
3
4
5
Power ground
Supply voltage
I
I
EN
Enable input (High = enabled, Low = disabled)
Analog ground
AGND
FB
I
Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended
to connect FB to AGND on fixed output voltage versions for improved thermal performance.
VOS
SW
PG
6
7
8
I
Output voltage sense pin and connection for the control loop circuitry.
Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
O
O
Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires
pull-up resistor; goes high impedance, when device is switched off)
Exposed
Thermal Pad
Must be connected to AGND. Must be soldered to achieve appropriate power dissipation and
mechanical reliability.
(1) For more information about connecting pins, see Detailed Description and Application and Implementation sections.
Copyright © 2014–2017, Texas Instruments Incorporated
3
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
-0.3
–0.3
MAX
20
UNIT
VIN
V
EN
VIN+0.3
VIN+0.3
7
Pin voltage(2)
SW
V
V
FB, PG, VOS
Power Good sink current
PG
10
mA
°C
°C
Operating junction temperature range, TJ
Storage temperature range, Tstg
–40
–65
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
TYP MAX
3 17
UNIT
V
VIN
VOUT
TJ
Supply voltage
Output voltage range
Operating junction temperature
0.9
6
V
–40
125
°C
7.4 Thermal Information
TPS6217x-Q1
THERMAL METRIC(1)
UNIT
DSG (8 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
65.5
66.4
35.5
1.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
35.8
8.4
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, .
4
Copyright © 2014–2017, Texas Instruments Incorporated
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
www.ti.com.cn
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
7.5 Electrical Characteristics
over junction temperature range (TJ = –40°C to +125°C), typical values at VIN = 12 V and TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input voltage range(1)
Operating quiescent current
Shutdown current(2)
3
17
V
µA
µA
V
IQ
EN = High, IOUT = 0 mA, Device not switching
17
30
25
ISD
EN = Low
1.8
2.7
180
160
20
Falling input voltage
Hysteresis
2.6
0.9
2.82
VUVLO
Undervoltage lockout threshold
mV
Thermal shutdown temperature
Thermal shutdown hysteresis
TSD
°C
CONTROL (EN, PG)
VEN_H
VEN_L
High-level input threshold voltage (EN)
Low-level input threshold voltage (EN)
V
V
0.3
1
ILKG_EN Input leakage current (EN)
EN = VIN or GND
0.01
95%
90%
0.07
1
µA
Rising (%VOUT
)
92%
87%
98%
93%
0.3
VTH_PG Power Good threshold voltage
Falling (%VOUT
IPG = –2 mA
VPG = 1.8 V
)
VOL_PG Power Good output low
ILKG_PG Input leakage current (PG)
POWER SWITCH
V
400
nA
VIN ≥ 6 V
VIN = 3 V
VIN ≥ 6 V
VIN = 3 V
300
430
120
165
1.05
600
200
High-side MOSFET ON-resistance
RDS(ON)
mΩ
Low-side MOSFET ON-resistance
mΩ
ILIMF
High-side MOSFET forward current limit(3) VIN = 12 V, TA = 25°C
0.85
1.35
A
OUTPUT
VREF
Internal reference voltage
0.8
5
V
nA
V
ILKG_FB Pin leakage current (FB)
Output voltage range
TPS62170-Q1, VFB = 1.2 V
400
6.0
3%
4%
TPS62170-Q1, VIN ≥ VOUT
0.9
–3%
PWM Mode operation, VIN ≥ VOUT + 1 V
Power Save Mode operation, COUT = 22 µF(5)
VIN = 12 V, VOUT = 3.3 V, PWM Mode operation
Feedback voltage accuracy(4)
–3.5%
VOUT
DC output voltage load regulation(6)
0.05
0.02
% / A
% / V
(6)
DC output voltage line regulation
3 V ≤ VIN ≤ 17 V, VOUT = 3.3 V, IOUT = 0.5 A,
PWM Mode operation
(1) The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
(2) Current into VIN pin.
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short
Circuit Protection).
(4) For fixed voltage versions, the (internal) resistive feedback divider is included.
(5) The accuracy in Power Save Mode can be improved by increasing the COUT value, reducing the output voltage ripple.
(6) Line and load regulation are depending on external component selection and layout (see Figure 14 and Figure 15).
Copyright © 2014–2017, Texas Instruments Incorporated
5
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
www.ti.com.cn
7.6 Typical Characteristics
At VIN = 12 V, VOUT = 3.3 V and TJ = 25°C (unless otherwise noted)
Figure 1. Quiescent Current
Figure 2. Shutdown Current
Figure 3. High-Side Static Drain-Source-Resistance (RDSon
)
Figure 4. Low-Side Static Drain-Source-Resistance (RDSon)
6
Copyright © 2014–2017, Texas Instruments Incorporated
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
www.ti.com.cn
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
8 Detailed Description
8.1 Overview
The TPS6217x-Q1 synchronous switched mode power converters are based on DCS-Control™ (Direct Control
with Seamless transition into power save mode), an advanced regulation topology, that combines the advantages
of hysteretic, voltage mode and current mode control including an AC loop directly associated to the output
voltage. This control loop takes information about output voltage changes and feeds it directly to a fast
comparator stage. It sets the switching frequency, which is constant for steady state operating conditions, and
provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback
loop is used. The internally compensated regulation network achieves fast and stable operation with small
external components and low ESR capacitors.
The DCS-ControlTM topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.25 MHz with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the
load current. Since DCS-ControlTM supports both operation modes within one single building block, the transition
from PWM to Power Save Mode is seamless without effects on the output voltage.
8.2 Functional Block Diagram
PG
VIN
Soft
start
Thermal
Shtdwn
UVLO
PG control
HS lim
comp
power
control
gate
drive
control logic
EN*
SW
comp
LS lim
direct control
&
compensation
VOS
FB
ramp
_
comparator
timer tON
error
amplifier
+
DCS - ControlTM
AGND
PGND
Copyright © 2016, Texas Instruments Incorporated
* This pin is connected to a pull down resistor internally (see Feature Description section).
Copyright © 2014–2017, Texas Instruments Incorporated
7
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
www.ti.com.cn
8.3 Feature Description
8.3.1 Enable / Shutdown (EN)
When Enable (EN) is set High, the device starts operation.
Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.8 µA. During shutdown, the internal
power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the
output voltage smoothly. If the EN pin goes Low, an internal pull-down resistor of about 400 kΩ is connected and
keeps it Low in case of floating pin. To avoid ON/OFF oscillations, a minimum slew rate of about 50 mV/s is
recommended for the EN signal.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
8.3.2 Softstart
The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high-
impedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50 µs and VOUT rises with a slope of about 25 mV/µs. See Figure 26 and Figure 27 for typical
startup operation.
The TPS6217x-Q1 can start into a pre-biased output. During monotonic pre-biased startup, the low-side
MOSFET is not allowed to turn on until the device's internal ramp sets an output voltage above the pre-bias
voltage.
8.3.3 Power Good (PG)
The TPS6217x-Q1 has a built in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 7 V). It can sink 2 mA of current and
maintain its specified logic low level. It is high impedance when the device is turned off due to EN, UVLO, or
thermal shutdown.
8.3.4 Under Voltage Lockout (UVLO)
If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the
power FETs. The under voltage lockout threshold is set typically to 2.7 V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 180 mV.
8.3.5 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C
(typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG
goes high impedance. When TJ decreases below the hysteresis amount, the converter resumes normal
operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shut down temperature.
8.4 Device Functional Modes
8.4.1 Pulse Width Modulation (PWM) Operation
The TPS62170-Q1 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of about 2.25 MHz. The frequency variation in PWM is controlled and depends on VIN, VOUT
and the inductance. The device operates in PWM mode as long the output current is higher than half the
inductor's ripple current. To maintain high efficiency at light loads, the device enters Power Save Mode at the
boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than
half the inductor's ripple current.
8
Copyright © 2014–2017, Texas Instruments Incorporated
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
www.ti.com.cn
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
Device Functional Modes (continued)
8.4.2 Power Save Mode Operation
The TPS6217x-Q1's built in Power Save Mode will be entered seamlessly, if the load current decreases. This
secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor
current is discontinuous.
In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in
both directions.
The TPS6217x-Q1 includes a fixed on-time circuitry. This on-time, in steady-state operation, can be estimated
as:
space
VOUT
tON
=
×420ns
VIN
(1)
space
For very small output voltages, the on-time increases beyond the result of Equation 1, to stay above an absolute
minimum on-time, tON(min), which is around 80 ns to limit switching losses. The peak inductor current in PSM can
be approximated by:
space
(VIN -VOUT
)
ILPSM ( peak )
=
×tON
L
(2)
space
When VIN decreases to typically 15% above VOUT, the TPS62170-Q1 does not enter Power Save Mode,
regardless of the load current. The device maintains output regulation in PWM mode.
8.4.3 100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D = Vout/Vin and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal
setpoint. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of
battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
space
VIN(min) =VOUT(min) + IOUT (RDS( on ) + RL )
(3)
where
IOUT is the output current,
RDS(on) is the RDS(on) of the high-side FET and
RL is the DC resistance of the inductor used.
space
8.4.4 Current Limit and Short Circuit Protection
The TPS6217x-Q1 devices are protected against heavy load and short circuit events. At heavy loads, the current
limit determines the maximum output current. If the current limit is reached, the high-side FET will be turned off.
Avoiding shoot through current, the low-side FET is then switched on to allow the inductor current to decrease.
The high-side FET will turn on again, only if the current in the low-side FET has decreased below the low side
current limit threshold.
Copyright © 2014–2017, Texas Instruments Incorporated
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TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
www.ti.com.cn
Device Functional Modes (continued)
The output current of the device is limited by the current limit (see Electrical Characteristics). Due to internal
propagation delay, the actual current can exceed the static current limit during that time. The dynamic current
limit can be calculated as follows:
space
VL
I peak(typ) = ILIMF
+
× tPD
L
(4)
where
ILIMF is the static current limit, specified in the electrical characteristic table,
L is the inductor value,
VL is the voltage across the inductor and
tPD is the internal propagation delay.
space
The dynamic high side switch peak current can be calculated as follows:
space
(VIN -VOUT
)
I peak(typ) = ILIMF _ HS
+
× 30ns
L
(5)
space
Care on the current limit has to be taken if the input voltage is high and very small inductances are used.
8.4.5 Operation Above TJ = 125°C
The operating junction temperature of the device is specified up to 125°C. In power supply circuits, the self
heating effect causes, that the junction temperature, TJ, is even higher than the ambient temperature TA.
Depending on TA and the load current, the maximum operating temperature TJ can be exceeded. However, the
electrical characteristics are specified up to a TJ of 125°C only. The device operates as long as thermal
shutdown threshold is not triggered.
10
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ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following information is intended to be a guideline through the individual power supply design process.
9.2 Typical TPS62170-Q1 Application
space
VIN
2.2µH
3.3V / 0.5A
VIN
EN
SW
VOS
PG
R1
470k
100k
C1
10uF
C2
22uF
TPS62170-Q1
AGND
R2
150k
PGND
FB
Figure 5. 3.3-V/0.5-A Power Supply
9.2.1 Design Requirements
The step-down converter design can be adapted to different output voltage and load current needs by choosing
external components appropriate. The following design procedure is adequate for whole VIN, VOUT and load
current range of TPS62170-Q1. Using Table 2, the design procedure needs minimum effort.
Table 1. List of Components
REFERENCE
DESCRIPTION
17-V, 0.5-A step-down converter, WSON
2.2-µH, 1.4-A, 3 x 2.8 x 1.2 mm
10-µF, 25-V, ceramic
MANUFACTURER(1)
TPS62170QDSG, Texas Instruments
VLF3012ST-2R2M1R4, TDK
Standard
IC
L1
C1
C2
R1
R2
R3
22-µF, 6.3-V, ceramic
Standard
Depending on Vout
Depending on Vout
100-kΩ, chip, 0603, 1/16-W, 1%
Standard
(1) See Third-Party Products disclaimer.
space
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62170-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
Run electrical simulations to see important waveforms and circuit performance
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ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
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•
•
•
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Programming the Output Voltage
While the output voltage of the TPS62170-Q1 is adjustable, the TPS62171-Q1 and TPS62172-Q1 are
programmed to a fixed output voltage. For fixed output versions, the FB pin is pulled down internally and may be
left floating. it is recommended to connect it to AGND to improve thermal resistance. The adjustable version can
be programmed for output voltages from 0.9 V to 6 V by using a resistive divider from VOUT to FB to AGND. The
voltage at the FB pin is regulated to 800 mV. The value of the output voltage is set by the selection of the
resistive divider from Equation 6. It is recommended to choose resistor values which allow a cross current of at
least 2 uA, meaning the value of R2 should not exceed 400 kΩ. Lower resistor values are recommended for
highest accuracy and most robust design. For applications requiring lowest current consumption, the use of fixed
output voltage versions is recommended.
space
V
æ
ç
è
ö
OUT
R1 = R2
-1
÷
0.8V
ø
(6)
space
In case the FB pin gets opened, the device clamps the output voltage at the VOS pin to about 7.4 V.
9.2.2.3 External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the devices
control loop. The TPS62170-Q1 is optimized to work within a range of external components. The LC output filters
inductance and capacitance have to be considered together, creating a double pole, responsible for the corner
frequency of the converter (see Output Filter and Loop Stability section). Table 2 can be used to simplify the
output filter component selection.
space
Table 2. Recommended LC Output Filter Combinations(1)
4.7µF
10µF
22µF
47µF
100µF
200µF
400µF
1µH
(2)
2.2µH
3.3µH
4.7µH
√
√
√
√
√
√
√
√
√
(1) The values in the table are nominal values. Variations of typically ±20% due to tolerance, saturation and DC bias are assumed.
(2) This LC combination is the standard value and recommended for most applications.
More detailed information on further LC combinations can be found in SLVA463.
9.2.2.3.1 Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under
static load conditions.
space
DIL(max)
IL(max) = IOUT(max)
+
2
(7)
12
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ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
VOUT
æ
ç
ç
ç
ç
ç
è
ö
÷
÷
÷
÷
÷
ø
1-
VIN(max)
DIL(max) = VOUT
×
L(min) × fSW
(8)
where
IL(max) is the maximum inductor current,
ΔIL is the Peak to Peak Inductor Ripple Current,
L(min) is the minimum effective inductor value and
fSW is the actual PWM Switching Frequency.
space
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS62170-Q1 and are recommended for use:
Table 3. List of Inductors
TYPE
INDUCTANCE [µH]
2.2 µH, ±20%
2.2 µH, ±20%
2.2 µH, ±20%
2.2 µH, ±20%
3.3 µH, ±20%
2.2 µH, ±20%
3.3 µH, ±20%
3.3 µH, ±20%
2.2 µH, ±20%
3.3 µH, ±20%
3.3 µH, ±30%
2.2 µH, ±20%
2.2 µH, ±20%
2.2 µH, ±20%
3.3 µH, ±20%
CURRENT [A](1)
DIMENSIONS [L x B x H] mm
3.0 x 2.8 x 1.2
3.0 x 2.5 x 1.2
2.5 x 2.0 x 1.2
3.0 x 3.0 x 1.2
3.0 x 3.0 x 1.2
1.9 x 2.0 x 1.0
1.9 x 2.0 x 1.0
3.0 x 3.0 x 1.4
2.8 x 2.3 x 1.2
2.8 x 2.3 x 1.2
2.8 x 2.8 x 1.1
2.0 x 2.5 x 1.2
3.0 x 3.0 x 1.5
2.0 x 1.25 x 1.4
2.0 x 1.25 x 1.4
MANUFACTURER(2)
TDK
VLF3012ST-2R2M1R4
VLF302512MT-2R2M
VLS252012-2R2
XFL3012-222MEC
XFL3012-332MEC
XPL2010-222MLC
XPL2010-332MLC
LPS3015-332ML
PFL2512-222ME
PFL2512-333ME
744028003
1.9 A
1.9 A
TDK
1.3 A
TDK
1.9 A
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Coilcraft
Wuerth
1.6 A
1.3 A
1.1 A
1.4 A
1.0 A
0.78 A
1.0 A
PSI25201B-2R2MS
NR3015T-2R2M
BRC2012T2R2MD
BRC2012T3R3MD
1.3 A
Cyntec
1.5 A
Taiyo Yuden
Taiyo Yuden
Taiyo Yuden
1.0 A
0.87 A
(1) IRMS at 40°C rise or ISAT at 30% drop.
(2) See Third-Party Products disclaimer.
The TPS6217x-Q1 can be run with an inductor as low as 2.2 µH. However, for applications running with low
input voltages, 3.3 µH is recommended, to allow the full output current. The inductor value also determines the
load current at which Power Save Mode is entered:
space
1
Iload(PSM )
=
DIL
2
(9)
space
Using Equation 8, this current level can be adjusted by changing the inductor value.
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9.2.2.3.2 Capacitor Selection
9.2.2.3.2.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TPS6217x-Q1 allows the use
of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low
output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can
have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see
SLVA463).
NOTE
In Power Save Mode, the output voltage ripple depends on the output capacitance, its
ESR and the peak inductor current. Using ceramic capacitors provides small ESR and low
ripple.
9.2.2.3.2.2 Input Capacitor
For most applications, 10 µF is sufficient and is recommended, though a larger value reduces input current ripple
further. The input capacitor buffers the input voltage for transient events and also decouples the converter from
the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between VIN and GND as close as possible to those pins.
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
9.2.2.4 Output Filter and Loop Stability
The devices of the TPS6217x-Q1 family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 10:
space
1
fLC
=
2p L × C
(10)
space
Proven nominal values for inductance and ceramic capacitance are given in Table 2 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which might be affected. More
information including a detailed L-C stability matrix can be found in SLVA463.
The TPS6217x-Q1 devices, both fixed and adjustable versions, include an internal 25-pF feedforward capacitor,
connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and
zero in the control loop with the resistors of the feedback divider, per Equation 11 and Equation 12:
space
1
fzero
space
f pole
space
=
2p × R × 25pF
1
(11)
(12)
æ
ö
1
1
1
ç
ç
÷
÷
=
×
+
2p × 25pF
R
R
2
è
1
ø
14
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TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
www.ti.com.cn
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
Though the TPS6217x-Q1 devices are stable without the pole and zero being in a particular location, adjusting
their location to the specific needs of the application can provide better performance in Power Save mode and/or
improved transient response. An external feed-forward capacitor can also be added. A more detailed discussion
on the optimization for stability vs transient response can be found in SLVA289 and SLVA466.
If using ceramic capacitors, the DC bias effect has to be considered. The DC bias effect results in a drop in
effective capacitance as the voltage across the capacitor increases (see DC Bias effect NOTE in the Input
Capacitor section).
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9.2.3 Application Performance Plots
At VIN = 12 V, VOUT = 3.3 V and TJ = 25°C (unless otherwise noted)
100.0
90.0
80.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
70.0
VIN=17V
IOUT=1mA
IOUT=100mA
60.0
VIN=12V
IOUT=10mA
IOUT=500mA
50.0
40.0
30.0
VIN=6V
20.0
10.0
0.0
0.0001
0.001
0.01
0.1
1
7
8
9
10
11
12
13
14
15
16
17
Output Current (A)
Input Voltage (V)
G001
G001
Vout = 6 V
Vout = 6 V
Figure 6. Efficiency vs Output Current
Figure 7. Efficiency vs Input Voltage
100.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=5V
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=17V
VIN=17V
VIN=12V
VIN=5V
VIN=12V
0.0001
0.001
0.01
Output Current (A)
0.1
1
0.0001
0.001
0.01
Output Current (A)
0.1
1
G001
G001
Vout = 3.3 V
Vout = 3.3 V
Figure 8. Efficiency vs Output Current
Figure 9. Efficiency vs Input Voltage
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
VIN=5V
IOUT=500mA
VIN=17V
IOUT=1mA
IOUT=10mA
IOUT=100mA
VIN=12V
0.0001
0.001
0.01
Output Current (A)
0.1
1
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Input Voltage (V)
G001
G001
Vout = 1.8 V
Vout = 1.8 V
Figure 10. Efficiency vs Output Current
Figure 11. Efficiency vs Input Voltage
16
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At VIN = 12 V, VOUT = 3.3 V and TJ = 25°C (unless otherwise noted)
100.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
90.0
VIN=5V
80.0
IOUT=10mA
IOUT=100mA IOUT=500mA
70.0
60.0
50.0
VIN=17V
IOUT=1mA
40.0
VIN=12V
30.0
20.0
10.0
0.0
0.0001
0.001
0.01
0.1
1
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Output Current (A)
Input Voltage (V)
G001
G001
Vout = 0.9 V
Vout = 0.9 V
Figure 12. Efficiency vs Output Current
Figure 13. Efficiency vs Input Voltage
3.35
3.30
3.25
3.20
3.35
3.30
3.25
3.20
IOUT=1mA
IOUT=10mA
IOUT=500mA
VIN=5V
VIN=12V
VIN=17V
IOUT=100mA
0.0001
0.001
0.01
Output Current (A)
0.1
1
4
7
10
13
16
Input Voltage (V)
G001
G001
Figure 14. Output Voltage Accuracy (Load Regulation)
Figure 15. Output Voltage Accuracy (Line Regulation)
4
3.5
3
4
3.5
3
2.5
2
2.5
2
IOUT=0.5A
1.5
1
1.5
1
0.5
0
0.5
0
0
0.1
0.2
0.3
0.4
0.5
4
6
8
10
12
14
16
18
Output Current (A)
Input Voltage (V)
G000
G000
Figure 16. Switching Frequency vs Output Current
Figure 17. Switching Frequency vs Input Voltage
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At VIN = 12 V, VOUT = 3.3 V and TJ = 25°C (unless otherwise noted)
0.05
1.5
1.2
1
0.04
0.03
0.02
0.01
0
VIN=17V
−40°C
25°C
0.8
0.5
0.2
0
VIN=12V
85°C
VIN=5V
0
0.1
0.2 0.3
Output Current (A)
0.4
0.5
4
5
6
7
8
9
Input Voltage (V)
10 11 12 13 14 15 16 17
G000
G000
Figure 18. Output Voltage Ripple
Figure 19. Maximum Output Current
Figure 20. PWM / PSM Mode Transition
Figure 21. PWM to PSM Mode Transition
200 mA to 500 mA
Figure 22. Load Transient Response in PWM Mode
100 mA to 500 mA
Figure 23. Load Transient Response from Power Save
Mode
18
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ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
At VIN = 12 V, VOUT = 3.3 V and TJ = 25°C (unless otherwise noted)
200 mA to 500 mA
200 mA to 500 mA
Figure 25. Load Transient Response in PWM Mode, Falling
Edge
Figure 24. Load Transient Response in PWM Mode, Rising
Edge
Iout = 100 mA
Iout = 500 mA
Figure 26. Startup to VOUT = 3.3 V
Figure 27. Startup to VOUT = 3.3 V
Iout = 66 mA
Iout = 500 mA
Figure 28. Typical Operation in Power Save Mode
Figure 29. Typical Operation in PWM Mode
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9.3 System Examples
9.3.1 Inverting Power Supply
The TPS62170-Q1 can be used as inverting power supply by rearranging external circuitry as shown in
Figure 30. As the former GND node now represents a voltage level below system ground, the voltage difference
between VIN and VOUT has to be limited for operation to the maximum supply voltage of 17 V (see Equation 13).
space
VIN + VOUT £VIN max
(13)
space
10uF
2.2µH
VIN
EN
SW
VOS
PG
680k
130k
100k
10uF
TPS62170-Q1
22uF
GND
PGND
FB
-5V
Figure 30. –5-V Inverting Power Supply
space
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output
capacitance of at least 22 µF is recommended. A detailed design example is given in SLVA469.
9.3.2 Various Output Voltages
The TPS62170-Q1 can be set for different output voltages between 0.9 V and 6 V. Some examples are shown
below.
space
space
(5 .. 17)V
2.2µH
5V / 0.5A
VIN
EN
SW
VOS
PG
680k
130k
100k
10uF
TPS62170-Q1
22uF
AGND
PGND
FB
Figure 31. 5-V/0.5-A Power Supply
space
space
20
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System Examples (continued)
(3.3 .. 17)V
2.2µH
3.3V / 0.5A
VIN
EN
SW
VOS
PG
470k
100k
10uF
TPS62170-Q1
22uF
AGND
150k
PGND
FB
Figure 32. 3.3-V/0.5-A Power Supply
space
space
(3 .. 17)V
2.2µH
2.5V / 0.5A
VIN
EN
SW
VOS
PG
390k
180k
100k
10uF
TPS62170-Q1
22uF
AGND
PGND
FB
Figure 33. 2.5-V/0.5-A Power Supply
space
space
(3 .. 17)V
2.2µH
1.8V / 0.5A
VIN
EN
SW
VOS
PG
200k
160k
100k
10uF
TPS62170-Q1
22uF
AGND
PGND
FB
Figure 34. 1.8-V/0.5-A Power Supply
space
space
(3 .. 17)V
2.2µH
1.5V / 0.5A
VIN
EN
SW
VOS
PG
130k
150k
100k
10uF
TPS62170-Q1
22uF
AGND
PGND
FB
Figure 35. 1.5-V/0.5-A Power Supply
space
space
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System Examples (continued)
(3 .. 17)V
2.2µH
1.2V / 0.5A
VIN
SW
VOS
PG
EN
75k
100k
10uF
TPS62170-Q1
22uF
AGND
150k
PGND
FB
Figure 36. 1.2-V/0.5-A Power Supply
space
space
(3 .. 17)V
2.2µH
1V / 0.5A
VIN
EN
SW
VOS
PG
51k
100k
10uF
TPS62170-Q1
22uF
AGND
200k
PGND
FB
Figure 37. 1-V/0.5-A Power Supply
space
10 Power Supply Recommendations
The TPS6217x-Q1 are designed to operate from a 3-V to 17-V input voltage supply. The input power supply's
output current needs to be rated according to the output voltage and the output current of the power rail
application.
22
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ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
11 Layout
11.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS6217x-Q1 demands careful attention to ensure operation and
to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load),
stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. Considering the following
topics ensures best electrical and optimized thermal performance:
1) The input capacitor must be placed as close as possible to the VIN and PGND pin of the IC. This provides low
resistive and inductive path for the high di/dt input current.
2) The VOS pin must be connect in the shortest way to VOUT at the output capacitor - avoiding noise coupling.
3) The feedback resistors, R1 and R2 must be connected close to the FB and AGND pins - avoiding noise
coupling.
4) The output capacitor should be placed such that its ground is as close as possible to the IC's PGND pins -
avoiding additional voltage drop in traces.
5) The inductor should be placed close to the SW pin and connect directly to the output capacitor - minimizing
the loop area between the SW pin, inductor, output capacitor and PGND pin.
More detailed information can be found in the EVM Users Guide, SLVU483.
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve
appropriate power dissipation. Although the Exposed Thermal Pad can be connected to a floating circuit board
trace, the device will have better thermal performance if it is connected to a larger ground plane. The Exposed
Thermal Pad is electrically connected to AGND.
11.2 Layout Example
space
space
VOUT
GND
C2
L1
PGND
PG
SW
VOS
FB
VIN
EN
C1
AGND
AGND
VIN
R1
R2
Figure 38. Layout Example
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11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad
Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and (SPRA953).
The TPS6217x-Q1 are designed for a maximum operating junction temperature (TJ) of 125°C. Therefore the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. Since the thermal resistance of the package is fixed,
increasing the size of the surrounding copper area and improving the thermal connection to the IC can reduce
the thermal resistance. To get an improved thermal behavior, it's recommended to use top layer metal to connect
the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for
improved thermal performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
24
版权 © 2014–2017, Texas Instruments Incorporated
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
www.ti.com.cn
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
12.1.1.1 使用 WEBENCH® 工具定制设计方案
请单击此处，借助 WEBENCH® 电源设计器并使用 TPS62170-Q1 器件创建定制设计方案。
1. 在开始阶段键入输出电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。
12.1.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 文档支持
12.2.1 相关文档ꢀ
应用报告《优化 TPS62130/40/50/60/70 输出滤波器》（文献编号：SLVA463）
应用报告《采用前馈电容优化内部补偿 DC-DC 转换器的瞬态响应》（文献编号：SLVA289）
应用报告《采用前馈电容优化 TPS62130/40/50/60/70 的稳定性和带宽》（文件编号：SLVA466）
应用报告《在反向降压/升压拓扑中使用 TPS6215x》（文献编号：SLVA469）
用户指南《TPS62160EVM-627 和 TPS62170EVM-627 评估模块》（文献编号：SLVU483）
应用报告《采用 JEDEC PCB 设计的线性和逻辑封装散热特性》（文件编号：SZZA017）
应用报告《半导体和 IC 封装热指标》（文件编号：SPRA953）
版权 © 2014–2017, Texas Instruments Incorporated
25
TPS62170-Q1, TPS62171-Q1, TPS62172-Q1
ZHCSD50D –DECEMBER 2014–REVISED FEBRUARY 2017
www.ti.com.cn
12.3 相关链接
以下表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 4. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
TPS62170-Q1
TPS62171-Q1
TPS62172-Q1
12.4 商标
DCS-Control, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.7 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS62170QDSGRQ1
TPS62170QDSGTQ1
TPS62171QDSGRQ1
TPS62171QDSGTQ1
TPS62172QDSGRQ1
TPS62172QDSGTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
QUEQ
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
QUEQ
QUFQ
QUFQ
QUGQ
QUGQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS62170QDSGRQ1
TPS62170QDSGTQ1
TPS62171QDSGRQ1
TPS62171QDSGTQ1
TPS62172QDSGRQ1
TPS62172QDSGTQ1
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS62170QDSGRQ1
TPS62170QDSGTQ1
TPS62171QDSGRQ1
TPS62171QDSGTQ1
TPS62172QDSGRQ1
TPS62172QDSGTQ1
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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