TPS6209733RWKR [TI]
采用 HotRod 封装并具有可选开关频率的 2A 降压转换器 | RWK | 11 | -40 to 125;
| 型号： | TPS6209733RWKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 HotRod 封装并具有可选开关频率的 2A 降压转换器 | RWK | 11 | -40 to 125 开关 转换器 |
| 文件： | 总30页 (文件大小：2631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62097
ZHCSMN1A –DECEMBER 2015 –REVISED JANUARY 2021
具有iDCS-Control、强制PWM 模式和可选开关频率的TPS62097 2A 高效降压转
换器
1 特性
3 说明
• 推出的新产品：采用SOT583 封装的TPS62851x
6V、0.5A/1A/2A 降压转换器
• iDCS-Control 拓扑
• 强制PWM 或省电模式
• 效率高达97%
• 2.5V 至6.0V 输入电压
• 可调输出电压：0.8V 至VIN
• 1.8V 和3.3V 固定输出电压
• ±1% 的输出电压精度
• 断续短路保护
• 可编程软启动
• 输出电压跟踪
• 可选开关频率
• 100% 占空比，可实现超低压降
• 输出放电
• 电源正常状态输出
• 热关断保护
• -40°C 至125°C 的工作结温范围
• 采用2mm × 2mm VQFN 封装
TPS62097 器件是一款同步降压转换器，针对高效率和
噪声关键型应用进行了优化。此器件主要用于宽输出电
流范围内的高效转换。在中等负载至重负载状态下，此
转换器在PWM 模式下运行，且会在轻负载下自动进入
节能运行模式。可使用外部电阻器在 1.5MHz 至
2.5MHz 之间选择开关频率。iDCS-Control 可在强制
PWM 模式下以恒定开关频率实现低噪声运行。
为了解决系统电源轨的需求，内部补偿电路支持使用电
容值高于 150µF 的各种外部输出电容器。为在启动过
程中控制浪涌电流，此器件通过连接至 SS/TR 引脚的
外部电容器提供了可编程的软启动。SS/TR 引脚还可
用于电压跟踪配置中。此器件还集成了短路保护、电源
正常和热关断特性。此器件采用 2mm x 2mm VQFN
封装。
新产品 TPS62851x 提供更低的 BOM 成本、更小的解
决方案总尺寸以及其他特性。
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS62097
2 应用
TPS6209718
TPS6209733
VQFN (11)
2.0mm x 2.0mm
• 电机驱动器
• 可编程逻辑控制器(PLC)
• 固态硬盘(SSD)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 负载点(POL) 稳压器
L1
TPS6209718
1.0µH
100
VIN
2.5V to 6.0V
VOUT
1.8V/2A
PVIN
AVIN
EN
SW
C1
10µF
C2
22µF
VOS
90
VIN
R3
100k
FB
SS/TR
MODE
C3
10nF
PG
POWER GOOD
80
AGND PGND
70
VIN = 2.7 V
VIN = 3.3 V
1.8V 输出，PWM/PSM 模式应用
VIN = 4.2 V
VIN = 5.0 V
60
1m
10m
100m
Load (A)
1
5
D003
1.8V 输出，PWM/PSM 模式效率
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCD6
TPS62097
www.ti.com.cn
ZHCSMN1A –DECEMBER 2015 –REVISED JANUARY 2021
Table of Contents
8.4 Device Function Modes.............................................. 8
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 1.2-V Output Application...........................................12
10 Power Supply Recommendations..............................20
11 Layout...........................................................................21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Device Support....................................................... 22
12.2 支持资源..................................................................22
12.3 接收文档更新通知................................................... 22
12.4 Trademarks.............................................................22
12.5 静电放电警告.......................................................... 22
12.6 术语表..................................................................... 22
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommend Operating Conditions.............................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................6
8 Detailed Description........................................................7
8.1 Overview.....................................................................7
8.2 Functional Block Diagram...........................................7
8.3 Feature Description.....................................................8
Information.................................................................... 22
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2015) to Revision A (January 2021)
Page
• 添加了指向新器件(TPS62851x) 的链接.............................................................................................................1
• 添加了指向TI 网站上相关应用页面的链接......................................................................................................... 1
• 更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1
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5 Device Options
PART NUMBER(1)
OUTPUT VOLTAGE
Adjustable
1.8V
PACKAGE MARKING
TPS62097
TPS6209718
TPS6209733
ZFZ5
ZGB5
ZGC5
3.3V
(1) For detailed ordering information, please check the Mechanical, Packaging, and Orderable Information section at the end of this
datasheet.
6 Pin Configuration and Functions
AGND MODE SS/TR AVIN
11
10
9
8
7
PGND
SW
1
2
PVIN
SW
3
4
5
6
VOS
FB
PG
EN
图6-1. 11-Pin VQFN RWK Package (Top View)
表6-1. Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
1
PGND
SW
Power ground pin
2
PWR Switch pin. It is connected to the internal MOSFET switches. Connect the external inductor between this terminal
and the output capacitor.
VOS
FB
3
4
I
I
Output voltage sense pin. This pin must be directly connected to the output capacitor.
Feedback pin. For the fixed output voltage versions, this pin is recommended to be connected to AGND for
improved thermal performance. The pin also can be left floating as an internal 400-kΩresistor is connected
between this pin and AGND for fixed output voltage versions. For the adjustable output voltage version, a resistor
divider sets the output voltage.
PG
EN
5
6
O
I
Power-good open-drain output pin. The pullup resistor should not be connected to any voltage higher than 6 V. If
it is not used, leave the pin floating.
Enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables the device. This
pin has an internal pulldown resistor of typically 375 kΩwhen the device is disabled.
PVIN
AVIN
7
8
9
PWR Power input supply pin
I
I
Analog input supply pin. Connect it to the PVIN pin together.
SS/TR
Soft start-up and voltage tracking pin. A capacitor is connected to this pin to set the soft start-up time. Leaving
this pin floating sets the minimum start-up time.
MODE
AGND
10
11
I
Mode selection pin. Connect this pin to AGND to enable Power Save Mode with automatic transition between
PWM and Power Save Mode. Connect this pin to an external resistor or leave floating to enable forced PWM
mode only. See 表8-1.
Analog ground pin
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
0
MAX
6.0
UNIT
Voltage at Pins(2)
AVIN, PVIN, EN, VOS, PG
MODE, SS/TR, SW
FB
V
VIN+0.3V
3.0
Sink current
Temperature
PG
1.0
mA
°C
Operating Junction, TJ
Storage, Tstg
-40
150
150
–65
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human Body Model (HBM) ESD stress voltage(1)
Charged Device Model (CDM) ESD stress voltage(2)
Electrostatic
discharge
VESD
V
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommend Operating Conditions
Over operating free-air temperature range, unless otherwise noted.
MIN
2.5
0
MAX
UNIT
VIN
Input voltage range
6.0
6.0
VIN
2.0
125
V
V
VPG
VOUT
IOUT
TJ
Pull-up resistor voltage
Output voltage range
Output current range
0.8
0
V
A
Operating junction temperature
-40
°C
7.4 Thermal Information
TPS62097xx
RWK (11 TERMINALS)
THERMAL METRIC(1)
UNITS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
83.4
61.0
19.9
4.4
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
19.9
2.0
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
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7.5 Electrical Characteristics
TJ = -40°C to 125°C, and VIN = 2.5V to 6.0V. Typical values are at TJ = 25°C and VIN = 3.6V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY
40
40
57
65
3
EN = High, Device not switching, TJ = –40°C to 85°C
IQ
Quiescent current into AVIN, PVIN
µA
µA
V
EN = High, Device not switching
0.7
0.7
2.3
2.4
160
20
EN = Low, TJ = –40°C to 85°C
EN = Low
ISD
Shutdown current into AVIN, PVIN
Under voltage lock out threshold
10
2.4
2.5
VIN falling
2.2
2.3
VUVLO
VIN rising
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
°C
°C
TJSD
TJ falling
LOGIC INTERFACE (EN, MODE)
VH_EN
VL_EN
IEN,LKG
RPD
High-level input voltage, EN pin
2.0
1.2
5.5
1.6
1.3
V
V
Low-level input voltage, EN pin
Input leakage current into EN pin
Pull-down resistance at EN pin
High-level input voltage, MODE pin
Low-level input voltage, MODE pin
1.0
0.9
EN = High
EN = Low
0.01
375
µA
kΩ
V
VH_MO
VL_MO
0.4
V
IMO,LKG Input leakage current into MODE pin
MODE = High
0.01
0.16
µA
SOFT STARTUP, POWER GOOD (SS/TR, PG)
ISS
Soft startup current
7.5
1
9.5
µA
Voltage tracking gain factor
VFB / VSS/TR
VOUT rising, referenced to VOUT nominal
VOUT falling, referenced to VOUT nominal
Isink = 1mA
92
87
95
90
98
92
VPG
Power good threshold
%
VPG,OL
Low-level output voltage, PG pin
Input leakage current into PG pin
0.4
1.6
V
IPG,LKG
VPG = 5.0V
0.01
µA
OUTPUT
PWM mode, No load
PSM mode(1)
1.0
2.1
–1.0
–1.0
792
Output voltage accuracy
TPS6209718, TPS6209733
VOUT
%
PWM mode
800
800
0.01
165
0.02
0.2
808
817
0.1
VFB
Feedback reference voltage
mV
µA
PSM mode(1)
792
IFB,LKG
RDIS
Input leakage current into FB pin
Output discharge resistor
Line regulation
VFB = 0.8V
EN = Low, VOUT = 1.8V
IOUT = 0.5A, VOUT = 1.8V(1)
PWM mode, VOUT = 1.8V (1)
Ω
%/V
Load regulation
%/A
POWER SWITCH
ISW = 500mA, VIN = 5.0V
ISW = 500mA, VIN = 3.6V
ISW = 500mA, VIN = 5.0V
ISW = 500mA, VIN = 3.6V
40
50
73
96
High-side FET on-resistance
mΩ
mΩ
RDS(on)
40
68
Low-side FET on-resistance
50
85
3.1
3.3
3.6
3.6
4.2
3.9
-0.7
ILIMF
ILIMN
High-side FET forward current limit
Low-side FET negative current limit
A
A
VIN = 5.0V
Forced PWM mode
–1.25 –1.1
(1) Conditions: L = 1 μH, COUT = 22 μF, Switching Frequency = 2.0 MHz
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7.6 Typical Characteristics
120
120
100
80
60
40
20
0
TJ = -40°C
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
100
80
60
40
20
0
2.5
3.0
3.5
4.0 4.5
Input Voltage (V)
5.0
5.5
6.0
2.5
3.0
3.5
4.0 4.5
Input Voltage (V)
5.0
5.5
6.0
D015
D014
图7-2. Low-Side FET On-Resistance
图7-1. High-Side FET On-Resistance
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8 Detailed Description
8.1 Overview
The TPS62097 synchronous step-down converter is based on the iDCS-Control (Industrial Direct Control with
Seamless transition into Power Save Mode) topology. The control topology not only keeps the advantages of
DCS-Control, but also provides other features:
• Forced PWM mode over the whole load range
• Selectable PWM switching frequency
• 1% output voltage accuracy
• Output voltage sequencing and tracking
The iDCS-Control topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in Power Save Mode (PSM) at light load conditions. Or it forces the device in fixed frequency
PWM mode only operation for the whole load range.
In PWM mode, the device operates with a predictive on-time switching pulse. A quasi-fixed switching frequency
over the input and output voltage range is achieved by using an input and output voltage feedforward to set the
on-time, as shown in 表 8-1. The converter enters Power Save Mode, reducing the switching frequency and
minimizing current consumption, to achieve high efficiency over the entire load current range. Since iDCS-
Control supports both operation modes within a single building block, the transition from PWM mode to Power
Save Mode is seamless and without effects on the output voltage.
8.2 Functional Block Diagram
AVIN
Hiccup
Counter
PG
PVIN
VFB
High-side
Current Sense
VREF
Low-side
Current Sense
EN
Bandgap
Undervoltage Lockout
Thermal Shutdown
375kΩ(2)
AGND
SW
MOSFET Driver
Control Logic
VIN
Voltage
Clamp
VREF
PGND
VOS
SS/TR
MODE
Ramp
VIN
Direct Control
and
Compensation
Comparator
R1(1)
R2(1)
On time
Selection
tON
Timer
FB
VREF
Error Amplifier
165Ω
iDCS - Control
EN Output Discharge
Logic
Note:
(1) R1, R2 are implemented in the fixed output voltage versions only.
(2) When the device is enabled, the 375 kΩ resistor is disconnected.
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8.3 Feature Description
8.3.1 100% Duty Cycle Mode
The device offers a low input to output voltage dropout by entering 100% duty cycle mode when the input
voltage reaches the level of the output voltage. In this mode, the high-side MOSFET switch is constantly turned
on and the low-side MOSFET is switched off. The minimum input voltage to maintain output regulation,
depending on the load current and output voltage, is calculated as:
VIN(min) = VOUT(min) + IOUT x (RDS(on) + RL)
(1)
where
• VIN(min) = Minimum input voltage to maintain a minimum output voltage
• IOUT = Output current
• RDS(on) = High side FET on-resistance
• RL = Inductor ohmic resistance (DCR)
When the device operates close to 100% duty cycle mode, the TPS62097 cannot enter Power Save Mode
regardless of the load current if the input voltage decreases to typically 15% above the output voltage. The
device maintains output regulation in PWM mode.
8.3.2 Switch Current Limit and Hiccup Short Circuit Protection
The switch current limit prevents the devices from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted/saturated inductor or a heavy load/
shorted output circuit condition. If the inductor current reaches the threshold ILIMF, the high-side MOSFET is
turned off and the low-side MOSFET is turned on to ramp down the inductor current. Once this switch current
limit is triggered 32 times, the devices stop switching and enable the output discharge. The devices then
automatically start a new start-up after a typical delay time of 100 µs has passed. This is HICCUP short circuit
protection and is implemented to reduce the current drawn during a short circuit condition. The devices repeat
this mode until the high load condition disappears.
When the device is in forced PWM mode, the negative current limit of the low-side MOSFET is active. The
negative current limit prevents excessive current from flowing back through the inductor to the input.
8.3.3 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is implemented, which shuts
down the devices at voltages lower than VUVLO with a hysteresis of 100 mV.
8.3.4 Thermal Shutdown
The device goes into thermal shutdown and stops switching once the junction temperature exceeds TJSD. Once
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
8.4 Device Function Modes
8.4.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic high. Accordingly, shutdown mode is forced if the EN pin is
pulled low with a shutdown current of typically 0.7 μA.
In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal
resistor of 165 Ωdischarges the output through the VOS pin smoothly. The output discharge function also works
when thermal shutdown, undervoltage lockout, or HICCUP short circuit protection are triggered.
An internal pulldown resistor of 375 kΩis connected to the EN pin when the EN pin is low. The pulldown resistor
is disconnected when the EN pin is high.
8.4.2 Power Save Mode and Forced PWM Mode (MODE)
The MODE pin is a multi-functional pin that allows the device operation in forced PWM mode or PWM/PSM
mode, and to select the PWM switching frequency.
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Once the EN pin is pulled high, the IC enables internal circuit blocks and prepares to ramp the output up. The
period between the rising edge of the EN pin and the beginning of the power stage switching is called the MODE
detection time, typically 50 µs. During the MODE detection time period, shown in 图 8-1, the PWM switching
frequency and operating mode are set by the MODE pin status, as shown in 表8-1.
The PWM switching frequency cannot be changed after the detection time period. Only when the device is set in
PWM/PSM mode during the MODE detection time period (MODE = AGND), it is possible to switch between
PWM/PSM and forced PWM operation modes by toggling the MODE pin with a GPIO pin of a microcontroller, for
example. The other four MODE pin selections force the device in PWM mode only.
EN
Disable
Enable
VOUT
Soft Startup
PG
MODE
Detection
图8-1. Power-up Sequence
表8-1. Switching Frequency and Mode Selection
TYPICAL PWM
SWITCHING
FREQUENCY
(MHZ)
RESISTANCE AT MODE
TOGGLE MODE PIN
AFTER MODE DETECTION
OPERATING
MODE
PIN
ON-TIME EQUATION
(E24 EIA VALUE)
1.50
1.75
No
No
tON = 667 ns x VOUT / VIN
tON = 571 ns x VOUT / VIN
Forced PWM
Forced PWM
8.2 kΩ±5%
18 kΩ±5%
PWM/PSM and
Forced PWM
2.00
AGND
Yes
tON = 500 ns x VOUT / VIN
2.25
2.50
No
No
tON = 444 ns x VOUT / VIN
tON = 400 ns x VOUT / VIN
Forced PWM
Forced PWM
39 kΩ±5%
75 kΩ±5% or Open
Connecting the MODE pin to AGND with a resistor or leaving the MODE pin open forces the device into PWM
mode for the whole load range. The device operates with a fixed switching frequency that allows simple filtering
of the switching frequency for noise sensitive applications. In forced PWM mode, the efficiency is lower than that
of PSM at light load.
Connecting the MODE pin to the AGND pin enables Power Save Mode with an automatic transition between
PWM and Power Save Mode. As the load current decreases and the inductor current becomes discontinuous,
the device enters Power Save Mode operation automatically. In Power Save Mode, the switching frequency is
reduced and estimated by 方程式 2. In Power Save Mode, the output voltage rises slightly above the nominal
output voltage, as shown in Load Regulation, PWM/PSM Mode (2.0 MHz). This effect is minimized by increasing
the output capacitor.
2´IOUT
fPSM
=
V
VIN - VOUT
2
IN
´
tON
´
VOUT
L
(2)
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When the device operates close to 100% duty cycle mode, the TPS62097 cannot enter Power Save Mode
regardless of the load current if the input voltage decreases to typically 15% above the output voltage. The
device maintains output regulation in PWM mode.
8.4.3 Soft Start-up (SS/TR)
The TPS62097 programs its output voltage ramp rate with the SS/TR pin. Connecting an external capacitor to
SS/TR enables output soft start-up to reduce inrush current from the input supply. The device charges the
capacitor voltage to the input supply voltage with a constant current of typically 7.5 μA. The FB pin voltage
follows the SS/TR pin voltage until the internal reference voltage of 0.8 V is reached. The soft start-up time is
calculated using 方程式3. Keep the SS/TR pin floating to set the minimum start-up time.
0.8V
tSS = CSS / TR
´
7.5mA
(3)
An active pulldown circuit is connected to the SS/TR pin. It discharges the external soft start-up capacitor in case
of disable, UVLO, thermal shutdown, and HICCUP short circuit protection.
8.4.4 Voltage Tracking (SS/TR)
The SS/TR pin is externally driven by another voltage source to achieve output voltage tracking. The application
circuit is shown in 图 8-2. From 0 V to 0.8 V, the internal reference voltage to the internal error amplifier follows
the SS/TR pin voltage. When the SS/TR pin voltage is above 0.8 V, the voltage tracking is disabled and the FB
pin voltage is regulated at 0.8 V. The device achieves ratiometric or coincidental (simultaneous) output tracking,
as shown in 图8-3.
VOUT1
VOUT2
TPS62097
R1
R3
SS/TR
FB
R2
R4
图8-2. Output Voltage Tracking
Voltage
Voltage
VOUT1
VOUT1
VOUT2
VOUT2
R3 R1
<
R3 R1
=
R4 R2
R4 R2
t
t
a) Ratiometric Tracking
b) Coincidental Tracking
图8-3. Voltage Tracking Options
The R2 value should be set properly to achieve accurate voltage tracking by taking 7.5 µA soft start-up current
into account. 1 kΩor smaller is a sufficient value for R2.
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For decreasing SS/TR pin voltage, the device does not sink current from the output when the device is in PSM,
so the resulting decreases of the output voltage can be slower than the SS/TR pin voltage if the load is light.
When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is
VIN + 0.3 V.
8.4.5 Power Good (PG)
The TPS62097 has a power-good output. The PG pin goes high impedance once the output voltage is above
95% of the nominal voltage and is driven low once the output voltage falls below typically 90% of the nominal
voltage. The PG pin is an open-drain output and is specified to sink up to 1 mA. The power-good output requires
a pullup resistor connected to any voltage rail less than 6 V. The PG pin goes low when the device is disabled or
in thermal shutdown. When the devices are in UVLO, the PG pin is high impedance.
The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.
Leave the PG pin floating when not used.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design of
the TPS62097.
9.2 1.2-V Output Application
L1
TPS62097
1.0µH
VIN
2.5V to 6.0V
VOUT
1.2V/2A
PVIN
AVIN
EN
SW
C1
10µF
C2
22µF
VOS
R1
10k
VIN
SS/TR
MODE
FB
C3
10nF
R2
20k
R3
100k
PG
AGND PGND
POWER GOOD
图9-1. 1.2-V Output Application Schematic
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
表9-1. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
2.5 V to 6 V
1.2 V
Output voltage
Output current
2.0 A
Output voltage ripple
< 30 mV
表9-2 lists the components used for the example.
表9-2. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
C1
C2
C3
L1
TDK
TDK
10 μF, Ceramic Capacitor, 6.3 V, X7R, size 0805, C2012X7R0J106M125AB
22 μF, Ceramic Capacitor, 6.3 V, X7S, size 0805, C2012X7S1A226M125AC
10 nF, Ceramic Capacitor, 6.3 V, X7R, size 0603, GRM188R70J103KA01
1 µH, Shielded, 5.4 A, XFL4020-102MEB
Murata
Coilcraft
Std
R1
R2
R3
Depending on the output voltage, 1% accuracy
20 kΩ, 1% accuracy
Std
Std
100 Ωk, 1% accuracy
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9.2.2 Detailed Design Procedure
9.2.2.1 Setting the Output Voltage
The output voltage is set by an external resistor divider according to 方程式4:
R1
R2
R1
R2
æ
ö
æ
ö
VOUT = VFB
´
1 +
= 0.8 V ´ 1 +
ç
÷
ç
÷
è
ø
è
ø
(4)
R2 should not be higher than 20 kΩ to reduce noise coupling into the FB pin and improve the output voltage
regulation. 图9-1 shows the external resistor divider value for 1.2-V output. Choose additional resistor values for
other outputs. A feedforward capacitor is not required.
The fixed output voltage versions, TPS6209718 and TPS6209733, do not need the external resistor divider. TI
recommends to connect the FB pin to AGND for improved thermal performance.
9.2.2.2 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify the selection process, 表 9-3
outlines possible inductor and capacitor value combinations for most applications.
表9-3. Output Capacitor / Inductor Combinations
NOMINAL COUT [µF](3)
NOMINAL L [µH](2)
10
22
47
100
150
0.47
1
(1)
+
+
+
+
2.2
(1) Typical application configuration. Other '+' mark indicates recommended filter combinations. Other
values may be acceptable in applications but should be fully tested by the user. Refer to the
application note SLVA710.
(2) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20%
and -30%. The required effective inductance is 500-nH minimum.
(3) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary
by 20% and -50%.
9.2.2.3 Inductor Selection
The main parameters for the inductor selection are the inductor value and the saturation current. To calculate the
maximum inductor current under static load conditions, 方程式5 is given.
DIL
IL,MAX = IOUT,MAX
+
2
VOUT
1-
V
IN
DIL = VOUT
´
L ´ fSW
(5)
Where:
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value
TI recommends to choose the saturation current for the inductor 20% to 30% higher than the IL,MAX, out of 方程
式 5. A higher inductor value is also useful to lower ripple current but increases the transient response time as
well. The following inductors are recommended to be used in designs.
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表9-4. List of Recommended Inductors
DC RESISTANCE
INDUCTANCE
[µH]
CURRENT RATING
[A]
DIMENSIONS
PART NUMBER(1)
L x W x H [mm3]
[mΩTYP]
1
1
1
1
1
1
1
5.4
5.3
3.4
5.1
4.2
2.6
6.6
4.0x4.0x2.0
2.5x2.0x1.2
2.0x1.2x1.0
3.0x3.0x1.2
2.5x2.0x1.2
2.5x2.0x1.2
3.0x3.0x1.2
11
33
62
43
43
48
42
COILCRAFT XFL4020-102ME
TOKO DFE252012F-1R0M
TOKO DFE201210S-1R0M
TAIYO YUDEN MDMK3030T1R0MM
CYNTEC SDEM25201B-1R0MS-79
Murata LQH2HPN1R0NJR
Wurth Electronics 74438334010
(1) See Third-Party Products Disclaimer
9.2.2.4 Capacitor Selection
The input capacitor is the low impedance energy source for the converters which helps to provide stable
operation. A low-ESR multilayer ceramic capacitor is required for best filtering and should be placed between
PVIN and PGND as close as possible to those pins. For most applications, a 10-μF capacitor is sufficient,
though a larger value reduces input current ripple.
The architecture of the TPS62097 allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends to
use X7R or X5R dielectrics. The recommended typical output capacitor value is 22 μF and can vary over a wide
range as outlined in 表9-4.
Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance.
Choose the right capacitor carefully in combination with considering its package size and voltage rating. Ensure
that the input effective capacitance is at least 5 μF and the output effective capacitance is at least 10 μF.
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9.2.3 Application Performance Curves
TA = 25°C, VIN = 3.6 V, unless otherwise noted.
100
90
100
90
80
70
60
80
70
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
1m
0
0.5
1
Load (A)
1.5
2
10m
100m
Load (A)
1
5
D002
D001
VOUT = 1.2 V
VOUT = 1.2 V
图9-3. Efficiency, Forced PWM Mode (2.0 MHz)
图9-2. Efficiency, PWM/PSM Mode (2.0 MHz)
100
100
90
80
90
80
70
70
VIN = 2.7 V
VIN = 3.3 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 4.2 V
VIN = 5.0 V
60
1m
60
10m
100m
Load (A)
1
5
0
0.5
1
Load (A)
1.5
2
D003
D004
VOUT = 1.8 V
VOUT = 1.8 V
图9-4. Efficiency, PWM/PSM Mode (2.0 MHz)
图9-5. Efficiency, Forced PWM Mode (2.0 MHz)
100
100
90
80
70
90
80
70
VIN = 4.2 V
VIN = 5.0 V
VIN = 4.2 V
VIN = 5.0 V
60
1m
60
10m
100m
Load (A)
1
5
0
0.5
1
Load (A)
1.5
2
D005
D006
VOUT = 3.3 V
VOUT = 3.3 V
图9-6. Efficiency, PWM/PSM Mode (2.0 MHz)
图9-7. Efficiency, Forced PWM Mode (2.0 MHz)
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1.0
0.5
1.0
0.5
0.0
0.0
-0.5
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
TA = -40°C
TA = 25°C
TA = 85°C
-1.0
-1.0
1m
10m
100m
Load (A)
1
5
1m
10m
100m
Load (A)
1
5
D007
D008
VOUT = 1.2 V
VOUT = 1.2 V
图9-8. Load Regulation, PWM/PSM Mode (2.0 MHz) 图9-9. Load Regulation, Forced PWM Mode (2.0
MHz)
5x106
1.0
106
0.5
105
0.0
104
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
VIN = 3.3 V
VIN = 5.0 V
103
-1.0
1m
10m
100m
Load (A)
1
5
2.5
3.0
3.5
4.0 4.5
Input Voltage (V)
5.0
5.5
6.0
D010
D009
VOUT = 1.2 V
MODE = AGND
VOUT = 1.2 V
IOUT = 500 mA
图9-11. Switching Frequency, PWM/PSM Mode (2.0
图9-10. Line Regulation, Forced PWM Mode (2.0
MHz)
MHz)
3.0
2.5
2.0
1.5
1.0
3.0
2.5
2.0
1.5
1.0
IOUT = 0 A
IOUT = 1 A
IOUT = 2 A
IOUT = 1 A
IOUT = 2 A
0.5
0.5
2.5
3.0
3.5
4.0 4.5
Input Voltage (V)
5.0
5.5
6.0
2.5
3.0
3.5
4.0 4.5
Input Voltage (V)
5.0
5.5
6.0
D012
D011
VOUT = 1.2 V
VOUT = 1.2 V
MODE = High after PWM/PSM Selection
RMode = 8.2 kΩ
图9-12. Switching Frequency, Forced PWM Mode
图9-13. Switching Frequency, Forced PWM Mode
(2.0 MHz)
(1.5 MHz)
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3.0
VSW
2.5
2.0
1.5
1.0
2V/DIV
VOUT
10mV/DIV
AC
ICOIL
200mA/DIV
2A OFFSET
IOUT = 0 A
IOUT = 1 A
IOUT = 2 A
Time - 200ns/DIV
0.5
2.5
D016
3.0
3.5
4.0 4.5
Input Voltage (V)
5.0
5.5
6.0
VOUT = 1.2 V
IOUT = 2 A
D013
VOUT = 1.2 V
MODE = Open
图9-15. Output Ripple, PWM Operation (2.0 MHz)
图9-14. Switching Frequency, Forced PWM Mode
(2.5 MHz)
IOUT
VSW
2A/DIV
2V/DIV
VOUT
100mV/DIV
AC
VOUT
20mV/DIV
AC
ICOIL
ICOIL
2A/DIV
300mA/DIV
Time - 2ꢀs/DIV
Time - 5ꢀs/DIV
D017
D018
VOUT = 1.2 V
IOUT = 30 mA
VOUT = 1.2 V
IOUT = 0 A to 2 A, 1 A / µs
图9-16. Output Ripple, Power Save Operation
图9-17. Load Transient, PWM/PSM Mode (2.0 MHz)
IOUT
VEN
2A/DIV
2V/DIV
VOUT
100mV/DIV
AC
VOUT
500mV/DIV
ICOIL
ICOIL
300mA/DIV
2A/DIV
Time - 250ꢀs/DIV
Time - 5ꢀs/DIV
D020
D019
VOUT = 1.2 V
ROUT = No Load
VOUT = 1.2 V
IOUT = 0 A to 2 A, 1 A / µs
图9-19. Startup and Shutdown without Load
图9-18. Load Transient, Forced PWM Mode (2.0
MHz)
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Short
Recovery
VEN
2V/DIV
VOUT
500mV/DIV
VOUT
500mV/DIV
ICOIL
2A/DIV
ICOIL
1A/DIV
Time - 300ꢀs/DIV
Time - 250ꢀs/DIV
D022
D021
VOUT = 1.2 V
VOUT = 1.2 V
ROUT = 0.8 Ω(1.5 A) with 1-ms short
ROUT = 0.6 Ω(2 A)
图9-21. Short Circuit Protection, HICCUP
图9-20. Startup and Shutdown with Load
9.2.4 Coincidental Voltage Tracking
L1
1.0µH
TPS6209718
VOUT1
1.8V
VIN
2.5V to 6.0V
C1
PVIN
AVIN
EN
SW
C2
22µF
VOS
10µF
VEN
SS/TR
MODE
FB
C3
10nF
PG
AGND PGND
L1
1.0µH
TPS62097
VOUT2
1.2V
PVIN
AVIN
EN
SW
C4
10µF
C5
22µF
VOS
R3
10k
R1
0.5k
SS/TR
MODE
FB
R4
20k
PG
R2
1k
AGND PGND
图9-22. 1.8-V and 1.2-V Coincidental Voltage Tracking Schematic
9.2.4.1 Design Requirements
For this design example, use the following as the input parameters.
表9-5. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
2.5 V to 6 V
1.8 V
Input voltage range
Output voltage 1
Output voltage 2
1.2 V
Output voltage 2 follows output voltage 1 coincidentally.
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9.2.4.2 Detailed Design Procedure
Set 1 kΩ for R2 and 0.5 kΩ for R1. Connect the two converters as shown in 图 9-22. Set up two converters in
forced PWM mode.
9.2.4.3 Application Performance Curve
TA = 25°C, VIN = 5.0 V, unless otherwise noted.
VEN
2V/DIV
VOUT1
500mV/DIV
VOUT2
500mV/DIV
Time - 1ms/DIV
D023
VOUT1 = 1.8 V
VOUT2 = 1.2 V
图9-23. Coincidental Tracking Waveform
9.2.5 Switching Frequency Selection
L1
1.0µH
TPS6209718
VIN
2.5V to 6.0V
VOUT
1.8V/2A
PVIN
AVIN
EN
SW
C1
10µF
C2
22µF
VOS
VIN
R3
100k
FB
SS/TR
MODE
C3
10nF
PG
POWER GOOD
R4
AGND PGND
图9-24. Switching Frequency Selection by an External Resistor
9.2.5.1 Design Requirements
For this design example, use the following as the input parameters.
表9-6. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
2.5 V to 6 V
1.8 V
Input voltage range
Output voltage 1
Switching Frequency Selection
1.5 MHz, 2.0 MHz, or 2.5 MHz
9.2.5.2 Detailed Design Procedure
Set 8.2 kΩ and 75 kΩ for 1.5-MHz, 2.0-MHz, and 2.5-MHz switching frequency. R4 uses the standard E24
series resistor values.
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9.2.5.3 Application Performance Curves
TA = 25°C, VIN = 5.0, unless otherwise noted.
80
70
60
50
40
30
20
100
90
1.5MHz (FPWM)
2.0MHz (FPWM)
2.5MHz (FPWM)
1.5MHz (FPWM)
2.0MHz (FPWM)
2.5MHz (FPWM)
10
0
80
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
0
1
2
3
4
5
6
Frequency (Hz)
7
8
9
10
D025
D024
VOUT = 1.8 V
IOUT = 1 A
VOUT = 1.8 V
IOUT = 1 A
图9-26. Efficiency with Different Switching
图9-25. Spurious Output Noise with Different
Frequency
Switching Frequency
10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 2.5 V and 6 V. The average
input current of the TPS62097 is calculated as:
VOUT ´IOUT
1
IIN
=
´
h
V
IN
(6)
Ensure that a power supply has a sufficient current rating for the application.
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11 Layout
11.1 Layout Guidelines
• TI recommends to place all components as close as possible to the IC. Specifically, the input capacitor
placement must be closest to the PVIN and PGND pins of the device.
• The low side of the input and output capacitors must be connected directly to the PGND pin to avoid a ground
potential shift.
• Use the terminal of the input capacitor as the common node for AVIN and PVIN, AGND, and PGND. It helps
reduce the noise coupling into the internal analog circuit blocks. Do not use a solid plane pour to connect
these nodes.
• Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
• The sense trace connected to VOS pin is a signal trace. Special care should be taken to avoid noise being
induced. By a direct routing, parasitic inductance can be kept small. Keep the trace away from SW nodes.
• Refer to the 图11-1 for an example of component placement, routing, and thermal design.
11.2 Layout Example
VIN
C1
L1
AVIN
EN
SS/TR
PG
FB
MODE
AGND
VOS
C2
VOUT
GND
C3
R4
R1
R2
Single Point
Ground
图11-1. TPS62097 PCB Layout
11.2.1 Thermal Information
Implementation of integrated circuits in low-profile and fine pitch surface mount packages typically requires
special attention to power dissipation. Many system dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
节 7.4 provides the thermal metric of the device on the TPS62097 EVM after considering the PCB design of real
applications. The big copper planes connecting to the pads of the IC on the PCB board improve the thermal
performance of the device. For more details on how to use the thermal parameters, see the application notes:
Thermal Characteristics Application Notes SZZA017 and SPRA953.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
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Product Folder Links: TPS62097
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS6209718RWKR
TPS6209718RWKT
TPS6209733RWKR
TPS6209733RWKT
TPS62097RWKR
TPS62097RWKT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RWK
RWK
RWK
RWK
RWK
RWK
11
11
11
11
11
11
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ZGB5
ZGB5
ZGC5
ZGC5
ZFZ5
ZFZ5
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Nov-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS6209718RWKR
TPS6209718RWKT
TPS6209733RWKR
TPS6209733RWKT
TPS62097RWKR
TPS62097RWKT
VQFN-
HR
RWK
RWK
RWK
RWK
RWK
RWK
11
11
11
11
11
11
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
VQFN-
HR
VQFN-
HR
3000
250
VQFN-
HR
VQFN-
HR
3000
250
VQFN-
HR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Nov-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS6209718RWKR
TPS6209718RWKT
TPS6209733RWKR
TPS6209733RWKT
TPS62097RWKR
TPS62097RWKT
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RWK
RWK
RWK
RWK
RWK
RWK
11
11
11
11
11
11
3000
250
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
20.0
20.0
20.0
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RWK0011B
VQFN - 1 mm max height
SCALE 4.600
PLASTIC QUAD FLATPACK - NO LEAD
A
2.1
1.9
B
PIN 1 INDEX AREA
2.1
1.9
1 MAX
C
SEATING PLANE
0.08 C
(0.2) TYP
2X 1.5
SYMM
(0.2) TYP
0.05
0.00
6X 0.5
3
6
0.25
3X
0.15
2
1
PKG
0.45
7
0.475
0.275
8X
11
8
0.3
0.2
8X
0.9
0.8
0.1
0.05
C A
C
B
0.9
0.8
4221714/B 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Package pin numbers 1, 2, and 7 must be soldered to the printed circuit board for thermal and mechanical performance.
Refer to product data sheet for specific thermal pad and via recommendations.
www.ti.com
EXAMPLE BOARD LAYOUT
RWK0011B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.35)
2X (1.05)
11
8
NOTE 5
7
1
2
3X (0.2)
(1.825)
PKG
(0.45)
NOTE 5
8X (0.575)
8X (0.25)
3
6
SYMM
(2.4)
6X (0.5)
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
ALL AROUND
(0.05) MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
PADS 1,2 & 7
NON SOLDER MASK
DEFINED
PADS 3-6 & 8-11
SOLDER MASK DETAILS
4221714/B 12/2015
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
5. Size of metal pad may vary due to creepage requirements.
www.ti.com
EXAMPLE STENCIL DESIGN
RWK0011B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.3625)
2X (0.625)
8X (0.25)
SYMM
11
8
SOLDER MASK
EDGE, TYP
8X (0.575)
METAL UNDER
SOLDER MASK
TYP
4X (0.425)
7
1
2
PKG
(0.45)
TYP
(1.825)
2X
EXPOSED
METAL
7X (0.2)
4X
EXPOSED
METAL
3
6
6X (0.5)
3X (0.648)
2X (0.85)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PADS 1,2 & 7
81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4221714/B 12/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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