TPS61390RTER [TI]
具有电流镜和采样保持功能且输出电压为 85V 的升压转换器 | RTE | 16 | -40 to 125;
| 型号： | TPS61390RTER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电流镜和采样保持功能且输出电压为 85V 的升压转换器 | RTE | 16 | -40 to 125 升压转换器 开关 输出元件 |
| 文件： | 总28页 (文件大小：1998K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS61390
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
TPS61390 85-VOUT 升压转换器，具有电流镜和采样/保持功能
1 特性
3 说明
1
•
•
•
•
•
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输入电压范围：2.5V 至 5.5V
TPS61390 是一个 700kHz 脉宽调制 (PWM) 升压转换
器，具有 85V 开关 FET，输入范围为 2.5V 至 5.5V。
开关峰值电流高达 1000mA。TPS61390 包括具有两
个可选增益选项（1:5 或 4:5）的精确电流镜。
输出电压范围：高达 85V
开关 FET 的 R(DS)on：0.9Ω
开关电流限制：1000mA
最短响应时间为 400ns 的采样窗口
具有 0.5µs 响应时间的高光功率保护
开关频率：700kHz
此外，TPS61390 还集成了一个适用于突发模式光学
接收器 应用 的采样/保持电路，可捕获流经 APD 的电
流并将此电流传递给外部 ADC。当在强弱光学密度之
间转换时，此器件可实现快速的响应时间。TPS61390
还提供了高光功率保护，并将一个额外的 FET 与 APD
电源路径串联在一起，典型响应时间为 0.5µs。当高光
功率下降时，它能够自动恢复。
瞬态电流：来自 VIN 时为 110µA，来自 VOUT 时
为 340µA，来自 AVCC 时为 140µA
•
•
软启动时间：4.8ms
封装：3mm × 3mm × 0.75mm QFN
2 应用
TPS61390 可采用下面带有外露散热垫的 3mm × 3mm
QFN 封装。
•
•
•
APD 偏置
光线路终端
器件信息(1)
高压传感器电源
器件型号
TPS61390
封装
WQFN (16)
封装尺寸（标称值）
3.00mm × 3.00mm
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
典型应用电路
Diode
L
VIN
VOUT
COUT1
RFILTER
RPROTECT
SW
MONIN
VIN
EN
ON
OFF
CFILTER
CAP
CCAP
RUP
VOUT_ADJ
FB
RSVCC
VIN
RADJ
AVCC
VSP
RDOWN
CAVCC
ISHORT
CAP
To ADC
RSHORT
4:5
1:5
GAIN
CCAP
AGND
APD
SAMPLE
MON2
MON1 GND
CAPD
CMON1
1:5
4:5
CMON2
RMON2
RMON1
TIA
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEL7
TPS61390
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
www.ti.com.cn
目录
7.4 Device Functional Mode ......................................... 12
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
Power Supply Recommendations...................... 17
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Recommended Operating Conditions....................... 4
6.2 Absolute Maximum Ratings ...................................... 4
6.3 ESD Ratings.............................................................. 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
8
9
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 接收文档更新通知 ................................................. 19
11.2 社区资源................................................................ 19
11.3 商标....................................................................... 19
11.4 静电放电警告......................................................... 19
11.5 Glossary................................................................ 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (June 2019) to Revision B
Page
•
已更改 text string in Current Mirror section from "The voltage of MON1 is up to 400 mV......." to "The maximum
voltage of MON1 and MON2 is 2.5 V."................................................................................................................................. 11
Changes from Original (April 2019) to Revision A
Page
•
已更改 将状态更改为“生产数据” ............................................................................................................................................. 1
2
Copyright © 2019, Texas Instruments Incorporated
TPS61390
www.ti.com.cn
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
5 Pin Configuration and Functions
RTE Package
16-Pin WQFN
Top View
VSP
GAIN
1
12
11
10
9
FB
2
3
4
ISHORT
VIN
Thermal
Pad
MON2
MON1
CAP
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
VSP
1
O
Sample/Hold voltage output with single-ended output.
GAIN of the current mirror selection indicator of the sample/hold output:
Output low: sample/hold for current mirror gain 4 : 5;
Output high: sample/hold for current mirror gain 1 : 5;
This pin can also be any input pin:
GAIN
2
I
Input low: sample/hold for current mirror gain 4 : 5;
Input high: sample/hold for current mirror gain 1 : 5
Current mirror output pin of 1 : 5 ratio (Mirror current: APD current)
Current mirror output pin of 4 : 5 ratio (Mirror current: APD current)
Power supply for the APD, connect this pin with the cathode of APD
Current mirror input pin
MON2
MON1
APD
3
4
5
6
7
O
O
O
I
MONIN
GND
–
Power Ground
The switching node pin of the converter. It is connected to the drain of the internal low-side power
MOSFET and the source of the internal high-side power MOSFET
SW
8
PWR
CAP
VIN
9
O
I
Connecting a capacitor externally to lower the noise for current mirror.
IC power supply input
10
Programming the current limit for high optical power protection by a resistor between this pin and
GND.
ISHORT
FB
11
12
13
O
I
Feedback voltage
Enable logic input. Logic high level enables the device. Logic low level disables the device and turns it
into shutdown mode
EN
I
The sample trigger pin, the rising edge of this pin to trigger the sample and falling edge to hold the
sampled voltage.
SAMPLE
14
I
AVCC
AGND
15
16
I
Power supply for the sample/hold circuitry
–
Analog ground for the sample / hold and current mirror circuitry
Connect with GND, TI recommends connecting to Power GND on PCB
Exposed Thermal Pad
Copyright © 2019, Texas Instruments Incorporated
3
TPS61390
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
www.ti.com.cn
6 Specifications
6.1 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
20
NOM
MAX
UNIT
V
VIN
VOUT
TJ
Input voltage
5.5
85
Output voltage
V
Junction temperature
Effective Inductance
Effective Input Capacitance
Effective Output Capacitance
–40
125
°C
µH
µF
µF
L
4.7
1
CIN
COUT
0.1
6.2 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
85
UNIT
SW, APD, MONIN,CAP
–0.3
–0.3
–40
–65
V
V
Voltage
Other pins
6
TJ
Operating junction temperature
Storage temperature
125
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.3 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±1500
ANSI/ESDA/JEDEC JS-001, allpins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.4 Thermal Information
TPS61390
THERMAL METRIC(1)
RTE (WQFN)
16 PINS
52.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
54.4
27.9
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.0
YJB
27.8
RθJC(bot)
12.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2019, Texas Instruments Incorporated
TPS61390
www.ti.com.cn
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
6.5 Electrical Characteristics
Over recommended free-air temperature range, VIN = 3.3 V, AVCC = 3.3 V, VMONIN = 20 V to 85 V, TJ = - 40°C to 125°C,
typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
2.5
5.5
2.5
V
V
Under voltage lock out
VIN falling
2.4
VUVLO
Under voltage lock out hysteresis
VUVLO rising - VUVLO falling
200
mV
VIN = 3.3 V, VFB =VREF + 0.1 V, No
switching, -40 °C ≤ TJ ≤ 85 °C
IQ_IN
Quiescent current into VIN pin
110
140
uA
VIN = 3.3 V, VFB =VREF + 0.1 V,No
switching, -40 °C ≤ TJ ≤ 85 °C
IQ_OUT
IQ_VCC
Quiescent current into VOUT pin
Quiescent current into AVCC pin
Shutdown current into VIN pin
Shutdown current into VOUT pin
Shutdown current into AVCC pin
340
140
430
180
1
uA
uA
uA
uA
uA
AVCC = 3.3 V -40 °C ≤ TJ ≤ 85 °C
2.5 V ≤ VIN ≤ 5.5 V, EN = 0, -40 °C ≤
TJ ≤ 85 °C
ISD
EN = 0, -40 °C ≤ TJ ≤ 85 °C
1
AVCC = 3.3 V, EN = 0, -40 °C ≤ TJ ≤
85 °C
1
OUTPUT
VOUT
Output voltage range
85
V
V
VIN = 2.5 V to 5.5 V, TJ = 25 °C
1.188
1.182
1.2
1.2
1
1.212
VREF
Feedback regulation reference voltage
Feedback input leakage current
VIN = 2.5 V to 5.5 V, -40 °C ≤ TJ ≤
125 °C
1.218
25
V
IFB
POWER SWITCH
nA
RDS(on)
Low-side FET on resistance
3 V ≤ VIN ≤ 5.5 V
900
700
1300
800
mΩ
SWITCHING CHARACTERISTIC
fSW
Switching frequency
VIN = 3.3 V, VOUT = 60 V
600
kHz
CURRENT MIRROR
kMON1
kMON2
VMON
4:5 Current mirror gain
IAPD = 5 µA to 200 µA
IAPD = 100 µA to 2 mA
0.76
0.19
380
2.2
0.8
0.2
0.84
0.21
420
2.8
1:5 Current mirror gain
MON1 / MON2 Threshold
400
2.5
mV
V
IAPD = 1 mA
IAPD = 5 µA
VAPD_DRP
Current mirror voltage drop
Current mirror bias current
2.45
20
V
IBIAS
SAMPLE / HOLD
Sample/hold output error steady,+/-6
15
25
µA
IAPD = 20 uA, GAIN = 0.8, RMON = 3
kΩ
VERROR
-15
-5
+15
+5
%
%
sigma
Sample/hold output error steady,+/-6
sigma
IAPD = 500 µA, GAIN = 0.2, RMON =
3 kΩ
VERROR
tSP_DEL
Amplifier settling down time
10
8
µs
µs
tGAIN_COMP
Gain selection comparator time
+/-20% gap of threshold
Sample voltage sensing value
variation at 10-100 µs, (Max-
Min)/Average
VDROP_SP
Drop voltage during sample/hold
1
%
CURRENT LIMIT
ILIM_SW Peak switching current limit
VIN = 3.3 V, VOUT = 60 V
RISHORT = 25 kΩ
800
3.7
1.8
1000
1200
4.3
mA
mA
mA
4
2
ISHORT
High optical power current limit
RISHORT = 50 kΩ
2.2
Copyright © 2019, Texas Instruments Incorporated
5
TPS61390
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
Over recommended free-air temperature range, VIN = 3.3 V, AVCC = 3.3 V, VMONIN = 20 V to 85 V, TJ = - 40°C to 125°C,
typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CONTROL (EN, SAMPLE, GAIN)
VEN_H
VEN_L
REN
EN Logic high threshold
EN Logic low threshold
EN pull down resistor
1.2
V
V
0.4
800
kΩ
0.7 x
AVCC
VSAMPLE_H
VSAMPLE_L
VGAIN_H
Sample Logic high threshold
Sample Logic low threshold
Gain Logic high threshold
V
V
V
0.3 x
AVCC
0.7 x
AVCC
0.3 x
AVCC
VGAIN_L
Gain Logic low threshold
Output resistor
V
RGAIN_OUT
TIMING
tSS
5.5
kΩ
Soft start time
Ref voltage 0 to 1.2V
4.8
0.5
ms
µs
Delay time for high optical power
protection
tDELAY
IAPD = 5 mA, ISHORT = 3 mA
THERMAL PROTECTION
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
150
20
°C
°C
TSD_HYS
TJ falling below TSD
6
版权 © 2019, Texas Instruments Incorporated
TPS61390
www.ti.com.cn
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
6.6 Typical Characteristics
80
60
40
20
0
41
40.8
40.6
40.4
40.2
40
39.8
39.6
39.4
39.2
39
VOUT (V)
60
40
5E-6 1E-5 2E-5
0.0001 0.001
Output Current (A)
0.005
0
0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008
Output Current (A)
D001
D002
VIN = 3.3 V
L = 4. 7 µH
COUT = 0.1 µF
VIN = 3.3 V
L = 4. 7 µH
COUT = 0.1 µF
Output current
Output current
(boost) = 0 to 8 mA
(boost) = 0 to 8 mA
图 1. Efficiency vs. Output Current
图 2. Load regulation
1.201
1.2005
1.2
135
130
125
120
115
110
105
100
1.1995
1.199
1.1985
1.198
1.1975
1.197
-40oC
25oC
85oC
-40
-20
0
20
40
60
80
100 120 140
2.4 2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
Input voltage (V)
Temperature (èC)
D003
D004
VIN = 3.3 V
VOUT = 60 V
COUT = 0.1 µF
VOUT = 60 V
图 4. Quiescent current vs. Input voltage
图 3. Reference voltage
380
1200
1000
800
375
370
365
360
355
350
345
340
600
-40èC
25èC
85èC
VIN = 3.3 V
400
20 25 30 35 40 45 50 55 60 65 70 75 80 85
Output voltage (V)
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D005
D006
VIN = 3.3 V
图 5. Quiescent current vs. Output voltage
VIN = 3.3 V
VOUT = 60 V
图 6. Rdson vs. Temperature
版权 © 2019, Texas Instruments Incorporated
7
TPS61390
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
www.ti.com.cn
Typical Characteristics (接下页)
2.7
2.75
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.65
2.6
2.55
2.5
TJ (èC)
25
-40
Rising
Falling
85
2.45
-40
-20
0
20
40
60
80
100
120
0
200 400 600 800 1000 1200 1400 1600 1800 2000
APD current (mA)
Temperature (èC)
D007
D008
VOUT = 60 V
VIN = 3.3 V
VOUT = 60 V
图 7. Vin UVLO
图 8. Voltage drop of current mirror vs. current
860
810
760
710
660
2.5
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
MON resistor = 3.01 kohm
0.005 0.01 0.02 0.05 0.1 0.20.3 0.5
Output current (mA)
1
2
3 4 5678
0
200
400
600
800
1000 1200 1400
APD current (mA)
D009
D010
VIN = 3.3 V
VOUT = 60 V
VIN = 3.3 V
VOUT = 60 V
图 9. Switching frequency vs. Output current
图 10. VSP voltage vs. APD current
8
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TPS61390
www.ti.com.cn
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
7 Detailed Description
7.1 Overview
The TPS61390 is a fully integrated boost converter with an 85-V FET to convert a low input voltage to a higher
voltage for biasing the APD. The TPS61390 supports an input voltage ranging from 2.5 V to 5.5 V. The device
operates at a 700 kHz pulse-width modulation (PWM) crossing the whole load range.
The device can accurately mirror the APD current ranging from 0.5 uA to 2 mA. There are two ratio options for
the current proportional to APD current: the MON1 (4 : 5) and MON2 (1 : 5). By connecting a resistor from the
mirror output (MON1 or MON2) to GND, the current flowing through the APD is converted into the voltage
crossing the resistor from MON1 / MON2 to GND.
With the sample / hold circuitry built-in and triggered by an external sampling clock, the current mirror signal
(voltage) is transferred and stored on the holdup capacitor, the voltage on the holdup capacitor is then passed
over to the output of an operational amplifier. An external ADC can sense the voltage of the output of the
operational amplifier to measure the optical intensity.
Additionally, a high power optical protection is integrated by clamping the pre-set current limit (program by the
ISHORT resistor). The response time of the high optical power is typically 0.5 µs. The device could recovery
automatically when the high optical power is removed.
The device comes in a 3-mm × 3-mm QFN package with the operating junction temperature covering from –40°C
to 125°C.
版权 © 2019, Texas Instruments Incorporated
9
TPS61390
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
www.ti.com.cn
7.2 Functional Block Diagram
SW
VIN
EN
DRIVER
Control
MONIN
VREF
R
S
Q
FB
VCC
AVCC
ISHORT
ISHORT_REF
ISHORT_SEN
VSP
AVCC
CAP
GAIN
4:5
1:5
APD
AGND
Discharge
MON2
MON1
SAMPLE
GND
7.3 Feature Description
7.3.1 Undervoltage Lockout
An undervoltage lockout (UVLO) circuit stops the operation of the converter when the input voltage drops below
the typical UVLO threshold of 2.5 V. A hysteresis of 200 mV is added so that the device cannot be enabled again
until the input voltage goes up to 200 mV.
7.3.2 Enable and Disable
When the input voltage is above maximal UVLO rising threshold of 2.5 V and the EN pin is pulled above the high
threshold (1.2 V min.), the TPS61390 is enabled. When the EN pin is pulled below the low threshold (0.4
maximum), the device goes into shutdown mode.
10
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TPS61390
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ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
Feature Description (接下页)
7.3.3 Current Mirror
There are two current mirror options for TPS61390: the gain of 4: 5 (MON1) and 1: 5 (MON2). The maximum
voltage of MON1 and MON2 is 2.5 V.
7.3.4 Sample and Hold
The TPS61390 has the sample-and-hold circuitry built in, including a holdup capacitor for storing the voltage
capture, a FET switch, and one operational amplifier, illustrated in Functional Block Diagram.
To sample the current mirror signal, the switch connects the capacitor to the input of the common-mode
operational amplifier. The amplifier converts the voltage of the capacitor to the output terminal with 4:1 ratio.
In hold mode the switch disconnects the hold-up capacitor from the operation amplifier, the voltage of the
capacitor is discharged to 0 before connecting with current mirror output terminal (MON1 and MON2).
These are two ratios of the current mirror that can be selected automatically by comparing the MON1 voltage
with the internal 400-mV reference. The voltage of MON1 is sampled if the MON1 voltage is below 400 mV, while
the voltage of MON2 is sampled if MON1 being larger than 400 mV. The GAIN pin reports which ratio is selected
for the sample and hold, the logic low (0) for MON1 while logic high (AVCC) for MON2 selected.
Also, the GAIN can be externally selected, pulling low to select the 1 : 5 while high for 4 : 5 ratio.
The voltage measured on VSP pin is calculated by 公式 1 and 公式 2 :
VSP = 4´ 0.8´I
(
´RMON1 + 4´ I
(
´RMON1
)
)
APD
BIAS
where
•
•
•
•
VSP is the voltage sampled on VSP pin
IAPD is the current flowing through the APD pin.
RMON1 is the resistor connecting with MON1 pin
IBIAS is the bias current of current mirror
(1)
(2)
VSP = 4´ 0.2´I
(
´RMON2 + 4´ I
(
´RMON2
)
)
APD
BIAS
where
•
RMON2 is the resistor connecting with MON2 pin
The bias current is around 20 µA (typical) when there is no APD current flowing through. The bias voltage of
MON1 or MON2 is 60 mV given a 3-kΩ MON resistor connected with MON1 or MON2. Also, the VSP voltage is
reset to 250 mV prior to every sample clock coming. The maximum voltage of the MON1 is clamped to 400 mV
while maximum of MON2 is 2.5 V. The maximum voltage of VSP is close to the AVCC (0.1 V lower typically),
which is the supply voltage of the sample and hold circuitry.
As the timing diagram shown in 图 11, the sample and hold is enabled by the rising edge of an external clock
connecting to the SAMPLE pin, the holdup capacitor captures the voltage of current mirror signal (the voltage of
MON1 and MON2).
At the falling edge, the sampling is stopped, and the voltage stored on the holdup capacitor is transferred to the
output of the operational amplifier. The minimum time of the sampling time the TPS61390 supports is 350 ns
(typically). The voltage on the stored capacitor is switched to the amplifier’s input voltage. There is approximately
10-µs delay time to make the output voltage of the amplifier ready.
The GAIN selector is always active and the GAIN value is captured by the falling edge of the sample signal.
版权 © 2019, Texas Instruments Incorporated
11
TPS61390
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
www.ti.com.cn
Feature Description (接下页)
IAPD
MON1 / MON2
Sample time
Sample
Amplifier settling down
time 10 us (max.)
Sample Value Valid Time
(for ADC capture the voltage)
VSP
Gain
Gain Valid Time
图 11. TPS61390 Sample / Hold Circuit Timing
The output settling time of the operational amplifier is 10 µs while the maximum duration time is 100 µs with 1%
derating (with the nominal voltage).
7.3.5 High Optical Power Protection
There is an additional FET in series of power path connecting with the APD. When the current flowing through
the APD exceeds the short protection threshold (set by connecting the resistor from ISHORT to GND), the on
resistance of the FET becomes larger to clamp the current within the protection threshold by lowering the APD
bias voltage. It takes typically 0.5 µs for the FET to respond in case of high optical power occuring.
When the high optical power condition releases, the TPS61390 recovers automatically back to the normal
operation mode.
7.4 Device Functional Mode
7.4.1 PFM Operation
The TPS61390 integrates a power save mode with pulse frequency modulation (PFM) at the light load. When a
light load condition occurs, the COMP pin voltage naturally decreases and reduces the peak current. When the
COMP pin voltage further goes down with the load lowered and reaches the pre-set low threshold, the output of
the error amplifier is clamped at this threshold and does not go down any more. If the load is further lowered, the
device skips the switching cycles and reduces the switching losses and improves efficiency at the light load
condition by reducing the average switching frequency.
12
版权 © 2019, Texas Instruments Incorporated
TPS61390
www.ti.com.cn
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS61390 is a step-up DC/DC converter with current monitor and sample / hold circuitry integrated. The
following design procedure can be used to select component values for the TPS61390. This section presents a
simplified discussion of the design process.
8.2 Typical Application
This application is designed for 2.5-V to 5.5-V input, and 60-V output user case
Diode
L
VIN
VOUT
COUT1
RFILTER
RPROTECT
SW
MONIN
VIN
EN
ON
OFF
CFILTER
CAP
CCAP
RUP
VOUT_ADJ
FB
RSVCC
VIN
RADJ
AVCC
VSP
RDOWN
CAVCC
ISHORT
CAP
To ADC
RSHORT
4:5
1:5
GAIN
CCAP
AGND
APD
SAMPLE
MON2
MON1 GND
CAPD
CMON1
1:5
4:5
CMON2
RMON2
RMON1
TIA
图 12. TPS61390 Typical Application
8.2.1 Design Requirement
For this design example, use 表 1 as the design parameters.
表 1. Design Parameters
PARAMETER
Input voltage range
Output voltage
VALUE
2.5 V to 5.5 V
60 V
Operating frequency
APD Current
700 kHz
0 to 2 mA
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13
TPS61390
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Selecting the Rectifier Diode
A Schottky diode is the preferred type for the rectifier diode due to its low forward voltage drop and small reverse
recovery charge. Low reverse leakage current is important parameter when selecting the Schottky diode. The
diode must be rated to handle the maximum output voltage plus the switching node ringing. Also, it must be able
to handle the average output current.
8.2.2.2 Selecting the Inductor
It is suggested that the TPS61390 device works in the DCM operation; otherwise the output voltage would not be
delivered for low input voltage to high output voltage.
With the device working in DCM operation, the maximum inductor could be calculated by equation 公式 3 and 公
式 4:
VIN ´ D
LMAX
=
fSW ´ILIM
where
•
•
•
•
VIN is input voltage
D is duty cycle
fSW is switching frequency
ILIM is current limit
(3)
For instance, if VIN = 3.3 V, VOUT = 60 V, fSW = 600 kHz, ILIM = 0.8 A, the LMAX = 6.5 µH
However, there is minimum inductance is determined by the power delivered to the output side at given input
condition.
V
OUT ´ IOUT
LMIN = 2 ´
2
eff ´ fSW ´ ILIM
where
•
•
•
•
•
VOUT is output voltage
IOUT is output current
eff is the efficiency
fSW is switching frequency
ILIM is current limit
(4)
For instance, if IOUT = 8 mA, VOUT = 60 V, fSW = 600 kHz, ILIM = 0.8 A, eff = 0.6, the LMIN = 4.2 µH
With the calculation aforementioned, the operating inductor is recommended between the LMIN and LMAX
The 4.7 µH inductance is optimum value for using the TPS61390 in application.
.
8.2.2.3 Selecting Output Capacitor
Use low ESR capacitors at the output to minimize output voltage ripple. Use only X5R and X7R types, which
retain their capacitance over wider voltage and temperature ranges than other types. Typically use a 0.1-μF to 1-
μF capacitor for output voltage. Take care when evaluating the derating of a ceramic capacitor under the DC
bias. Ceramic capacitors can derate its capacitance at its rated voltage. Therefore, consider enough margins on
the voltage rating to ensure adequate capacitance at the required output voltage.
8.2.2.4 Selecting Filter Resistor and Capacitor
TI recommends an additional R-C filter be added for low ripple applications. The filter parameters is
characterized based on the ripple requirement. Typically, use a 100-Ω and 0.1-µF filter to reduce the switching
output ripple.
8.2.2.5 Setting the Output Voltage
The output voltage of the TPS61390 is externally adjustable using a resistor divider network. The relationship
between the output voltage and the resistor divider is given by 公式 5.
14
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TPS61390
www.ti.com.cn
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
RUP
VOUT = VFB ´ (1+
)
RDOWN
where
•
•
•
VOUT is the output voltage
RUP the top divider resistor
RDOWN is the bottom divider resistor
(5)
Choose RDOWN to be approximately 10 kΩ. Slightly increasing or decreasing RDOWN can result in closer output
voltage matching when using standard value resistors. In this design, RDOWN = 10 kΩ and RUP = 487 kΩ,
resulting in an output voltage of 60 V.
8.2.2.6 Selecting Sample Window
A pulse signal is connected with SAMPLE pin; the minimum window is 350 ns while the frequency of the pulse is
lower than 100 kHz.
8.2.2.7 Selecting Capacitor for CAP pin
TI recommends placing a ceramic capacitor from CAP pin to GND to lower the noise for the APD current mirror.
A ceramic capacitor between 10 nF and 100 nF is recommended from CAP pin to GND.
8.2.2.8 Selecting Capacitor for AVCC pin
The control circuitry is powered by AVCC. A ceramic capacitor must be placed close to AVCC, with a typical
capacitor value of 2.2 µF.
8.2.2.9 Selecting Capacitor for APD pin
A ceramic capacitor is required to make the APD current mirror more accurately against the noise coupling. The
recommended values are from 100 pF to 470 pF.
8.2.2.10 Selecting the Resistors of MON1 or MON2
The TPS61390 provides two currents proportional to APD current on the MON pins, 4 : 5 and 1 : 5. The voltage
of the resistors connecting to the MON pins convert the APD current to voltage. The relation between APD
current and the voltage on MON 1 or MON 2 pins is shown in 公式 1 and 公式 2 .
The resistor value depends on the VSP pin voltage. While RC time constant of MON 1 and MON 2 is
recommended to be 1/10 of the sample window time.
8.2.2.11 Selecting the Capacitors of MON1 or MON2
The capacitors are added to the MON1 or MON2 pins to decouple the noise of APD transient current. Suggested
RC time (formed by the MON1 or MON2 is 1/10 with that of the sample window. With 3-kΩ RMON resistance, TI
recommends a 10-pF capacitor connecting MON1 or MON2 pins to make sure the voltage on MON1 or MON2 is
stable before sample signal coming.
It is recommended that RC time constant of MON 1 and MON 2 is around 1/10 of the sample window time.
8.2.2.12 Selecting the Resistor of Gain pin
The GAIN pin can be configured as both input and output. If the GAIN pin is configured as output pin, TI
recommends that it be directly connected with the external I/O.
If the pin is configured as the input pin to select the current mirror ratio, the pull up or pull down resistor must be
lower than 1-kΩ as there is an internal 5-kΩ resistor on the GAIN pin.
8.2.2.13 Selecting the Short Current Limit
The output current short-protection threshold of the TPS61390 can be programmed by an external resistor with
公式 6 .The short protection threshold is calculated by 公式 1 and 公式 2:
100
ISHORT =
RSHORT
版权 © 2019, Texas Instruments Incorporated
15
TPS61390
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
www.ti.com.cn
where
•
•
ISHORT (mA) is the short protection threshold
RSHORT(kΩ) is the resistor connecting from ISHORT pin to GND
(6)
For instance, if RSHORT = 25 kΩ, the ISHORT = 4 mA.
8.2.3 Application Curves
Typical condition VIN = 3.3 V, VOUT = 60 V, RSHORT = 5 kΩ, RMON1/2 = 3.01 kΩ and CMON1/2 = 10 pF.
Application waveforms are measured with the inductor 4.7 µH and the output capacitance 0.1 µF at room
temperature.
CH3: Sample,
2.0 V / DIV
CH2: MON2,
2.0 V / DIV
CH3: APD
current control
Low-0, High-4mA
CH1: APD current control
(High-5uA; Low-1mA)
CH1: Sample,
1.0 V / DIV
CH2: VSP,
2.0 V / DIV
Time 100 ns / DIV
Time 100 ns / DIV
VIN = 3.3 V
VOUT = 60 V APD current = 1mA
VIN = 3.3 V
VOUT = 60 V
APD current = 0 to
4 mA transient
to 5 µA transient
图 13. APD current transient
图 14. High optical current protection
CH1: VMONIN_ripple (AC)
20 mv / DIV
CH2: Sample
1.0 V / DIV
CH4: Inductor current,
500 mA / DIV
CH1: MON1
1.0 V / DIV
Time 1 us / DIV
Time 100 ns / DIV
VIN = 3.3 V
VOUT = 60 V
APD current = 1
mA
VIN = 3.3 V
VOUT = 60 V
APD current = 1
mA
图 15. Output voltage ripple with 100 Ω / 0.1 µF filter
图 16. MON 1 settling time
16
版权 © 2019, Texas Instruments Incorporated
TPS61390
www.ti.com.cn
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
CH2: EN
2.0 V / DIV
CH3: VOUT
20 V / DIV
CH4: Inductor current
500 mA / DIV
Time 2ms / DIV
VIN = 3.3 V
VOUT = 60 V
图 17. Startup
APD current = 1mA
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.5 V and 5.5 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the device, the bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value
of 47 µF is a typical choice.
版权 © 2019, Texas Instruments Incorporated
17
TPS61390
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
The basic PCB board layout requires a separation of sensitive signal and power paths. If the layout is not
carefully done, the regulator could suffer from the instability or noise problems. Use the following checklist to get
good performance for a well-designed board:
•
Minimize the high current path including the switch FET, rectifier FET, and the output capacitor. This loop
contains high di / dt switching currents (nano seconds per ampere) and easy to transduce the high frequency
noise;
•
•
Place the noise sensitive network like sample hold and current mirror output (MON1, MON2) being far away
from the SW trace;
Split the ground for the power GND, signal GND. Use a separate ground trace to connect the sample/hold
and boost circuitry. Connect this ground trace to the main power ground at a single point to minimize
circulating currents.
10.2 Layout Example
GND
AGND
C
R
R
VSP
FB
R
ISHORT
VIN
GAIN
C
C
GND
MON2
R
MON1
CAP
R
AGND
SW
VIN
L
D
APD
C
R
C
GND
TIA
VOUT
图 18. Layout Example
18
版权 © 2019, Texas Instruments Incorporated
TPS61390
www.ti.com.cn
ZHCSJN0B –APRIL 2019–REVISED OCTOBER 2019
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61390RTER
TPS61390RTET
ACTIVE
ACTIVE
WQFN
WQFN
RTE
RTE
16
16
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
1XQH
1XQH
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS61390RTER
TPS61390RTET
WQFN
WQFN
RTE
RTE
16
16
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS61390RTER
TPS61390RTET
WQFN
WQFN
RTE
RTE
16
16
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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