TPS61169 [TI]
TPS61169 38V 高电流升压 WLED 驱动器;型号: | TPS61169 |
厂家: | TEXAS INSTRUMENTS |
描述: | TPS61169 38V 高电流升压 WLED 驱动器 驱动 驱动器 |
文件: | 总22页 (文件大小:882K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS61169
ZHCSD24 –OCTOBER 2014
TPS61169 采用 PWM 控制的 38V 高电流
升压 WLED 驱动器
1 特性
3 说明
1
•
•
2.7V 至 5.5V 输入电压
TPS61169 是一款升压转换器,配有额定电压为 40V
的集成开关场效应晶体管 (FET),可驱动 LED 串。 该
升压转换器内部具有一个 40V、1.8A 金属氧化物半导
体场效应晶体管 (MOSFET),电流下限为 1.2A,可针
对小型或大型面板背光照明驱动单个 LED 或 LED
串。 默认的白色 LED 电流通过外部传感器电阻 RSET
设定,反馈电压稳压至 204mV,如简化电路原理图 所
示。 运行期间,LED 电流可通过施加到 CTRL 引脚上
的脉宽调制 (PWM) 信号加以控制,该信号的占空比决
定反馈基准电压。 TPS61169 不会突发 LED 电流,因
此不会在输出电容器上产生可闻噪声。 为提供最佳保
护,该器件集成了 LED 开路保护特性,该特性会在
LED 开路状态下禁用 TPS61169,以防止输出电压超
过 IC 最大绝对额定电压。
集成 40V、1.8A 金属氧化物半导体场效应晶体管
(MOSFET)
•
•
•
•
•
•
•
•
•
•
•
高达 38V 的 LED 串驱动电压
1.2A 开关电流下限
1.2MHz 开关频率
204mV 基准电压
内部补偿
PWM 亮度控制
LED 开路保护
欠压保护
内置软启动
热关断
效率高达 90%
TPS61169 采用节省空间的 5 引脚 SC70 封装。
2 应用
器件信息(1)
•
•
•
•
•
智能手机背光照明
平板电脑背光照明
器件型号
TPS61169
封装
封装尺寸(标称值)
SOT (5)
2.00mm × 1.25mm
PDA、掌上电脑、GPS 接收器
便携式媒体播放器,便携式电视
针对小尺寸媒体播放器的白色 LED 背光照明
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
4 简化电路原理图
L
D
VBAT
CIN
TPS61169
COUT
VIN
SW
FB
CTRL
GND
PWM DIMMING
CONTROL
RSET
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SNVSA40
TPS61169
ZHCSD24 –OCTOBER 2014
www.ti.com.cn
目录
8.3 Feature Description .................................................. 8
8.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application .................................................. 11
9.3 TPS61169 Application Curves ................................ 13
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings ...................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 8
9
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 器件和文档支持 ..................................................... 17
12.1 第三方产品免责声明.............................................. 17
12.2 商标....................................................................... 17
12.3 静电放电警告......................................................... 17
12.4 术语表 ................................................................... 17
13 机械封装和可订购信息 .......................................... 17
8
5 修订历史记录
日期
修订版本
注释
2014 年 10 月
*
最初发布版本
2
Copyright © 2014, Texas Instruments Incorporated
TPS61169
www.ti.com.cn
ZHCSD24 –OCTOBER 2014
6 Pin Configuration and Functions
SC70 (DCK) Package
5 Pins
(Top View)
SW
GND
FB
1
2
3
5
VIN
4
CTRL
Pin Functions
PIN
I/O
DESCRIPTION
NAME
SW
NO.
1
I
O
I
Drain connection of the internal power FET.
Ground
GND
FB
2
3
Feedback pin for current. Connect the sense resistor from FB to GND.
PWM dimming signal input
CTRL
VIN
4
I
5
I
Supply input pin
Copyright © 2014, Texas Instruments Incorporated
3
TPS61169
ZHCSD24 –OCTOBER 2014
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
MAX
7
UNIT
Voltage(2)
VIN, CTRL, PWM, FB
SW
V
40
PD
TJ
Continuous power dissipation
See Thermal Information
Table
Operating junction temperature
–40
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
7.2 Handling Ratings
MIN
–65
MAX
150
UNIT
Tstg
Storage temperature range
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
–2000
2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
–500
500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
2.7
VIN
4.7
1
NOM
MAX
UNIT
V
VIN
VOUT
L
Input voltage
5.5
38
10
Output voltage
V
Inductor
µH
µF
µF
kHz
CI
Input capacitor
CO
Output capacitor
1
10
100
FPWM
DPWM
TJ
PWM dimming signal frequency
PWM dimming signal duty cycle
Operating junction temperature
5
1%
–40
100%
125
°C
4
Copyright © 2014, Texas Instruments Incorporated
TPS61169
www.ti.com.cn
ZHCSD24 –OCTOBER 2014
7.4 Thermal Information
TPS61169
THERMAL METRIC(1)
DCK
(5 PINS)
263.8
76.1
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
51.4
°C/W
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
1.1
ψJB
50.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining R θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
7.5 Electrical Characteristics
Over operating free-air temperature range, VIN = 3.6 V, CTRL = VIN (unless otherwise specified).
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage range
2.7
5.5
V
V
VVIN_UVLO
Undervoltage lockout threshold
VIN falling
VIN rising
2
2.3
2.6
VVIN_HYS
IQ_VIN
VIN UVLO hysteresis
200
0.3
mV
mA
Operating quiescent current into
VIN
Device enable, switching 1.2 MHz
and no load,
0.45
2
ISD
Shutdown current
CTRL = GND
1
µA
CONTROL LOGIC AND TIMING
VH
CTRL Logic high voltage
CTRL Logic Low voltage
1.2
V
V
VL
0.4
RPD
CTRL pin internal pull-down
resistor
300
204
KΩ
tSD
CTRL logic low time to shutdown
CTRL high to low
2.5
ms
VOLTAGE AND CURRENT REGULATION
VREF
Voltage feedback regulation
voltage
Duty = 100%, TA ≥ 25ºC
188
220
2.5
mV
IFB
FB pin bias current
VFB = 204 mV
µA
ms
tREF
VREF filter time constant
1
POWER SWITCH
RDS(ON) N-channel MOSFET on-resistance
ILN_NFET N-channel leakage current
SWITCHING FREQUENCY
0.35
0.7
1
Ω
VSW = 35 V
µA
fSW
Switching frequency
VIN = 3 V
0.75
1.2
1.2
1.5
2.4
MHz
PROTECTION AND SOFT START
ILIM
Switching MOSFET current limit
D = DMAX , TA ≤ 85ºC
1.8
A
ILIM_Start
Switching MOSFET start-up
current limit
TA ≤ 85ºC
0.72
tHalf_LIM
Time step for half current limit
6.5
ms
Copyright © 2014, Texas Instruments Incorporated
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TPS61169
ZHCSD24 –OCTOBER 2014
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Electrical Characteristics (continued)
Over operating free-air temperature range, VIN = 3.6 V, CTRL = VIN (unless otherwise specified).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOVP_SW
Output voltage overvoltage
threshold
36
37.5
39
V
THERMAL SHUTDOWN
Tshutdown Thermal shutdown threshold
Thys Thermal shutdown hysteresis
160
15
°C
°C
7.6 Typical Characteristics
At TA = 25°C, unless otherwise noted.
250
200
150
100
50
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0
0
10
20
30
40
50
60
70
80
90 100
-60
-40
-20
0
20
40
60
80
100 120
Dimming Duty Cycle (%)
Temperature (°C)
D001
D002
Figure 1. FB Voltage vs Dimming Duty Cycle
Figure 2. Current Limit vs Temperature
6
Copyright © 2014, Texas Instruments Incorporated
TPS61169
www.ti.com.cn
ZHCSD24 –OCTOBER 2014
8 Detailed Description
8.1 Overview
The TPS61169 is a high-efficiency, high-output voltage boost converter in small package size. The device
integrates 40-V/1.8-A switch FET and is designed for output voltage up to 39 V with a switch peak current limit of
1.2 A minimum. Its large driving capability can drive single or parallel LED strings for small to large size panel
backlighting.
The TPS61169 operates in a current mode scheme with quasi-constant frequency. It is internally compensated
for maximum flexibility and stability. The switching frequency is 1.2 MHz, and the minimum input voltage is 2.7 V.
During the on-time, the current rises into the inductor. When the current reaches a threshold value set by the
internal GM amplifier, the power switch MOSFET is turned off. The polarity of the inductor changes and forward
biases the schottky diode which lets the current flow towards the output of the boost converter. The off-time is
fixed for a certain VIN and VOUT, and therefore maintains the same frequency when varying these parameters.
However, for different output loads, the frequency slightly changes due to the voltage drop across the RDS(ON)
of the power switch MOSFET, this has an effect on the voltage across the inductor and thus on tON (tOFF remains
fixed). The fixed off-time maintains a quasi-fixed frequency that provides better stability for the system over a
wider range of input and output voltages than conventional boost converters. The TPS61169 topology has also
the benefits of providing very good load and line regulations, and excellent line and load transient responses.
The feedback loop regulates the FB pin to a low reference voltage (204 mV typical), reducing the power
dissipation in the current sense resistor.
Copyright © 2014, Texas Instruments Incorporated
7
TPS61169
ZHCSD24 –OCTOBER 2014
www.ti.com.cn
8.2 Functional Block Diagram
L
D
VBAT
VOUT
COUT
CIN
SW
VIN
UVLO
OVP
Current Limit and
Soft Start
TOFF
Generator
Ton
PWM
Gate Driver of
Generator
Power MOSFET
FB
GM Amplifier
VREF
RSET
CTRL
PWM Dimming
Reference Control
Shutdown
GND
8.3 Feature Description
8.3.1 Soft Start-Up
Soft-start circuitry is integrated into the IC to avoid high inrush current spike during start-up. After the device is
enabled, the GM amplifier output voltage ramps up very slowly, which ensures that the output voltage rises
slowly to reduce the input current. During this period, the switch current limit is set to 0.72 A. After around 6.5
ms, the switch current limit changes back to ILIM, and the FB pin voltage ramps up to the reference voltage
slowly. These features ensure the smooth start-up and minimize the inrush current. See Figure 12 for a typical
example.
8.3.2 Open LED Protection
Open LED protection circuitry prevents IC damage as the result of white LED disconnection. The TPS61169
monitors the voltage at the SW pin and FB pin during each switching cycle. The circuitry turns off the switch FET
and shuts down the IC when both of the following conditions persist for 3 switching cycles: (1) the SW voltage
exceeds the VOVP threshold, and (2) the FB voltage is less than 30 mV. As the result, the output voltage falls to
the level of the input supply. The device remains in shutdown mode until it is enabled by toggling the CTRL pin.
8
Copyright © 2014, Texas Instruments Incorporated
TPS61169
www.ti.com.cn
ZHCSD24 –OCTOBER 2014
Feature Description (continued)
8.3.3 Shutdown
The TPS61169 enters shutdown mode when the CTRL voltage is logic low for more than 2.5 ms. During
shutdown, the input supply current for the device is less than 2 μA (max). Although the internal switch FET does
not switch in shutdown, there is still a DC current path between the input and the LEDs through the inductor and
Schottky diode. The minimum forward voltage of the LED array must exceed the maximum input voltage to
ensure that the LEDs remain off in shutdown.
8.3.4 Current Program
The FB voltage is regulated by a low 204-mV reference voltage. The LED current is programmed externally using
a current-sense resistor in series with the LED string(s). The value of the RSET is calculated using:
VFB
ILED
RSET
where
•
•
•
ILED = total output current of LED string(s)
VFB = regulated voltage of FB pin
RSET = current sense resistor
(1)
The output current tolerance depends on the FB accuracy and the current sensor resistor accuracy.
8.3.5 LED Brightness Dimming
The TPS61169 receives PWM dimming signal at CTRL pin to control the total output current. When the CTRL
pin is constantly high, the FB voltage is regulated to 204 mV typically. When the duty cycle of the input PWM
signal is low, the regulation voltage at FB pin is reduced, and the total output current is reduced; therefore, it
achieves LED brightness dimming. The relationship between the duty cycle and FB regulation voltage is given
by:
VFB Duty u 204 mV
where
•
•
Duty = Duty cycle of the PWM signal
204 mV = internal reference voltage
(2)
Thus, the user can easily control the WLED brightness by controlling the duty cycle of the PWM signal.
As shown in Figure 3, the IC chops up the internal 204-mV reference voltage at the duty cycle of the PWM
signal. The pulse signal is then filtered by an internal low-pass filter. The output of the filter is connected to the
GM amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for
brightness dimming, only the WLED DC current is modulated, which is often referred as analog dimming. This
eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and
duty cycle of PWM control. Unlike other methods which filter the PWM signal for analog dimming, TPS61169
regulation voltage is independent of the PWM logic voltage level which often has large variations.
For optimum performance, use the PWM dimming frequency in the range of 5 kHz to 100 kHz. If the PWM
frequency is lower than 5 kHz, it is out of the low pass filter's filter range, the FB regulation voltage ripple
becomes large, causing large output ripple and may generate audible noise.
Copyright © 2014, Texas Instruments Incorporated
9
TPS61169
ZHCSD24 –OCTOBER 2014
www.ti.com.cn
Feature Description (continued)
VBG
204 mV
CTRL
VREF
EA Output
FB
GM
Amplifier
Figure 3. Programmable FB Voltage Using PWM Signal
8.3.6 Undervoltage Lockout
An undervoltage lockout prevents operation of the device at input voltages below typical 2 V. When the input
voltage is below the undervoltage threshold, the device is shut down, and the internal switch FET is turned off. If
the input voltage rises by undervoltage lockout hysteresis, the IC restarts.
8.3.7 Thermal Foldback and Thermal Shutdown
When TPS61169 drives heavy load for large size panel applications, the power dissipation increases a lot and
the device junction temperature may reach a very high value, affecting the device function and reliability. In order
to lower the thermal stress, the TPS61169 features a thermal foldback function. When the junction temperature is
higher than 100°C, the switch current limit ILIM is reduced automatically as Figure 2 shows. This thermal foldback
mechanism controls the power dissipation and keeps the junction temperature from rising to a very high value. If
the typical junction temperature of 160°C is exceeded, an internal thermal shutdown turns off the device. The
device is released from shutdown automatically when the junction temperature decreases by 15°C.
8.4 Device Functional Modes
8.4.1 Operation With CTRL
The enable rising edge threshold voltage is 1.2 V. With the CTRL terminal is held below that voltage the device
is disabled and switching is inhibited. The IC quiescent current is reduced in this state. When input voltage is
above the UVLO threshold, and the CTRL terminal voltage is increased above the rising edge threshold, the
device becomes active. Switching enables, and the soft-start sequence initiates.
10
Copyright © 2014, Texas Instruments Incorporated
TPS61169
www.ti.com.cn
ZHCSD24 –OCTOBER 2014
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS61169 device is a step-up DC-DC converter which can drive single or parallel LED strings for small- to
large-size panel backlighting. This section includes a design procedure (Detailed Design Procedure) to select
component values for the TPS61169 typical application (Figure 4).
9.2 Typical Application
L
2.7 V to 5.5 V
VBAT
4.7 µH
D
10s1p
CIN
4.7 µF
COUT
1 µF
TPS61169
VIN
SW
FB
CTRL
GND
PWM DIMMING
CONTROL
RSET
10.2 ꢀ
Figure 4. TPS61169 2.7-V to 5.5-V Input, 10 LEDs in Series Output Converter
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
2.7 V to 5.5 V
Output, LED number in a string
Output, LED string number
Output, LED current per string
10
1
20 mA
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The selection of the inductor affects power efficiency, steady state operation as well as transient behavior and
loop stability. These factors make it the most important component in power regulator design. There are three
important inductor specifications, inductor value, DC resistance and saturation current. Considering inductor
value alone is not enough. The inductor value determines the inductor ripple current. Choose an inductor that
can handle the necessary peak current without saturating. Follow Equation 3 to Equation 4 to calculate the
inductor's peak current. To calculate the current in the worst case, use the minimum input voltage, maximum
output voltage and maximum load current of application. In a boost regulator, the input DC current can be
calculated as Equation 3.
Copyright © 2014, Texas Instruments Incorporated
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TPS61169
ZHCSD24 –OCTOBER 2014
www.ti.com.cn
VOUT uIOUT
IL(DC)
V u K
IN
where
•
•
•
•
VOUT = boost output voltage
IOUT = boost output current
VIN = boost input voltage
η = power conversion efficiency
(3)
The inductor current peak to peak ripple can be calculated as Equation 4.
1
'IL(PꢀP)
1
1
L u(
ꢁ
)uFS
VOUT ꢀ V
V
IN
IN
where
•
•
•
•
•
ΔIL(PP) = inductor peak-to-peak ripple
L = inductor value
FS = boost switching frequency
VOUT = boost output voltage
VIN = boost input voltage
(4)
(5)
Therefore, the peak current IL(P) seen by the inductor is calculated with Equation 5.
'IL(PꢀP)
IL(P) IL(DC)
ꢁ
2
Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation
level, its inductance can decrease 20% to 35% from the 0-A value depending on how the inductor vendor defines
saturation current. Using an inductor with a smaller inductance value forces discontinuous PWM when the
inductor current ramps down to zero before the end of each switching cycle. This reduces the boost converter’s
maximum output current, causes large input voltage ripple and reduces efficiency. Large inductance value
provides much more output current and higher conversion efficiency. For these reasons, a 4.7-μH to 10-μH
inductor value range is recommended, and 4.7-μH inductor is recommended for higher than 5-V input voltage by
considering inductor peak current and loop stability. Table 2 lists the recommended inductor for the TPS61169.
Table 2. Recommended Inductors for TPS61169
SATURATION
CURRENT (A)
SIZE (L x W x H
mm)
PART NUMBER
L (µH)
DCR MAX (mΩ)
VENDOR
LPS4018-472ML
LPS4018-103ML
PCMB051H-4R7M
PCMB051H-100M
4.7
10
125
200
85
1.9
1.3
4
4 x 4 x 1.8
4 x 4 x 1.8
Coilcraft
Coilcraft
Cyntec
Cyntec
4.7
10
5.4 x 5.2 x 1.8
5.4 x 5.2x 1.8
155
3
9.2.2.2 Schottky Diode Selection
The TPS61169 demands a low forward voltage, high-speed and low capacitance Schottky diode for optimum
efficiency. Ensure that the diode average and peak current rating exceeds the average output current and peak
inductor current. In addition, the diode reverse breakdown voltage must exceed the open LED protection voltage.
ONSemi NSR0240 is recommended for the TPS61169.
9.2.2.3 Output Capacitor Selection
The output capacitor is mainly selected to meet the requirement for the output ripple and loop stability. This ripple
voltage is related to capacitor capacitance and its equivalent series resistance (ESR). Assuming a capacitor with
zero ESR, the minimum capacitance needed for a given ripple can be calculated with Equation 6:
(VOUT ꢀ V )uIOUT
IN
COUT
VOUT uFS u V
ripple
12
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TPS61169
www.ti.com.cn
ZHCSD24 –OCTOBER 2014
where
•
Vripple = peak-to-peak output ripple
(6)
The additional part of the ripple caused by ESR is calculated using: Vripple_ESR = IOUT × RESR
Due to its low ESR, Vripple_ESR could be neglected for ceramic capacitors, a 1-µF to 4.7-µF capacitor is
recommended for typical application.
9.2.2.4 LED Current Set Resistor
The LED current set resistor can be calculated by Equation 1.
9.2.2.5 Thermal Considerations
The allowable IC junction temperature should be considered under normal operating conditions. This restriction
limits the power dissipation of the TPS61169. The allowable power dissipation for the device can be determined
by Equation 7:
TJ - TA
PD
RTJA
where
•
•
•
TJ is allowable junction temperature given in recommended operating conditions
TA is the ambient temperature for the application
RθJA is the thermal resistance junction-to-ambient given in Power Dissipation Table
(7)
The TPS61169 device also features a thermal foldback function to reduce the thermal stress automatically.
9.3 TPS61169 Application Curves
Typical application condition is as in Figure 4, VIN = 3.6 V, RSET=10.2 Ω, L = 4.7 µH, COUT = 1 µF, 10 LEDs in series (unless
otherwise specified).
100
90
80
70
60
50
100
90
80
70
60
50
10 LEDs in series
6 LEDs in series
Vin = 3.0 V
Vin = 3.6 V
Vin = 4.2 V
Vin = 5.0 V
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Dimming Duty Cycle (%)
Dimming Duty Cycle (%)
D003
D004
10 LEDs in series
Figure 5. Efficiency vs Dimming Duty Cycle
Figure 6. Efficiency vs Dimming Duty Cycle
Copyright © 2014, Texas Instruments Incorporated
13
TPS61169
ZHCSD24 –OCTOBER 2014
www.ti.com.cn
TPS61169 Application Curves (continued)
Typical application condition is as in Figure 4, VIN = 3.6 V, RSET=10.2 Ω, L = 4.7 µH, COUT = 1 µF, 10 LEDs in series (unless
otherwise specified).
100
90
80
70
60
50
100
90
80
70
60
50
Vin = 3.0 V
Vin = 3.6 V
Vin = 4.2 V
Vin = 5.0 V
Vin = 3.0 V
Vin = 3.6 V
Vin = 4.2 V
Vin = 5.0 V
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Dimming Duty Cycle (%)
Dimming Duty Cycle (%)
D005
D006
8 LEDs in series
6 LEDs in series
Figure 7. Efficiency vs Dimming Duty Cycle
Figure 8. Efficiency vs Dimming Duty Cycle
SW (20 V/DIV)
SW (20 V/DIV)
VOUT (100 mV/DIV, AC coupled)
IInductor (500 mA/DIV)
VOUT (100 mV/DIV, AC coupled)
IInductor (500 mA/DIV)
ILED (9 mA/DIV)
ILED (9 mA/DIV)
Time = 1 µs/DIV
Time = 1 µs/DIV
Figure 9. Switching-Dimming Duty = 100%
Figure 10. Switching-Dimming Duty = 50%
SW (20 V/DIV)
PWM
(2 V/DIV)
VOUT (100 mV/DIV, AC coupled)
IInductor (500 mA/DIV)
IInductor
(300 mA/DIV)
VOUT (20 V/DIV)
ILED (9 mA/DIV)
ILED (5 mA/DIV)
Time = 2 µs/DIV
Time = 2 ms/DIV
Figure 11. Switching-Dimming Duty = 10%
Figure 12. Start-Up Dimming Duty = 100%
14
Copyright © 2014, Texas Instruments Incorporated
TPS61169
www.ti.com.cn
ZHCSD24 –OCTOBER 2014
TPS61169 Application Curves (continued)
Typical application condition is as in Figure 4, VIN = 3.6 V, RSET=10.2 Ω, L = 4.7 µH, COUT = 1 µF, 10 LEDs in series (unless
otherwise specified).
PWM (2 V/DIV)
PWM (2 V/DIV)
IInductor (300 mA/DIV)
IInductor
(300 mA/DIV)
VOUT (20 V/DIV)
ILED (9 mA/DIV)
VOUT (20 V/DIV)
ILED (9 mA/DIV)
Time = 2 ms/DIV
Time = 2 ms/DIV
Figure 13. Start-Up Dimming Duty = 50%
Figure 14. Shutdown Dimming Duty = 100%
PWM (2 V/DIV)
PWM (2 V/DIV)
VOUT (5 V/DIV, AC coupled)
IInductor (300 mA/DIV)
IInductor (300 mA/DIV)
VOUT (20 V/DIV)
ILED (9 mA/DIV)
ILED (9 mA/DIV)
Time = 2 ms/DIV
Duty = 50%
Time = 5 ms/DIV
Duty = 1%-100%-1%
Figure 15. Shutdown Dimming
Figure 16. Dimming Transient-Dimming
VFB (200 mV/DIV)
VOUT (20 V/DIV)
IInductor (600 mA/DIV)
ILED (9 mA/DIV)
Time = 50 µs/DIV
Figure 17. Open LED Protection
Copyright © 2014, Texas Instruments Incorporated
15
TPS61169
ZHCSD24 –OCTOBER 2014
www.ti.com.cn
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.7 V and 5.5 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the TPS61169 device,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
11 Layout
11.1 Layout Guidelines
As for all switching power supplies, especially those high frequency and high current ones, layout is an important
design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems.
Therefore, use wide and short traces for high current paths. The input capacitor CIN needs to be close to VIN pin
and GND pin in order to reduce the input ripple seen by the IC. If possible choose higher capacitance value for it.
The SW pin carries high current with fast rising and falling edge, therefore, the connection between the SW pin to
the inductor should be kept as short and wide as possible. The output capacitor COUT should be put close to
VOUT pin. It is also beneficial to have the ground of COUT close to the GND pin since there is large ground return
current flowing between them. FB resistor should be put close to FB pin. When laying out signal ground, it is
recommended to use short traces separated from power ground traces, and connect them together at a single
point close to the GND pin.
11.2 Layout Example
Bottom
GND
GND
Plane
VIN
GND
VOUT
Figure 18. TPS61169 Board Layout
16
版权 © 2014, Texas Instruments Incorporated
TPS61169
www.ti.com.cn
ZHCSD24 –OCTOBER 2014
12 器件和文档支持
12.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 商标
All trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2014, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
30-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS61169DCKR
ACTIVE
SC70
DCK
5
3000 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
SZL
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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