TPS566235 [TI]
采用 2mm x 3mm QFN 封装的 4.5V 至 18V、6A 同步降压转换器;
| 型号： | TPS566235 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2mm x 3mm QFN 封装的 4.5V 至 18V、6A 同步降压转换器 转换器 |
| 文件： | 总29页 (文件大小：1210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS566235
ZHCSJL9B –APRIL 2019–REVISED APRIL 2019
TPS566235 4.5V 至 18V 输入、6A 同步降压转换器
1 特性
3 说明
1
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输入电压范围：4.5V 至 18V
TPS566235 是一款具有成本效益、高电压输入、高效
的同步降压转换器，配备了集成 FET。该器件使系统
设计人员能够以经济高效、低组件数和低待机电流的解
决方案来完善包含各种终端设备电源总线稳压器的套
件。
输出电压范围：0.6V 至 7V
室温下的基准电压 ±1%
支持 6A 的连续输出电流
D-CAP3™架构控制，可实现快速瞬态响应
集成 25mΩ 和 12mΩ RDS(on) 电源 FET
108µA 低静态电流
TPS566235 采用 D-CAP3™模式控制，此控制方式无
需外部补偿组件即可实现快速瞬态响应和出色的线路/
负载调整。该器件具有一个专用电路，可支持低等效串
联电阻 (ESR) 输出电容器（例如专用聚合物电容器和
超低 ESR 陶瓷电容器）。控制拓扑可支持高负载条件
下的 CCM 模式与轻负载条件下的 DCM 运行模式之间
的无缝切换。在轻负载条件下，可通过 MODE 引脚配
置三种工作模式： Eco-Mode™、 Out-Of-Audio™
(OOA) 和强制连续导通模式 (FCCM)。OOA 模式是一
种独特的控制功能，可将开关频率保持在可闻频率以
上，同时可将对效率的影响降至最低。
可选 Eco-Mode™、 Out-Of-Audio™ 和 FCCM
（通过 MODE 引脚）
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•
•
•
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Out-Of-Audio™ 轻负载运行，开关频率超过 25kHz
支持预偏置启动功能
600kHz 开关频率
内部 1ms 软启动
支持陶瓷输出电容器
电源正常指示器
逐周期谷值过流保护功能
非闭锁，可提供 OC、OV、UV、OT 和 UVLO 保
护
TPS566235 支持预偏置启动和电源正常指示器。它提
供包括 OVP、UVP、OCP、OTP 和 UVLO 在内的全
面保护。该器件采用 3.0mm x 2.0mm HotRod™封
装，额定结温范围为 –40°C 至 125°C。
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3.0mm × 2.0mm HotRod™VQFN 封装
使用 TPS566235 并借助 WEBENCH® 电源设计器
创建定制设计方案
器件信息(1)
2 应用
器件型号
TPS566235
封装
VQFN (13)
封装尺寸（标称值）
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DTV 和 STB
3.00mm × 2.00mm
交换机和路由器
服务器和企业 SSD
监控和单板计算机
分布式电源系统
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
典型应用
效率与输出电流 Eco-mode
100
Vout
L
Vin
SW
VIN
EN
Cout
Cin
90
80
70
60
BST
TPS566235
FB
PG
VCC
MODE
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
50
40
AGND
PGND
0.001
0.01
0.1
I-Load (A)
1
10
D013
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEW1
TPS566235
ZHCSJL9B –APRIL 2019–REVISED APRIL 2019
www.ti.com.cn
目录
12.4 Device Functional Modes...................................... 12
13 Application and Implementation........................ 15
13.1 Application Information.......................................... 15
13.2 Typical Application ............................................... 15
14 Power Supply Recommendations ..................... 19
15 Layout................................................................... 20
15.1 Layout Guidelines ................................................. 20
15.2 Layout Example .................................................... 20
16 器件和文档支持 ..................................................... 21
16.1 器件支持 ............................................................... 21
16.2 接收文档更新通知 ................................................. 21
16.3 社区资源................................................................ 21
16.4 商标....................................................................... 21
16.5 静电放电警告......................................................... 21
16.6 术语表 ................................................................... 21
17 机械、封装和可订购信息....................................... 22
1
2
3
4
5
6
7
8
9
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
Absolute Maximum Ratings.................................. 4
ESD Ratings ........................................................... 4
Recommended Operating Conditions ................. 4
10 Thermal Information.............................................. 5
11 Electrical Characteristics ..................................... 5
11.1 Typical Characteristics............................................ 7
12 Detailed Description ........................................... 10
12.1 Overview ............................................................... 10
12.2 Functional Block Diagram ..................................... 10
12.3 Feature Description............................................... 11
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (April 2019) to Revision B
Page
•
已更改 将销售状态从“预告信息”更改为“初始发行版”。........................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
TPS566235
www.ti.com.cn
ZHCSJL9B –APRIL 2019–REVISED APRIL 2019
5 Pin Configuration and Functions
RJN Package
13-Pin VQFN
Top View
VCC
10
FB
AGND
PG
13
12
11
BST
9
VIN
1
8
7
SW
PGND
2
MODE
3
PGND
4
5
6
PGND
EN
PGND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VIN
NO.
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
PGND.
1
2,3,4,6
5
P
G
I
PGND
EN
Power GND terminal for the controller circuit and the internal circuitry.
Enable pin of Buck converter. EN pin is a digital input pin, decides turn on/off Buck converter. Internal pull
down current to disable converter if leave this pin open.
MODE
SW
7
8
I
Eco-Mode™/OOA/FCCM Mode selection pin with external 1% resistor or connecting to VCC.
Switching node connection to the output inductor and bootstrap capacitor.
O
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BST and SW, 0.1 uF is recommended.
BST
9
I
Internal LDO output for control and driver. Decouple with a minimum 1 μF ceramic capacitor as close to VCC
as possible.
VCC
AGND
FB
10
11
12
P
G
I
Ground of internal analog circuitry. Connect AGND to GND plane with a short trace.
Feedback sensing pin for Buck output voltage. Connect this pin to the resistor divider between output voltage
and AGND.
Open drain power good indicator. It is asserted low if output voltage is out of PG threshold, over voltage or if
the device is under thermal shutdown, EN shutdown or during soft start.
PG
13
O
Copyright © 2019, Texas Instruments Incorporated
3
TPS566235
ZHCSJL9B –APRIL 2019–REVISED APRIL 2019
www.ti.com.cn
6 Specifications
7 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–3.0
–0.3
–40
MAX
UNIT
V
VIN
20
6
BST – SW
V
Input voltage
BST
25
6
V
FB, EN, MODE
PGND, AGND
SW
V
0.3
20
22
6
V
V
Output voltage
SW (10-ns transient)
PG
V
V
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
9 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
UNIT
V
VIN
18
5.5
23
BST – SW
BST
–0.3
–0.3
–0.3
–0.3
–0.3
–3.0
–0.3
V
Input voltage
V
FB, EN, MODE
PGND, AGND
SW
5.5
0.3
18
V
V
V
Output voltage
SW(10 ns transient)
PG, VCC
20
V
5.5
6
V
IOUT
TJ
Output current(1)
A
Operating junction temperature
Storage temperature
–40
–40
125
150
°C
°C
Tstg
(1) In order to be consistent with the TI reliability requirement of 100k Power-On-Hours at 105°C junction temperature, the output current
should not exceed 6A continuously under 100% duty operation as to prevent electromigration failure in the solder. Higher junction
temperature or longer power-on hours are achievable at lower than 6A continuous output current.
4
Copyright © 2019, Texas Instruments Incorporated
TPS566235
www.ti.com.cn
ZHCSJL9B –APRIL 2019–REVISED APRIL 2019
10 Thermal Information
TPS566235
THERMAL METRIC(1)
RJN (VQFN)
13 PINS
70
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA_effective
RθJC(top)
RθJB
Junction-to-ambient thermal resistance with TI EVM
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
34.8
46.4
22.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.4
ψJB
22.4
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
11 Electrical Characteristics
Tj = -40°C to 125°C, VIN = 12 V, typical values are at Tj = 25°C (unless otherwise noted)
PARAMETER
INPUT SUPPLY VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input Voltage Range
VIN Supply Current
VIN Shutdown Current
4.5
18
V
IVIN
VEN = 3.3V,Non Switching
VEN = 0V
108
3
µA
µA
IVINSDN
VCC OUTPUT
VIN > 5.0V
4.75
4.3
20
4.83
4.5
4.92
V
V
VCC
IVCC
VCC Output Voltage
VCC Current Limit
VIN = 4.5, no Load
mA
FEEDBACK VOLTAGE
TJ = 25°C
594
591
600
600
606
609
mV
mV
VFB
VFB Voltage
TJ = -40 to 125°C
UVLO
Wake up VIN voltage
Shut down VIN voltage
Hysteresis VIN voltage
4.2
3.7
4.4
V
V
UVLO
VIN Under-Voltage Lockout
3.6
500
mV
LOGIC THRESHOLD
VEN(ON)
VEN(OFF)
IEN
EN Threshold High-level
1.22
1.04
1.32
1.12
2
1.42
1.20
V
V
EN Threshold Low-level
EN Pull Down Current
MODE Sourcing Current
VEN = 0.8V
µA
µA
IMODE
5
Copyright © 2019, Texas Instruments Incorporated
5
TPS566235
ZHCSJL9B –APRIL 2019–REVISED APRIL 2019
www.ti.com.cn
Electrical Characteristics (continued)
Tj = -40°C to 125°C, VIN = 12 V, typical values are at Tj = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOSFET
RDS(ON)H
RDS(ON)L
High Side MOSFET Rds(on)
Low Side MOSFET Rds(on)
25
12
mΩ
mΩ
DUTY CYCLE and FREQUENCY CONTROL
FSW
Switching Frequency
Minimum On-time
Minimum Off-time
600
50
kHz
ns
TMIN_ON
TMIN_OFF
OOA Function
TOOA
200
ns
Mode Operation Period
Soft Start Time
32
1
µs
SOFT START
TSS
ms
POWER GOOD
TPGDLYLH
TPGDLYHL
PG Low to High Delay
PG High to Low Delay
PG from low to high
160
32
µs
µs
%
PG from high to low
VFB falling (fault)
VFB rising (good)
VFB rising (fault)
VFB falling (good)
VPG = 0.5V
85
90
%
VPGTH
PG Threshold
115
110
52
%
%
IPGSK
IPGLK
PG Sink Current
PG Leak Current
mA
µA
VPG = 5.5V
1
CURRENT LIMIT
IOCL
Over Current Threshold
Negative Over Current Threshold
Valley current set point
6.6
7.6
3.4
8.6
A
A
INOCL
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VFB rising (fault)
VFB falling (good)
125
120
32
%
%
µs
%
%
µs
VOVP
OVP Trip Threshold
OVP Prop Deglitch
UVP Trip Threshold
UVP Prop Deglitch
tOVPDLY
VUVP
VFB falling (fault)
VFB rising (good)
60
65
tUVPDLY
256
THERMAL PROTECTION
TOTP
OTP Trip Threshold(1)
OTP Hysteresis(1)
150
20
°C
°C
TOTPHYS
(1) Not production tested
6
版权 © 2019, Texas Instruments Incorporated
TPS566235
www.ti.com.cn
ZHCSJL9B –APRIL 2019–REVISED APRIL 2019
11.1 Typical Characteristics
TJ=-40oC to 125oC, VIN=12V(unless otherwise noted)
140
130
120
110
100
90
5
4.5
4
3.5
3
2.5
2
80
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D002
D003
VEN = 5 V
VEN = 0 V
图 1. Supply Current vs Junction Temperature
图 2. Shutdown Current vs Temperature
615
1.44
1.4
610
605
600
595
590
585
1.36
1.32
1.28
1.24
1.2
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D004
D005
图 3. Feedback Voltage vs Junction Temperature
图 4. Enable On Voltage vs Junction Temperature
1.25
1.2
40
35
30
25
20
15
10
1.15
1.1
1.05
1
0.95
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D006
D007
图 5. Enable Off Voltage vs Junction Temperature
图 6. High-Side RDS(on) vs Junction Temperature
版权 © 2019, Texas Instruments Incorporated
7
TPS566235
ZHCSJL9B –APRIL 2019–REVISED APRIL 2019
www.ti.com.cn
Typical Characteristics (接下页)
TJ=-40oC to 125oC, VIN=12V(unless otherwise noted)
18
130
128
126
124
122
120
16
14
12
10
8
6
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D008
D009
图 7. Low-Side RDS(on) vs Junction Temperature
图 8. OVP Threshold vs Junction Temperature
8.2
8
62
61
60
59
58
57
56
7.8
7.6
7.4
7.2
7
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (èC)
Junction Temperature (èC)
D010
D011
图 9. UVP Threshold vs Junction Temperature
图 10. Valley Current Limit vs Junction Temperature
1.15
1.1
1.05
1
0.95
0.9
0.85
-50
-20
10
40
70
100
130
Junction Temperature (èC)
D012
图 11. Soft-Start Time vs Junction Temperature
8
版权 © 2019, Texas Instruments Incorporated
TPS566235
www.ti.com.cn
ZHCSJL9B –APRIL 2019–REVISED APRIL 2019
Typical Characteristics (接下页)
TJ=-40oC to 125oC, VIN=12V(unless otherwise noted)
100
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
50
40
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D013
D015
图 12. Efficiency, Eco-mode
图 13. Efficiency, OOA-mode
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
100
90
80
70
60
50
40
30
20
10
0
700
600
500
400
300
200
100
0
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D014
D023
图 14. Efficiency, FCCM
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
图 15. Switching Frequency vs Output Load, Eco-mode
800
700
600
500
400
300
200
100
0
700
600
500
400
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D017
D018
图 16. Switching Frequency vs Output Load, OOA-mode
图 17. Switching Frequency vs Output Load, FCCM
版权 © 2019, Texas Instruments Incorporated
9
TPS566235
ZHCSJL9B –APRIL 2019–REVISED APRIL 2019
www.ti.com.cn
12 Detailed Description
12.1 Overview
The TPS566235 is high density synchronous Buck converter which operates from 4.5 V to 18 V input voltage
(VIN), and the output range is from 0.6 V to 7 V. It has 25-mΩ and 12-mΩ integrated MOSFETs that enable high
efficiency up to 6 A. The proprietary D-CAP3™ mode enables low external component count, ease of design,
optimization of the power design for cost, size and efficiency. The TPS566235 has ultra-low quiescent current
(ULQ™) mode. This feature is beneficial for long battery life in system standby mode. The device employs D-
CAP3™ mode control that provides fast transient response with no external compensation components. The
control topology supports seamless transition between CCM mode at heavy load conditions and DCM operation
at light load conditions. There are three operation modes can be configured by MODE pin at light load: Eco-
Mode™, OOA and FCCM. Eco-Mode™ allows the TPS566235 to maintain high efficiency at light load. OOA
mode makes switching frequency above audible frequency (25kHz), even there is no loading at output side.
FCCM mode has the constant switching frequency at both light and heavy load. TPS566235 are able to adapt to
both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR
ceramic capacitors.
12.2 Functional Block Diagram
PG high
threshold
PG
+
UV threshold
OV threshold
+
UV
OV
Delay
+
PG low
threshold
+
VIN
+
LDO
4.2V /
3.7V
Internal SS
VCC
0.6 V
+
+
+
Control Logic
PWM
BST
VIN
FB
SS
+
Internal Ramp
ñ
ñ
ñ
ñ
ñ
ñ
On/Off time
Minimum On/Off
OVP/UVP/TSD
Eco-Mode/OOA/FCCM
Soft-Start
SW
Ripple injection
XCON
SW
PGOOD
One Shot
PGND
EN
+
+
OCL
EN Threshold
+
+
ZC
Eco-Mode/OOA/FCCM
MODE
NOCL
THOK
+
150°C /20°C
AGND
10
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TPS566235
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ZHCSJL9B –APRIL 2019–REVISED APRIL 2019
12.3 Feature Description
12.3.1 PWM Operation and D-CAP3™ Control
The main control loop of the Buck is adaptive on-time pulse width modulation (PWM) controller that supports a
proprietary D-CAP3™ mode control. The D-CAP3™ mode control combines adaptive on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The
TPS566235 also includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and it is inversely
proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for D-CAP3™ control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the TPS566235 is a low-pass L-C circuit. This L-C filter has a double-pole frequency
described in 公式 1.
1
fp =
2ìpì LOUTìCOUT
(1)
At low frequency, the overall loop gain is set by the output set-point resistor divider network and the internal gain
of the TPS566235. The low-frequency L-C double pole has a 180 degree drop in phase. At the output filter
frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and leads the 90 degree phase boost. The internal ripple injection high-frequency zero is related to the
switching frequency. The crossover frequency of the overall system should usually be targeted to be less than
one-third of the switching frequency (FSW).
12.3.2 Power Good
The Power Good (PG) pin is an open drain output. Once the FB pin voltage is between 90% and 110% of the
internal reference voltage (VREF=0.6V), the PG is de-asserted and floats after a 160 µs de-glitch time. A pull-up
resistor of 100 kΩ is recommended to pull it up to VCC. The PG pin is pulled low when the FB pin voltage is
lower than 85% or greater than 115% threshold or in an event of thermal shutdown or during the soft-start period.
PG de-glitch time (from high to low) is 32 µs.
12.3.3 Soft Start and Pre-Biased Soft Start
The TPS566235 has an internal 1.0 ms soft-start time. Soft start can prevent the overshoot of output voltage
during start up. When the EN pin becomes high, internal soft-start function begins ramping up the reference
voltage to the PWM comparator.
The TPS566235 can prevent current from being pulled from the output during startup if the output is pre-biased.
The device disables the switching of both the high-side and low-side FETs until the soft-start commands a
voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage VFB). Then, the
controller start the first high side FET gate driver pulses. This scheme prevents the initial sinking of the pre-bias
output, and ensure that the output voltage starts and ramps up into regulation and the control loop is given time
to transition from pre-biased start-up to normal mode operation.
12.3.4 Over current Protection and Undervoltage Protection
The TPS566235 has the over current protection and undervoltage protection. The output over current limit (OCL)
is implemented using a cycle-by-cycle valley detect circuit. The switch current is monitored during the OFF state
by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. To
improve accuracy, the voltage sensing is temperature compensated.
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Feature Description (接下页)
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over current protection. When the load current is higher
than the over current threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the current is being limited, the output voltage tends to drop because the load demand is higher than what the
converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it, the device will shut off after a wait time of 256 µs and then re-start after the hiccup time (typically
7xTss). When the over current condition is removed, the output will be recovered.
12.3.5 Over Voltage Protection
TPS566235 has the over voltage protection function by monitoring the feedback voltage (VFB). When the
feedback voltage becomes higher than 125% of VREF, the OVP comparator output goes high and turns off both
high-side and low-side MOSFETs after a wait time of 32 µs. This protection is a non-latching operation. The
device re-starts switching when the feedback voltage falls below 120% of VREF
.
12.3.6 UVLO Protection
The undervoltage lockout (UVLO) protection monitors the VCC pin voltage to protect the internal circuitry from
low input voltages. When the voltage is lower than UVLO threshold voltage, the under-voltage lockout circuit
prevents mis-operation of the device by turning off both high-side and low-side MOSFETs. The converter begins
operation again when the input voltage exceeds the threshold by a hysteresis of 500 mV (typical).This is a non-
latch protection.
12.3.7 Thermal Shutdown
The device monitors the internal die temperature. If it exceeds the thermal shutdown threshold value (typically
150°C), the device shuts off. This is a non-latch protection.
12.4 Device Functional Modes
12.4.1 Light Load Operation
TPS566235 has a MODE pin which can setup three different modes of operation for light load running. The light
load operation mode includes Eco-Mode™, Out-Of-Audio™ mode and FCCM mode.
12.4.2 MODE Pin Configuration
TPS566235 detect the voltage on the MODE pin during start-up and latches onto one of the MODE options listed
below in 表 1. TPS566235 internally has a comparator to compare this voltage with reference voltage and decide
which mode to choose. The voltage on the MODE pin can be set by connecting to VCC pin or connecting a
resistor RM between this pin and AGND. There is a source current of 5 µA at the mode pin and generate voltage
for mode selection to avoid noise and spurious trigger. The VMODE voltage range and recommended resistor
value is shown in 表 1. The MODE pin setting can be reset only by VIN power cycling or EN toggle.
表 1. Mode Pin Settings
VMODE
0-0.3 V
0.3 V-1.2 V
100 kΩ-150 kΩ
OOA
>1.2 V
To VCC (recommend) or
Recommended Resistor
Operating Mode
0 Ω
RM>400kΩ
Eco-Mode™
FCCM
12
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图 18 shows the typical start-up sequence of the device once the enable signal crosses the EN turn on threshold
(VIN is higher then UVLO threshold). After the voltage on VCC crosses the rising UVLO threshold, it takes about
60 µs to read the mode setting .The output voltage starts ramping after 10 µs from the mode reading is done.
EN threshold
EN
VCC UVLO
VCC
MODE3
MODE2
MODE1
MODE
VOUT
PGOOD
60…s
10…s
Tss
60…s
500…s
图 18. Start-Up Sequence
12.4.3 Advanced Eco-Mode™ Control
The advanced Eco-Mode™ control scheme to maintain high efficiency at light loads. As the output current
decreases from heavy load conditions, the inductor current is also reduced and eventually comes to a point
where the rippled valley touches zero level, which is the boundary between continuous conduction and
discontinuous conduction modes. The low-side MOSFET is turned off when a zero inductor current is detected.
As the load current further decreases, the converter runs into discontinuous conduction mode. The on-time is
kept almost the same as it is in continuous conduction mode so that it takes more time to discharge the output to
the level of reference voltage with a smaller load current. The light load current where the transition to Eco-
Mode™ operation happens ( IOUT(LL) ) can be calculated from 公式 2.
(V -VOUT ) × VOUT
1
IN
IOUT(LL)
=
×
2 × LOUT × FSW
V
IN
(2)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-to-
peak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application).
12.4.4 Out-Of-Audio™ Mode
Out-Of-Audio™ (OOA) light-load mode is a unique control feature that keeps the switching frequency above
audible frequency with minimum reduction in efficiency. It prevents audio noise generation from the output
capacitors and inductor. During Out-of-Audio operation, the OOA control circuit monitors the states of both high-
side and low-side MOSFETs and forces them switching if both MOSFETs are off for more than 32 μs. When both
high-side and low-side MOSFETs are off for more than 32 μs during a light-load condition, the low side FET will
discharge until reverse OC happens or output voltage drops to trigger the high-side FET on.
If the MODE pin is selected to operate in OOA mode, when the device works at light load, the minimum
switching frequency is above 25 kHz which avoids the audible noise in the system.
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12.4.5 Force CCM Mode
Force CCM (FCCM) mode keeps the converter to operate in continuous conduction mode during light-load
conditions and allows the inductor current to become negative. During FCCM mode, the switching frequency
(FSW) is maintained at an almost constant level over the entire load range, which is suitable for applications
requiring tight control of the switching frequency and output voltage ripple at the cost of lower efficiency under
light load.
12.4.6 Standby Operation
The TPS566235 can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 3 µA when in standby condition. EN pin is pulled low internally when it is floating and the device is
disabled by default.
14
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13 Application and Implementation
注
Information in the following application sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
13.1 Application Information
The schematic of 图 19 shows a typical application for TPS566235. This design converts an input voltage range
of 4.5 V to 18 V down to 1.05 V with a maximum output current of 6 A.
13.2 Typical Application
图 19. Application Schematic
13.2.1 Design Requirements
表 2. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
1.05
MAX
UNIT
V
VOUT
IOUT
Output voltage
Output current
6
A
ΔVOUT
VIN
Transient response
Input voltage
IOUT: 10%-90%, 2.5A/µs
±5% x VOUT
12
4.5
18
V
VOUT(ripple)
FSW
Output voltage ripple
Switching frequency
Light load operation mode
Ambient temperature
2% x VOUT
600
kHz
°C
Eco-Mode™
25
TA
13.2.2 Detailed Design Procedure
13.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS566235 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
Run electrical simulations to see important waveforms and circuit performance
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•
•
•
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.2.2.2 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See 表 3 for recommended
inductor values.
The RMS and peak currents through the inductor can be calculated using 公式 3 and 公式 4. It is important that
the inductor is rated to handle these currents.
æ
2 ö
÷
÷
÷
ø
æ
ç
ö
÷
VOUT × V
- VOUT
(
× LOUT × FSW
IN(max)
)
1
IN(max)
ç 2
I
IL(rms)=
+
×
OUT
ç
ç
è
÷
ø
12
V
ç
è
(3)
(4)
IOUT(ripple)
I
= IOUT
+
L(peak)
During transient/short circuit conditions the inductor current can increase up to the current limit of the device so it
is safe to choose an inductor with a saturation current higher than the peak current under current limit condition.
13.2.2.3 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In D-CAP3™, the regulator reacts within
one cycle to the change in the duty cycle so the good transient performance can be achieved without needing
large amounts of output capacitance. The recommended output capacitance range is given in 表 3
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple)
表 3. Recommended Component Values
LOUT (µH)
TYP
1
COUT (µF)
MAX
CFF (pF)
RLOWER
(kΩ)
RUPPER
(kΩ)
VOUT (V)
MIN
0.68
0.68
1
MAX
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
MIN
44
44
44
44
44
44
44
44
MIN
MAX
1
1.05
1.2
1.5
1.8
2.5
3.3
5
20
20
20
20
20
20
20
20
13.3
15
110
110
110
110
110
110
110
110
-
-
-
1
-
20
1.2
-
-
30
1
1.2
-
-
-
40
1.2
1.5
1.5
1.5
1.5
-
63.3
90
2.2
-
-
2.2
10
10
220
220
146.6
2.2
13.2.2.4 Input Capacitor Selection
The minimum input capacitance required is given in 公式 5.
IOUT×VOUT
CIN(min)
=
V
INripple×V ×FSW
IN
(5)
TI recommends using a high quality X5R or X7R input decoupling capacitors of 44 µF on the input voltage pin.
The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of the application. The input ripple
current is calculated by 公式 6 below:
VIN(min)-VOUT
(
)
VOUT
ICIN(rms) = IOUT ×
×
VIN(min)
VIN(min)
(6)
16
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13.2.3 Application Curves
图 20 through 图 35 applies to the circuit of 图 19. VIN = 12 V, TJ = 25°C (unless otherwise specified)
100
90
80
70
60
50
40
30
20
10
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
VIN=5V, VOUT=1.05V
VIN=8.4V, VOUT=1.05V
VIN=12V, VOUT=1.05V
VIN=18V, VOUT=1.05V
VIN=5V, VOUT=1.05V
VIN=8.4V, VOUT=1.05V
VIN=12V, VOUT=1.05V
VIN=18V, VOUT=1.05V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D001
D019
图 20. Efficiency Curve
图 21. Load Regulation
800
700
600
500
400
300
200
700
600
500
400
300
200
100
0
VIN=5V, VOUT=1.05V
VIN=8.4V, VOUT=1.05V
VIN=12V, VOUT=1.05V
VIN=18V, VOUT=1.05V
4
6
8
10
VIN (V)
12
14
16
18
0.001
0.01
0.1
I-Load (A)
1
10
D022
D016
IOUT = 6 A
图 22. Switching Frequency vs Input Voltage
图 23. Switching Frequency vs Output Load
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
4
6
8
10
12
14
16
18
4
6
8
10
12
14
16
18
VIN (V)
VIN (V)
D020
D021
图 24. Line Regulation, IOUT = 0.1 A
图 25. Line Regulation, IOUT = 6 A
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EN=5V/div
EN=5V/div
Vout=1V/div
Vout=1V/div
IL=5A/div
IL=5A/div
400…s/div
2ms/div
图 26. Start-Up Through EN, IOUT = 3 A
图 27. Shut-down Through EN, IOUT = 3 A
Vin=10V/div
Vout=1V/div
Vin=10V/div
Vout=1V/div
IL=5A/div
IL=5A/div
400…s/div
4ms/div
图 28. Start Up Relative to VIN Rising, IOUT = 3 A
图 29. Start Up Relative to VIN Falling, IOUT = 3 A
Vout=50mV/div (AC coupled)
Vout=20mV/div (AC coupled)
SW=10V/div
SW=10V/div
2…s/div
100…s/div
图 31. Output Voltage Ripple, IOUT = 6 A
图 30. Output Voltage Ripple, IOUT = 0.01 A
18
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Vout=100mV/div (AC coupled)
Vout=100mV/div (AC coupled)
Iout=5A/div
Iout=5A/div
200…s/div
200…s/div
Slew Rate=2.5A/µs
Slew Rate=2.5A/µs
图 32. Transient Response, 0.6 A to 5.4 A
图 33. Transient Response, 0 A to 6 A
Vout=1V/div
Vout=1V/div
SW=10V/div
IL=10A/div
SW=10V/div
IL=10A/div
4ms/div
80…s/div
图 35. Output Hard Short Hiccup
图 34. Normal Operation to Output Hard Short
14 Power Supply Recommendations
The TPS566235 is intended to be powered by a well regulated dc voltage. The input voltage range is 4.5 V to 18
V. TPS566235 is Buck converter, the input supply voltage must be bigger than the desired output voltage for
proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS566235 circuit, some additional input bulk capacitance is recommended.
Typical values are 100 µF to 470 µF.
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15 Layout
15.1 Layout Guidelines
When laying out the printed circuit board, the following guideline should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the layout diagram of 图 36
•
Recommend a four-layer PCB for good thermal performance and with maximum ground plane. 3" x 3", four-
layer PCB with 2-oz. copper used as example.
•
•
Place the decoupling capacitors right across VIN as close as possible.
Place output inductors and capacitors with IC at the same layer, SW routing should be as short as possible to
minimize EMI, and should be a wide plane to carry big current, enough vias should be added to the PGND
connection of output capacitor and also as close to the output pin as possible.
•
•
Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace
is recommended to reduce line parasitic inductance.
FB could be wide and must be routed away from the switching node, BST node or other high efficiency
signal.
•
•
VIN trace must be wide to reduce the trace impedance and provide enough current capability.
Place multiple vias near GND and near input capacitors to reduce parasitic inductance and improve thermal
performance.
15.2 Layout Example
R
R
Trace on internal or
bottom layer
R
C
VIN
VIN
BST
R
C
SW
C
C
Mode setting
PGND
MODE
L
OOA FCCM
PSM
Additional Vias to
the GND plane
Additional Vias to
the GND plane
To Enable
Control
GND
GND
VOUT
C
图 36. PCB Layout Recommendation Diagram
20
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16 器件和文档支持
16.1 器件支持
16.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
16.1.2 开发支持
16.1.2.1 使用 WEBENCH® 工具创建定制设计
单击此处，使用 TPS566235 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
16.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
16.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
16.4 商标
D-CAP3, Eco-Mode, Out-Of-Audio, HotRod, Advanced Eco-Mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
16.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
16.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
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17 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
22
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重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
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所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
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束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
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Copyright © 2020 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS566235RJNR
TPS566235RJNT
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RJN
RJN
13
13
3000 RoHS & Green
250 RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
566235
566235
Call TI | NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2021
Addendum-Page 2
PACKAGE OUTLINE
VSON-HR - 1 mm max height
PLASTIC SMALL OUTLINE- NO LEAD
RJN0013A
A
2.1
1.9
B
PIN 1 INDEX AREA
3.1
2.9
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.5
SYMM
(0.1) TYP
3
6
2
1
7
SYMM
1
9
0.3
0.2
13X
0.1
C A B
C
0.05
13
10
0.5
0.3
8X 0.5
10X
1.3
1.1
3X
4223830/C 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VSON-HR - 1 mm max height
PLASTIC SMALL OUTLINE- NO LEAD
RJN0013A
3X (1.4)
(1.5)
(0.5)
(0.9)
13
10
1
9
SYMM
(2.8)
(1)
7
2
10X (0.6)
3
6
13X (0.25)
SYMM
8X (0.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223830/C 06/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
VSON-HR - 1 mm max height
PLASTIC SMALL OUTLINE- NO LEAD
RJN0013A
(1.5)
3X (0.8)
(0.1)
13
10
1
9
7
SYMM
(2.8)
(1)
2
16X (0.6)
6
3
16X (0.25)
SYMM
8X (0.5)
SOLDER PASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
EXPOSED PAD
86% PRINTED COVERAGE BY AREA
SCALE: 25X
4223830/C 06/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
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有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
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