TPS54335-2ADRCR [TI]
具有 Eco-mode 的 4.5V 至 28V 输入、3A 同步降压转换器 | DRC | 10 | -40 to 85;
| 型号： | TPS54335-2ADRCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 Eco-mode 的 4.5V 至 28V 输入、3A 同步降压转换器 | DRC | 10 | -40 to 85 开关 光电二极管 输出元件 转换器 |
| 文件： | 总41页 (文件大小：2190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS54335-2A
ZHCSF67 –JULY 2016
TPS54335-2A 4.5V 至 28V 输入、3A 输出、同步
降压 DC-DC 转换器
1 特性
3 说明
1
•
同步 128mΩ 和 84mΩ MOSFET，适用于
3A 持续输出电流
TPS54335-2A 同步转换器，输入电压范围为 4.5V 到
28V。此器件带有一个集成低侧开关场效应晶体管
(FET)，无需使用外部二极管，从而减少组件数量。
•
2ms 内部软启动，
50kHz 到 1.5MHz 可调节频率
通过集成 128mΩ 和 84mΩ MOSFET、低 IQ 以及轻载
条件下的脉冲跳跃，能够实现效率最大化。通过使能引
脚可以将关断电源电流减小至 2µA。该降压转换器的
基准电压在整个温度范围内保持 1.5% 的精度，可为各
类负载提供精确稳压。
•
•
•
•
•
•
•
关断时静态电流低至 2µA
0.8V 基准电压，精度为 ±0.8%
电流模式控制
针对预偏置输出的单调性启动
用于在轻负载时提高效率的脉冲跳跃模式
断续模式过流保护
高侧 MOSFET 的逐周期电流限制功能可在过载条件下
保护 TPS54335-2A，并通过低侧拉电流限制功能防止
电流失控，从而实现功能增强。低侧灌电流限制可关闭
低侧 MOSFET，以防止过多的反向电流。在过流情况
持续时间超过预设时间时，将触发断续保护功能。热关
断将在芯片温度超出阈值时禁用器件，并在经过一段内
置的热断续时间后再次使能器件。
热关断 (TSD) 和
过压变换保护
•
10 引脚超薄小外形尺寸无引线 (VSON) 封装
2 应用范围
•
消费类 应用 消费类应用，例如数字电视 (DTV)、
机顶盒（STB、数字化视频光盘 (DVD)/蓝光播放
器）、液晶显示器、客户端设备 (CPE)（电缆调制
解调器、WiFi 路由器）、数字光处理 (DLP) 投影
仪、智能电表
器件信息(1)
器件型号
封装
VSON (10)
封装尺寸（标称值）
TPS54335-2A
3.00mm x 3.00mm
•
•
•
电池充电器
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
工业用和车载音频电源
5V、12V 和 24V 分布式电源总线供电
简化电路原理图
CBOOT
1
8
VIN
EN
BOOT
PH
9
3
2
6
LO
C1
VOUT
CO
NC
w01
10 RT
VSENSE
wwÇ
7
COMP
CC
GND GND
w02
C2
4
5
w/
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCK3
TPS54335-2A
ZHCSF67 –JULY 2016
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 20
Power Supply Recommendations...................... 30
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 32
11 器件和文档支持 ..................................................... 33
11.1 器件支持................................................................ 33
11.2 文档支持................................................................ 33
11.3 相关链接................................................................ 33
11.4 接收文档更新通知 ................................................. 33
11.5 社区资源................................................................ 33
11.6 商标....................................................................... 33
11.7 静电放电警告......................................................... 33
11.8 Glossary................................................................ 33
12 机械、封装和可订购信息....................................... 33
7
4 修订历史记录
日期
修订版本
注释
2016 年7 月
*
最初发布版本
2
Copyright © 2016, Texas Instruments Incorporated
TPS54335-2A
www.ti.com.cn
ZHCSF67 –JULY 2016
5 Pin Configuration and Functions
DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
VIN
NC
1
2
3
4
5
10 RT
9
8
7
6
BOOT
Exposed
Thermal
Pad
PH
EN
GND
GND
COMP
VSENSE
Pin Functions
PIN
I/O
DESCRIPTION
NAME
VSON
A bootstrap capacitor is required between the BOOT and PH pins. If the voltage on this
capacitor is below the minimum required by the output device, the output is forced to switch
off until the capacitor is refreshed.
BOOT
COMP
9
O
O
This pin is the error-amplifier output and the input to the output switch-current comparator.
Connect frequency compensation components to this pin.
7
EN
8
2
4
5
3
I
This pin is the enable pin. Float the EN pin to enable.
NC
—
—
—
O
No Connect
GND
GND
PH
Ground
Ground
The PH pin is the source of the internal high-side power MOSFET.
Connect the RT pin to an external timing resistor to adjust the switching frequency of the
device.
RT
10
O
VIN
1
6
—
I
This pin is the 4.5-V to 28-V input supply voltage.
VSENSE
This pin is the inverting node of the transconductance (gm) error amplifier.
For proper operation, connect the GND pin to the exposed thermal pad. This thermal pad
should be connected to any internal PCB ground plane using multiple vias for good thermal
performance.
Thermal pad
—
Copyright © 2016, Texas Instruments Incorporated
3
TPS54335-2A
ZHCSF67 –JULY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
UNIT
V
VIN
EN
30
6
V
BOOT
Input voltage
(VPH + 7.5)
V
VSENSE
3
V
COMP
RT
3
V
3
V
BOOT-PH
7.5
V
Output voltage
PH
–1
30
30
V
PH, 10-ns transient
–3.5
–0.2
100
100
V
VDIFF (GND to exposed thermal pad)
EN
0.2
V
100
µA
µA
A
Source current
RT
100
PH
Current-limit
Current-limit
200
PH
A
Sink current
COMP
200
–40
–65
µA
°C
°C
Operating junction temperature
Storage temperature, Tstg
150
150
(1) Stresses beyond those listed under the absolute maximum ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the recommended
operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS–001, all pins(1)
2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
28
UNIT
V
VSS Supply input voltage
VOUT Output voltage
IOUT Output current
4.5
0.8
0
24
V
3
A
TJ
Operating junction temperature(1)
–40
150
°C
(1) The device must operate within 150°C to ensure continuous function and operation of the device.
4
Copyright © 2016, Texas Instruments Incorporated
TPS54335-2A
www.ti.com.cn
ZHCSF67 –JULY 2016
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
TPS54335-2A
DRC (VSON)
10 PINS
43.9
THERMAL METRIC
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
55.4
18.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
ψJB
19.1
RθJC(bot)
5.3
6.5 Electrical Characteristics
The electrical ratings specified in this section apply to all specifications in this document unless otherwise noted. These
specifications are interpreted as conditions that will not degrade the parametric or functional specifications of the device for
the life of the product containing it. TJ = –40°C to 150°C, V = 4.5 to 28 V, (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE AND UVLO (VIN PIN)
Operating input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.5
28
4.5
400
10
V
V
Input UVLO threshold
Rising V
4
180
2
Input UVLO hysteresis
mV
µA
VIN-shutdown supply current
= 0 V
VIN-operating non-switching supply
current
= 810 mV
310
800
µA
ENABLE (EN PIN)
Enable threshold
Enable threshold
Input current
Rising
Falling
= 1.1 V
= 1.3 V
1.21
1.17
1.15
3.3
1.28
V
V
1.1
µA
µA
Hysteresis current
VOLTAGE REFERENCE
TJ =25°C
0.7936
0.788
0.8 0.8064
0.8 0.812
Reference
V
MOSFET
= 3 V
160
128
84
280
230
170
mΩ
mΩ
mΩ
High-side switch resistance(1)
= 6 V
Low-side switch resistance(1)
ERROR AMPLIFIER
V = 12 V
Error-amplifier transconductance (gm)
Error-amplifier source and sink
Start switching peak current threshold(2)
COMP to ISWITCH gm
–2 µA < ICOMP < 2 µA, VCOMP = 1 V
VCOMP = 1 V, 100-mV overdrive
1300
100
0.5
8
µmhos
µA
A
A/V
CURRENT-LIMIT
High-side switch current-limit threshold
Low-side switch sourcing current-limit
Low-side switch sinking current-limit
4
4.9
4.7
0
6.5
6.1
A
A
A
3.5
(1) Measured at pins
(2) Not production tested.
Copyright © 2016, Texas Instruments Incorporated
5
TPS54335-2A
ZHCSF67 –JULY 2016
www.ti.com.cn
Electrical Characteristics (continued)
The electrical ratings specified in this section apply to all specifications in this document unless otherwise noted. These
specifications are interpreted as conditions that will not degrade the parametric or functional specifications of the device for
the life of the product containing it. TJ = –40°C to 150°C, V = 4.5 to 28 V, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN
Thermal shutdown(2)
Thermal shutdown hysteresis(2)
160
175
10
°C
°C
BOOT PIN
BOOT-PH UVLO
2.1
3
V
6.6 Timing Requirements
MIN
TYP
MAX
UNIT
CURRENT-LIMIT
Hiccup wait time
512
Cycles
Cycles
Hiccup time before restart
THERMAL SHUTDOWN
Thermal shutdown hiccup time
SOFT START
16384
32768
2
Cycles
ms
Internal soft-start time, TPS54335-2A
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PH PIN
Minimum on time
Measured at 90% to 90% of VIN, IPH = 2 A
94
145
ns
Minimum off time
≥ 3 V
0%
SWITCHING FREQUENCY
50
384
40
1500
576
60
kHz
kHz
kHz
kHz
R = 100 kΩ
480
50
Switching frequency range, TPS54335-2A
R = 1000 kΩ, –40°C to 105°C
R = 30 kΩ
1200
1500
1800
6
Copyright © 2016, Texas Instruments Incorporated
TPS54335-2A
www.ti.com.cn
ZHCSF67 –JULY 2016
6.8 Typical Characteristics
140
130
120
110
100
90
210
190
170
150
130
110
90
80
70
60
50
70
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C002
Junction Temperature (°C)
C001
Junction Temperature (°C)
VIN = 12 V
VIN = 12 V
Figure 2. Low-Side MOSFET on Resistance vs Junction
Temperature
Figure 1. High-Side MOSFET on Resistance vs Junction
Temperature
0.808
0.804
0.800
0.796
0.792
495
490
485
480
475
470
465
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C003
C004
Junction Temperature (°C)
Junction Temperature (°C)
Figure 3. Voltage Reference vs Junction Temperature
Figure 4. Oscillator Frequency vs Junction Temperature
1.230
3.50
3.45
3.40
3.35
3.30
3.25
3.20
1.225
1.220
1.215
1.210
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C005
C006
Junction Temperature (°C)
Junction Temperature (°C)
VIN = 12 V
VIN = 12 V
Figure 5. UVLO Threshold vs Junction Temperature
Figure 6. Hysteresis Current vs Junction Temperature
Copyright © 2016, Texas Instruments Incorporated
7
TPS54335-2A
ZHCSF67 –JULY 2016
www.ti.com.cn
Typical Characteristics (continued)
1.2
400
350
300
250
200
1.175
1.15
1.125
1.1
T = œ40°C
J
T = 25°C
J
T = 150°C
J
œ50
œ25
0
25
50
75
100
125
150
4
8
12
16
20
24
28
C007
C008
Junction Temperature (°C)
Input Voltage (V)
VIN = 12 V
Figure 7. Pullup Current vs Junction Temperature
Figure 8. Non-Switching Operating Quiescent Current vs
Input Voltage
10
2.40
2.35
2.30
2.25
2.20
TJ = œ40°C
T=25°C
J
8
6
4
2
0
T=150°C
J
4
8
12
16
20
24
28
œ50
œ25
0
25
50
75
100
125
150
C009
C010
Input Voltage (V)
Junction Temperature (°C)
VEN = 0 V
Figure 9. Shutdown Quiescent Current vs Input Voltage
Figure 10. SS Charge Current vs Junction Temperature
120
6.0
110
100
90
5.0
4.0
3.0
80
70
œ50
œ25
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
150
C011
C012
Junction Temperature (°)
Junction Temperature (°C)
VIN = 12 V
VIN = 12 V
Figure 11. Minimum Controllable On Time vs Junction
Temperature
Figure 12. Minimum Controllable Duty Ratio vs Junction
Temperature
8
Copyright © 2016, Texas Instruments Incorporated
TPS54335-2A
www.ti.com.cn
ZHCSF67 –JULY 2016
Typical Characteristics (continued)
6.0
5.5
5.0
4.5
4.0
2.3
TJ=–40°C
T = 25°C
J
T = 150°C
J
2.2
2.1
2.0
4
8
12
16
20
24
28
œ50
œ25
0
25
50
75
100
125
150
C014
Input Voltage (V)
C013
Junction Temperature (°C)
Figure 14. Current Limit Threshold vs Input Voltage
Figure 13. BOOT-PH UVLO Threshold vs Junction
Temperature
Copyright © 2016, Texas Instruments Incorporated
9
TPS54335-2A
ZHCSF67 –JULY 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The device is a 28-V, 3-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To
improve performance during line and load transients the device implements a constant-frequency, peak current-
mode control which reduces output capacitance and simplifies external frequency-compensation design.
The device has been designed for safe monotonic startup into pre-biased loads. The device has a typical default
startup voltage of 4 V. The EN pin has an internal pullup-current source that can provide a default condition when
the EN pin is floating for the device to operate. The total operating current for the device is 310 µA (typical) when
not switching and under no load. When the device is disabled, the supply current is less than 5 μA.
The integrated 128-mΩ and 84-mΩ MOSFETs allow for high-efficiency power-supply designs with continuous
output currents up to 3 A.
The device reduces the external component count by integrating the boot recharge diode. The bias voltage for
the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor
voltage is monitored by an UVLO circuit and turns off the high-side MOSFET when the voltage falls below a
preset threshold. The output voltage can be stepped down to as low as the 0.8-V reference voltage.
The device minimizes excessive output overvoltage transients by taking advantage of the overvoltage power-
good comparator. When the regulated output voltage is greater than 106% of the nominal voltage, the
overvoltage comparator is activated, and the high-side MOSFET is turned off and masked from turning on until
the output voltage is lower than 104%.
The TPS54335–2A device has a wide switching frequency of 50 kHz to 1500 kHz which allows for efficiency and
size optimization when selecting the output filter components. The internal 2-ms soft-start time is implemented to
minimize inrush currents.
7.2 Functional Block Diagram
EN
8
VIN
1
IP
IH
Thermal
Hiccup
UVLO
Shutdown
Logic
Hiccuup
Shutdown
Enable
Threshold
0 V
+
Boot
Charge
Minimum
Clamp Pulse
Skip
Current
Sense
Error
Amplifier
9
3
BOOT
PH
Boot
UVLO
VSENSE
6
+
+
HS MOSFET
Current
Comparator
Voltage
Reference
Power Stage
and Dead-Time
Control Logic
Slope
Compensation
Hiccuup
Shutdown
VIN
Regulator
Current
Sense
Overload
Recovery
Maximum
Clamp
LS MOSFET
Current Limit
Oscillator
4/5
7
10
COMP
RT
Exposed Thermal Pad
Copyright © 2016, Texas Instruments Incorporated
10
Copyright © 2016, Texas Instruments Incorporated
TPS54335-2A
www.ti.com.cn
ZHCSF67 –JULY 2016
7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
The device uses a fixed-frequency, peak current-mode control. The output voltage is compared through external
resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin.
An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is compared to
the current of the high-side power switch. When the power-switch current reaches the COMP voltage level the
high-side power switch is turned off and the low-side power switch is turned on. The COMP pin voltage increases
and decreases as the output current increases and decreases. The device implements a current-limit by
clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved
transient-response performance.
7.3.2 Light-Load Operation
The device monitors the peak switch current of the high-side MOSFET. When the peak switch current is lower
than 0.5 A (typical), the device stops switching to boost the efficiency until the peak switch current again rises
higher than 0.5 A (typical).
7.3.3 Voltage Reference
The voltage-reference system produces a precise ±1.5% voltage-reference over temperature by scaling the
output of a temperature-stable bandgap circuit.
7.3.4 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. Using divider resistors
with 1% tolerance or better is recommended. Begin with a value of 10 kΩ for the upper resistor divider, R1, and
use Equation 1 to calculate the value of R2. Consider using larger value resistors to improve efficiency at light
loads. If the values are too high then the regulator is more susceptible to noise and voltage errors from the
VSENSE input current are noticeable.
VREF
R2 =
´R1
VOUT - VREF
(1)
Copyright © 2016, Texas Instruments Incorporated
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ZHCSF67 –JULY 2016
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Feature Description (continued)
7.3.5 Enabling and Adjusting Undervoltage Lockout
The EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the threshold
voltage, the device begins operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters the low-quiescent (IQ) state.
The EN pin has an internal pullup-current source which allows the user to float the EN pin to enable the device. If
an application requires control of the EN pin, use open-drain or open-collector output logic to interface with the
pin.
The device implements internal undervoltage-lockout (UVLO) circuitry on the VIN pin. The device is disabled
when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a
hysteresis of 180 mV.
If an application requires a higher UVLO threshold on the VIN pin, then the EN pin can be configured as shown
in Figure 15. When using the external UVLO function, setting the hysteresis at a value greater than 500 mV is
recommended.
The EN pin has a small pullup-current, Ip, which sets the default state of the pin to enable when no external
components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO
function because it increases by Ih when the EN pin crosses the enable threshold. Use Equation 2, and
Equation 3 to calculate the values of R1 and R2 for a specified UVLO threshold.
Device
VIN
Ip
Ih
R1
R2
EN
Figure 15. Adjustable VIN Undervoltage Lockout
æ
ç
ç
è
ö
÷
÷
ø
VENfalling
VSTART
- VSTOP
VENrising
R1 =
æ
ö
÷
÷
ø
VENfalling
I
1-
+I
ç
p ç
h
VENrising
è
where
•
•
•
•
IP = 1.15 μA
IH = 3.3 μA
VENfalling = 1.17 V
VENrising = 1.21 V
(2)
R1´ VENfalling
R2 =
V
STOP - VENfalling +R1(Ip +Ih )
where
•
•
•
•
IP = 1.15 μA
IH = 3.3 μA
VENfalling = 1.17 V
VENrising = 1.21 V
(3)
12
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Feature Description (continued)
7.3.6 Error Amplifier
The device has a transconductance amplifier as the error amplifier. The error amplifier compares the VSENSE
voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference. The
transconductance of the error amplifier is 1300 μA/V (typical). The frequency compensation components are
placed between the COMP pin and ground.
7.3.7 Slope Compensation and Output Current
The device adds a compensating ramp to the signal of the switch current. This slope compensation prevents
subharmonic oscillations as the duty cycle increases. The available peak inductor current remains constant over
the full duty-cycle range.
7.3.8 Safe Startup into Pre-Biased Outputs
The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During
monotonic pre-biased startup, both high-side and low-side MOSFETs are not allowed to be turned on until the
internal soft-start voltage is higher than VSENSE pin voltage.
7.3.9 Bootstrap Voltage (BOOT)
The device has an integrated boot regulator. The boot regulator requires a small ceramic capacitor between the
BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The boot capacitor is charged
when the BOOT pin voltage is less than the VIN voltage and when the BOOT-PH voltage is below regulation.
The value of this ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric
with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature
and voltage. When the voltage between BOOT and PH pins drops below the BOOT-PH UVLO threshold, which
is 2.1 V (typical), the high-side MOSFET turns off and the low-side MOSFET turns on, allowing the boot
capacitor to recharge.
7.3.10 Output Overvoltage Protection (OVP)
The device incorporates an output overvoltage-protection (OVP) circuit to minimize output voltage overshoot. For
example, when the power-supply output is overloaded, the error amplifier compares the actual output voltage to
the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier demands maximum output current. When the condition is
removed, the regulator output rises and the error-amplifier output transitions to the steady-state voltage. In some
applications with small output capacitance, the power-supply output voltage can respond faster than the error
amplifier which leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by
comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP
threshold, the high-side MOSFET is turned off which prevents current from flowing to the output and minimizes
output overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is
allowed to turn on at the next clock cycle.
7.3.11 Overcurrent Protection
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
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Feature Description (continued)
7.3.11.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control which uses the COMP pin voltage to control the turn off of the high-
side MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. During each cycle, the switch
current and the current reference generated by the COMP pin voltage are compared. When the peak switch
current intersects the current reference the high-side switch turns off.
7.3.11.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on, the conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current-limit. If the low-side
sourcing current-limit is exceeded, the high-side MOSFET does not turn on and the low-side MOSFET stays on
for the next cycle. The high-side MOSFET turns on again when the low-side current is below the low-side
sourcing current-limit at the start of a cycle.
The low-side MOSFET can also sink current from the load. If the low-side sinking current-limit is exceeded the
low-side MOSFET turns off immediately for the remainder of that clock cycle. In this scenario, both MOSFETs
are off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) occurs for more than the
hiccup wait time, which is programmed for 512 switching cycles, the device shuts down and restarts after the
hiccup time of 16384 cycles. The hiccup mode helps to reduce the device power dissipation under severe
overcurrent conditions.
7.3.12 Thermal Shutdown
The internal thermal-shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C typically. When the junction temperature drops below 165°C typically, the internal thermal-hiccup timer
begins to count. The device reinitiates the power-up sequence after the built-in thermal-shutdown hiccup time
(32768 cycles) is over.
7.3.13 Small-Signal Model for Loop Response
Figure 16 shows an equivalent model for the device control loop which can be modeled in a circuit-simulation
program to check frequency and transient responses. The error amplifier is a transconductance amplifier with a
gm of 1300 μA/V. The error amplifier can be modeled using an ideal voltage-controlled current source. The
resistor, Roea (3.07 MΩ), and capacitor, Coea (20.7 pF), model the open-loop gain and frequency response of the
error amplifier. The 1-mV AC-voltage source between the nodes a and b effectively breaks the control loop for
the frequency response measurements. Plotting ac-c and c-b show the small-signal responses of the power
stage and frequency compensation respectively. Plotting a-b shows the small-signal response of the overall loop.
The dynamic loop response can be checked by replacing the load resistance, RL, with a current source with the
appropriate load-step amplitude and step rate in a time-domain analysis.
PH
VOUT
Power Stage
8 A/V
a
b
RESR
R1
VSENSE
COMP
R3
RL
c
+
VREF
CO
Roea
gmea
C2
Coea
R2
1300 µA/V
C1
Figure 16. Small-Signal Model For Loop Response
14
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Feature Description (continued)
7.3.14 Simple Small-Signal Model for Peak Current-Mode Control
Figure 17 is a simple small-signal model that can be used to understand how to design the frequency
compensation. The device power stage can be approximated to a voltage-controlled current-source (duty-cycle
modulator) supplying current to the output capacitor and load resistor. The control-to-output transfer function is
shown in Equation 4 and consists of a DC gain, one dominant pole and one ESR zero. The quotient of the
change in switch current and the change in the COMP pin voltage (node c in Figure 16) is the power-stage
transconductance (gmps) which is 8 A/V for the device. The DC gain of the power stage is the product of gmps
and the load resistance, RL, with resistive loads as shown in Equation 5. As the load current increases, the DC
gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole
moves with the load current (see Equation 6). The combined effect is highlighted by the dashed line in Figure 18.
As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
frequency the same for the varying load conditions which makes designing the frequency compensation easier.
VOUT
VC
RESR
RL
gmps
CO
Figure 17. Simplified Small-Signal Model for Peak Current-Mode Control
VOUT
Adc
VC
RESR
ƒp
RL
gmps
CO
ƒz
Figure 18. Simplified Frequency Response for Peak Current-Mode Control
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Feature Description (continued)
æ
ç
è
ö
÷
ø
s
1+
1+
2p ´ ƒz
VOUT
VC
= Adc ´
æ
ç
ç
è
ö
÷
÷
ø
s
2p ´ ƒp
(4)
(5)
(6)
(7)
Adc = gmps ´ RL
where
•
•
gmps is the power stage gain (8 A/V)
RL is the load resistance
1
ƒp
=
CO ´ RL ´ 2p
where
•
CO is the output capacitance
1
ƒz =
CO ´ RESR ´ 2p
where
•
RESR is the equivalent series resistance of the output capacitor
7.3.15 Small-Signal Model for Frequency Compensation
The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly
used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 19. In
Type 2A, one additional high frequency pole, C6, is added to attenuate high frequency noise. In Type III, one
additional capacitor, C11, is added to provide a phase boost at the crossover frequency. See Designing Type III
Compensation for Current Mode Step-Down Converters (SLVA352) for a complete explanation of Type III
compensation.
The following design guidelines are provided for advanced users who prefer to compensate using the general
method. The following equations only apply to designs whose ESR zero is above the bandwidth of the control
loop which is usually true with ceramic output capacitors.
VOUT
C11
R8
VSENSE
Type 2A
Type 2B
COMP
Coea
Type III
R9
VREF
+
R4
C4
R4
C4
gmea
C6
Roea
Figure 19. Types of Frequency Compensation
16
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Feature Description (continued)
The general design guidelines for device loop compensation are as follows:
1. Determine the crossover frequency, ƒc. A good starting value for ƒc is 1/10th of the switching frequency, ƒSW
.
2. Use Equation 8 to calculate the value of R4.
2p ´ ƒc ´ VOUT ´ CO
R4 =
gmea ´ VREF ´ gmps
where
•
•
•
gmea is the GM amplifier gain (1300 μA/V)
gmps is the power stage gain (8 A/V)
VREF is the reference voltage (0.8 V)
(8)
3. Place a compensation zero at the dominant pole and use Equation 9 to calculate the value of ƒp.
æ
ç
è
ö
÷
ø
1
ƒ =
p
CO ´ RL ´ 2p
(9)
4. Use Equation 10 to calculate the value of C4.
RL ´ CO
C4 =
R4
(10)
5. The use of C6 is optional. C6 can be used to cancel the zero from the ESR (equivalent series resistance) of
the output capacitor CO. If used, use Equation 11 to calculate the value of C6.
RESR ´ CO
C6 =
R4
(11)
6. Type III compensation can be implemented with the addition of one capacitor, C11. The use of C11 allows
for slightly higher loop bandwidths and higher phase margins. If used, use Equation 12 to calculate the value
of C11.
1
C11=
2´ p´R8´ ƒ
(
)
C
(12)
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7.4 Device Functional Modes
7.4.1 Operation With VI < 4.5 V (minimum VI)
The device is designed to operate with input voltages above 4.5 V. The typical VIN UVLO threshold is 4V and if
VIN falls below this threshold the device stops switching. If the EN pin voltage is above EN threshold the device
becomes active when the VIN pin passes the UVLO threshold. .
7.4.2 Operation With EN Control
The enable threshold is 1.2-V typical. If the EN pin voltage is below this threshold the device does not switch
even though the Vin is above the UVLO threshold. The IC quiescent current is reduced in this state. Once the
EN is above the threshold with VIN above UVLO threshold the device is active again and the soft-start sequence
is initiated.
7.4.3 Operation With EN Control
The enable threshold is 1.2-V typical. If the EN pin voltage is below this threshold the device does not switch
even though the VIN is above the UVLO threshold. The device's quiescent current is reduced in this state. Once
the EN is above the threshold with VIN above UVLO threshold the device is active again and the soft-start
sequence is initiated.
18
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54335-2A family of devices are step-down DC-DC converters. The devices are typically used to convert
a higher DC voltage to a lower DC voltage with a maximum available output current of 3 A. Use the following
design procedure to select component values for each device. Alternately, use the WEBENCH software to
generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a
comprehensive database of components when generating a design. This section presents a simplified discussion
of the design process.
8.1.1 Supplementary Guidance
The device must operate within 150°C to ensure continuous function and operation of the device.
8.1.2 The DRC Package
The TPS54335-2A device is packaged in the a 3-mm × 3-mm SON package which is designated as DRC (see
the 机械、封装和可订购信息 section for all package options).
TPS54335-2A
1mm
Figure 20. TPS54335-2A DRC Package
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8.2 Typical Applications
TPS54335-2A typical application.
L1 = 15 mH
C3
0.1 mF
VIN
8 V to 28 V
VOUT
1
VIN
BOOT
9
5 V, 3 A max
C1
10 mF
C2
0.1 mF
VSENSE
C6
47 mF
R4
51.1 W
C7
47 mF
R1
220 kW
6
8
VSENSE
EN
PH
3
7
COMP
R5
100 kW
R3
3.74 kW
C5
120 pF
R2
43.2 kW
10 RT
GND 4,5
PAD
VSENSE
C4
12 nF
R6
19.1 kW
R7
143 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Typical Application Schematic, TPS54335-2A
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage range
EXAMPLE VALUE
8 to 28 V
5 V
Output voltage
Transient response, 1.5-A load step
Input ripple voltage
ΔVO = ±5 %
400 mV
Output ripple voltage
Output current rating
Operating Frequency
30 mV
3 A
340 kHz
20
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8.2.2 Detailed Design Procedure
The following design procedure can be used to select component values for the TPS54335-2A device.
Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH software
uses an iterative design procedure and accesses a comprehensive database of components when generating a
design. This section presents a simplified discussion of the design process using the TPS54335-2A device.
For this design example, use the input parameters listed in Table 1.
8.2.2.1 Switching Frequency
Use to calculate the required value for R7. The calculated value is 140.6 kΩ. Use the next higher standard value
of 143 kΩ for R7.
8.2.2.2 Output Voltage Set Point
The output voltage of the TPS54335-2A device is externally adjustable using a resistor divider network. In the
application circuit of , this divider network is comprised of R5 and R6. Use Equation 13 and Equation 14 to
calculate the relationship of the output voltage to the resistor divider.
R5 ´ V
ref
R6 =
VOUT - V
ref
(13)
R5
é
ù
VOUT = V
´
+1
ref
ê
ú
R6
ë
û
(14)
Select a value of R5 to be approximately 100 kΩ. Slightly increasing or decreasing R5 can result in closer output-
voltage matching when using standard value resistors. In this design, R5 = 100 kΩ and R6 = 19.1 kΩ which
results in a 4.988-V output voltage. The 51.1-Ω resistor, R4, is provided as a convenient location to break the
control loop for stability testing.
8.2.2.3 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) set point can be adjusted using the external-voltage divider network of R1 and
R2. R1 is connected between the VIN and EN pins of the TPS54335-2A device. R2 is connected between the
EN and GND pins. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the minimum input voltage
is 8 V, so the start-voltage threshold is set to 7.15 V with 1-V hysteresis. Use Equation 2 and Equation 3 to
calculate the values for the upper and lower resistor values of R1 and R2.
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8.2.2.4 Input Capacitors
The TPS54335-2A device requires an input decoupling capacitor and, depending on the application, a bulk input
capacitor. The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R
or X7R is recommended. The voltage rating should be greater than the maximum input voltage. A smaller value
can be used as long as all other requirements are met; however a 10-μF capacitor has been shown to work well
in a wide variety of circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54335-2A
circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical
but should be rated to handle the maximum input voltage including ripple voltage, and should filter the output so
that input ripple voltage is acceptable. For this design, a 10-μF, X7R dielectric capacitor rated for 35 V is used for
the input decoupling capacitor. The ESR is approximately 2 mΩ, and the current rating is 3 A. Additionally, a
small 0.1-μF capacitor is included for high frequency filtering.
Use Equation 15 to calculate the input ripple voltage (ΔVIN).
IOUT(MAX) ´ 0.25
DV
=
+ IOUT(MAX) ´ ESRMAX
(
)
IN
CBULK ´ ƒSW
where
•
•
•
•
CBULK is the bulk capacitor value
ƒSW is the switching frequency
IOUT(MAX) is the maximum load current
ESRMAX is the maximum series resistance of the bulk capacitor
(15)
The maximum RMS (root mean square) ripple current must also be checked. For worst case conditions, use
Equation 16 to calculate ICIN(RMS)
IO(MAX)
.
ICIN(RMS)
=
2
(16)
In this case, the input ripple voltage is 227 mV and the RMS ripple current is 1.5 A.
NOTE
The actual input-voltage ripple is greatly affected by parasitics associated with the layout
and the output impedance of the voltage source.
The Design Requirements section shows the actual input voltage ripple for this circuit which is larger than the
calculated value. This measured value is still below the specified input limit of 400 mV. The maximum voltage
across the input capacitors is VIN(MAX) + ΔVIN / 2. The selected bypass capacitor is rated for 35 V and the ripple
current capacity is greater than 3 A. Both values provide ample margin. The maximum ratings for voltage and
current must not be exceeded under any circumstance.
22
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8.2.2.5 Output Filter Components
Two components must be selected for the output filter, the output inductor (LO) and CO. Because the TPS54335-
2A device is an externally compensated device, a wide range of filter component types and values can be
supported.
8.2.2.5.1 Inductor Selection
Use Equation 17 to calculate the minimum value of the output inductor (LMIN).
VOUT
´
VIN(MAX) - VOUT
(
)
´ KIND ´ IOUT ´ ƒSW
LMIN
=
V
IN(MAX)
where
•
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output
current
(17)
In general, the value of KIND is at the discretion of the designer; however, the following guidelines may be used.
For designs using low-ESR output capacitors, such as ceramics, a value as high as KIND = 0.3 can be used.
When using higher ESR output capacitors, KIND = 0.2 yields better results.
For this design example, use KIND = 0.3. The minimum inductor value is calculated as 13.4 μH. For this design, a
close standard value of 15 µH was selected for LMIN
.
For the output filter inductor, the RMS current and saturation current ratings must not be exceeded. Use
Equation 18 to calculate the RMS inductor current (IL(RMS)).
æ
ç
ö2
÷
VOUT
´
V
- VOUT
(
)
IN(MAX)
1
IL(RMS)
=
IO2 UT(MAX)
+
´
ç
÷
12
V
´ LOUT ´ ƒSW ´ 0.8
IN(MAX)
è
ø
(18)
Use Equation 19 to calculate the peak inductor current (IL(PK)).
VOUT
´
V
- VOUT
)
´ LOUT ´ ƒSW
(
IN(MAX)
IN(MAX)
IL(PK) = IOUT(MAX)
+
1.6 ´ V
(19)
For this design, the RMS inductor current is 3.002 A and the peak inductor current is 3.503 A. The selected
inductor is a Coilcraft 15 μH, XAL6060-153MEB. This inductor has a saturation current rating of 5.8 A and an
RMS current rating of 6 A which meets the requirements. Smaller or larger inductor values can be used
depending on the amount of ripple current the designer wants to allow so long as the other design requirements
are met. Larger value inductors have lower AC current and result in lower output voltage ripple. Smaller inductor
values increase AC current and output voltage ripple. In general, for the TPS54335-2A device, use inductors with
values in the range of 0.68 μH to 100 μH.
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8.2.2.5.2 Capacitor Selection
Consider three primary factors when selecting the value of the output capacitor. The output capacitor determines
the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current.
The output capacitance must be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the load with current when the regulator cannot. This situation occurs if the desired hold-up times are present for
the regulator. In this case, the output capacitor must hold the output voltage above a certain level for a specified
amount of time after the input power is removed. The regulator is also temporarily unable to supply sufficient
output current if a large, fast increase occurs affecting the current requirements of the load, such as a transition
from no load to full load. The regulator usually requires two or more clock cycles for the control loop to notice the
change in load current and output voltage and to adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only
allowing a tolerable amount of drop in the output voltage. Use Equation 20 to calculate the minimum required
output capacitance.
2´DIOUT
CO
>
ƒ
SW ´DVOUT
where
•
•
•
ΔIOUT is the change in output current
ƒSW is the switching frequency of the regulator
ΔVOUT is the allowable change in the output voltage
(20)
For this example, the transient load response is specified as a 5% change in the output voltage, VOUT, for a load
step of 1.5 A. For this example, ΔIOUT = 1.5 A and ΔVOUT = 0.05 × 5 = 0.25 V. Using these values results in a
minimum capacitance of 35.3 μF. This value does not consider the ESR of the output capacitor in the output
voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.
Equation 21 calculates the minimum output capacitance required to meet the output voltage ripple specification.
In this case, the maximum output voltage ripple is 30 mV. Under this requirement, Equation 21 yields 12.3 µF.
1
1
CO
>
´
VOUTripple
8´ ƒSW
Iripple
where
•
•
•
ƒSW is the switching frequency
VOUTripple is the maximum allowable output voltage ripple
Iripple is the inductor ripple current
(21)
Use Equation 22 to calculate the maximum ESR an output capacitor can have to meet the output-voltage ripple
specification. Equation 22 indicates the ESR should be less than 29.8 mΩ. In this case, the ESR of the ceramic
capacitor is much smaller than 29.8 mΩ.
VOUTripple
RESR
<
Iripple
(22)
Additional capacitance deratings for aging, temperature, and DC bias should be considered which increases this
minimum value. For this example, two 47-μF 10-V X5R ceramic capacitors with 3 mΩ of ESR are used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS value of the maximum ripple current. Use Equation 23 to calculate the RMS ripple
current that the output capacitor must support. For this application, Equation 23 yields 116.2 mA for each
capacitor.
æ
ç
ç
è
ö
÷
÷
ø
VOUT
´
V
- VOUT
(
)
IN(MAX)
1
ICOUT(RMS)
=
´
V
´ LOUT ´ ƒSW ´ NC
12
IN(MAX)
(23)
24
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8.2.2.6 Compensation Components
Several possible methods exist to design closed loop compensation for DC-DC converters. For the ideal current-
mode control, the design equations can be easily simplified. The power stage gain is constant at low frequencies,
and rolls off at –20 dB/decade above the modulator pole frequency. The power stage phase is 0 degrees at low
frequencies and begins to fall one decade below the modulator pole frequency reaching a minimum of –90
degrees which is one decade above the modulator pole frequency. Use Equation 24 to calculate the simple
modulator pole (ƒp_mod).
IOUT max
ƒp_mod
=
2p´ VOUT ´ COUT
(24)
For the TPS54335-2A device, most circuits have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics deviate from the ideal approximations. The phase loss
of the power stage will now approach –180 degrees, making compensation more difficult. The power stage
transfer function can be solved but it requires a tedious calculation. Use the PSpice model to accurately model
the power-stage gain and phase so that a reliable compensation circuit can be designed. Alternately, a direct
measurement of the power stage characteristics can be used which is the technique used in this design
procedure. For this design, the calculated values are as follows:
L1 = 15 µH
C6 and C7 = 47 µF
ESR = 3 mΩ
Figure 22 shows the power stage characteristics.
60
180
120
60
40
Gain = 2.23 dB
at ƒ = 31.62 kHz
20
0
0
–20
–40
–60
–60
–120
–180
Gain
Phase
10
100
1000
10000
100000
C020
Frequency (Hz)
Figure 22. Power Stage Gain and Phase Characteristics
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For this design, the intended crossover frequency is 31.62 kHz (an actual measured data point exists for that
frequency). From the power stage gain and phase plots, the gain at 31.62 kHz is 2.23 dB and the phase is about
-106 degrees. For 60 degrees of phase margin, additional phase boost from a feed-forward capacitor in parallel
with the upper resistor of the voltage set point divider is not needed. R3 sets the gain of the compensated error
amplifier to be equal and opposite the power stage gain at crossover. Use Equation 25 to calculate the required
value of R3.
-GPWRSTG
20
VOUT
VREF
10
R3 =
´
gmea
(25)
To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 31.62
kHz. Use Equation 26 to calculate the required value for C4.
1
C4 =
ƒCO
2´ p´R3´
10
(26)
To maximize phase gain the high frequency pole is placed one decade above the crossover frequency of 31.62
kHz. The pole can also be useful to offset the ESR of aluminum electrolytic output capacitors. Use Equation 27
to calculate the value of C5.
1
C5 =
2´ p´R3´10´ ƒCO
(27)
For this design the calculated values for the compensation components are as follows:
R3 = 3.74 kΩ
C4 = 0.012 µF
C5 = 120 pF
26
Copyright © 2016, Texas Instruments Incorporated
TPS54335-2A
www.ti.com.cn
ZHCSF67 –JULY 2016
8.2.2.7 Bootstrap Capacitor
Every TPS54335-2A design requires a bootstrap capacitor, C3. The bootstrap capacitor value must 0.1 μF. The
bootstrap capacitor is located between the PH and BOOT pins. The bootstrap capacitor should be a high-quality
ceramic type with X7R or X5R grade dielectric for temperature stability.
8.2.2.8 Power Dissipation Estimate
The following formulas show how to estimate the device power dissipation under continuous-conduction mode
operations. These formulas should not be used if the device is working in the discontinuous conduction mode
(DCM) or pulse-skipping Eco-mode™.
The device power dissipation includes:
1. Conduction loss:
PCON = IOUT2 × rDS(on) × VOUT / VIN
where
•
•
•
•
IOUT is the output current (A)
rDS(on) is the on-resistance of the high-side MOSFET (Ω)
VOUT is the output voltage (V)
VIN is the input voltage (V)
(28)
2. Switching loss:
E = 0.5 × 10–9 × VIN 2 × IOUT × ƒSW
where
•
ƒSW is the switching frequency (Hz)
(29)
(30)
(31)
3. Gate charge loss:
PG = 22.8 × 10–9 × ƒSW
4. Quiescent current loss:
PQ = 0.11 × 10-3 × VIN
Therefore:
Ptot = PCON + E + PG + PQ
where
•
Ptot is the total device power dissipation (W)
(32)
For given TA :
TJ = TA + Rth × Ptot
where
•
•
•
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
Rth is the thermal resistance of the package (°C/W)
(33)
(34)
For given TJ = 150°C:
TAmax = TJmax – Rth × Ptot
where
•
•
TAmax is the maximum ambient temperature (°C)
TJmax is the maximum junction temperature (°C)
Copyright © 2016, Texas Instruments Incorporated
27
TPS54335-2A
ZHCSF67 –JULY 2016
www.ti.com.cn
8.2.3 Application Curves
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
100
80
60
40
20
VIN = 12 V
VIN = 24 V
VIN = 24 V
VIN = 12 V
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Ouput Current (A)
3
3.3
0.001 0.002 0.005 0.01 0.02
0.05 0.1 0.2 0.3 0.5
1
Output Current (A)
D001
D001
Figure 23. TPS54335-2A Efficiency
Figure 24. TPS54335-2A Low-Current Efficiency
±0.
±0ꢀ
±0.±
±0±8
VIN = ꢃꢂ V
VIN = ꢂꢀ V
IOUT = .05 A
±0ꢁ
±0±6
±0ꢂ
±0±4
±0ꢃ
±0±2
±0±
±0±±
±±0ꢃ
±±0ꢂ
±±0ꢁ
±±0ꢀ
±±0.
±±0±2
±±0±4
±±0±6
±±0±8
±±0.±
±0±
±0.
ꢃ0±
ꢃ0.
ꢂ0±
ꢂ0.
ꢁ0±
8
.±
.2
.4
.6
.8
2±
22
24
26
28
C±ꢃ7
C±.8
Output Current (A)
Input Voltage (V)
Figure 25. TPS54335-2A Load Regulation
Figure 26. TPS54335-2A Line Regulation
60
40
180
120
60
V
= 200 mV/div (AC coupled)
OUT
20
0
0
I
= 1 A/div
OUT
–20
–40
–60
–60
–120
–180
Gain
Phase
10
100
1000
10000
100000
1000000
C019
Frequency (Hz)
Time = 200 µs/div
0.75- to 2.25-A load step
Slew rate = 500 mA/µs
Figure 28. TPS54335-2A Loop Response
Figure 27. TPS54335-2A Transient Response
28
Copyright © 2016, Texas Instruments Incorporated
TPS54335-2A
www.ti.com.cn
ZHCSF67 –JULY 2016
V
= 20 mV/div (AC coupled)
OUT
V
= 20 mV/div (AC coupled)
OUT
PH = 10 V/div
PH = 10 V/div
Time = 2 µs/div
Time = 2 µs/div
Figure 29. TPS54335-2A Full-Load Output Ripple
Figure 30. TPS54335-2A 100-mA Output Ripple
V
= 200 mV/div (AC coupled)
IN
V
= 20 mV/div (AC coupled)
OUT
PH = 10 V/div
PH = 10 V/div
Time = 100 µs/div
Time = 2 µs/div
Figure 31. TPS54335-2A No-Load Output Ripple
Figure 32. TPS54335-2A Full-Load Input Ripple
V
= 10 V/div
IN
V
= 10 V/div
IN
EN = 2 V/div
EN = 2 V/div
V
= 2 V/div
V
= 2 V/div
OUT
OUT
Time = 2 ms/div
Time = 2 ms/div
Figure 33. TPS54335-2A Startup Relative To VIN
Figure 34. TPS54335-2A Startup Relative To Enable
Copyright © 2016, Texas Instruments Incorporated
29
TPS54335-2A
ZHCSF67 –JULY 2016
www.ti.com.cn
V
= 10 V/div
V
= 10 V/div
IN
IN
EN = 2 V/div
EN = 2 V/div
V
= 2 V/div
V
= 2 V/div
OUT
OUT
Time = 2 ms/div
Time = 2 ms/div
Figure 35. TPS54335-2A Shutdown Relative To VIN
Figure 36. TPS54335-2A Shutdown Relative To EN
9 Power Supply Recommendations
The devices are designed to operate from an input supply ranging from 4.5 V to 28 V. The input supply should
be well regulated. If the input supply is located more than a few inches from the converter an additional bulk
capacitance typically 100 µF may be required in addition to the ceramic bypass capacitors.
30
Copyright © 2016, Texas Instruments Incorporated
TPS54335-2A
www.ti.com.cn
ZHCSF67 –JULY 2016
10 Layout
10.1 Layout Guidelines
The VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor. Care should be taken to
minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the IC. The
typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum
placement is closest to the VIN and GND pins of the device. See Figure 37 for a PCB layout example. The GND
pin should be tied to the PCB ground plane at the pin of the IC. To facilitate close placement of the input bypass
capacitors, the PH pin should be routed to a small copper area directly adjacent to the pin. Use vias to route the
PH signal to the bottom side or an inner layer. If necessary, allow the top-side copper area to extend slightly
under the body of the closest input bypass capacitor. Make the copper trace on the bottom or internal layer short
and wide as practical to reduce EMI issues. Connect the trace with vias back to the top side to connect with the
output inductor as shown after the GND pin. In the same way use a bottom or internal layer trace to route the PH
signal across the VIN pin to connect to the boot capacitor as shown. Make the circulating loop from the PH pin to
the output inductor and output capacitors and then back to GND as tight as possible while preserving adequate
etch width to reduce conduction losses in the copper . For operation at a full rated load, the ground area near the
IC must provide adequate heat dissipating area. Connect the exposed thermal pad to the bottom or internal layer
ground plane using vias as shown. Additional vias may be used adjacent to the IC to tie top-side copper to the
internal or bottom layer copper. The additional external components can be placed approximately as shown. Use
a separate ground trace to connect the feedback, compensation, UVLO, and RT returns. Connect this ground
trace to the main power ground at a single point to minimize circulating currents. Obtaining acceptable
performance with alternate layout schemes is possible; however this layout has been shown to produce good
results and is intended as a guideline.
版权 © 2016, Texas Instruments Incorporated
31
TPS54335-2A
ZHCSF67 –JULY 2016
www.ti.com.cn
10.2 Layout Example
Via to Power ground plane
Via to SW copper pour on
bottom plane
Analog
Ground
Trace
VIN
SW trace on
Bottom layer
VIN
VIN
Byapass
Capacitor
High-
frequency
Byapass
Capacitor
UVLO resistor
Power
Ground
Feedback
Resistor
Exposed thermal
pad
Power
Ground
SW node copper
pour area
Output
Inductor
VOUT
Output filter capacitor
Figure 37. TPS54335-2ADRC Board Layout
32
版权 © 2016, Texas Instruments Incorporated
TPS54335-2A
www.ti.com.cn
ZHCSF67 –JULY 2016
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
如需 WEBENCH 电路设计和选择仿真服务，请访问：www.ti.com/WEBENCH。
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
《设计电流模式降压转换器的第 III 类补偿》（文献编号：SLVA352）
11.3 相关链接
以下表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
11.4 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.5 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 商标
Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
33
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都遵循在订单确认时所提供的TI 销售条款与条件。
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS54335-2ADRCR
TPS54335-2ADRCT
ACTIVE
ACTIVE
VSON
VSON
DRC
DRC
10
10
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
543352
543352
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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