TPS536C9RSLR [TI]
具有 VR14 SVID 和 PMBus 的双通道十二相降压数字多相 D-CAP+™ 控制器 | RSL | 48 | -40 to 125;
| 型号： | TPS536C9RSLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 VR14 SVID 和 PMBus 的双通道十二相降压数字多相 D-CAP+™ 控制器 | RSL | 48 | -40 to 125 控制器 |
| 文件： | 总9页 (文件大小：1049K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS536C9
ZHCSOG1A – JUNE 2021 – REVISED DECEMBER 2021
TPS536C9 具有 PMBus 和 VR14 SVID 接口的双 channel（N + M ≤ 12 相）D-CAP+™、
降压
多相控制器
1 特性
3 说明
•
•
•
输入电压范围：4.5V 至 17V
TPS536C9 是一款符合 VR14 SVID 标准的降压控
制器，具有双通道、内置非易失性存储器 (NVM) 和
PMBus™ 接口，而且与 TI NexFET™ 功率级完全兼
容。D-CAP+ 架构等高级控制特性以及下冲衰减 (USR)
和过冲衰减 (OSR) 可提供快速瞬态响应、最低输出波
纹和出色的动态电流共享。该器件还提供全新的相位交
错策略和动态切相功能，可有效提升轻负载条件下的效
率。还本地支持输出电压转换率和自适应电压定位的可
调控制。此外，该器件还支持 PMBus 通信接口，可向
主机系统报告遥测的电压、电流、功率、温度和故障状
况。所有可编程参数均可通过 PMBus 接口进行配置，
而且可作为新的默认值存储在 NVM 中，以尽可能减少
外部组件数量。
输出电压范围：0.25V 至 5.5V
支持 N+M 相位配置（N+M ≤ 12，M ≤ 6）的双路输
出
•
•
•
•
•
符合 Intel® VR14 SVID 标准且支持 PSYS
向后兼容 VR13.HC/VR13.0 SVID
自动 NVM 故障状态记录
动态电流限制，可提高快速电压模式性能
与 TI NexFET™ 功率级完全兼容，可实现高密度解
决方案
•
•
•
增强型 D-CAP+ 控制可提供卓越的瞬态性能和出色
的动态电流共享
可通过可编程阈值实现动态切相，从而提高轻负载
和重负载下的效率
TPS536C9 器件采用散热增强型 48 引脚 QFN 封装，
额定工作温度为 –40°C 至 125°C。
可通过非易失性存储器 (NVM) 进行配置，从而减少
外部组件数量
•
•
支持精确可调自适应电压定位（AVP、负载线）
单独的每相位 IMON 校准，具有多斜率增益校准以
提高系统精度。
器件信息
器件型号
TPS536C9
封装(1)
封装尺寸（标称值）
QFN (48)
6.00 × 6.00 mm
•
•
•
•
•
快速增相可实现瞬态下冲衰减
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
具有可编程超时的二极管制动，可减少瞬态过冲
获得专利的 AutoBalance™ 电流共享
可编程的每相位谷值电流限制 (OCL)
PMBus™ v1.3.1 系统接口，用于遥测电压、电流、
功率、温度和故障条件
录。
TPS536C9
PWM1
Power
Stage
CSP1
•
•
•
可通过 PMBus 对环路补偿进行编程
无驱动器配置，有助于实现高效的高频开关
6 mm × 6 mm 48 引脚 QFN 封装
PWM2
CSP2
PMBus
Power
Stage
2 应用
•
•
•
•
数据中心和企业计算 机架式服务器
硬件加速器
网络接口卡 (NIC)
ASIC 和 高性能客户端
PWM12
CSP12
Power
Stage
Copyright © 2019, Texas Instruments Incorporated
简化版应用
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEL8
TPS536C9
www.ti.com.cn
ZHCSOG1A – JUNE 2021 – REVISED DECEMBER 2021
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (June 2021) to Revision A (December 2021)
Page
•
将文档状态从预告信息 更改为量产数据 ............................................................................................................ 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSEL8
2
Submit Document Feedback
Product Folder Links: TPS536C9
TPS536C9
www.ti.com.cn
ZHCSOG1A – JUNE 2021 – REVISED DECEMBER 2021
5 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
5.1 Getting Started and Next Steps
5.2 Device Support
5.2.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
5.3 Device Nomenclature
5.4 Tools and Software
5.5 Documentation Support
5.5.1 Related Documentation
5.6 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
5.7 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
5.8 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Intel® is a registered trademark of Intel Corporation.
所有商标均为其各自所有者的财产。
5.9 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
5.10 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
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3
Product Folder Links: TPS536C9
English Data Sheet: SLUSEL8
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS536C9RSLR
ACTIVE
VQFN
RSL
48
3000 RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-40 to 125
TPS
536C9
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
A
6.1
5.9
B
PIN 1 INDEX AREA
6.1
5.9
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
4.4
13
24
44X 0.4
12
23
SYMM
49
4.5
4.3
4.4
1
36
0.25
0.15
48X
PIN 1 IDENTIFICATION
(OPTIONAL)
37
48
0.1
C A B
C
SYMM
0.5
0.3
0.05
48X
4219205/A 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
(
4.4)
SYMM
48
37
48X (0.6)
48X (0.2)
1
36
44X (0.4)
SYMM
(5.8)
10X (1.12)
49
6X (0.83)
(R0.05) TYP
12
25
13
6X (0.83)
24
(Ø0.2) VIA
10X (1.12)
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
0.05 MAX
0.05 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219205/A 02/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
SYMM
48
37
48X (0.6)
48X (0.2)
1
49
36
44X (0.4)
16X
(
0.92)
SYMM
8X (0.56)
(5.8)
8X (1.12)
(R0.05) TYP
12
25
13
8X (1.12)
24
METAL TYP
8X (0.56)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED COVERAGE BY AREA
SCALE: 12X
4219205/A 02/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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