TPS53511_V01 [TI]
4.5-V to 18-V Input, 1.5-A Step-Down Regulator with Integrated Switcher;
| 型号： | TPS53511_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.5-V to 18-V Input, 1.5-A Step-Down Regulator with Integrated Switcher |
| 文件： | 总25页 (文件大小：1177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS53511
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SLUSBG4A –MARCH 2013–REVISED JANUARY 2014
4.5-V to 18-V Input, 1.5-A Step-Down Regulator with Integrated Switcher
Check for Samples: TPS53511
1
FEATURES
APPLICATIONS
2
•
•
•
•
Continuous 1.5-A Output Current
4.5-V to 18-V Supply Voltage Range
2-V to 18-V Conversion Voltage Range
•
•
Points-of-Load for Server
Distributed Non-Isolated DC-DC Converters for
Computing Power System
DCAP2™ Mode Control Enables Fast Transient
Response
DESCRIPTION
The TPS53511 is an adaptive on-time D-CAP2™
mode synchronous buck converter. The device is
suitable for points-of-load (POL) in computing power
•
Low Output Ripple and Support all MLCC
Output Capacitor
•
•
Skip Mode for Light Load Control
systems, and provides
a
cost-effective, low
component count, low standby current solution. The
main control loop for the TPS53511 uses the D-
CAP2™ mode control providing a fast transient
response with no external components. The adaptive
on-time control supports seamless operation between
PWM mode during heavy load conditions and
reduced frequency operation during light load
conditions for high efficiency.
Highly Efficient Integrated FETs Optimized for
Lower Duty Cycle Applications
•
High Efficiency, Less than 10-µA Supply
Current at Shutdown
•
•
•
•
•
•
•
Adjustable Soft-Start Time
Support Pre-Biased Soft Start
700-kHz Switching Frequency
Cycle-By-Cycle Overcurrent Limit
Open Drain Power Good Indication
Internal Bootstrap Switch
The TPS53511 includes a proprietary circuit that
enables the device to adapt to both low equivalent
series resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device operates from 4.5-V to 18-V
supply input, and from 2-V to 18-V input power supply
voltage. The device features an adjustable slow start
time and a power good function. It also supports pre-
biased soft start. The TPS53511 is available in the
16-pin QFN package, and designed to operate from
–40°C to 85°C.
Small 3 mm × 3 mm, 16-Pin QFN (RGT)
Package
TYPICAL APPLICATION
+
VIN
–
16
VO
15
14
VIN
13
VCC
VIN
VBST 12
1
2
3
4
VFB
SGND PGND
VREG5
SS
SW 11
SW 10
TPS53511
+
GND
PG
9
SW
VOUT
EN
PGND PGND
5
6
7
8
–
Output Signal
Input Signal
UDG-13043
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
DCAP2, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013–2014, Texas Instruments Incorporated
TPS53511
SLUSBG4A –MARCH 2013–REVISED JANUARY 2014
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
ORDERING DEVICE
NUMBER
MINIMUM
QUANTITY
TA
PACKAGE
PINS
OUTPUT SUPPLY
ECO PLAN
TPS53511RGTR
TPS53511RGTT
Tape and reel
Mini reel
3000
250
Plastic QFN
(RGT)
Green (RoHS and
no Pb/Br)
–40°C to 85°C
16
ABSOLUTE MAXIMUM RATINGS(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–2
MAX
20
UNIT
VIN, VCC, EN
VBST
26
VBST(with respect to SW)
Input voltage range
6.5
6.5
20
V
SS, VO, VFB
dc
SW
transient < 10 ns
–3
20
Voltage differential
Output voltage range
Output current
GND to PowerPAD
PG, VREG5
–0.2
–0.3
–0.3
0.2
6.5
0.3
1.5
2000
500
150
150
V
V
A
V
PGND
IOUT
Human Body Model (HBM)
Charged Device Model (CDM)
Electrostatic Discharge
Storage junction temperature
Operating junction temperature
–55
–40
˚C
˚C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.
2
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RECOMMENDED OPERATING CONDITIONS
MIN
2.0
TYP
MAX
18.0
18.0
18.0
24.0
5.7
UNIT
VIN
VCC
EN
4.5
–0.1
–0.1
–0.1
–0.1
–1.8
–3
V
VBST
Input voltage range
VBST(with respect to SW)
VO, VFB, SS
5.5
dc
SW
18.0
18
transient , <10 ns
PG, VREG5
Output voltage range
PGND
–0.1
–0.1
–40
–40
5.7
V
0.1
Junction temperature range, TJ
125
85
°C
°C
Operating free-air temperature, TA
THERMAL INFORMATION
TPS53511
QFN (RGT)
16 PINS
45.3
THERMAL METRIC(1)
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
57.3
18.4
°C/W
ψJT
1.1
ψJB
18.4
θJCbot
3.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VVIN = 12 V, PGND = GND (unless otherwise noted).(1)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX UNIT
Operating, non-switching supply
current
IVCC
TA = 25°C, VEN = 5 V, VVFB = 0.8 V
TA = 25°C, VEN = 0 V
850
1.8
1300
10
µA
µA
IVCC(sdn)
Shutdown supply current
LOGIC THRESHOLD
VENH
VENL
EN high-level input voltage
EN low-level input voltage
2
V
V
0.4
VVFB VOLTAGE AND DISCHARGE RESISTANCE
Voltage light load mode
TA = 25°C, VOUT = 1.05 V, IOUT = 10 mA
771
765
mV
mV
TA = 25°C, VOUT = 1.05 V
757
753
751
-0.1
773
777
779
0.1
VVFB
(2)
Threshold voltage, continuous mode TA = 0°C to 85°C, VOUT = 1.05 V
TA = –40°C to 85°C, VOUT = 1.05 V(2)
IVFB
Input current
VFB = 0.8 V, TA = 25°C
0
µA
RDischg
VO discharge resistance
VEN = 0 V, VOUT = 0.5 V, TA = 25°C
50
100
Ω
VVREG5 OUTPUT
VVREG5 Output voltage
VLN5
TA = 25°C, 6 V < VVCC < 18 V, 0 < IVREG5 < 5 mA
6 V < VVCC < 18 V, IVREG5 = 5 mA
0 < IVREG5 < 5 mA
5.3
5.5
70
5.7
20
V
Line regulation
Load regulation
Output current
mV
mV
mA
VLD5
100
IVREG5
MOSFET
RDS(on)H
RDS(on)L
Vcc = 6 V, VVREG5 = 4 V, TA = 25°C
High-side switch resistance
Low-side switch resistance
TA = 25°C, (VBST–VSW) = 5.5 V
TA = 25°C
120
70
mΩ
mΩ
CURRENT LIMIT
IOCL
Current limit
LOUT = 1.5 µH(2)
1.65
2.00
2.75
A
THERMAL SHUTDOWN
Shutdown temperature(2)
Hysteresis(2)
150
25
TSDN
Thermal shutdown threshold
°C
(1) See PS pin description for levels.
(2) Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VVIN = 12 V, PGND = GND (unless otherwise noted).()
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ON-TIME TIMER CONTROL
tON
On time
VVIN = 12 V, VOUT = 1.05 V
145
260
ns
tOFF(min)
Minimum off time
TA = 25°C, VVFB = 0.7 V
310
2.6
ns
SOFT-START FUNCTION
ISSC Soft-start charge current
ISSD Soft-start discharge current
VSS = 0 V
1.4
0.1
2.0
0.2
µA
VSS = 0.5 V
mA
POWER GOOD
VVFB rising (good)
VVFB falling (fault)
VVFB rising (fault)
VVFB falling (good)
VPG = 0.5 V
85%
110%
2.5
90%
85%
95%
VTHPG(UV) Power good undervoltage threshold
115% 120%
110%
VTHPG(OV) Power good overvoltage threshold
IPG
Sink current
5.0
mA
µs
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
OVP detect
110%
65%
115% 120%
5
tOVPDEL
Output OVP propagation delay
UVP detect
Hysteresis
70%
10%
75%
VUVP
Output UVP trip threshold
tUVPDEL
tUVPEN
Output UVP delay
0.25
ms
V
Output UVP enable delay
Relative to soft-start time
tSS×1.7
UNDERVOLTAGE LOCKOUT
Wake-up VREG5 voltage threshold
Hysteresis VREG5 voltage threshold
3.55
0.23
3.80
0.35
4.05
0.47
UVLO
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DEVICE INFORMATION
PIN FUNCTIONS
PIN
I/O/P
DESCRIPTION
NAME
EN
NO.
6
I
Enable control input
Signal ground pin
GND
PG
4
–
5
O
Open drain power good output
7
Ground returns for low-side MOSFET. Also serves as inputs of current comparators. Connect PGND and
GND strongly together near the device.
PGND
SS
P
8
3
I/O
Soft-start control. An external capacitor should be connected to GND.
9
Switch node connection between high-side N-channel FET and low-side N-channel FET. Also serves as
inputs to current comparator.
SW
10
11
I/O
Supply input for high-side N-channel FET gate driver (boost terminal). Connect capacitor from this pin to
respective SW terminals. An internal PN diode is connected between VREG5 to VBST pin.
VBST
12
I
VCC
VFB
15
1
I
I
Supply input for 5V internal linear regulator for the control circuitry
Converter feedback input. Connect with feedback resistor divider.
13
14
16
2
VIN
I
Power input and connected to high side N-channel FET drain
VO
I
Connect to output of converter. This terminal is used for on-time adjustment.
5.5-V power supply output. A capacitor (typical 1-µF) should be connected to GND.
VREG5
O
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to
PGND.
PowerPAD
–
RGT PACKAGE
16 PIN
(TOP VIEW)
16
15
14
13
VFB
VREG5
SS
1
2
3
4
12 VBST
11 SW
10 SW
TPS53511
PowerPAD TM
GND
9
SW
5
6
7
8
6
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SLUSBG4A –MARCH 2013–REVISED JANUARY 2014
FUNCTIONAL BLOCK DIAGRAM
VREF –30%
+
+
UV
TPS53511
VREG5
VO 16
VCC
15 VCC
OV
GND
VREG5
VFB
4
2
1
Reference
UVLO
Ref
12 VBST
VREF +15%
VREG5
14 VIN
13 VIN
VREF
+
+
Soft
SS
3
1-shot
Start
9
XCON
SW
VREF +15%
+
+
VREG5
11 SW
SW
10
7
VREF –15%
PGND
PGND
PG
EN
5
6
SW
UV
OV
+
ZC
8
PGOOD Logic
PGND
Protection
Logic
UVLO
TSD
SW
+
OCP
Enable Logic
PGND
UDG-13088
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DETAILED DESCRIPTION
The TPS53511 is a 1.5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
PWM Operation
The main control loop of the TPS53511 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot timer is set by the converter input voltage, VVIN, and the output voltage, VVO, to
maintain a pseudo-fixed frequency over the output voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the
need for ESR induced output ripple from D-CAP2™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS53511 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
device runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to set the
on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output
voltage. The actual frequency may vary from 700 kHz depending on the off time, which is ended when the fed
back portion of the output voltage falls to the VFB threshold voltage.
Light Load Mode Control
The TPS53511 is designed with Auto-Skip mode to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1.
V
- V
´ V
(
)
OUT OUT
V
IN
1
IN
I
=
´
OUT(LL)
2´L ´ f
SW
(1)
Soft-Start and Pre-Biased Soft-Start Function
The soft-start time function is adjustable. When the EN pin becomes high, 2-µA current begins charging the
capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during
start up. The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source
current is 2 µA.
CSS ´ VREF CSS ´0.765
=
tSS ms
=
( )
ISS mA
2
( )
where
•
•
CSS is the value of the capacitor connected between the SS pin and GND
CSS is expressed in nF
(2)
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This unique circuit prevents current from being pulled from the output during startup if the output is pre-biased.
When the soft-start commands a voltage higher than the pre-bias level (internal soft-start voltage becomes
greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first
low-side FET gate driver pulses with a narrow on-time. It then increments the on-time on a cycle-by-cycle basis
until it coincides with the time dictated by (1–D), where D is the duty cycle of the converter. This scheme
prevents the initial sinking of the pre-bias output, and ensures that the output voltage (the VO pin) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
Power Good
The power good function is activated after soft-start has finished. The power good function becomes active after
1.7 times soft-start time. When the feedback voltage is within ±10% of the target value, internal comparators
detect power good state and the power good signal becomes high. The power good output, PG, is an open drain
output. When the feedback voltage goes ±15% outside of the target value, the power good signal becomes low
after 10-µs internal delay. During an undervoltage condition, when the feedback voltage returns to be within
±10% of the target value, the power good signal goes HIGH again.
Output Discharge Control
TPS53511 discharges the output when EN is low, or the controller is turned off by the protection function (OVP,
UVP, UVLO and thermal shutdown). The output is discharged by an internal 50-Ω MOSFET which is connected
from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge operation to
avoid the possibility of causing negative voltage at the output.
Current Protection
Output current is limited by cycle-by-cycle overcurrent limiting control. The inductor current is monitored during
the OFF state and the controller keeps the OFF state when the inductor current is larger than the over current
trip level. To provide accuracy and a cost-effective solution, the device supports temperature compensated
internal MOSFET RDS(on) sensing.
The inductor current is monitored by the voltage between the PGND pin and the SW pin. In an overcurrent
condition, the current to the load exceeds the current to the output capacitor; thus, the output voltage tends to fall
off. Eventually the output voltage becomes less than the undervoltage protection threshold and the device shuts
down.
Overvoltage/Undervoltage Protection
The TPS53511 detects over and under-voltage conditions by monitoring the feedback voltage (the VFB pin). This
function is enabled after approximately 1.7 times the soft-start time. When the feedback voltage becomes higher
than 115% of the target voltage, the OVP comparator output goes high and the circuit latches the high-side
MOSFET driver turns off and the low-side MOSFET turns on. Normal operation can be restored only by cycling
the VCC or EN pin voltage. When the feedback voltage becomes lower than 70% of the target voltage, the UVP
comparator output goes high and an internal UVP delay counter begins. After 250 µs, the device latches off both
internal high-side and low-side MOSFET. Similar to the overvoltage protection, the device is latched off, and
normal operation can be restored only by cycling the VCC or EN pin voltage.
UVLO Protection
Undervoltage lockout protection (UVLO) monitors the voltage of the VVREG5 pin. When the VVREG5 voltage is lower
than UVLO threshold voltage, the TPS53511 is shut off. This protection is non-latching.
Thermal Shutdown
Thermal protection is self-activating. If the junction temperature exceeds the threshold value (typically 150°C),
the TPS53511 shuts off. This protection is non-latching.
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TYPICAL CHARACTERISTICS
1200
1000
800
8
6
4
600
400
200
0
2
0
-50
0
50
100
150
-50
0
50 100
TJ - Junction Temperature - °C
150
TJ - Junction Temperature - °C
Figure 1. VCC SUPPLY CURRENT vs. JUNCTION
TEMPERATURE
Figure 2. VCC SHUTDOWN CURRENT VS. JUNCTION
TEMPERATURE
1.100
1.1
IO = 10 mA
1.075
1.075
1.05
1.025
1
1.050
1.025
1.000
IO = 1 mA
V
IN
V
IN
V
IN
= 15 V
= 12 V
= 18 V
0
0.25
0.50
0.75
1.00
1.25
1.50
0
5
10
VI - Input Voltage - V
15
20
Output Current (A)
Figure 3. 1.05-V Output Voltage vs. Output Current
Figure 4. 1.05-V Output Voltage vs. Input Voltage
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TYPICAL CHARACTERISTICS (continued)
VOUT (1 V/div)
EN (5 mV/div)
VOUT (20 mV/div)
IOUT (2 A/div)
IOUT (1 A/div)
PGOOD (5 V/div)
Time (200 µs/div)
Time (400 µs/div)
Figure 5. Load Transient Response, 1.05-V, 0-A TO 1.5-A
Figure 6. Start-Up
95
90
85
80
75
70
65
60
55
90
85
V
= 12 V
IN
1.5-µH Inductor
9.7-mΩ DCR
80
75
70
65
60
VOUT = 1.2 V
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 1.2 V
V
= 12 V
1.5-µH Inductor
IN
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 2.5 V
55
50
9.7-uQꢀꢁꢂZ
50
10
20
30
40
50
60
70
80
90
100
0
0.25
0.50
0.75
1.00
1.25
1.50
Output Current (mA)
Output Current (A)
Figure 7. Efficiency vs. Output Current
Figure 8. Light Load Efficiency vs. Output Current
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TYPICAL CHARACTERISTICS (continued)
900
900
800
700
600
500
800
700
VO = 1.8 V
600
500
400
300
200
100
0
VO = 1.8 V
VO = 2.5 V
VO = 3.3 V
0.001
0.01
IO - Output Current - A
0.1
0
5
10
VI - Input Voltage - V
Figure 9. Switching Frequency vs Input Voltage
15
20
Figure 10. Switching Frequency vs Output Current
VIN (10 mV/div)
VOUT (10 mV/div)
SW (5 V/div)
SW (5 V/div)
Time (400 ns/div)
Time (400 ns/div)
Figure 11. Output Voltage Ripple
Figure 12. Input Voltage Ripple
12
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APPLICATION INFORMATION
The following example illustrates the design process and component selection for a single output synchronous
buck converter using TPS53511. The schematic of a design example is shown in Figure 13. The specification of
the converter is listed in Table 1.
Table 1. Specification of the Single Output Synchronous Buck Converter
PARAMETER
Input voltage
Output voltage
TEST CONDITION
MIN
TYP
12
MAX UNIT
VIN
4.5
18
V
V
V
VOUT
1.05
VRIPPLE Output ripple
IOUT = 1.5 A
3% of
VOUT
IOUT
fSW
Output current
1.5
A
Switching frequency
700
kHz
C1
10 PF
C2
10 PF
VIN
R1
8.25 k:
16
15
VCC
14
13
C3
VO
VIN
VIN
0.1 PF
1
2
3
VFB
VBST 12
SGND
PGND
3.3 PH
VREG5
SS
SW 11
SW 10
R2
22.1 k:
TPS53511
C7
1 PF
+
C6
3300 pF
R3
VOUT
C5
22 PF
C4
22 PF
4
GND
PG
5
9
100 k:
SW
EN PGND PGND
6
7
8
±
Output Signal
Input Signal
UDG-13044
Figure 13. Typical 12-V Input Application Circuit
Output Inductor Selection
The value of the output filtering inductor determines the magnitude of the current ripple, which also affects the
output voltage ripple for a certain output capacitance value. Increasing the inductance value reduces the ripple
current, and thus, results in reduced conduction loss and output ripple voltage. Alternatively, low inductance
value is needed due to the demand of low profile and fast transient response. Therefore, it is important to obtain
a compromise between the low ripple current and low inductance value.
In practical application, the peak-to-peak current ripple is usually designed to be between 1/4 to1/2 of the rated
load current. Since the magnitude of the current ripple is determined by inductance value, switching frequency,
input voltage and output voltage, the required inductance value for a certain required ripple ∆I is shown in
Equation 3. Also, the chosen inductor should be rated for the peak current calculated from Equation 4.
V
- V
´ V
(
)
OUT OUT
IN
L =
V
´I
´ f
IN RIPPLE SW
(3)
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I
æ
ç
è
ö
÷
ø
RIPPLE
IL peak = IOUT
+
(
)
2
where
•
•
•
•
VIN is the input voltage
VOUT is the output voltage
IRIPPLE is the required current ripple
ƒSW is the switching frequency
(4)
For this design example, the inductance value is selected to provide approximately 30% peak-to-peak ripple
current at maximum load. For this design, a nearest standard value was chosen: 3.3 µH. For 3.3 µH, the
calculated peak current is 1.71 A.
Output Capacitor Selection
The capacitor value and ESR determines the amount of output voltage ripple. Recommend to use ceramic output
capacitor. Using Equation 5 to Equation 6, an initial estimate for the capacitor value and ESR can be calculated.
Of the load transients are significant consider using the load step, instead of ripple current to calculate the
maximum ESR.
1
1
C >
´
V
8´ f
RIPPLE
SW
- ESR
I
RIPPLE
(5)
(6)
VOUT ripple
(
)
ESR <
IRIPPLE
For this design, the minimum required capacitance is 8.45 µF and maximum ESR is 33 mΩ. Therefore, two TDK
C3216JB0J226M 22-µF output capacitors are used. The maximum ESR is 12 mΩ for each capacitor.
Input Capacitor Selection
The device requires an input decoupling capacitor and a bulk capacitor. A ceramic capacitor over 10 µF is
recommended for the decoupling capacitor. The capacitor voltage rating must to be greater than the maximum
input voltage. In case of separate VVCC and VVIN, a ceramic capacitor over 10 µF is recommended for the input
voltage. Placing a ceramic capacitor with a value higher than 0.1-µF for the VCC is recommended also.
Bootstrap Capacitor Selection
A 0.1-µF capacitor must be connected between the VBST and SW pin for proper operation. A ceramic capacitor
is recommended.
VREG5 Capacitor Selection
A 1-µF capacitor must be connected between the VREG5 and SW pin for proper operation. A ceramic capacitor
is recommended.
14
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Output Voltage Setting Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Begin by using Equation 7 and Equation 8 to calculate VOUT
.
To improve efficiency at light-load condition, use resistors with a relatively larger value. However, too high
resistance value make the circuit more susceptible to noise, and voltage errors from the VFB input current is
more noticeable.
For output voltages from 0.76 V to 2.5 V:
æ
ö
÷
ø
R1
R2
æ
ö
V
= 0.765´ 1+
ç
OUT
ç
÷
è
ø
è
(7)
For output voltages over 2.5 V:
R1
R2
æ
ö
VOUT = 0.763 + 0.0017 ´ V
´ 1+
(
)
OUT
ç
÷
è
ø
(8)
The required output voltage for this design is 1.05 V. So Equation 7 is used to calculate the value of R1. R2 is
22.1 kΩ, therefore, R1 is 8.25 kΩ.
Thermal Information
This PowerPAD™ package incorporates an exposed thermal pad that is designed to be connected to an external
heat sink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heat sink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heat sink structure designed into the PCB. This design optimizes the heat transfer from the device.
For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Lilterature
Number SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature Number
SLMA004
Layout Considerations
•
•
Keep the input switching current loop as small as possible
Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
•
•
•
•
•
•
•
•
•
•
•
•
•
Keep analog and non-switching components away from switching components.
Make a single point connection between the signal and power grounds.
Do not allow switching current to flow under the device.
Keep the pattern lines for VIN and PGND broad.
Exposed pad of the device must be connected to PGND with solder.
VREG5 capacitor should be connected to a broad pattern of the PGND.
Output capacitor should be connected to a broad pattern of the PGND.
Voltage feedback loop should be as short as possible, and preferably with ground shield.
Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
Providing sufficient via is preferable for VIN, SW and PGND connection.
PCB pattern for VIN, SW and PGND should be as broad as possible.
If VIN and VCC are shorted, VIN and VCC patterns need to be connected with broad pattern lines.
VIN capacitor should be placed as close as possible to the device.
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Changes from Original (MARCH 2013) to Revision A
Page
•
•
•
•
•
•
•
•
Changed minimum value for Current limit specification in Electrical characteristics table ................................................... 4
Changed Figure 3 ............................................................................................................................................................... 10
Changed Figure 5 ............................................................................................................................................................... 11
Changed Figure 6 ............................................................................................................................................................... 11
Changed Figure 7 ............................................................................................................................................................... 11
Changed Figure 11 ............................................................................................................................................................. 12
Changed Figure 12 ............................................................................................................................................................. 12
Changed Figure 13 ............................................................................................................................................................. 13
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
HPA02165RGTR
TPS53511RGTR
TPS53511RGTT
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
RGT
RGT
RGT
16
16
16
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
53511
53511
53511
NIPDAU
NIPDAU
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS53511RGTR
TPS53511RGTT
VQFN
VQFN
RGT
RGT
16
16
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS53511RGTR
TPS53511RGTT
VQFN
VQFN
RGT
RGT
16
16
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/C 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/C 04/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/C 04/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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