TPS53317A [TI]

0.9V 至 6V 输入、6A 输出、D-CAP+ 模式的 SWIFT 同步降压 DDR VTT 转换器;


型号：	TPS53317A
厂家：	TEXAS INSTRUMENTS
描述：	0.9V 至 6V 输入、6A 输出、D-CAP+ 模式的 SWIFT 同步降压 DDR VTT 转换器双倍数据速率转换器
文件：	总33页 (文件大小：1643K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS53317A

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

TPS53317A 用于 DDR 存储器终端的 6A 输出、D-CAP+ 模式、同步降压

集成 FET 转换器

1 特性

3 说明

•

采用 TI 专有的集成金属氧化物半导体场效应晶体管

(MOSFET) 和封装技术

TPS53317A 器件是一款设计为主要用于 DDR 终端的

集成场效应晶体管 (FET) 同步降压稳压器。它能够提

供一个值为 ½ V_DDQ的经稳压输出，此输出具有吸收电

流和源电流功能。 TPS53317A 器件采用 D-CAP+ 运

行模式，简单易用，所需外部组件数较少并可提供快速

瞬态响应。该器件还可用于其他电流要求高达 6A 的

负载点 (POL) 稳压应用。此外，该器件支持具有严格

电压调节功能的 6A 完整灌电流输出。

•

支持 DDR 内存终止，具有高达 6A 的持续输出源

电流或者吸收电流

•

外部跟踪

最少的外部组件数

0.9V 至 6V 转换电压

D-CAP+™ 模式架构

支持所有多层片式陶瓷输出电容器和 SP/POSCAP

可选跳跃 (SKIP) 模式或者强制 CCM

轻量级负载与重负载下的优化效率

可选 600kHz 或者1MHz 开关频率

可选过流限制 (OCL)

该器件具有两种开关频率设定值（600kHz 和

1MHz），可提供集成压降支持、外部跟踪功能、预偏

置启动、输出软放电、集成自举开关、电源正常功能、

V5IN 引脚欠压锁定 (UVLO) 保护功能，支持采用陶瓷

和 SP/POSCAP 电容。该器件支持的输入电压最高可

达 6V，而输出电压在 0.45V 至 2.0V 范围内可调。

过压、过热和断续欠压保护

可调输出电压范围为 0.45V 至 2V

TPS53317A 器件采用 3.5mm × 4mm 20 引脚超薄四

方扁平无引线 (VQFN) 封装（绿色环保，符合 RoHS

标准并且无铅），其中应用了 TI 专有的集成 MOSFET

和封装技术，其额定运行温度范围为 –40°C 至 85°C。

3.5mm × 4mm 20 引脚超薄四方扁平无引线

(VQFN) 封装

2 应用

•

用于 DDR、DDR2、DDR3 和 DDR4 的存储器终

端稳压器

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

•

VTT 终止

TPS53317A

VQFN (20)

3.50mm × 4.00mm

用于 0.9V 至 6V 输入电源轨的低电压应用

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

简化应用

DDR VDDQ IN

VIN

BST

TPS53317A

VTT

COMP

VREF

PGOOD

PGND

VOUT

MODE

GND

REFIN

V5IN

5VIN

PowerPAD

UDG-11105

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSC63

TPS53317A

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 15

Application and Implementation ........................ 19

8.1 Application Information............................................ 19

8.2 Typical Applications ............................................... 19

Power Supply Recommendations...................... 25

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 10

10 Layout................................................................... 25

10.1 Layout Guidelines ................................................. 25

10.2 Layout Example .................................................... 25

11 器件和文档支持 ..................................................... 26

11.1 社区资源................................................................ 26

11.2 商标....................................................................... 26

11.3 静电放电警告......................................................... 26

11.4 Glossary................................................................ 26

12 机械、封装和可订购信息....................................... 26

4 修订历史记录

Changes from Original (November 2015) to Revision A

Page

•

文档状态已由产品预览更改为量产数据。 .............................................................................................................................. 1

TPS53317A

www.ti.com.cn

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

5 Pin Configuration and Functions

RGB Package

20-Pin VFQN

Top View

19 18 17 16

PGND

VIN

Exposed

Thermal Pad

VIN

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

BST

NO.

Power supply for internal high-side gate driver. Connect a 0.1-µF bootstrap capacitor between

this pin and the SW pin. Include a series boot resistor when the voltage spike on switching node

is above 7 V.

COMP

Connect an R-C-C network between this pin and VREF for loop compensation.

Enable pin (3.3-V logic compatible).

GND

MODE

–

Analog ground.

Allows selection of different operation modes. (See 表 1)

PGND

Power ground.

PGOOD

REFIN

Open drain power good output. Connect pullup resistor.

External tracking reference input. Apply voltage between 0.45 V to 2.0 V. For non-tracking mode,

connect REFIN to VREF via resistor divider.

I/O

Switching node output.

V5IN

VIN

5-V power supply for analog circuits and gate drive.

Power supply input pin.

VOUT

VREF

Output voltage monitor input pin.

2.0-V reference output. Connect a ceramic capacitor with a value of 0.22-µF or greater between

this pin and GND.

(1) I = Input, O = Output, G = Ground

TPS53317A

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

–1

MAX

UNIT

BST (with respect to SW), V5IN, VIN

BST

Input voltage range

Output voltage range

MODE, REFIN

3.6

VOUT

–2

SW (transient 20 ns and E = 5 µJ)

–3

COMP, VREF

PGOOD

–0.3

–40

3.6

PGND

0.3

150

300

150

Operating junction temperature, T_J

˚C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

Storage temperature, T_stg

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

–0.1

4.5

NOM

MAX

6.5

UNIT

BST (with respect to SW), EN, VIN

V5IN

6.5

Input voltage range

BST

–0.1

–1.0

–0.1

13.5

6.5

VOUT, MODE, REFIN

COMP

3.5

VREF

Output voltage range

PGOOD

–0.1

-40

6.5

0.1

PGND

Operating temperature range, T_A

°C

TPS53317A

www.ti.com.cn

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

6.4 Thermal Information

TPS53317A

THERMAL METRIC⁽¹⁾

RGB (VQFN)

20 PINS

35.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

39.6

12.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

12.5

R_θJC(bot)

3.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

over recommended free-air temperature range, V_V5IN= 5.0 V, PGND = GND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY: VOLTAGE, CURRENTS AND 5-V UVLO

I_VINSD

V_V5IN

VIN shutdown current

V5IN supply voltage

EN = 'LO'

0.02

5.0

µA

V5IN voltage range

4.5

6.5

EN =’HI’, V5IN supply current, f_SW

= 600 kHz

I_V5IN

V5IN supply current

1.1

I_V5INSD

V5IN shutdown current

V5IN UVLO

EN = ‘LO’, V5IN shutdown current

Ramp up; EN = 'HI'

0.2

4.37

440

1.8

7.0

µA

V_V5UVLO

4.20

1.5

4.50

V_V5UVHYS

V_VREFUVLO

V_VREFUVHYS

V5IN UVLO hysteresis

REF UVLO⁽¹⁾

REF UVLO hysteresis⁽¹⁾

Falling hysteresis

Rising edge of VREF, EN = 'HI'

100

OVP latch is reset by V5IN falling

below the reset threshold

V_POR5VFILT

Reset

2.3

3.1

VOLTAGE FEEDBACK LOOP: VREF, VOUT, AND VOLTAGE GM AMPLIFIER

V_REFIN= 1 V, No droop

V_REFIN= 0.6 V, No droop

I_VREF= 0 µA

–1%

V_OUTTOL

Output voltage accuracy

VREF

1.98

2.00

2.000

2.5

2.02

2.025

V_VREF

I_VREF= 50 µA

1.975

I_REFSNK

g_M

VREF sink current

V_VREF= 2.05 V

Transconductance

Common mode input voltage range⁽¹⁾

1.00

V_CM

V_DM

Differential mode input voltage

V_COMP= 2 V, (V_REFIN– V_OUT) = 80

I_COMPSNK

COMP pin maximum sinking current

µA

I_COMPSRC

V_OFFSET

R_DSCH

COMP pin maximum sourcing current

Input offset voltage

V_COMP= 2 V

T_A= 25°C

-80

µA

Output voltage discharge resistance

–3dB Frequency⁽¹⁾

6.0

f_–3dbVL

4.5

7.5

MHz

CURRENT SENSE: CURRENT SENSE AMPLIFIER, OVERCURRENT AND ZERO CROSSING

Gain from the current of the low-

side FET to PWM comparator

when PWM = "OFF"

A_CSINT

Internal current sense gain

mV/A

I_OCL

Positive overcurrent limit (valley)

Negative overcurrent limit (valley)

Zero crossing comp internal offset

7.6

–9.3

I_OCL(neg)

V_ZXOFF

(1) Ensured by design, not production tested.

TPS53317A

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

Electrical Characteristics (continued)

over recommended free-air temperature range, V_V5IN= 5.0 V, PGND = GND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN

PGOOD deassert to lower

(PGOOD → Low)

Measured at the VOUT pin wrt/

V_REFIN

V_PGDLL

84%

V_PGHYSHL

V_PGDLH

PGOOD high hysteresis

PGOOD de-assert to higher

(PGOOD → Low)

Measured at the VOUT pin wrt/

V_REFIN

116%

-8%

V_PGHYSHH

PGOOD high hysteresis

Measured at the VIN pin with a 2-

mA sink current on PGOOD pin.

V5IN is grounded here.⁽²⁾

V_INMINPG

Minimum VIN voltage for valid PGOOD

0.9

117%

65%

1.3

120%

68%

1.5

123%

71%

Measured at the VOUT pin wrt/

V_REFIN,V_REFIN= 1 V

V_OVP

OVP threshold

UVP threshold

Measured at the VOUT pin wrt/

V_REFIN, device latches OFF, begins

soft-stop, V_REFIN= 1 V

V_UVP

Latch off controller, attempt soft-

stop.

TH_SD

Thermal shutdown⁽¹⁾

145

°C

Controller re-starts after

temperature has dropped

TH_SD(hys)

Thermal Shutdown hysteresis⁽¹⁾

DRIVERS: BOOT STRAP SWITCH

R_DSONBSTInternal BST switch on-resistance

I_BSTLKInternal BST switch leakage current

TIMERS: ON-TIME, MINIMUM OFF-TIME, SS, AND I/O TIMINGS

I_BST= 10 mA, T_A= 25°C

V_BST= 14 V, V_SW= 7 V

µA

V_VIN= 5 V, V_VOUT= 1.05 V, f_SW= 1

MHz

210

310

t_ONESHOTC

PWM one-shot⁽¹⁾

V_VIN= 5 V, V_VOUT= 1.05 V, f_SW

600 kHz

V_VIN= 5 V, V_VOUT= 1.05 V, f_SW= 1

MHz, DRVL on,

t_MIN(off)

Minimum OFF time

270

SW = PGND, V_VOUT< V_REFIN

From V_OUTramp starting to V_OUT

=95%, default setting

t_INT(SS)

Soft-start time

1.6

260

µs

From V_VREF= 2 V to V_OUTis ready

to ramp up

t_INT(SSDLY)

t_PGDDLY

Internal soft-start delay time

PGOOD startup delay time

At external tracking, the time from

VOUT is ready to ramp up

t_PGDPDLYH

t_PGDPDLYL

PGOOD high propagation delay time

PGOOD low propagation delay time

50 mV over drive, rising edge

50 mV over drive, falling edge

0.8

1.2

µs

Time from the VOUT pin out of

+20% of REFIN to OVP fault

t_OVPDLY

t_UVDLYEN

t_UVPDLY

OVP delay time

µs

Time from EN_INT going high to

undervoltage fault is ready

Undervoltage fault enable delay

External tracking from VOUT ramp

starts

Time from the VOUT pin out of

–32% of REFIN to UVP fault

UVP delay time

256

LOGIC PINS: I/O VOLTAGE AND CURRENT

PGOOD low impedance, I_SINK= 4

mA, V_V5IN= 4.5 V

PGOOD pull-down voltage

0.3

PGOOD high impedance, forced to

5.5 V

PGOOD leakage current

–1

µA

EN logic high

EN logic low

EN, VCCP logic

0.5

EN input current

µA

(2) If V5IN is higher than 1.5 V, PGOOD is valid regardless of the voltage applied at VIN. This is based on bench testing.

TPS53317A

www.ti.com.cn

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

Electrical Characteristics (continued)

over recommended free-air temperature range, V_V5IN= 5.0 V, PGND = GND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

130

250

420

600

880

1250

1800

MAX

180

UNIT

Threshold 1

Threshold 2

Threshold 3

Threshold 4

Threshold 5

Threshold 6

Threshold 7

200

370

550

830

1200

1765

300

470

MODE threshold voltage⁽³⁾

650

930

1300

1850

MODE current

µA

(3) See 表 1 for descriptions of MODE parameters.

6.6 Typical Characteristics

Characterization data tested using the TPS53317AEVM-726 where the external tracking input sets the output voltage and

operates in non-droop mode. See SLUUBD2 for detailed configuration.

Ambient Temp T_A

œ40°C

0°C

25°C

60°C

85°C

œ40°C

0°C

25°C

60°C

85°C

V_IN= 1.2 V

V_OUT= 0.6 V

f_SW= 600 kHz PWM

V_IN= 1.5 V

V_OUT= 0.75 V

f_SW= 600 kHz PWM

Output Current (A)

C001

C004

图 1. Efficiency vs. Output Current

图 2. Efficiency vs. Output Current

Ambient Temp T_A

œ40°C

0°C

25°C

60°C

85°C

œ40°C

0°C

25°C

60°C

85°C

V_IN= 2.5 V

V_OUT= 0.6 V

f_SW= 600 kHz PWM

V_IN= 2.5 V

V_OUT= 0.75 V

f_SW= 600 kHz PWM

Output Current (A)

C002

C005

图 3. Efficiency vs. Output Current

图 4. Efficiency vs. Output Current

TPS53317A

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

Typical Characteristics (接下页)

Characterization data tested using the TPS53317AEVM-726 where the external tracking input sets the output voltage and

operates in non-droop mode. See SLUUBD2 for detailed configuration.

Ambient Temp T_A

œ40°C

0°C

25°C

60°C

85°C

œ40°C

0°C

25°C

60°C

85°C

V_IN= 3.3 V

V_OUT= 0.6 V

f_SW= 600 kHz PWM

V_IN= 3.3 V

V_OUT= 0.75 V

f_SW= 600 kHz PWM

Output Current (A)

C003

C006

图 5. Efficiency vs. Output Current

图 6. Efficiency vs. Output Current

0.610

0.608

0.606

0.604

0.602

0.600

0.598

0.596

0.594

0.592

0.590

0.760

0.758

0.756

0.754

0.752

0.750

0.748

0.746

0.744

0.742

0.740

V_IN= 1.2 V

f_SW= 600 kHz PWM

V_IN= 1.5 V

f_SW= 600 kHz PWM

Ambient Temp T_A

œ40°C

0°C

25°C

60°C

85°C

œ40°C

0°C

25°C

60°C

85°C

œ6

œ4

œ2

œ6

œ4

œ2

Output Current (A)

C007

C010

图 7. Load Regulation

图 8. Load Regulation

0.610

0.608

0.606

0.604

0.602

0.600

0.598

0.596

0.594

0.592

0.590

0.760

0.758

0.756

0.754

0.752

0.750

0.748

0.746

0.744

0.742

0.740

V_IN= 2.5 V

f_SW= 600 kHz PWM

V_IN= 2.5 V

f_SW= 600 kHz PWM

Ambient Temp T_A

œ40°C

0°C

25°C

60°C

85°C

œ40°C

0°C

25°C

60°C

85°C

œ6

œ4

œ2

œ6

œ4

œ2

Output Current (A)

C008

C011

图 9. Load Regulation

图 10. Load Regulation

TPS53317A

www.ti.com.cn

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

Typical Characteristics (接下页)

Characterization data tested using the TPS53317AEVM-726 where the external tracking input sets the output voltage and

operates in non-droop mode. See SLUUBD2 for detailed configuration.

0.610

0.608

0.606

0.604

0.602

0.600

0.598

0.596

0.594

0.592

0.590

0.760

0.758

0.756

0.754

0.752

0.750

0.748

0.746

0.744

0.742

0.740

V_IN= 3.3 V

f_SW= 600 kHz PWM

V_IN= 3.3 V

f_SW= 600 kHz PWM

Ambient Temp T_A

œ40°C

0°C

25°C

60°C

85°C

œ40°C

0°C

25°C

60°C

85°C

œ6

œ4

œ2

œ6

œ4

œ2

Output Current (A)

C009

C012

图 11. Load Regulation

图 12. Load Regulation

0.760

0.758

0.756

0.754

0.752

0.750

0.748

0.746

0.744

0.742

0.740

Skip Mode, f_SW= 600 kHz

Skip Mode, f_SW=1 MHz

PWM Mode, f_SW= 600 kHz

PWM Mode, f_SW= 1 MHz

Skip Mode, f_SW=1 MHz

PWM Mode, f_SW= 600 kHz

PWM Mode, f_SW= 1 MHz

Output Current (A)

G001

V_IN= 1.5 V

V_OUT= 0.75 V

V_IN= 1.5 V

V_OUT= 0.75 V

图 13. Efficiency vs Output Current

图 14. Load Regulation

1400

1200

1000

800

600

400

200

V_IN

1.8 V

V_OUT= 0.45 V, f_SW= 600 kHz

V_OUT= 0.6 V, f_SW= 600 kHz

V_OUT= 0.45 V, f_SW= 1 MHz

V_OUT= 0.6 V, f_SW= 1 MHz

T_A= 25°C

V_OUT= 0.9 V

f_SW= 600 kHz PWM

2.5 V

3.3 V

Input Voltage (V)

D001

Output Current (A)

C013

T_A= 25°C

I_OUT= 2 A

图 15. Efficiency vs. Output Current

图 16. Switching Frequency vs. Input Voltage

TPS53317A

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPS53317A device is a D-CAP+™ mode adaptive on-time converter. Integrated high-side and low-side

FETs support a maximum of 6-A DC output current. The converter automatically operates in discontinuous

conduction mode (DCM) to optimize light-load efficiency. Multiple switching frequencies are provided to enable

optimization of the power train for the cost, size and efficiency requirements of the design (see 表 1).

In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to

maintain a nearly constant frequency during steady-state conditions. In conventional constant on-time converters,

each cycle begins when the output voltage crosses to a fixed reference level. However, in the TPS53317A

device, the cycle begins when the current feedback reaches an error voltage level which is the amplified

difference between the reference voltage and the feedback voltage.

7.2 Functional Block Diagram

TPS53317A

19 PGOOD

V_REFIN+ 16%

V_REFINœ32%

Delay

V_REFINœ 16%

GND

V_REFIN+20%

COMP

REFIN

15 mA

Control Logic

UVP

OVP

On-Time

Selection

Amplifier

On/Off Time

18 MODE

16 BST

Minimum On/Off

SKIP/FPWM

OCL/OVP/UVP

Discharge

Ramp

Comp

DAC

PWM

EN 17

VIN

VREF

DRVH

Internal Voltage

Reference

VOUT 10

Current Sense

Amplifier

11 SW

12 SW

13 SW

14 SW

15 SW

20 V5IN

8 R

XCON

t_ON

One-

Shot

PGND

GND

Current

Sense

DRVL

ZC Threshold

Modulation

PGND

GND

Pad

Discharge

PGND

UDG-11106

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7.3 Feature Description

7.3.1 PWM Operation

Referring to 图 17, in steady state, continuous conduction mode, the converter operates in the following way.

Starting with the condition that the top FET is off and the bottom FET is on, the current feedback (V_CS) is higher

than the error amplifier output (V_COMP). V_CSfalls until it hits V_COMP, which contains a component of the output

ripple voltage. V_CSis not directly accessible by measuring signals on pins of TPS53317A device. The PWM

comparator senses where the two waveforms cross and triggers the on-time generator.

Current

Feedback

COMP

REF

Time (ms)

UDG-10187

图 17. D-CAP+™ Mode Basic Waveforms

The current feedback is an amplified and filtered version of the voltage between PGND and SW during low-side

FET on-time. The device also provides a single-ended voltage (V_OUT) feedback to increase the system accuracy

and reduce the dependence of circuit performance on layout.

7.3.2 PWM Frequency and Adaptive On-Time Control

In general, the on-time (at the SW node) can be estimated by 公式 1.

OUT

where

•

f_SWis the frequency selected by the connection of the MODE pin

(1)

The on-time pulse is sent to the top FET. The inductor current and the current feedback rises to peak value.

Each ON pulse is latched to prevent double pulsing. Switching frequency settings are shown in 表 1.

7.3.3 Light-Load Power Saving Features

The TPS53317A device has an automatic pulse-skipping mode to provide excellent efficiency over a wide load

range. The converter senses inductor current and prevents negative flow by shutting off the low-side gate driver.

This saves power by eliminating re-circulation of the inductor current. Further, when the bottom FET shuts off,

the converter enters discontinuous mode, and the switching frequency decreases, thus reducing switching losses

as well.

The device also provides a special light-load power saving feature, called ripple reduction. Essentially, it reduces

the on-time in SKIP mode to effectively reduce the output voltage ripple associated with using an all MLCC

capacitor output power stage design.

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Feature Description (接下页)

7.3.4 Power Sequences

7.3.4.1 Non-Tracking Startup

The TPS53317A device can be configured for non-tracking application. When non-tracking is configured, output

voltage is regulated to the REFIN voltage which taps off the voltage dividers from the 2-V reference voltage.

Either the EN pin or the V5IN pin can be used to start up the device. The device uses internal voltage servo DAC

to provide a 1.6-ms soft-start time during soft-start initialization. (See 图 19.)

In a non-tracking application, the output voltage is determined by the resistive divider between the VREF pin and

the REFIN pin.

V_OUT= V_REF

R1+ R2

(2)

TPS53317A

VREF

REFIN

图 18. Non-Tracking Configuration

EN AND

V5IN

VREF

400 µs typical

Internal soft-start delay time

260 µs typical

REFIN

+16%

+8%

Power good window,

œ5%

œ8%

œ16%

reference to REFIN

VOUT

Fixed

1.6 ms

soft-start

PGOOD

delay

1.0 ms

PGOOD

Time

图 19. Non-Tracking Startup Timing

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Feature Description (接下页)

7.3.4.2 Tracking Startup

The TPS53317A device can also be configured for tracking application. When tracking configuration is desired,

output voltage is also regulated to the REFIN voltage which comes from an external power source. In order for

the device to differentiate between a non-tracking configuration or a tracking configuration, there is a minimum

delay time of 260 µs required between the time when VREF reaches 2 V to the time when the REFIN pin voltage

can be applied, in order for the device to track properly (see 图 22). The valid REFIN voltage range is between

0.45 V and 2 V.

In a tracking application, the output voltage should be one half of the VDDQ voltage. VDDQ can be VIN or it can

be an additional voltage rail. Thus, R1= R2 both in 图 20 and 图 21.

V_OUT

´ V_VDDQ

(3)

TPS53317A

VIN

VDDQ

VIN

REFIN

VDDQ

图 20. Tracking Configuration 1

图 21. Tracking Configuration 2

EN and

V5IN

400 µs typical

VOUT is ready to ramp up

(REFIN can be applied)

VREF

450 mV

REFIN

260 µs

minimum

Loop

determined

operation

Forced

CCM

operation

VOUT

450 mV

PGOOD

startup

Delay

PGOOD propagation

delay 1.0 ms

8.0 ms

PGOOD

图 22. Tracking Startup Timing

Select PWM mode for an application that requires external tracking, because the output voltage can not be

decreased during a no-load condition when the device operates in SKIP mode.

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Feature Description (接下页)

7.3.5 Protection Features

The TPS53317A device offers many features to protect the converter power train as well as the system

electronics.

7.3.5.1 5-V Undervoltage Protection (UVLO)

The TPS53317A device continuously monitors the voltage on the V5IN pin to ensure that the voltage level is high

enough to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. The

converter starts with approximately 4.3 V and has a nominal 440 mV of hysteresis. If the 5-V UVLO limit is

reached, the converter transitions the phase node into an off function, and the converter remains in the off state

until the device is reset by cycling the 5-V supply until the 5-V POR is reached (2.3-V nominal). The power input

does not have a UVLO function.

7.3.5.2 Power Good Signals

The TPS53317A device has one open-drain power good (PGOOD) pin. During startup, there is a 1-ms power

good high propagation delay. The PGOOD pin de-asserts as soon as the EN pin is pulled low or an undervoltage

condition on V5IN or any other fault is detected.

7.3.5.3 Output Overvoltage Protection (OVP)

In addition to the power good function described above, the TPS53317A device has additional OVP and UVP

thresholds and protection circuits.

An OVP condition is detected when the output voltage is approximately 120% × V_REFIN. In this case, the

converter de-asserts the PGOOD signals and performs the overvoltage protection function. During OVP, the low-

side FET is always on before triggering a negative overcurrent. When a negative OC is also tripped, the low-side

FET is no longer continuously on, and pulsed signals are generated to limit the negative inductor current. When

the VOUT pin voltage drops below 250 mV, the low-side FET turns off and the converter latches off. The

converter remains in the off state until the device is reset by cycling the 5-V supply until the 5-V POR is reached

(2.3-V nominal) or when the EN pin is toggled off and on.

7.3.5.4 Output Undervoltage Protection (UVP)

Output undervoltage protection works in conjunction with the current protection described in the Overcurrent

Protection and Overcurrent Limit sections. If the output voltage drops below 68% of V_REFIN, after approximately a

250-µs delay, the device stops switching and enters hiccup mode. After a hiccup waiting time, a restart is

attempted. If the fault condition is not cleared, hiccup mode operation may continue indefinitely.

7.3.5.5 Overcurrent Protection

Both positive and negative overcurrent protection are provided in the TPS53317A device.

•

Overcurrent Limit (OCL)

Negative OCL

7.3.5.5.1 Overcurrent Limit

If the sensed current value is above the OCL setting, the converter delays the next ON pulse until the current

drops below the OCL limit. Current limiting occurs on a pulse-by-pulse basis. The device uses a valley current

limiting scheme where the DC OCL trip point is the OCL limit plus half of the inductor ripple current. The typical

valley OCL threshold is 7.6 A or 5.4 A (depending on mode selection). The average output current limit

calculation is shown in 公式 4.

During the overcurrent protection event, the output voltage droops if the duty cycle cannot satisfy output voltage

requirements and continues to droop until the UVP limit is reached. Then, the converter de-asserts the PGOOD

pin, and then enters hiccup mode after a 250-µs delay. The converter remains in hiccup mode until the fault is

cleared.

I_{OCL dc}= I_{OCL valley}

´I_P-P

( )

(

)

(4)

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Feature Description (接下页)

7.3.5.5.2 Negative OCL

The negative OCL circuit acts when the converter is sinking current from the output capacitor(s). The converter

continues to act in a valley mode, the typical value of the negative OCL set point is –9.3 A or –6.5 A (depending

on mode selection).

7.3.6 Thermal Protection

The TPS53317A device has an internal temperature sensor. When the temperature reaches a nominal 145°C,

the device shuts down until the temperature decreases by approximately 10°C, when the converter restarts.

7.4 Device Functional Modes

7.4.1 Non-Droop Configuration

The TPS53317A device can be configured as a non-droop solution. The benefit of a non-droop approach is that

load regulation is flat, therefore, in a system where tight DC tolerance is desired, the non-droop approach is

recommended. For the Intel system agent application, non-droop is recommended as the standard configuration.

The non-droop approach can be implemented by connecting a resistor and a capacitor between the COMP and

the VREF pins. The purpose of the type II compensation is to obtain high DC feedback gain while minimizing the

phase delay at unity gain cross over frequency of the converter.

The value of the resistor (R_C) can be calculated using the desired unity gain bandwidth of the converter, and the

value of the capacitor (C_C) can be calculated by knowing where the zero location is desired. The capacitor C_Pis

optional, but recommended. Its appropriate capacitance value can be calculated using the desired pole location.

图 23 shows the basic implementation of the non-droop mode using the device

C_P

R_C

C_C

V_IN

COMP

VREF

VOUT

g_MV= 1 mS

V_SLEW

L_OUT

g_MC= 1 mS

5river

ESR

R_DS(on)

PWM

Comparator

R_LOAD

R_OUT

8 kW

C_OUT

VREF

图 23. Non-Droop Mode Basic Implementation

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Device Functional Modes (接下页)

图 24 shows shows the load regulation using non-droop configuration.

图 25 shows the transient response of the device using non-droop configuration, where C_OUT= 3 x 47 µF. The

applied step load is from 0 A to 2 A.

0.85

0.83

0.81

0.79

0.77

0.75

0.73

0.71

0.69

0.67

Non−Droop Configuration

0.65

Output Current (A)

V_IN= 1.5 V

V_OUT= 0.75 V

CH 2: V_OUT

(20 mV/div)

CH 4: I_OUT

(1 A/div)

CH 3: SW

(1 V/div)

图 25. Non-Droop Configuration Transient Response

图 24. Load Regulation (Non-Droop Configuration)

7.4.2 Droop Configuration

The terminology for droop is the same as load line or voltage positioning as defined in the Intel CPU V_CORE

specification. Based on the actual tolerance requirement of the application, load-line set points can be defined to

maximize either cost savings (by reducing output capacitors) or power reduction benefits.

Accurate droop voltage response is provided by the finite gain of the droop amplifier. The equation for droop

voltage is shown in 公式 5.

´I

CSINT OUT

DROOP

´ g

DROOP

where

•

low-side on-resistance is used as the current sensing element

A_CSINTis a constant, which nominally is 53 mV/A.

I_OUTis the DC current of the inductor, or the load current

R_DROOPis the value of resistor from the COMP pin to the VREF pin

g_Mis the transconductance of the droop amplifier with nominal value of 1 mS

(5)

(6)

公式 6 can be used to easily derive R_DROOPfor any load line slope/droop design target.

CSINT

DROOP

CSINT

\ R

LOAD _LINE

DROOP

´ g

OUT

DROOP

LOAD _LINE M

Choose a value for the R_DROOPresistor that is below 20 kΩ. More than 20 kΩ of droop resistance may cause the

loop to become unstable.

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Device Functional Modes (接下页)

图 26 shows the basic implementation of the droop mode using the TPS53317A device.

R_DROOP

V_IN

COMP

VREF

VOUT

g_MV= 1 mS

V_SLEW

L_OUT

g_MC= 1 mS

5river

ESR

R_DS(on)

PWM

Comparator

R_LOAD

R_OUT

8 kW

C_OUT

VREF

图 26. DROOP Mode Basic Implementation

The droop (voltage positioning) method was originally recommended to reduce the number of external output

capacitors required. The effective transient voltage range is increased because of the active voltage positioning

(see 图 27).

Load insertion

OUT

Load release

Droop

setpoint at 0 A

OUT

Maximum transient voltage

= (5%œ1%) x 2 = 8% x V

OUT

setpoint at 6 A

OUT

Non-

Droop

Maximum overshoot voltage =(5%œ1%) x 1 = 4% x V

OUT

setpoint at 0 A

OUT

Maximum undershoot voltage =(5%œ1%) x 1 = 4% x V

OUT

图 27. DROOP vs Non-DROOP in Transient Voltage Window

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Device Functional Modes (接下页)

In applications where the DC and the AC tolerances are not separated, (meaning that there is no strict DC

tolerance requirement) the droop method can be used.

表 1. Mode Definitions

LIGHT-LOAD

POWER SAVING

MODE

SWITCHING

FREQUENCY

OVERCURRENT

LIMIT (OCL)

VALLEY (A)

MODE

RESISTANCE (kΩ)

MODE

(f_SW

)

600 kHz

1 MHz

7.6

5.4

7.6

5.4

7.6

SKIP

PWM

1 MHz

600 kHz

1 MHz

100

OPEN

1 MHz

图 28 shows the load regulation of the 1.5-V rail using an R_DROOPvalue of 6.8 kΩ.

图 29 shows the transient response of the TPS53317A device using droop configuration and C_OUT= 3 × 47 µF.

The applied step load is from 0 A to 2 A.

0.85

0.83

0.81

0.79

0.77

0.75

0.73

0.71

0.69

0.67

Droop Configuration

0.65

Output Current (A)

V_IN= 1.5 V

V_OUT= 0.75 V

CH 2: V_OUT

(20 mV/div)

CH 4: I_OUT

(1 A/div)

CH 3: SW

(1 V/div)

图 29. Droop Configuration Transient Response

图 28. Load Regulation (Droop Configuration)

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS53317A device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It

can provide a regulated output at ½ VDDQ with both sink and source capability. The device employs D-CAP+

mode operation that provides ease-of-use, low external component count and fast transient response.

8.2 Typical Applications

8.2.1 DDR4 SDRAM Application

This DDR4 application requires a tight load tolerance, fast transient response, and sinking current capability, the

design uses a non-droop PWM configuration.

100 kΩ

68 kΩ

5 V

0 Ω

2.2 µF

0.1 mF

PGND

V5IN

PGOOD MODE EN

BST

PGND

SW 15

SW 14

SW 13

SW 12

SW 11

V_OUT

0.25 mH

PGND

22 mF 22 mF 22 mF 22 mF

C7 C8

C10 C11 C12

1 mF 22 mF 22 mF 22 mF 22 mF 22 mF

PGND

VIN

TPS53317A

VIN

V_IN

C13 C14 C15 C16 C17 C18

22 mF 22 mF 22 mF 22 mF 22 mF 22 mF

GND

VREF COMP REFIN VOUT

10 Ω

C22

1 mF

AGND

0 Ω

V_IN

C23

0.1 mF

60.4 kΩ

3.9 kΩ

C20

33 pF

C19

10 nF

60.4 kΩ

C21

2.2 nF

图 30. DDR4 SDRAM Application

8.2.1.1 Design Requirements

•

Input voltage : V_IN= 1.2 V

Output voltage: V_OUT= 0.6 V

Maximum load step size of 3 A @ slew rate 7 A/µs (–1.5 A to 1.5 A)

DC +AC + Ripple voltage regulation limit at sense point: ±42 mV (0.642 V overshoot, 0.558 V undershoot)

Maximum load: I_MAX= 2.5 A

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Typical Applications (接下页)

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Step 1. Determine Configuration

Because this DDR4 application requires a tight load tolerance, fast transient response, and sinking current

capability, the design uses a non-droop PWM configuration. Choose 600-kHz switching frequency due to the

duty cycle and minimim off-time of the device, and set an overcurrent (OC) valley limit of 5.4 A due to the

maximum load requirement of 2.5 A. Referring to 表 1 select an R_MODEvalue of 68 kΩ.

8.2.1.2.2 Step 2. Select Inductor

Smaller inductor values have better transient performance but higher ripple and lower efficiency. High values

have the opposite characteristics. It is common practice to limit the ripple current to 30% to 50% of the maximum

current. Choose 50% to allow use of a smaller inductor for faster transient performance.

ꢀ+_2F2= 2.5 # × 0.5 = 1.25 #

(7)

. =

× 8₁₇₆× (1 F &)

× ꢀ+_2F2

where

•

D = duty cycle

(8)

Because this device operates in DCAP+ mode, the frequency and duty cycle vary based on the input voltage, the

output voltage and load. With a 2.5-A load, a 1.2-V input voltage and 0.60 V output voltage, f_SWis experimentally

measured at approximately 800 kHz and duty cycle of 0.55. Therefore L is calculated as shown in 公式 10.

. =

× 0.68 × 0.45 = 0.270 µ*

(800 G*V × 1.25 #)

(9)

Choose the closest standard value, 0.25 µH.

8.2.1.2.3 Step 3. Determine Output Capacitance

Use 公式 10 to calculate the output capacitance for a desired maximum overshoot.

ꢀ+₁²₇₆× .

;

176 IEJ ,15

2 × 8₁₇₆× 8₁₅

where

•

C_OUT(min),OSis the minimum output capacitance for a desired overshoot

ΔI_OUTis the maximum output current change in the application

V_OUT= desired output voltage

V_OSis the desired output voltage change due to overshoot

(10)

(11)

Choose a value of 30 mV to account for normal output voltage ripple.

;

3 ! × 0.25 µ*

= 62.5 µ(

;

176 IEJ ,15

2 × 0.6

× 0.03

Use 公式 12 to calculate the necessary output capacitance for a desired maximum undershoot.

8₁₇₆

ꢀ+₁²₇₆× . × @

× P₅₉+ P_{/+0 KBB}_;A

;

176 IEJ ,75

₊₀F 8₁₇₆

2 × 8₁₇₆× 8₇₅× @

× P₅₉F P_{/+0 KBB}_;A

where

•

C_OUT(min),USis the minimum output capacitance for a desired undershoot

V_USis the desired output voltage change due to overshoot

t_SWis the period of switch node

t_MIN(off)is the minimum off-time (270 ns)

(12)

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Typical Applications (接下页)

Again, choose 30 mV to account for normal output voltage ripple.

0.6 8

3 ! × 0.25 µ* × @

1.2 8 800 G*V

;

+ 270 JOA

= 157.6 µ(

;

176 IEJ ,75

1.2 8 F 0.6 8

2 × 0.6 8 × 0.03 8 × @

F 270 JOA

1.2

800

G*V

(13)

The undershoot requirements determine, so there must be a minimum of 157.6 µF. Because this is a DDR

application where size is also a consideration, this design uses only ceramic capacitors. To account for voltage

de-rating of capacitors and provide additional margin, this design includes eleven 22-µF output capacitors.

8.2.1.2.4 Step 4. Input Capacitance

This design requires sufficient input capacitance to filter the input current from the host source. Use 公式 14 to

calculate the necessary input capacitance.

& × (1 F &)

= + ×

KQP

;

+0 IEJ

ꢀ8_+0(2F2)× B

where

•

ΔV_IN(P-P)is the desired input voltage ripple (typically 1% of the input voltage)

(14)

(15)

0.55 × (1 F 0.55)

= 2.5 # ×

;

= ꢀ4.45 µ(

+0 IEJ

12 ≠6 × 800 G*V

As with the output capacitance selection, this design accounts for voltage de-rating of capacitors and provides

additional margin, using four 22-µF input capacitors.

8.2.1.2.5 Step 5. Compensation Network

In order to achieve stable operation, the crossover frequency should be less than 1/5 of the switching frequency.

ß_/

4_%

4₅

= 80 G*V

2è

176

where

•

R_S= 53 mΩ

(16)

(17)

Account for capacitor de-rating here and set the value of C_OUTto 160 µF, so that 公式 17 is true.

× 4₅× 2è × %₁₇₆80 G*V × 53 I3 × 2è × 160 ä(

4_%=

= 4.26 G3

C_/

1 I5

Choose an R_Cvalue of 3.9 kΩ. Determine C_Cby choosing the value of the zero created by R_Cand C_C. Using the

relationship described in 公式 18.

B =

2è × 4_%× %_%

(18)

公式 18 yields a C_Cvalue of 2.55 nF. Choose the closest common capacitor value of 2.2 nF. To determine a

value for C_P, first consider the relationship described in 公式 19.

2è × 4_%×

C_C>> C_P

B =

%_%× %₂

%_%+ %₂

2è × 4_%× %₂

•

(19)

(20)

Because C_C>> C_P, set the pole to be two times the switching frequency as described in 公式 20.

%₂ꢀ

= 25.5 L(

2è × 4_%× 2B

2è × 3.9 G3 × 2 × 800 G*V

To boost the gain margin, set C_Pto 33 pF.

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Typical Applications (接下页)

TPS53317A

R_C

VREF

C_P

C_C

COMP

图 31. Compensation Network Circuit

8.2.1.2.6 Peripheral Component Selection

As described in 表 1, connect a 0.22-µF capacitor from the VREF pin to GND and connect a 0.1-µF bootstrap

capacitor from the SW pin to the BST pin. Because the PGOOD pin is open drain, connect a pullup resistor

between it and the 5-V rail.

8.2.1.3 Application Curves

OUT

(20 mV/div)

Design Example

V_IN= 1.2 V

V_OUT= 0.6 V

f_SW= 600 kHz PWM

OUT

(1 A/div)

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

C018

图 32. Efficiency

图 33. Load Transient

200

160

200

160

120

V_IN= 1.2 V

V_OUT= 0.6 V

I_OUT= 0 A

f_SW= 600 kHz PWM

V_IN= 1.2 V

V_OUT= 0.6 V

I_OUT= 2.5 A

f_SW= 600 kHz PWM

120

œ40

œ80

œ120

œ160

œ200

œ40

œ80

œ120

œ160

œ200

f_CO= 86.66 kHz

Phase Margin = 63.3°

Gain Margin = 19.58 dB

f_CO= 89.83 kHz

Phase Margin = 64.7°

Gain Margin = 17.32 dB

œ10

œ20

œ30

œ40

œ10

œ20

œ30

Mag

Phase

œ40

10k

100k

10k

100k

Frequency (Hz)

C014

C015

图 34. Bode Plot, No Load

图 35. Bode Plot, Full Load

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Typical Applications (接下页)

700

695

690

685

680

675

670

665

660

655

650

645

640

0.610

0.608

0.606

0.604

0.602

0.600

0.598

0.596

0.594

0.592

0.590

Design Example

V_IN= 1.2 V

f_SW= 600 kHz PWM

-2.5 -2 -1.5 -1 -0.5

0.5

1.5

2.5

0.0 0.5 1.0 1.5 2.0 2.5

œ2.5 œ2.0 œ1.5 œ1.0 œ0.5

Output Current (A)

D001

Output Current (A)

C019

V_IN= 1.2

f_SW= 600 kHz

图 36. Switching Frequency vs. Load

图 37. Load Regulation

8.2.2 DDR3 SDRAM Application

100 kΩ

68 kΩ

5 V

0 Ω

2.2 µF

0.1 mF

PGND

V5IN

PGOOD MODE EN

BST

PGND

SW 15

SW 14

SW 13

SW 12

SW 11

V_OUT

0.25 mH

PGND

22 mF 22 mF 22 mF 22 mF

C7 C8

C10 C11 C12

1 mF 22 mF 22 mF 22 mF 22 mF 22 mF

PGND

VIN

TPS53317A

VIN

V_IN

C13 C14 C15 C16 C17 C18

22 mF 22 mF 22 mF 22 mF 22 mF 22 mF

GND

VREF COMP REFIN VOUT

10 Ω

C22

1 mF

AGND

0 Ω

V_IN

C23

0.1 mF

60.4 kΩ

3.9 kΩ

C20

33 pF

C19

10 nF

60.4 kΩ

C21

2.2 nF

图 38. Typical Application Schematic, DDR3

8.2.2.1 Design Requirements

•

V_IN= 1.5 V

V_OUT= 0.75 V

TPS53317A

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

Typical Applications (接下页)

8.2.3 Non-Tracking Point-of-Load (POL) Application

100 kΩ

47 kΩ

5-V V_IN

2 Ω

2.2 µF

0.1 mF

PGND

V5IN

PGOOD MODE EN

BST

PGND

SW 15

SW 14

SW 13

SW 12

SW 11

0.25 mH

PGND

V_OUT

22 mF 22 mF 22 mF 22 mF

C7 C8

C10 C11 C12

PGND

VIN

TPS53317A

1 mF 22 mF 22 mF 22 mF 22 mF 22 mF

VIN

V_IN

C13 C14 C15 C16 C17 C18

22 mF 22 mF 22 mF 22 mF 22 mF 22 mF

GND

VREF COMP REFIN VOUT

10 Ω

C22

1 mF

AGND

0 Ω

C19

10 nF

C23

0.1 mF

3.9 kΩ

C20

33 pF

150 kΩ

100 kΩ

C21

2.2 nF

图 39. Typical Application Schematic, Non-Tracking Point-of-Load (POL)

8.2.3.1 Design Requirements

•

V_IN= 3.3 V

V_OUT= 1.2 V

8.2.3.2 Application Curves

200

160

120

200

160

120

V_IN= 3.3 V

V_OUT= 1.2 V

I_OUT= 6 A

f_SW= 600 kHz PWM

V_IN= 3.3 V

V_OUT= 1.2 V

I_OUT= 0 A

f_SW= 600 kHz PWM

œ40

œ80

œ120

œ160

œ200

œ40

œ80

œ120

œ160

œ200

f_CO= 89.36 kHz

Phase Margin = 66.54°

Gain Margin = 15.58 dB

f_CO= 95.05 kHz

Phase Margin = 65.83°

Gain Margin = 14.18 dB

œ10

œ20

œ30

œ40

œ10

œ20

œ30

œ40

Mag

Phase

10k

100k

10k

100k

Frequency (Hz)

C016

C017

图 40. Bode Plot No Load

图 41. Bode Plot Full Load

TPS53317A

www.ti.com.cn

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

9 Power Supply Recommendations

This device operates from an input voltage supply between 0.9 V and 6 V. This device requires a separate 5-V

power supply for analog circuits and gate drive. Use the proper bypass capacitors for both the input supply and

the 5-V supply in order to filter noise and to ensure proper device operation.

10 Layout

10.1 Layout Guidelines

Stable power supply operation depends on proper layout. Follow these guidelines for an optimized PCB layout.

•

Connect PGND pins to the thermal pad underneath the device. Use four vias to connect the thermal pad to

internal ground planes.

•

Place VIN, V5IN and VREF decoupling capacitors as close to the device as possible.

Use wide traces for the VIN, PGND and SW pins. These nodes carry high current and also serve as heat

sinks.

•

Place feedback and compensation components as close to the device as possible.

Place COMP and VOUT analog signal traces away from noisy signals (SW, BST).

The GND pin should connect to the PGND in only one place, through a via or a 0-Ω resistor.

10.2 Layout Example

PGND

VIN

VOUT

Thermal Pad

VIN

PGND

VIN

图 42. TPS53317A Board Layout

TPS53317A

ZHCSED1A –NOVEMBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

11 器件和文档支持

11.1 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.2 商标

D-CAP+, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS53317ARGBR

TPS53317ARGBT

ACTIVE

VQFN

RGB

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

53317A

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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10-Dec-2020

Addendum-Page 2

重要声明和免责声明

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TPS53317A [TI]

相关型号：

TPS53317ARGBR

TPS53317ARGBT

TPS53317RGBR

TPS53317RGBT

TPS53317_15

TPS53317_17

TPS53318

TPS53318DQPR

TPS53318DQPT

TPS53319

TPS53319DQPR

TPS53319DQPT