TPS51396ARJET [TI]
4.5V 至 24V、8A 同步降压稳压器 | RJE | 20 | -40 to 125;
| 型号： | TPS51396ARJET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.5V 至 24V、8A 同步降压稳压器 | RJE | 20 | -40 to 125 稳压器 |
| 文件： | 总33页 (文件大小：2991K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS51396A
ZHCSNW0C –FEBRUARY 2019 –REVISED APRIL 2021
TPS51396A 具有ULQ™ 模式、可延长电池寿命的4.5V 至24V、8A 同步降压稳
压器
TPS51396A 的主要特性是其ULQ（超低静态电流），
可实现低偏置电流和大负荷运行。该 ULQ 特性非常有
1 特性
• 输入电压范围：4.5V 至24V
• D-CAP3™ 架构控制，可实现快速瞬态响应
• 输出电压范围：0.6V 至7V
• 1% 反馈电压精度(25°C)
• 持续输出电流：8A
益于在低功耗运行时延长电池寿命。TPS51396A 的电
源输入电压范围为 4.5V 至 24V。该器件使用 DCAP3
控制模式来提供快速瞬态响应、良好的线路和负载调
节，无需外部补偿，并支持低等效串联电阻 (ESR) 输
出电容器，如专用聚合物和超低ESR 陶瓷电容器。
• 集成19.5mΩ和9.5mΩRDS(on) 内部电源开关
• ULQ™ 运行，能够在系统待机期间延长电池寿命
• Eco-Mode™ 和OOA 模式，适用于轻负载运行（通
过MODE 引脚选择）
• 600kHz、800kHz 和1MHz 可选开关频率（通过
MODE 引脚选择）
• Out-of-Audio (OOA) 轻负载运行，开关频率超过
25kHz
• 支持大负荷运行
TPS51396A 提供 OVP、UVP、OCP、OTP 和 UVLO
的全面保护。它结合了电源正常信号和输出放电功能。
可使用 TPS51396A 中的 MODE 引脚来设置 Eco-
Mode 或 OOA 模式，从而实现轻负载运行。Eco-
Mode 在轻负载运行期间可保持高效率，OOA 模式工
作时的开关频率大于 25kHz（即使没有负载也是如
此）。
TPS51396A 同时支持内部和外部软启动时间选项。它
具有 1.3ms 的内部固定软启动时间。如果应用需要更
长的软启动时间，则可以使用外部 SS 引脚，通过连接
外部电容器来实现。
• 可调节软启动时间（通过SS 引脚调节）
• 电源正常指示器
• 内置输出放电功能
• 逐周期过流保护
• 锁存输出，可提供OV 和UV 保护
• 非锁存，可提供OT 和UVLO 保护
• 20 引脚3.0mm × 3.0mm HotRod™ VQFN 封装
TPS51396A 可采用 20 引脚 3.0mm × 3.0mm HotRod
封装，额定结温范围为–40°C 至125°C。
器件信息
封装(1)
封装尺寸（标称值）
2 应用
器件型号
TPS51396A
VQFN (20)
3.00mm × 3.00mm
• 笔记本电脑、DTV 和STB
• 电信和网络、负载点(POL)
• IPC、工厂自动化
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 分布式电源系统
3 说明
TPS51396A 是一款具有集成式 FET 且具有成本效益
的高电压输入、高效率同步降压转换器。
L
100
95
90
85
80
75
TPS51396A
VIN
VOUT
R1
SW
VIN
VCC
CIN
CBST
COUT
RM_H
VBST
FB
EN
RM_L
MODE
PGOOD
R5
R2
PGOOD
VCC
70
VVIN=6V, VOUT=5V,FSW=600kHz
VVIN=8.4V,VOUT=5V,FSW=600kHz
VVIN=12V, VOUT=5V,FSW=600kHz
VVIN=19V, VOUT=5V,FSW=600kHz
SS
AGND
PGND
Could be floating
Css
65
C1
60
0.001
0.01
0.1
I-Load (A)
1
10
D034
典型应用
效率与输出电流ECO 模式
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEY3
TPS51396A
ZHCSNW0C –FEBRUARY 2019 –REVISED APRIL 2021
www.ti.com.cn
Table of Contents
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 1V Output Typical Application...................................17
9 Power Supply Recommendations................................22
10 Layout...........................................................................23
10.1 Layout Guidelines................................................... 23
10.2 Layout Example...................................................... 23
11 Device and Documentation Support..........................24
11.1 Device Support........................................................24
11.2 接收文档更新通知................................................... 24
11.3 支持资源..................................................................24
11.4 Trademarks............................................................. 24
11.5 Electrostatic Discharge Caution..............................24
11.6 Glossary..................................................................24
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................14
Information.................................................................... 25
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (April 2020) to Revision C (April 2021)
Page
• 首次公开发布...................................................................................................................................................... 1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 更新了标题..........................................................................................................................................................1
• Added table note to the Recommended Operating Conditions ......................................................................... 4
Changes from Revision A (April 2020) to Revision B (April 2020)
Page
• 将销售状态从“保密协议限制”更改为“选择性披露”..................................................................................... 1
Changes from Revision * (February 2019) to Revision A (April 2020)
Page
• 将销售状态从“预告信息”更改为“量产版本”................................................................................................ 1
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5 Pin Configuration and Functions
SW
SW
GND
VCC
NC
18
20
16
19
17
1
15
BST
MODE
3
3
2
14 FB
VIN
VIN
VIN
VIN
4
3
4
13
GND
AGND
4
5
12
EN
11
SS
8
9
6
10
7
NC
PGOOD
GND
GND
SW
图5-1. RJE Package 20-Pin VQFN (Top View)
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BST and SW, 0.1 μF is recommended.
BST
1
I
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
GND.
VIN
2,3,4,5
6,19,20
P
SW
O
G
Switch node terminal. Connect the output inductor to this pin.
GND
7,8,18,Pad
9
Power GND terminal for the controller circuit and the internal circuitry.
Open drain power good indicator. It is asserted low if output voltage is out of PGOOD threshold, over
voltage or if the device is under thermal shutdown, EN shutdown or during soft start.
PGOOD
O
I
Soft-start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the soft-start time is about 1.3 ms.
SS
11
10,16
12
NC
Not connect. Can be connected to GND plane for better thermal achieved.
Enable pin of buck converter. EN pin is a digital input pin, decides turn on or off buck converter. Internal pull
down current to disable converter if leave this pin open.
EN
I
G
I
AGND
FB
13
Ground of internal analog circuitry. Connect AGND to GND plane with a short trace.
Converter feedback input. Connect to the center tap of the resistor divider between output voltage and
AGND.
14
Llight load operation mode selection pin. Connect this pin to a resistor divider from VCC and AGND, the
different MODE options are shown in 表7-1
MODE
VCC
15
17
I
5.0-V internal VCC LDO output. This pin supplies voltage to the internal circuitry and gate driver. Bypass
this pin with a 1-μF capacitor.
O
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
26
31
6
UNIT
V
VIN
VBST
V
Input voltage
VBST-SW
V
EN, MODE, FB, SS
PGND, AGND
SW
6
V
0.3
26
28
6
V
V
Output voltage
SW (10-ns transient)
PGOOD
V
–3
V
–0.3
–40
–55
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
Charged-device model (CDM), per JEDEC specification JESD22- V C101(2)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
24
UNIT
V
VIN(1)
4.5
–0.3
–0.3
–0.3
–0.3
–2
VBST
29
V
VBST-SW
EN, MODE, FB, SS
PGND, AGND
SW
5.5
5.5
0.3
24
V
Input voltage
V
V
V
Output voltage
SW (10-ns transient)
PGOOD
26
V
–3
5.5
8
V
–0.3
IOUT
TJ
Output current
A
Operating junction temperature
125
°C
–40
(1) Max DC input (inlcude tolerance) should be not over 24 V.
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6.4 Thermal Information
TPS51396A
THERMAL METRIC(1)
RJE (VQFN)
20 PINS
44.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
32.3
13.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.3
ψJT
13.5
ψJB
RθJC(bot)
16.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage range
VIN supply current
VIN
4.5
24
V
IVIN
No load, VEN = 3.3 V, Switching
No load, VEN = 0 V
90
2
uA
uA
IVINSDN
VCC OUTPUT
Shutdown supply current
VVIN > 5.0 V
VVIN = 4.5 V
4.85
20
5
5.15
V
V
VCC
VCC output voltage
VCC current limit
4.5
ICC
mA
FEEDBACK VOLTAGE
TJ = 25°C
594
592
600
600
606
611
mV
mV
VFB
FB voltage
TJ = -40°C to 125°C
DUTY CYCLE and FREQUENCY CONTROL
FSW
Switching frequency
SW minumum on time
SW minimum off time
TJ = 25°C , FSW = 600 kHz,Vo = 1 V
TJ = 25°C
600
60
kHz
ns
TON(MIN)
TOFF(MIN)
TJ = 25°C, VFB = 0.5 V
190
ns
MOSFET and DRIVERS
RDS(ON)H
High side switch resistance
TJ = 25°C
TJ = 25°C
19.5
9.5
mΩ
mΩ
RDS(ON)L
Low side switch resistance
OOA FUNCTION
TOOA
OOA mode operation period
28
us
OUTPUT DISCHARGE and SOFT START
RDIS
Discharge resistance
Soft start time
TJ = 25°C, VEN = 0 V
420
1.3
5
Ω
ms
uA
TSS
Internal soft-start time, SS floating
ISS
Soft start charge current
POWER GOOD
TPGDLY
PG start-up delay
PG threshold
PG from low to high
VFB falling (fault)
VFB rising (good)
VFB rising (fault)
VFB falling (good)
IOL = 4 mA
1
85
ms
%
%
%
%
V
90
VPGTH
115
110
VPG_L
IPGLK
PG sink current capability
PG leak current
0.4
1
VPGOOD = 5.5 V
uA
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TJ =-40°C to 125°C, VVIN = 12 V, unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
CURRENT LIMIT
IOCL
Over current threshold
Valley current set point
8.1
9.8
3.9
12
A
A
INOCL
Negative over current threshold
LOGIC THRESHOLD
VENH
VENL
EN high-level input voltage
1.2
1.4
V
V
EN low-level input voltage
0.8
1.05
Enable internal pull down
current
IEN
VEN = 0.8 V
2
µA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
OVP trip threshold
OVP prop deglitch
UVP trip threshold
UVP prop deglitch
125
20
%
us
%
tOVPDLY
VUVP
TJ = 25°C
60
tUVPDLY
UVLO
256
us
Wake up
4.2
3.8
0.4
4.4
V
V
V
VUVLOVIN
VIN UVLO threshold
Shutdown
Hysteresis
3.6
OVER TEMPERATURE PROTECTION
TOTP
OTP trip threshold(1)
OTP hysteresis(1)
Shutdown temperature
Hysteresis
150
20
°C
°C
TOTPHSY
(1) Not production tested
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6.6 Typical Characteristics
TJ=-40oC to 125oC, VVIN=12V(unless otherwise noted)
480
470
460
450
440
430
3.25
3
2.75
2.5
2.25
2
1.75
1.5
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (OC)
Junction Temperature (OC)
D002
D001
VEN = 0 V
VEN = 5 V
图6-2. Shutdown Current vs Temperature
图6-1. Supply Current vs Junction Temperature
615
1.36
1.34
1.32
1.3
610
605
600
595
590
1.28
1.26
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (OC)
Junction Temperature (OC)
D004
D003
图6-4. Enable On Voltage vs Junction Temperature
图6-3. Feedback Voltage vs Junction Temperature
1.13
27.5
1.12
1.11
1.1
25
22.5
20
1.09
17.5
1.08
15
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (OC)
Junction Temperature (OC)
D005
D011
图6-5. Enable Off Voltage vs Junction Temperature
图6-6. High-Side RDS(on) vs Junction Temperature
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16
14
12
10
8
130
128
126
124
122
120
6
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Juncition Temperature (OC)
Junction Temperature (OC)
D006
D012
图6-8. OVP Threshold vs Junction Temperature
图6-7. Low-Side RDS(on) vs Junction Temperature
64
440
435
430
425
420
415
63
62
61
60
59
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (OC)
Junction Temperature (OC)
D008
D007
图6-10. Discharge Resistor vs Junction
图6-9. UVP Threshold vs Junction Temperature
Temperature
11
10.6
10.2
9.8
9.4
9
1.35
1.33
1.31
1.29
1.27
1.25
-50
-20
10
40
70
100
130
-50
-20
10
40
70
100
130
Junction Temperature (OC)
Junction Temperature (OC)
D009
D010
图6-11. Valley Current Limit vs Junction
图6-12. Soft-Start Time vs Junction Temperature
Temperature
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100
95
90
85
80
75
70
65
100
90
80
70
60
50
40
30
20
10
0
VVIN=12V,VOUT=1V
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
60
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D027
D028
图6-13. Efficiency, Eco-mode, FSW = 600 kHz
图6-14. Efficiency, OOA-mode, FSW = 600 kHz
100
100
90
80
70
60
50
40
30
90
80
70
60
20
VVIN=12V, VOUT=1V
50
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
10
VVIN=12V, VOUT=5V
40
0.001
0
0.001
0.01
0.1
I-Load (A)
1
10
0.01
0.1
I-Load (A)
1
10
D030
D031
图6-15. Efficiency, Eco-mode, FSW = 1 MHz
图6-16. Efficiency, OOA-mode, FSW = 1 MHz
700
700
VVIN=5V,VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V,VOUT=1V
VVIN=19V,VOUT=1V
500
VVIN=5V,VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V,VOUT=1V
VVIN=19V,VOUT=1V
500
600
600
400
300
200
100
0
400
300
200
100
0
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D023
D036
图6-17. FSW Load Regulation, Eco-mode, FSW
=
图6-18. FSW Load Regulation, OOA-mode, FSW =
600 kHz
600 kHz
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900
900
800
700
600
500
400
300
200
100
0
VVIN=5V,VOUT=1V
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V,VOUT=1V
VVIN=19V,VOUT=1V
800
700
600
500
400
300
200
100
0
VVIN=8.4V,VOUT=1V
VVIN=12V,VOUT=1V
VVIN=19V,VOUT=1V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D038
D039
图6-19. FSW Load Regulation, Eco-mode, FSW
=
图6-20. FSW Load Regulation, OOA-mode, FSW =
800 kHz
800 kHz
1100
VVIN=12V, VOUT=1V
1000
1100
VVIN=12V, VOUT=1V
1000
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
VVIN=12V,VOUT=3.3V
VVIN=12V,VOUT=5V
900
800
700
600
500
400
300
200
100
0
900
800
700
600
500
400
300
200
100
0
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D052
D053
图6-21. FSW Load Regulation, Eco-mode, FSW = 1 图6-22. FSW Load Regulation, OOA-mode, FSW = 1
MHz
MHz
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7 Detailed Description
7.1 Overview
The TPS51396A is 8-A integrated FET synchronous buck converter which operates from 4.5-V to 24-V input
voltage (VIN), and the output is from 0.6 V to 7 V. The proprietary D-CAP3 mode enables low external
component count, ease of design, optimization of the power design for cost, size, and efficiency. The key feature
of the TPS51396A is ultra-low quiescent current (ULQ) mode. This feature is beneficial for long battery life in
system standby mode. The device employs D-CAP3 mode control that provides fast transient response with no
external compensation components and an accurate feedback voltage. The control topology provides seamless
transition between CCM operating mode at higher load condition and DCM operation at lighter load condition.
Eco-mode allows the TPS51396A to maintain high efficiency at light load. OOA (out of audio) mode makes
switching frequency above audible frequency larger than 25 kHz, even there is no loading at output side. The
TPS51396A is able to adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP
or SP-CAP, and ultra-low ESR ceramic capacitors.
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7.2 Functional Block Diagram
PG high
threshold
PGOOD
+
+
UV threshold
+
UV
Delay
PG low
threshold
+
OV
VIN
OV threshold
FB
+
LDO
VCC
0.6 V
VREGOK
4.2 V /
3.8 V
+
+
PWM
+
+
Control Logic
VBST
VIN
SS
ñ
ñ
ñ
ñ
ñ
ñ
ñ
On/Off time
Minimum On/Off
TON Extension
OVP/UVP/TSD
OOA/SKIP
Ripple injection
SW
XCON
SW
Internal SS
Soft-Start
PGOOD
SS
PGND
One shot
+
OCL
ZC
EN threshold
+
+
+
EN
NOCL
THOK
+
150°C /20°C
AGND
Light load operation set /
Switching frequency set
Discharge control
MODE
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3 Control
The main control loop of the buck is adaptive on-time pulse width modulation (PWM) controller that supports a
proprietary DCAP3 mode control. The DCAP3 mode control combines adaptive on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low-
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The TPS51396A also
includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inversely
proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for DCAP3 control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the TPS51396A is a low-pass L-C circuit. This L-C filter has a double-pole frequency
described in 方程式1.
1
fp =
2ìpì LOUTìCOUT
(1)
At low frequency, the overall loop gain is set by the output set-point resistor divider network and the internal gain
of the TPS51396A. The low-frequency L-C double pole has a 180 degree drop in phase. At the output filter
frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and leads the 90 degree phase boost. The internal ripple injection high-frequency zero is related to the
switching frequency. The crossover frequency of the overall system should usually be targeted to be less than
one-third of the switching frequency (FSW).
7.3.2 Soft Start
The TPS51396A has an internal 1.3-ms soft start, and also an external SS pin is provided for setting higher soft-
start time if needed. When the EN pin becomes high, the soft-start function begins ramping up the reference
voltage to the PWM comparator.
If the application needs a larger soft start time, it can be set by connecting a capacitor on SS pin. When the EN
pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS) connected
between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external soft-start
voltage as the reference. The equation for the soft-start time (TSS) is shown in 方程式2:
Css(nF)ìVREF(V)
T =
ss
Iss(mA)
(2)
where
• VREF is 0.6 V and ISS is 5 μA
7.3.3 Large Duty Operation
The TPS51396A can support large duty operations by its internal TON extension function. When the VIN/VOUT
<1.6, and the VFB is lower than internal VREF, the TON will be extended to implement the large duty operation and
also improve the performance of the load transient performance.
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7.3.4 Power Good
The Power Good (PGOOD) pin is an open-drain output. Once the VFB is between 90% and 110% of the target
output voltage, the PGOOD is de-asserted and floats after a 1-ms de-glitch time. A 100 kΩ pullup resistor is
recommended to pull the voltage up to VCC. The PGOOD pin is pulled low when:
• the FB pin voltage is lower than 85% or greater than 115% of the target output voltage
• in an OVP, UVP, or thermal shutdown event
• during the soft-start period.
7.3.5 Over Current Protection and Undervoltage Protection
The TPS51396A has the over current protection and undervoltage protection. The output over current limit
(OCL) is implemented using a cycle-by-cycle valley detect circuit. The switch current is monitored during the
OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch
current. To improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over current protection. When the load current is higher
than the over current threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the current is being limited, the output voltage tends to drop because the load demand is higher than what the
converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it, the output will be latched after a wait time of 256us. When the over current condition is removed, the
output voltage is latched till the EN is toggled or re-power the power input.
7.3.6 Over Voltage Protection
The TPS51396A has the over voltage protection feature. When the output voltage becomes higher than 125% of
the target voltage, the OVP comparator output goes high, the output will be discharged after a wait time of 20 µs.
When the over voltage condition is removed, the output voltage is latched till the EN is toggled or re-power the
power input.
7.3.7 UVLO Protection
Undervoltage Lockout protection (UVLO) monitors the VIN power input. When the voltage is lower than UVLO
threshold voltage, the device is shut off and output is discharged. This is a non-latch protection.
7.3.8 Output Voltage Discharge
The TPS51396A has the discharge function by using internal MOSFET about 420Ω RDS(on), which is connected
to the output terminal SW. The discharge is slow due to the lower current capability of the MOSFET.
7.3.9 Thermal Shutdown
The TPS51396A monitors the internal die temperature. If the temperature exceeds the threshold value (typically
150°C), the device is shut off and the output will be discharged. This is a non-latched protection, the device
restarts switching when the temperature goes below the thermal shutdown threshold.
7.4 Device Functional Modes
7.4.1 Light Load Operation
TPS51396A has a MODE pin which can setup three different modes of operation for light load running and 600
kHz/800 kHz/1 MHz switching frequency at heavy load .The light load running includes out-of-audio
mode ,advanced Eco-mode and force CCM mode.
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7.4.2 Advanced Eco-mode™ Control
The advanced Eco-mode™ control scheme to maintain high light load efficiency. As the output current decreases
from heavy load conditions, the inductor current is also reduced and eventually comes to a point where the
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases, the converter runs into discontinuous conduction mode. The on-time is kept almost
the same as it was in the continuous conduction mode so that it takes longer time to discharge the output
capacitor with smaller load current to the level of the reference voltage. This makes the switching frequency
lower, proportional to the load current, and keeps the light load efficiency high. The light load current where the
transition to Eco-mode™ operation happens ( IOUT(LL) ) can be calculated from 方程式3.
(V -VOUT ) × VOUT
1
IN
IOUT(LL)
=
×
2 × LOUT × FSW
V
IN
(3)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-to-
peak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application). It is
also important to size the inductor properly so that the valley current does not hit the negative low-side current
limit.
7.4.3 Out of Audio Mode
Out-of-Audio (OOA) light-load mode is a unique control feature that keeps the switching frequency above
audible frequency towards a virtual no-load condition. During Out-of-Audio operation, the OOA control circuit
monitors the states of both high-side and low-side MOSFETs and forces them switching if both MOSFETs are off
for more than 28 μs. When both high-side and low-side MOSFETs are off for more than 28 μs during a light-
load condition, the lowside FET will be on for discharge till reverse OC happens or output voltage drops to trigger
the high-side FET on. This mode initiates one cycle of the low-side MOSFET and the high-side MOSFET turning
on. Then, both MOSFETs stay turned off waiting for another 28 μs.
If the MODE pin is selected to operate in OOA mode, when the device works at light load, the minimum
switching frequency is above 25 kHz which avoids the audible noise in the system.
7.4.4 Mode Selection
The device reads the voltage on the MODE pin during start-up and latches onto one of the MODE options listed
below in 表 7-1 . The voltage on the MODE pin can be set by connecting this pin to the center tap of a resistor
divider connected between VCC and AGND. A guideline for the top resistor (RM_H) and the bottom resistor
(RM_L) is shown in 表 7-1, and 1% resistors are recommended. It is important that the voltage for the MODE pin
is derived from the VCC rail only since internally this voltage is referenced to detect the MODE option. The
MODE pin setting can be reset only by a VIN power cycling or EN toggle.
表7-1. MODE Pin Resistor Settings
Light Load Operation
Switching Frequency (kHz)
RM_H(kΩ)
330
RM_L (kΩ)
5.1
15
27
43
33
51
Eco-mode
600
800
330
Eco-mode
330
Eco-mode
1000
600
300
OOA mode
150
OOA mode
800
160
OOA mode
1000
图 7-1 below shows the typical start-up sequence of the device once the enable signal crosses the EN turn on
threshold. After the voltage on VCC crosses the rising UVLO threshold it takes about 500us to read the first
mode setting and approximately 100us from there to finish the last mode setting. The output voltage starts
ramping after the mode reading is done.
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EN threshold
1.2V
EN
VCC UVLO
4.2V
VCC
MODE6
100us
MODE1
MODE
500us
Tss
90% VOUT
1ms
VOUT
PGOOD
图7-1. Power-Up Sequence
7.4.5 Standby Operation
The TPS51396A can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 2 µA when in standby condition. EN pin is pulled low internally, when float, the part is disabled by
default.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The schematic of 图 8-1 shows a typical application for TPS51396A with 1-V output. This design converts an
input voltage range of 4.5 V to 24 V down to 1 V with a maximum output current of 8 A.
8.2 1V Output Typical Application
图8-1. 1V/8A Reference Design with Eco-mode, Fsw = 600 kHz
8.2.1 Design Requirements
表8-1 lists the design parameters for this example.
表8-1. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VOUT
Output voltage
1
V
A
IOUT
Output current
8
Transient response
Input voltage
0 A - 8 A load step,2.5A/us
±40
mV
V
ΔVOUT
VIN
4.5
12
18
24
VOUT(ripple)
FSW
Output voltage ripple (CCM)
Switching frequency
Light load operating mode
Ambient temperature
mV(P-P)
kHz
600
Eco-mode
25
TA
°C
8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor the user can change the output voltage above 0.6 V. See 方程式4
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RUPPER
VOUT = 0.6 ì (1+
)
RLOWER
(4)
8.2.2.1.2 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See 表8-2 for recommended
inductor values.
The RMS and peak currents through the inductor can be calculated using 方程式 5 and 方程式 6. It is important
that the inductor is rated to handle these currents.
2
≈
∆
’
÷
≈
∆
∆
«
’
÷
÷
◊
VOUT ì(V
- VOUT )
1
IN(max)
IL
=
I2
+
ì
OUT
(
RMS
)
∆
∆
«
÷
÷
◊
12
V
ìLOUT ìFSW
IN(max)
(5)
(6)
IL(ripple)
IL(peak) = IOUT
+
2
During transient and short-circuit conditions, the inductor current can increase up to the current limit of the
device so it is safe to choose an inductor with a saturation current higher than the peak current under current
limit condition.
8.2.2.1.3 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In DCAP3™, the regulator reacts within
one cycle to the change in the duty cycle so the good transient performance can be achieved without needing
large amounts of output capacitance. The recommended output capacitance range is given in 表8-2.
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple)
.
表8-2. Recommended Component Values
RUPPER
(kΩ)
VOUT (V)
Fsw (kHz)
LOUT (µH)
COUT(min) (µF)
COUT(max) (µF)
CFF (PF)
RLOWER (kΩ)
600
800
0.47
0.33
0.27
0.68
0.47
0.33
1.5
66
66
66
66
66
66
66
66
66
66
66
66
500
500
500
500
500
500
500
500
500
500
500
500
-
0.6
10
0
-
1000
600
-
-
1
30
20
30
20
800
-
1000
600
-
47-330
47-330
47-330
47-330
47-330
47-330
3.3
5.0
90
800
1.2
1000
600
1
2.2
220
800
1.5
1000
1.2
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8.2.2.1.4 Input Capacitor Selection
The TPS51396A requires input decoupling capacitors on power supply input VIN, and the bulk capacitors are
needed depending on the application. The minimum input capacitance required is given in 方程式7.
IOUT×VOUT
CIN(min)
=
V
INripple×V ×FSW
IN
(7)
TI recommends using a high-quality X5R or X7R input decoupling capacitors of 40 µF on the input voltage pin
VIN. The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor
must also have a ripple current rating greater than the maximum input current ripple of the application. The input
ripple current is calculated by 方程式8:
VIN(min)-VOUT
(
)
VOUT
ICIN(rms) = IOUT ×
×
VIN(min)
VIN(min)
(8)
A 1-µF ceramic capacitor is needed for the decoupling capacitor on VCC pin.
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8.2.3 Application Curves
图8-2 through 图8-15 apply to the circuit of 图8-1. VIN = 12 V. TJ = 25°C unless otherwise specified.
1.01
1.008
1.006
1.004
1.002
1
95
90
85
80
75
70
65
60
55
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
VVIN=19V, VOUT=1V
0.998
0.996
0.994
0.992
0.99
VVIN=5V, VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V, VOUT=1V
VVIN=19V, VOUT=1V
0.001
0.01
0.1
I-Load (A)
1
10
0.001
0.01
0.1
I-Load (A)
1
10
D019
D033
图8-3. Load Regulation ,Fsw = 600 kHz
图8-2. Efficiency Curve, Fsw = 600 kHz
800
700
600
500
400
300
200
100
0
700
600
500
400
300
200
VVIN=5V,VOUT=1V
VVIN=8.4V,VOUT=1V
VVIN=12V,VOUT=1V
VVIN=19V,VOUT=1V
4
6
8
10
12
14
VIN (V)
16
18
20
22
24
0
1
2
3
4
I-Load (A)
5
6
7
8
D025
D047
IOUT = 8 A
图8-4. Switching Frequency vs Input Voltage
图8-5. Switching Frequency vs Output Load
1.01
1.008
1.006
1.004
1.002
1
1.01
1.008
1.006
1.004
1.002
1
0.998
0.996
0.994
0.992
0.99
0.998
0.996
0.994
0.992
0.99
4
6
8
10
12
14
VIN (V)
16
18
20
22
24
4
6
8
10
12
14
VIN (V)
16
18
20
22
24
D027
D026
图8-6. Line Regulation,IOUT = 0.01 A
图8-7. Line Regulation,IOUT = 8 A
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Vout=20mV/div (AC coupled)
Vout=20mV/div (AC coupled)
SW=5V/div
SW=5V/div
200us/div
2us/div
图8-8. Output Voltage Ripple, IOUT = 0.01 A
图8-9. Output Voltage Ripple, IOUT = 8 A
EN=2V/div
EN=2V/div
Vout=1V/div
Vout=1V/div
IL=5A/div
IL=5A/div
2ms/div
400us/div
图8-10. Start-Up Through EN, IOUT = 4A
图8-11. Shut-down Through EN, IOUT = 4A
Vin=10V/div
Vout=1V/div
Vin=10V/div
Vout=1V/div
IL=5A/div
IL=5A/div
4ms/div
4ms/div
图8-13. Start Up Relative to VIN Falling, IOUT = 4 A
图8-12. Start Up Relative to VIN Rising, IOUT = 4 A
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Vout=50mV/div (AC coupled)
Iout=5A/div
Vout=50mV/div (AC coupled)
Iout=5A/div
200us/div
200us/div
A.
Slew Rate=2.5A/us
A.
Slew Rate=2.5A/us
图8-14. Transient Response, 0.8 A to 7.2 A
图8-15. Transient Response, 0 A to 8 A
9 Power Supply Recommendations
The TPS51396A is intended to be powered by a well regulated dc voltage. The input voltage range is 4.5 to 24
V. TPS51396A is a buck converter. The input supply voltage must be greater than the desired output voltage for
proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS51396A circuit, additional input bulk capacitance is recommended, typical
values are 100 μF to 470 μF.
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10 Layout
10.1 Layout Guidelines
• TI recommends a four-layer PCB for good thermal performance and with maximum ground plane. 3-inch × 3-
inch, four-layer PCB with 2-oz copper is used as example.
• Place the decoupling capacitors right across VIN and VCC as close as possible.
• Place output inductor and capacitors with IC at the same layer, SW routing should be as short as possible to
minimize EMI, and should be a width plane to carry big current, enough vias should be added to the GND
connection of output capacitor and also as close to the output pin as possible.
• Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace
is recommended to reduce line parasitic inductance.
• Feedback could be 20 mil and must be routed away from the switching node, BST node or other high
efficiency signal.
• VIN trace must be wide to reduce the trace impedance and provide enough current capability.
• Place multiple vias under the device near VIN and GND and near input capacitors to reduce parasitic
inductance and improve thermal performance
10.2 Layout Example
图 10-1 shows the recommended top-side layout. Component reference designators are the same as the circuit
shown in 图 8-1. Resistor divider for EN is not used in the circuit of 图 8-1, but are shown in the layout for
reference.
AGND
图10-1. Top-Layer Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
Eco-mode™, D-CAP3™, ULQ™, Eco-Mode™, HotRod™, DCAP3™, and TI E2E™ are trademarks of Texas
Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TPS51396A
TPS51396A
ZHCSNW0C –FEBRUARY 2019 –REVISED APRIL 2021
www.ti.com.cn
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
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Product Folder Links: TPS51396A
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS51396ARJER
TPS51396ARJET
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
RJE
RJE
20
20
3000 RoHS & Green Call TI | SN | NIPDAU Level-2-260C-1 YEAR
250 RoHS & Green Call TI | SN | NIPDAU Level-2-260C-1 YEAR
-40 to 125
-40 to 125
51396A
51396A
Samples
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2023
Addendum-Page 2
GENERIC PACKAGE VIEW
RJE 20
3 x 3, 0.45 mm pitch
VQFN-HR - 1 mm max height
QUAD FLATPACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224683/A
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0020A
3.1
2.9
A
B
ꢆꢇꢄ;ꢀꢁꢀꢈꢉꢊ7<3
(0.25)
DETAIL A
CHAMFERS ARE OPTIONAL
TYPICAL
3.1
2.9
PIN 1 INDEX AREA
0.5
0.3
0.25
0.15
DETAIL B
OPTIONAL PIN 1
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.8
PKG
(0.1) TYP
SEE TERMINAL
DETAIL A
10
6
16X 0.45
11
5
(0.018)
PKG
2X
1.8
ꢀꢁꢃꢂꢀꢁꢅ
21
0.25
20X
0.15
0.1
C B A
C
1
15
0.05
16
20
(0.06)
PIN 1 ID
DETAIL B
0.5
0.3
20X
ꢀꢁꢂꢃꢄꢀꢁꢅ
4223546 / B 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0020A
(0.675)
(0.06)
20
16
20X (0.6)
20X (0.2)
1
15
(0.018)
16X (0.45)
21
PKG
(2.8)
(0.76)
11
5
(R0.05) TYP
6
10
PKG
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PAD 21)
SOLDER MASK DETAILS
4223546 / B 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RJE0020A
(0.64)
(0.06)
20
16
20X (0.6)
20X (0.2)
1
15
(0.018)
(0.72)
16X (0.45)
21
PKG
(2.8)
5
11
(R0.05) TYP
10
6
PKG
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PAD 21: 90%
SCALE: 20X
4223546 / B 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TPS5140PAGG4
1.5A SWITCHING CONTROLLER, 300kHz SWITCHING FREQ-MAX, PQFP64, GREEN, PLASTIC, TQFP-64
TI
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