TPS43330AQDAPRQ1 [TI]
汽车类 2V 至 40V 低 Iq 单路升压和双路同步降压控制器 | DAP | 38 | -40 to 125;
| 型号： | TPS43330AQDAPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 2V 至 40V 低 Iq 单路升压和双路同步降压控制器 | DAP | 38 | -40 to 125 控制器 开关 光电二极管 |
| 文件： | 总45页 (文件大小：2173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS43330A-Q1
www.ti.com.cn
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
低 IQ，单升压双同步降压稳压器
查询样品: TPS43330A-Q1
1
特性
•
耐热增强型 38 引脚散热薄型小外形尺寸封装
(HTSSOP)(DAP) PowerPAD™ 封装
2
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
•
应用范围
–
–
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
•
•
汽车电子启动/停止、信息娱乐、导航仪表板系统
工业和汽车用多轨直流配电系统和电子控制单元
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
H2
说明
器件充电器件模型 (CDM) ESD 分类等级 C2
TPS43330A-Q1 包括两个电流模式同步降压控制器和
一个电压模式升压控制器。 此器件非常适合于作为对
IQ要求较低的预稳压器级，并且适用于在遇到由意外事
件引起的电源中断时，需要不对系统造成损害的应用。
集成升压控制器使得器件能够在输入低至 2V 时运行，
而又不会出现降压稳压器输出级的下降。 在轻负载
时，可以启用降压控制器来在自动低功耗模式下运行，
消耗的静态电流仅为 30μA。
•
•
•
两个同步降压控制器
一个预升压控制器
当启用升压时，输入电压范围高达 40V，（瞬态电
压高达 60V），运行电压低至 2V
•
低功耗模式 IQ：30µA（一个降压控制器打
开），35µA（两个降压控制器打开）
•
•
•
•
•
•
•
低关断电流 Ish<4µA
降压输出范围 0.9 至 11V
可选升压输出：7V，8.85V 或者 10V
可编程频率和外部同步范围为 150 至 600kHz
独立的使能输入（ENA，ENB，ENC）
轻负载时，可选择强制持续模式或自动低功耗模式
降压控制器有独立的软启动功能和电源正常指示器。
降压控制器中的电流折返和升压控制器中的逐周期电流
限制提供了外部金属氧化物半导体场效应晶体管
(MOSFET) 保护。 开关频率可在 150kHz 至 600kHz
之间进行设定或者可将它与一个处于同一范围内的外部
时钟同步。
感应电阻器或者电感器直流电阻 (DCR) 感测对于降
压控制器
•
•
降压通道之间的异相开关
峰值栅极驱动电流 1.5A
VBAT
VBuckA
TPS43330A-Q1
VBuckB
2 V
图 1. 典型应用图
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLVSC16
TPS43330A-Q1
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
PACKAGE AND ORDERING INFORMATION
For the most-current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI Web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
space
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.7
–1
MAX UNIT
Voltage
Input voltage: VIN, VBAT
60
0.3
60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
Ground: PGNDA–AGND, PGNDB–AGND
Enable inputs: ENA, ENB
Bootstrap inputs: CBA, CBB
68
Bootstrap inputs: CBA–PHA, CBB–PHB
Phase inputs: PHA, PHB
8.8
60
Phase inputs: PHA, PHB (for 150 ns)
Feedback inputs: FBA, FBB
60
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
13
Voltage
(buck function:
BuckA and BuckB)
Error-amplifier outputs: COMPA, COMPB
High-side MOSFET drivers: GA1-PHA, GB1-PHB
Low-side MOSFET drivers: GA2–PGNDA, GB2–PGNDB
Current-sense voltage: SA1, SA2, SB1, SB2
Soft start: SSA, SSB
13
8.8
8.8
13
13
Power-good outputs: PGA, PGB
Power-good delay: DLYAB
13
13
Switching-frequency timing resistor: RT
SYNC, EXTSUP
13
13
Low-side MOSFET driver: GC1–PGNDA
Error-amplifier output: COMPC
Enable input: ENC
8.8
13
Voltage
(boost function)
13
Current-limit sense: DS
60
Output-voltage select: DIV
8.8
60
P-channel MOSFET driver: GC2
P-channel MOSFET driver: VIN-GC2
Gate-driver supply: VREG
Voltage
(PMOS driver)
8.8
8.8
150
125
165
Junction temperature: TJ
Temperature
Operating temperature: TA
–40
Storage temperature: Tstg
–55
Human-body model (HBM) AEC-Q100 Classification
Level H2
±2
kV
VBAT, ENC, SYNC, VIN
All other pins
±750
±500
±150
±200
Charged-device model (CDM) AEC-Q100 Classification
Level C2
Electrostatic
discharge ratings
V
PGA, PGB
Machine model (MM)
All other pins
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to AGND, unless otherwise specified.
2
Copyright © 2013, Texas Instruments Incorporated
TPS43330A-Q1
www.ti.com.cn
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
THERMAL INFORMATION
TPS4333x-Q1
THERMAL METRIC(1)
DAP
38 PINS
27.3
UNIT
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
19.6
15.9
ψJT
0.24
ψJB
6.6
θJCbot
1.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
40
UNIT
Input voltage: VIN, VBAT
Enable inputs: ENA, ENB
Boot inputs: CBA, CBB
Phase inputs: PHA, PHB
Current-sense voltage: SA1, SA2, SB1, SB2
Power-good output: PGA, PGB
SYNC, EXTSUP
4
0
40
4
–0.6
0
48
Buck function:
BuckA and BuckB
voltage
40
V
11
0
11
0
9
Enable input: ENC
0
9
Boost function
Voltage sense: DS
40
V
DIV
0
VREG
125
Operating temperature: TA
–40
°C
Copyright © 2013, Texas Instruments Incorporated
3
TPS43330A-Q1
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
DC ELECTRICAL CHARACTERISTICS
VIN = 8 V to 18 V, TJ = –40°C to +150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.0
Input Supply
Boost controller enabled, after satisfying initial
start-up condition
1.1
1.2
VBAT
Supply voltage
2
6.5
4
40
40
40
3.8
4
V
Input voltage required for device
on initial start-up
VIN
V
Buck regulator operating range
after initial start-up
VIN falling. After a reset, initial start-up conditions
may apply.(1)
3.5
3.6
3.8
8.5
V
V
V
1.3
VIN(UV)
Buck undervoltage lockout
Boost unlock threshold
VIN rising. After a reset, initial start-up conditions
may apply.(1)
VBOOST_UNLOC
1.4
1.5
VBAT rising
8.2
8.8
K
VIN = 13 V, BuckA: LPM, BuckB: off, TA = 25°C
VIN = 13 V, BuckB: LPM, BuckA: off, TA = 25°C
VIN = 13 V, BuckA, B: LPM, TA = 25°C
VIN = 13 V, BuckA: LPM, BuckB: off, TA = 125°C
VIN = 13 V, BuckB: LPM, BuckA: off, TA = 125°C
VIN = 13 V, BuckA, B: LPM, TA = 125°C
SYNC = HIGH, TA = 25°C
30
35
40
45
40
45
50
55
µA
µA
µA
µA
LPM quiescent current:
IQ_LPM
(2)
LPM quiescent current:
1.6
1.7
IQ_LPM
(2)
VIN = 13 V, BuckA: CCM, BuckB: off, TA = 25°C
VIN = 13 V, BuckB: CCM, BuckA: off, TA = 25°C
VIN = 13 V, BuckA, B: CCM, TA = 25°C
SYNC = HIGH, TA = 125°C
4.85
7
5.3
7.6
5.5
Quiescent current:
IQ_NRM
mA
mA
normal (PWM) mode(2)
VIN = 13 V, BuckA: CCM, BuckB: off, TA = 125°C
VIN = 13 V, BuckB: CCM, BuckA: off, TA = 125°C
VIN = 13 V, BuckA, B: CCM, TA = 125°C
BuckA, B: off, VBAT = 13 V , TA = 25°C
BuckA, B: off, VBAT = 13 V, TA = 125°C
VIN falling
5
Quiescent current:
1.8
IQ_NRM
normal (PWM) mode(2)
7.5
2.5
3
8
4
1.9
1.10
1.11
1.12
1.13
2.0
Ibat_sh
Shutdown current
µA
µA
V
Ibat_sh
Shutdown current
5
VINLPMexit
VINLPMentry
VINLPMhys
VIN level to exit LPM
VIN level to enable entering LPM
Hysteresis
7.7
8.2
0.4
8
8.3
8.8
0.6
VIN rising
8.5
0.5
V
VIN rising or falling
V
Input Voltage VBAT - Undervoltage Lockout
VBAT falling. After a reset, initial start-up conditions
may apply.(1)
1.8
1.9
2.5
2
V
V
2.1
VBAT(UV)
Boost-input undervoltage
VBAT rising. After a reset, initial start-up conditions
may apply.(1)
2.4
2.6
2.2
2.3
3.0
UVLOHys
UVLOfilter
Hysteresis
Filter time
500
600
5
700
mV
µs
Input Voltage VIN - Overvoltage Lockout
VIN rising
VIN falling
45
43
1
46
44
2
47
45
3
3.1
VOVLO
Overvoltage shutdown
V
3.2
3.3
4.0
4.1
OVLOHys
OVLOfilter
Hysteresis
Filter time
V
5
µs
Boost Controller
Vboost7V
Boost VOUT = 7 V
DIV = low, VBAT = 2 V to 7 V
6.8
7.5
8
7
8
7.3
8.5
9
V
V
V
Boost-enable threshold
Boost-disable threshold
Boost hysteresis
Boost VOUT = 7 V, VBAT falling
Boost VOUT = 7 V, VBAT rising
Boost VOUT = 7 V, VBAT rising or falling
DIV = open, VBAT = 2 V to 10 V
4.2
4.3
Vboost7V-th
8.5
0.5
10
0.4
9.7
0.6
10.4
Vboost10V
Boost VOUT = 10 V
(1) If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.
(2) Quiescent current specification is non-switching current consumption without including the current in the external-feedback resistor
divider.
4
Copyright © 2013, Texas Instruments Incorporated
TPS43330A-Q1
www.ti.com.cn
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = –40°C to +150°C (unless otherwise noted)
NO.
4.4
4.5
4.6
PARAMETER
TEST CONDITIONS
MIN
10.5
11
TYP
11
MAX
11.5
12
UNIT
Boost-enable threshold
Boost-disable threshold
Boost hysteresis
Boost VOUT = 10 V, VBAT falling
Vboost10V-th
Vboost8.85V
Vboost8.85V-th
Boost VOUT = 10 V, VBAT rising
11.5
0.5
V
V
V
Boost VOUT = 10 V, VBAT rising or falling
DIV = VREG, VBAT = 2 V to 8.85 V
Boost VOUT = 8.85 V, VBAT falling
Boost VOUT = 8.85 V, VBAT rising
Boost VOUT = 8.85 V, VBAT rising or falling
0.4
0.6
Boost VOUT = 8.85 V
Boost-enable threshold
Boost-disable threshold
Boost hysteresis
8.35
9.15
9.65
0.4
8.85
9.85
10.35
0.5
9.35
10.45
10.85
0.6
Boost-Switch Current Limit
4.7
4.8
VDS
tDS
Current-limit sensing
Leading-edge blanking
DS input with respect to PGNDA
0.175
0.2
0.225
V
200
ns
Gate Driver for Boost Controller
IGC1 Peak Gate-driver peak current
rDS(on) Source and sink driver
Gate Driver for PMOS
4.9
1.5
A
4.10
VREG = 5.8 V, IGC1 current = 200 mA
2
20
10
Ω
4.11
4.12
4.13
rDS(on)
PMOS OFF
10
5
Ω
mA
µs
IPMOS_ON
tdelay_ON
Gate current
Turnon delay
VIN = 13.5 V, VGS = –5 V
C = 10 nF
10
Boost-Controller Switching Frequency
4.14
4.15
fsw-Boost
DBoost
Boost switching frequency
Boost duty cycle
fSW_Buck / 2
90%
kHz
Error Amplifier (OTA) for Boost Converters
VBAT = 12 V
VBAT = 5 V
0.8
1.35
0.65
4.16
GmBOOST Forward transconductance
mS
0.35
5.0
5.1
Buck Controllers
VBuckA or
VBuckB
Adjustable output-voltage range
0.9
11
V
V
Measure FBX pin
Measure FBX pin
0.792
–1%
0.8
0.8
0.808
1%
Internal reference and tolerance
voltage in normal mode
5.2
5.3
Vref, NRM
0.784
–2%
0.816
2%
V
Internal reference and tolerance
voltage in low-power mode
Vref, LPM
V sense for forward-current limit in Measured across Sx1 and Sx2, FBx = 0.75 V (low
5.4
5.5
60
75
90
mV
mV
CCM
duty-cycle)
Vsense
V sense for reverse-current limit in
CCM
Measured across Sx1 and Sx2, FBx = 1 V
Measured across Sx1 and Sx2, FBx = 0 V
–65
17
–37.5
–23
48
5.6
5.7
VI-Foldback
tdead
V sense for output short
32.5
20
mV
ns
Shoot-through delay, blanking time
High-side minimum on-time
100
ns
5.8
5.9
DCNRM
Maximum duty cycle (digitally
controlled)
98.75%
DCLPM
Duty cycle, LPM
80%
LPM entry-threshold load current
as fraction of maximum set load
current
(3)
ILPM_Entry
1%
.
5.10
LPM exit-threshold load current as
fraction of maximum set load
current
(3)
ILPM_Exit
10%
High-Side External NMOS Gate Drivers for Buck Controller
5.11
5.12
IGX1_peak
rDS(on)
Gate-driver peak current
Source and sink driver
1.5
A
VREG = 5.8 V, IGX1 current = 200 mA
2
Ω
(3) The exit threshold specification is to be always higher than the entry threshold.
Copyright © 2013, Texas Instruments Incorporated
5
TPS43330A-Q1
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = –40°C to +150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low-Side NMOS Gate Drivers for Buck Controller
5.13
5.14
IGX2_peak
RDS ON
Gate-driver peak current
Source and sink driver
1.5
A
VREG = 5.8 V, IGX2 current = 200 mA
2
Ω
Error Amplifier (OTA) for Buck Converters
GmBUCK Transconductance
Digital Inputs: ENA, ENB, ENC, SYNC
COMPA, COMPB = 0.8 V,
source/sink = 5 µA, test in feedback loop
5.15
0.72
1.7
1
1.35
mS
6.0
6.1
6.2
6.3
6.4
VIH
Higher threshold
VIN = 13 V
VIN = 13 V
VSYNC = 5 V
VENC = 5 V
V
V
VIL
Lower threshold
0.7
2
RIH_SYNC
RIL_ENC
Pulldown resistance on SYNC
Pulldown resistance on ENC
500
500
kΩ
kΩ
Pullup current source on ENA,
ENB
6.5
IIL_ENx
VENx = 0 V
0.5
µA
7.0
7.1
7.2
7.3
8.0
8.1
8.2
Boost Output Voltage: DIV
VIH_DIV
VIL_DIV
Voz_DIV
Higher threshold
VREG = 5.8 V
VREG – 0.2
V
V
V
Lower threshold
0.2
Voltage on DIV if unconnected
Voltage on DIV if unconnected
VREG / 2
Switching Parameter – Buck DC-DC Controllers
fSW_Buck
fSW_Buck
Buck switching frequency
Buck switching frequency
RT pin: GND
360
360
400
400
440
440
kHz
kHz
RT pin: 60-kΩ external resistor
Buck adjustable range with
external resistor
8.3
fSW_adj
fSYNC
RT pin: external resistor
External clock input
150
150
600
600
kHz
kHz
8.4
9.0
Buck synchronization range
Internal Gate-Driver Supply
Internal regulated supply
VIN = 8 V to 18 V, VEXTSUP = 0 V, SYNC = high
5.5
7.2
5.8
0.2%
7.5
6.1
1%
7.8
1%
V
V
9.1
VREG
IVREG = 0 mA to 100 mA, VEXTSUP = 0 V,
SYNC = high
Load regulation
Internal regulated supply
Load regulation
VEXTSUP = 8.5 V
9.2
9.3
VREG(EXTSUP)
IEXTSUP = 0 mA to 125 mA, SYNC = High
VEXTSUP = 8.5 V to 13 V
0.2%
EXTSUP switch-over voltage
threshold
IVREG = 0 mA to 100 mA,
VEXTSUP ramping positive
VEXTSUP-th
4.4
4.6
4.8
V
9.4
9.5
VEXTSUP-Hys
IVREG-Limit
EXTSUP switch-over hysteresis
Current limit on VREG
150
100
250
400
mV
mA
VEXTSUP = 0 V, normal mode as well as LPM
IVREG_EXTSUP- Current limit on VREG when using IVREG = 0 mA to 100 mA,
9.6
125
400
mA
EXTSUP
VEXTSUP = 8.5 V, SYNC = High
Limit
10.0
10.1
11.0
11.1
12.0
12.1
12.2
12.3
12.4
12.5
12.6
Soft Start
ISSx
Soft-start source current
Oscillator reference voltage
VSSA and VSSB = 0 V
40
50
60
µA
V
Oscillator (RT)
VRT
1.2
Power Good / Delay
PGth1
PGhys
PGdrop
Power-good threshold
FBx falling
–5%
–7%
2%
–9%
Hysteresis
Voltage drop
IPGA = 5 mA
450
100
1
mV
mV
µA
µs
IPGA = 1 mA
PGleak
tdeglitch
Power-good leakage
VSx2 = VPGx = 13 V
Power-good deglitch time
2
16
External capacitor = 1 nF
VBuckX < PGth1
12.7
12.8
12.9
tdelay
tdelay_fix
IOH
Reset delay
1
20
40
ms
µs
Fixed reset delay
No external capacitor, pin open
50
50
Activate current source (current to
charge external capacitor)
30
30
µA
Activate current sink (current to
discharge external capacitor)
12.10
IIL
40
50
µA
6
Copyright © 2013, Texas Instruments Incorporated
TPS43330A-Q1
www.ti.com.cn
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
DC ELECTRICAL CHARACTERISTICS (continued)
VIN = 8 V to 18 V, TJ = –40°C to +150°C (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
13.0
Overtemperature Protection
Junction-temperature shutdown
threshold
13.1
13.2
Tshutdown
Thys
150
165
15
°C
°C
Junction-temperature hysteresis
Copyright © 2013, Texas Instruments Incorporated
7
TPS43330A-Q1
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www.ti.com.cn
DEVICE INFORMATION
DAP PACKAGE
(TOP VIEW)
1
2
3
4
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VBAT
DS
VIN
EXTSUP
DIV
GC1
GC2
VREG
CBB
5
6
7
8
CBA
GA1
GB1
PHA
PHB
GA2
GB2
9
PGNDA
SA1
PGNDB
SB1
10
11
SA2
SB2
12
13
14
15
FBA
FBB
COMPA
SSA
COMPB
SSB
PGA
ENA
PGB
16
17
18
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
19
20
PIN FUNCTIONS
NAME
NO.
I/O
DESCRIPTION
AGND
23
O
Analog ground reference
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBA
5
I
I
A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck
controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the
high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBB
34
13
Error amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckA. Clamping this voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
COMPA
O
Error amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the
target for the peak current through the inductor of BuckB. Clamping this voltage on the upper and lower ends
provides current-limit protection for the external MOSFETs.
COMPB
COMPC
DIV
26
18
36
O
O
I
Error-amplifier output and loop-compensation node of the boost regulator
The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter
at 8.85 V, a low input sets the value at 7 V, and a floating pin sets 10 V. NOTE: DIV = high and ENC = high
inhibits low-power mode on the bucks.
The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-
good comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 µs typical.
DLYAB
DS
21
2
O
I
This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection. An
alternative connection for better noise immunity is to a sense resistor between the source of the low-side
MOSFET and ground via a filter network.
Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.7 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device shuts down and consumes less than 4 µA of current.
ENA
16
I
8
Copyright © 2013, Texas Instruments Incorporated
TPS43330A-Q1
www.ti.com.cn
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
PIN FUNCTIONS (continued)
NAME
NO.
I/O
DESCRIPTION
Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.7 V
enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and
ENB are low, the device shuts down and consumes less than 4 µA of current. NOTE: DIV = high and ENC = high
inhibits low-power mode on the bucks.
ENB
17
19
I
This input enables and disables the boost regulator. An input voltage higher than 1.7 V enables the controller.
Voltages lower than 0.7 V disable the controller. Because this pin provides an internal pulldown resistor (500 kΩ),
enabling the boost function requires pulling it high. When enabled, the controller starts switching as soon as VBAT
falls below the boost threshold, depending upon the programmed output voltage.
ENC
I
One can use EXTSUP to supply the VREG regulator from one of the TPS43330A-Q1 buck regulator rails to
reduce power dissipation in cases where there is an expectation of high VIN. If EXTSUP is unused, leave the pin
open without a capacitor installed.
EXTSUP
FBA
37
12
27
I
I
I
Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output
voltage.
Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of
0.8 V. A suitable resistor-divider network between the buck output and the feedback pin sets the desired output
voltage.
FBB
This output drives the external high-side N-channel MOSFET for buck regulator BuckA. The output provides high
peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHA that has
a voltage swing provided by CBA.
GA1
GA2
GB1
6
8
O
O
O
This output drives the external low-side N-channel MOSFET for buck regulator BuckA. The output provides high
peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
This output drives the external high-side N-channel MOSFET for buck regulator BuckB. The output provides high
peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHB that has
a voltage swing provided by CBB.
33
This output drives the external low-side N-channel MOSFET for buck regulator BuckB. The output provides high
peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GB2
GC1
31
3
O
O
This output drives an external low-side N-channel MOSFET for the boost regulator. This output provides high
peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET
bypasses the boost rectifier diode or a reverse-protection diode when the boost status is non-switching or
disabled, and thus reduce power losses.
GC2
PGA
PGB
4
O
O
O
Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or
VBAT drops below the respective undervoltage threshold.
15
24
Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the
feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or
VBAT drops below the respective undervoltage threshold.
PGNDA
PGNDB
9
O
O
Power-ground connection to the source of the low-side N-channel MOSFETs of BuckA
Power-ground connection to the source of the low-side N-channel MOSFETs of BuckB
30
Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gate-
driver circuitry. PHA senses current reversal in the inductor when discontinuous-mode operation is desired.
PHA
PHB
7
O
O
Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gate-
driver circuitry. PHB senses current reversal in the inductor when discontinuous-mode operation is desired.
32
Connecting a resistor to ground on this pin sets the operational switching frequency of the buck and boost
controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz
for the boost controller.
RT
22
O
SA1
SA2
SB1
SB2
10
11
29
28
I
I
I
I
High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
and VIN. (SA1 positive node, SA2 negative node).
High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for
each buck controller. Choose the current-sense element to set the maximum current through the inductor based
on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle
and VIN. (SB1 positive node, SB2 negative node).
Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of
0.8 V or the SSA pin voltage. An internal pullup current source of 50 µA is present at the pin, and an appropriate
capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another
supply provides a tracking input to this pin.
SSA
14
O
Copyright © 2013, Texas Instruments Incorporated
9
TPS43330A-Q1
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
PIN FUNCTIONS (continued)
NAME
NO.
I/O
DESCRIPTION
Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of
0.8 V or the SSB pin voltage. An internal pullup current source of 50 µA is present at the pin, and an appropriate
capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another
supply provides a tracking input to this pin.
SSB
25
O
If an external clock is present on this pin, the device detects it and the internal PLL locks onto the external clock,
overriding the internal oscillator frequency. The device synchronizes frequencies from 150 to 600 kHz. A high-logic
level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits transition to low-
power mode. An open or low allows discontinuous-mode operation and entry into low-power mode at light loads.
SYNC
20
I
Battery input sense for the boost controller. If, with the boost controller enabled, the voltage at VBAT falls below
the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed
boost output voltage.
VBAT
VIN
1
I
I
Main Input pin. VIN is the buck-controller input pin as well as the output of the boost regulator. Additionally, VIN
powers the internal control circuits of the device.
38
35
The device requires an external capacitor on this pin to provide a regulated supply for the gate drivers of the buck
and boost controllers. TI recommends capacitance on the order of 4.7 µF. The regulator obtains power from either
VIN or EXTSUP. This pin has current-limit protection; do not use it to drive any other loads.
VREG
O
10
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TPS43330A-Q1
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ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
5
CBA
Duplicate for second
Buck controller channel
Internal ref
(Band gap)
38
VIN
6
7
8
9
GA1
Gate Driver
Supply
37
35
EXTSUP
VREG
PWM
Logic
PHA
VREG
GA2
PGNDA
Internal
Oscillator
22
20
Slope
Comp
RT
Current sense
Amp
10
11
12
SA1
SA2
FBA
PWM
comp
SYNC and
LPM
SYNC
OTA
Gm
0.8 V
Source
and
Sink
SSA
4
GC2
Logic
13
15
COMPA
PGA
SA2
FBA
ENC
50 µA
14
16
25
SSA
ENA
SSB
VIN
Filter timer
ENA
500 nA
40 µA
40 µA
VIN
21
DLYAB
50 µA
ENB
500 nA
34
33
32
31
30
29
28
27
26
24
CBB
17
2
ENB
DS
GB1
OCP
OTA
Gm
VIN
VboostxV
PHB
0.2 V
18
36
COMPC
DIV
GB2
Second
Buck
Controller
Channel
PGNDB
SB1
Ramp
Vboost7V-th
Vboost8.85V-th
Vboost10V-th
1
VBAT
SB2
MUX
FBB
COMPB
PGB
PWM
comp
VREG
3
GC1
ENC
PWM
Logic
19
23
PGNDA
AGND
Figure 2. Functional Block Diagram
Copyright © 2013, Texas Instruments Incorporated
11
TPS43330A-Q1
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS
EFFICIENCY ACROSS OUTPUT CURRENTS (BUCKS)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR CURRENTS (BUCK)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mW
INDUCTOR = 4.7 µH, RSENSE = 10 mW
10000
100
EFFICIENCY,
SYNC = LOW
FORCED CONTINUOUS MODE (SYNC = 1), 200-mA LOAD
90
80
70
60
50
40
30
20
10
0
1 A/DIV
1000
100
10
POWER LOSS,
SYNC = HIGH
DISCONTINUOUS MODE (SYNC = 0), 200-mA LOAD
1 A/DIV
1 A/DIV
POWER LOSS,
SYNC = LOW
1
EFFICIENCY,
SYNC = HIGH
LOW-POWER MODE (SYNC = 0), 20-mA LOAD
0.1
2 µs/DIV
0.0001
0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
Figure 3.
Figure 4.
BUCK LOAD STEP: FORCED CONTINUOUS MODE
(0 TO 4 A AT 2.5 A/µs)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
SOFT-START OUTPUTS (BUCKS)
INDUCTOR = 4.7 µH, RSENSE = 10 mW
VOUT AC-COUPLED
VOUT BuckA, 1V / DIV
100 mV/DIV
VOUT BuckB, 0.5 V / DIV
2 A/DIV
IIND
5 ms / DIV
50 µs/DIV
Figure 5.
Figure 6.
BUCK LOAD STEP: LOW-POWER-MODE ENTRY
(4 A TO 90 mA AT 2.5 A/µs)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
BUCK LOAD STEP: LOW-POWER-MODE EXIT
(90 mA TO 4 A AT 2.5 A/µs)
VIN = 12 V, VOUT = 5 V, SWITCHING FREQUENCY = 400 kHz
INDUCTOR = 4.7 µH, RSENSE = 10 mW
INDUCTOR = 4.7 µH, RSENSE = 10 mW
100 mV/DIV
100 mV/DIV
VOUT AC-COUPLED
VOUT AC-COUPLED
2 A/DIV
IIND
2 A/DIV
IIND
50 µs/DIV
Figure 8.
50 µs/DIV
Figure 7.
12
Copyright © 2013, Texas Instruments Incorporated
TPS43330A-Q1
www.ti.com.cn
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS (continued)
LOAD STEP RESPONSE (BOOST)
(0 TO 5 A AT 10 A/µs)
EFFICIENCY ACROSS OUTPUT CURRENTS (BOOST)
VBAT (BOOST INPUT) = 5 V, VIN (BOOST OUTPUT) = 10 V,
VIN (BOOST OUTPUT) = 10 V, SWITCHING FREQUENCY = 200 kHz,
SWITCHING FREQUENCY = 200 KHz, INDUCTOR = 680 nH,
INDUCTOR = 1 µH, RSENSE = 7.5 mW
RSENSE = 10 mꢀ, CIN = 440 ꢁF, COUT = 660 ꢁF
100
90
VBAT = 8 V
80
70
VBAT = 5 V
60
VBAT = 3 V
50
40
30
20
10
0
0.01
1
10
Output Current (A)
Figure 9.
Figure 10.
CRANKING-PULSE BOOST RESPONSE
CRANKING-PULSE BOOST RESPONSE
(12 V TO 4 V IN 1 ms AT BOOST DIRECT OUTPUT 25 W)
VIN (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,
(12 V TO 3 V IN 1 ms AT BUCK OUTPUTS 7.5 AND 11.5 W)
VIN (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,
BuckB = 3.3 V AT 3.5 A, SWITCHING FREQUENCY = 200 kHz,
INDUCTOR = 1 µH, RSENSE = 7.5 mW, CIN = 440 µF, COUT = 660 µF
BuckB = 3.3V AT 3.5A, SWITCHING FREQUENCY = 200 kHz,
INDUCTOR = 1 µH, RSENSE = 7.5 mW, CIN = 440 µF, COUT = 660 µF
VBAT (BOOST INPUT)
5 V/DIV
VBAT (BOOST INPUT)
5 V/DIV
0 V
0 V
VIN (BOOST OUTPUT)
VOUT BuckA AC-COUPLED
200 mV/DIV
5 V/DIV
VOUT BuckB AC-COUPLED
200 mV/DIV
0V
10 A/DIV
10 A/DIV
0 A
IIND
IIND
0 A
20 ms/DIV
20 ms/DIV
Figure 12.
Figure 11.
INDUCTOR CURRENTS (BOOST)
VBAT (BOOST INPUT) = 5 V, VIN (BOOST OUTPUT) = 10 V,
SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 µH,
RSENSE = 7.5 mW, CIN = 440 µF, COUT = 660 µF
3-A LOAD
5 A/DIV
100-mA LOAD
5 A/DIV
2 µs/DIV
Figure 13.
Copyright © 2013, Texas Instruments Incorporated
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TPS43330A-Q1
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www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
NO-LOAD QUIESCENT CURRENT
versus
BUCKx PEAK CURRENT LIMIT
versus
TEMPERATURE
COMPx VOLTAGE
60
50
40
30
20
10
0
75
62.5
50
BOTH BUCKS ON
37.5
25
12.5
0
SYNC = LOW
ONE BUCK ON
–12.5
–25
–37.5
NEITHER BUCK ON
SYNC = HIGH
0.8 0.95
-40 -15 10
35
60
85 110 135 160
0.65
1.1
1.25
1.4
1.55
Temperature (°C)
COMPx Voltage (V)
Figure 15.
Figure 14.
CURRENT-SENSE PINS INPUT CURRENT (BUCK)
0.9
FOLDBACK CURRENT LIMIT (BUCK)
80
70
60
50
40
30
20
10
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
150°C
25°C
–0.1
–0.2
–0.3
0
1
2
3
4
5
6
7
8
9
10 11 12
0
0.2
0.4
0.6
0.8
Output Voltage (V)
FBx Voltage (V)
Figure 17.
Figure 16.
REGULATED FBx VOLTAGE
versus
TEMPERATURE (BUCK)
CURRENT LIMIT
versus
DUTY CYCLE (BUCK)
80
70
60
50
40
30
20
10
0
805
804
803
802
801
800
799
798
797
796
795
VIN = 8 V
VIN = 12 V
0
10 20 30 40 50 60 70 80 90 100
–40 –15 10
35
60
85 110 135 160
Duty Cycle (%)
Temperature (°C)
Figure 18.
Figure 19.
14
Copyright © 2013, Texas Instruments Incorporated
TPS43330A-Q1
www.ti.com.cn
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
DETAILED DESCRIPTION
BUCK CONTROLLERS: NORMAL MODE PWM OPERATION
Frequency Selection and External Synchronization
The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior
and ease of component choices. The switching frequency is programmable between 150 and 600 kHz,
depending upon the resistor value at the RT pin. A short-circuit to ground at this pin sets the default switching
frequency to 400 kHz. Using a resistor at RT, set another frequency according to Equation 1.
X
fSW
=
(X = 24 kW´MHz)
RT
109
fSW = 24´
(1)
For example,
600 kHz requires 40 kΩ
150 kHz requires 160 kΩ
Synchronizing to an external clock at the SYNC pin in the same frequency range of 150 to 600 kHz is also
possible. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the
specified range. The device also detects a loss of clock at this pin, and on detection of this condition, the device
sets the switching frequency to the internal oscillator. The two buck controllers operate at identical switching
frequencies, 180 degrees out-of-phase.
Enable Inputs
Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins,
with a threshold of 1.7 V for the high level, and with which direct connection to the battery is permissible for self-
bias. The low threshold is 0.7 V. These pins have internal pullup currents of 0.5 µA (typical). As a result, an open
circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device
shuts down and consumes a current of less than 4 µA.
Feedback Inputs
The resistor-feedback divider network connected to the FBx (feedback) pins sets the output voltage. Choose this
network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-nA pullup current
source as a protection feature in case the pins open up as a result of physical damage.
Soft-Start Inputs
In order to avoid large inrush currents, each buck controller has an independent programmable soft-start timer.
The voltage at the SSx pin acts as the soft-start reference voltage. The 1-µA pullup current available at the SSx
pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After
start-up, the pullup current ensures that SSx is higher than the internal reference of 0.8 V; 0.8 V then becomes
the reference for the buck controllers. Equation 2 calculates the soft-start ramp time:
I
SS ´ Dt
CSS
=
(Farads)
D
where,
•
•
•
ISS = 50 µA (typical)
∆V = 0.8 V
CSS is the required capacitor for ∆t, the desired soft-start time
(2)
An alternative use of the soft-start pins is as tracking inputs. In this case, connect them to the supply to be
tracked via a suitable resistor-divider network.
Copyright © 2013, Texas Instruments Incorporated
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www.ti.com.cn
Current-Mode Operation
Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at the
set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the
output of the error amplifier (COMPx) which serves as the target for the peak inductor current. The device
senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this
target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing VCOMPx to
fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current
matches the load. This process maintains the output voltage in regulation.
The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current
reaches the peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower N-
channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET
stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the
bootstrap capacitor at CBx, which allows a maximum duty cycle of 98.75% for the buck regulators. During
dropout, the buck regulator switches at one-fourth of the normal frequency.
Current Sensing and Current Limit With Foldback
Clamping of the maximum value of COMPx limits the maximum current through the inductor to a specified value.
When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value due to a short
circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus providing current
foldback protection, which protects the high-side external MOSFET from excess current (forward-direction current
limit).
Similarly, if a fault condition shorts the output to a high voltage and the low-side MOSFET turns fully on, the
COMPx node drops low. A clamp is on the lower end as well in order to limit the maximum current in the low-side
MOSFET (reverse-direction current limit).
An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum
forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified value is
for low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5 V output and 12 V input), 50
mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics (see
Figure 19) provide a guide for using the correct current-limit sense voltage.
The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range,
thus allowing DCR current-sensing using the dc resistance of the inductor for higher efficiency. Figure 20 shows
DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter
components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency,
it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance.
Hence, using the more-accurate sense resistor for current sensing is advantageous.
Inductor L
TPS43330A-Q1
VBuckX
DCR
R11
C11
Sx22
VC
Sx11
Figure 20. DCR Sensing Configuration
16
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ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
Slope Compensation
Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable
operation under all conditions. For optimal performance of this circuit, choose the inductor and sense resistor
according to the following:
L ´ fSW
= 200
RS
where
•
•
•
L is the buck-regulator inductor in henries
RS is the sense resistor in ohms
fsw is the buck-regulator switching frequency in hertz
(3)
Power-Good Outputs and Filter Delays
Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx
pins and indicating whether the output voltage falls below a specified power-good threshold. This threshold has a
typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-drain
output at the PGx pins. Shutdown of a buck controller causes an internal pulldown of the power-good indicator.
Connecting the pullup resistor to a rail other than the output of that particular buck channel causes a constant-
current flow through the resistor when the buck controller is powered down.
In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the
device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to the set value
after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after
the same delay. Use of this delay pauses the reset of circuits powered from the buck-regulator rail. Program the
duration of the delay by using a suitable capacitor at the DLYAB pin according to Equation 4.
tDELAY
1 msec
=
CDLYAB
1 nF
(4)
When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay
timing is common to both the buck rails, but the power-good comparators and indicators function independently.
Light-Load PFM Mode
An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An
open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by
turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.
In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn
off increases (deep-discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V,
the buck controller switches to a low-power operation mode. The design ensures that this switching typically
occurs at 1% of the set full-load current if the choice of the inductor and sense resistor is as recommended in the
Slope Compensation section.
In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference.
Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely
proportional to the difference VIN – Sx2. At the end of this on-time, the high-side MOSFET turns off and the
current in the inductor decays until the current becomes zero. The low-side MOSFET does not turn on. The next
pulse occurs the next time FBx falls below the reference value. This pulsing results in a constant volt-second ton
hysteretic operation with a total device-quiescent current consumption of 30 µA when a single-buck channel is
active and of 35 µA when both channels are active.
As the load increases, the pulses become more and more frequent and move closer to each other until the
current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency
current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher
than 80% duty cycle of the high-side MOSFET.
The TPS43330A-Q1 supports the full-current load during low-power mode until the transition to normal mode
takes place. The design ensures that exit of the low-power mode occurs at 10% (typical) of full-load current if the
selection of the inductor and sense resistor is as recommended. Moreover, a hysteresis always exists between
the entry and exit thresholds to avoid oscillating between the two modes.
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In the event that both buck controllers are active, low-power mode is only possible when both buck controllers
have light loads that are low enough for low-power mode entry. With the boost controller enabled, low-power
mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set to
GND. A high (VREG) level on DIV inhibits low-power mode, unless ENC is set to low.
Boost Controller
The boost controller has a fixed-frequency voltage-mode architecture and includes cycle-by-cycle current-limit
protection for the external N-channel MOSFET. The boost-controller switching-frequency setting is one-half of the
buck-controller switching frequency. An internal resistor-divider network programmable to 7 V, 8.85 V, or 10 V
sets the output voltage of the boost controller at the VIN pin, based on the low, open, or high status, respectively,
of the DIV pin. The device does not recognize a change of the DIV setting while in the low-power mode.
The active-high ENC pin enables the boost controller, which is active when the input voltage at the VBAT pin has
crossed the unlock threshold of 8.5 V at least once. A single threshold crossing arms with the boost controller,
which starts switching as soon as VIN falls below the value set by the DIV pin, regulating the VIN voltage. Thus,
the boost regulator maintains a stable input voltage for the buck regulators during transient events such as a
cranking pulse at VBAT.
A voltage at the DS pin exceeding 200 mV pulls the CG1 pin low, turning off the boost external MOSFET.
Connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET source and
ground achieves cycle-by-cycle overcurrent protection for the MOSFET. Choose the on-resistance of the
MOSFET or the value of the sense resistor in such a way that the on-state voltage at DS does not exceed 200
mV at the maximum-load and minimum-input-voltage conditions. When using a sense resistor, TI recommends
connecting a filter network between the DS pin and the sense resistor for better noise immunity.
The boost output (VIN) supplies other circuits in the system, however, they should be high-voltage tolerant. The
device regulates the boost output to the programmed value only when VIN is low, and so VIN reaches battery
levels.
VBAT
VIN
DS
TPS43330A-Q1
GC1
Figure 21. External Drain-Source Voltage Sensing
VBAT
VIN
TPS43330A-Q1
GC1
RIFLT
DS
CIFLT
RISEN
Figure 22. External Current Shunt Resistor
18
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Table 1. Mode Control
SYNC
Terminal
Comments
External clock
Device in forced-continuous mode, internal PLL locks into external clock between 150 and 600 kHz.
Device enters discontinuous mode. Automatic LPM entry and exit, depending on load conditions
Device in forced continuous mode
Low or open
High
Table 2. Mode of Operation
ENABLE AND INHIBIT PINS
ENA ENB ENC SYNC
DRIVER STATUS
DEVICE STATUS
QUIESCENT CURRENT
BUCK CONTROLLERS
BOOST CONTROLLER
Disabled
Low
Low
Low
X
Shut down
Shutdown
Approximately 4 µA
Approximately 30 µA (light loads)
mA range
Low
High
Low
High
BuckB: LPM enabled
BuckB: LPM inhibited
BuckA: LPM enabled
BuckA: LPM inhibited
Low
High
Low
BuckB running
BuckA running
Disabled
Disabled
Approximately 30 µA (light loads)
mA range
High
High
Low
Low
Low
BuckA and BuckB: LPM
enabled
Low
Approximately 35 µA (light loads)
BuckA and BuckB
running
High
Disabled
Disabled
BuckA and BuckB: LPM
inhibited
High
X
mA range
Low
Low
Low
Low
Shut down
Shutdown
Approximately 4 µA
Approximately 50 µA (no boost,
light loads)
Low
High
Low
High
Low
BuckB: LPM enabled
BuckB: LPM inhibited
BuckA: LPM enabled
BuckA: LPM inhibited
Boost running for VIN < set
boost output
High
High
BuckB running
mA range
Approximately 50 µA (no boost,
light loads)
Boost running for VIN < set
boost output
High
High
Low
High
High
BuckA running
mA range
BuckA and BuckB: LPM
enabled
Approximately 60 µA (no boost,
light loads)
BuckA and BuckB
running
Boost running for VIN < set
boost output
High
BuckA and BuckB: LPM
inhibited
High
mA range
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Gate-Driver Supply (VREG, EXTSUP)
The gate-driver supplies of the buck and boost controllers are from an internal linear regulator whose output (5.8
V typical) is on the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3 to 10 µF. This
pin has internal current-limit protection; do not use it to power any other circuits.
VIN powers the VREG linear regulator by default when the EXTSUP voltage is lower than 4.6 V (typical). If there
is an expectation of VIN going to high levels, an excessive power dissipation occurs in this regulator, especially at
high switching frequencies and when using large external MOSFETs. In this case, powering this regulator from
the EXTSUP pin, which has a connection to a supply lower than VIN but high enough to provide the gate drive, is
advantageous. When the voltage on EXTSUP is greater than 4.6 V, the linear regulator automatically switches to
EXTSUP as its input, to provide this advantage. Efficiency improvements are possible when using one of the
switching regulator rails from the TPS43330A-Q1 or any other voltage available in the system to power EXTSUP.
The maximum voltage for application to EXTSUP is 9 V.
VIN
EXTSUP
LDO
VIN
LDO
EXTSUP
typ 5.8 V
typ 7.5 V
typ 4.6 V
VREG
Figure 23. Internal Gate-Driver Supply
Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous, as this voltage provides a large
gate drive and hence better on-resistance of the external MOSFETs.
During low-power mode, the EXTSUP functionality is unavailable. The internal regulator operates as a shunt
regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in
low-power mode as well. If EXTSUP is unused, leave the pin open without a capacitor installed.
External P-Channel Drive (GC2) and Reverse-Battery Protection
The TPS43330A-Q1 includes a gate driver for an external P-channel MOSFET which connects across the
rectifier diode of the boost regulator. Such connection is useful to reduce power losses when the boost controller
is not switching. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-
channel MOSFET. When VBAT falls below the boost-enable threshold, the gate driver turns off the P-channel
MOSFET, eliminating the diode bypass.
Another use for the gate driver is to bypass any additional protection diodes connected in series, as shown in
Figure 24. Figure 25 also shows a different scheme of reverse battery protection, which may require only a
smaller-sized diode to protect the N-channel MOSFET, as the diode conducts only for a part of the switching
cycle. Because the diode is not always in the series path, the system efficiency improves.
20
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R10
GC2
TPS43330A-Q1
D3
Q7
Q6
L3
Fuse (S1)
VBAT
VIN
DS
D1
D2
C17
C15
C16
C14
GC1
COMPC
C13
R9
VBAT
Figure 24. Reverse-Battery Protection Option 1 for Buck-Boost Configuration
GC2
VBAT
VIN
Fuse
TPS43330A-Q1
DS
GC1
COMPC
VBAT
Figure 25. Reverse-Battery Protection Option 2 for Buck-Boost Configuration
Undervoltage Lockout and Overvoltage Protection
The TPS43330A-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG).
Once the device starts up, it operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage
lockout disables the device.
NOTE
If VIN drops, VREG drops as well which reduces the gate-drive voltage, whereas the digital
logic is fully functional. Even if ENC is high, there is a requirement to exceed the boost-
unlock voltage of typically 8.5 V once, before boost activation takes place (see the Boost
Controller section).
A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the device. In order to prevent
transient spikes from shutting down the device, the undervoltage and overvoltage protection have filter times of 5
µs (typical).
When the voltages return to the normal-operating region, the enabled switching regulators start including a new
soft-start ramp for the buck regulators.
With the boost controller enabled, a voltage less than 1.9 V (typical) on VBAT triggers an undervoltage lockout
and pulls the boost-gate driver (GC1) low (this action has a filter delay of 5 µs, typical). As a result, VIN falls at a
rate dependent on the capacitor and load, eventually triggering VIN undervoltage. A short-falling transient at
VBAT even lower than 2 V thus survives if VBAT returns above 2.5 V before VIN discharges to the undervoltage
threshold.
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Thermal Protection
The TPS43330A-Q1 protects from overheating using an internal thermal-shutdown circuit. If the die temperature
exceeds the thermal-shutdown threshold of 165ºC due to excessive power dissipation (for example, due to fault
conditions such as a short circuit at the gate drivers or VREG), the controllers turn off and then restart when the
temperature falls by 15ºC.
22
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APPLICATION INFORMATION
The following example illustrates the design process and component selection for the TPS43330A-Q1. Table 3
lists the design-goal parameters.
Table 3. Application Example
PARAMETER
VBuckA
VBuckB
BOOST
VIN = 6 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
VBAT = 5 V (cranking
pulse input) to 30 V
Input voltage
Output voltage, VOUTx
5 V
3 A
3.3 V
2 A
10 V
2.5 A
±0.5 V
Maximum output current, IOUTx
Load-step output tolerance, ∆VOUT
∆VOUT(Ripple)
+
±0.2 V
±0.12 V
Current output load-step, ∆IOUTx
0.1 to 3 A
400 kHz
0.1 to 2 A
400 kHz
0.1 to 2.5 A
200 kHz
Converter switching frequency, fSW
This example is a starting point and theoretical representation of the values for use in the application; improving
the performance of the device may require further optimization of the derived components.
Boost Component Selection
A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in its
transfer function. The RHP zero relates inversely to the load current and inductor value and directly to the input
voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the bandwidth is too
close to the RHP zero frequency, the regulator becomes unstable.
Thus, for high-power systems with low input voltages, choose a low inductor value. A low value increases the
amplitude of the ripple currents in the N-channel MOSFET, the inductor, and the capacitors for the boost
regulator. Select these components with the ripple-to-RHP zero trade-off in mind and considering the power
dissipation effects in the components due to parasitic series resistance.
A boost converter that operates always in the discontinuous mode does not contain the RHP zero in the transfer
function. However, designing for the discontinuous mode demands an even lower inductor value that has high
ripple currents. Also, ensure that the regulator never enters the continuous-conduction mode; otherwise, it
becomes unstable.
VIN
C O
7V
OTA-gmEA
COMPx
R ESR
-
8.85V
C 1
+
VREF
C 2
R3
10V
Figure 26. Boost Compensation Components
This design assumes operation in continuous-conduction mode. During light-load conditions, the boost converter
operates in discontinuous mode without affecting stability. Hence, the assumptions here cover the worst case for
stability.
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Boost Maximum Input Current IIN_MAX
The maximum input current flows at the minimum input voltage and maximum load. The efficiency for VBAT = 5 V
at 2.5 A is 80%, based on the typical characteristics plot.
POUT
25 W
P
=
=
= 31.3 W
INmax
Efficiency
0.8
(5)
(6)
Hence,
31.3 W
I
(at VBAT = 5 V) =
= 6.3 A
INmax
5 V
Boost Inductor Selection, L
Allow input ripple current of 40% of IIN max at VBAT = 5 V.
V
BAT ´ tON
VBAT
5 V
L =
=
=
IINripplemax ´ 2´ fSW 2.52 A ´ 2´ 200 kHz
= 4.9 mH
IINripplemax
(7)
Choose a lower value of 4 µH in order to ensure a high RHP-zero frequency while making a compromise that
expects a high current ripple. This inductor selection also makes the boost converter operate in discontinuous
conduction mode, where it is easier to compensate.
The inductor-saturation current must be higher than the peak-inductor current and some percentage higher than
the maximum current-limit value set by the external resistive-sensing element.
Determine the saturation rating at the minimum input voltage, maximum output current, and maximum core
temperature for the application.
Inductor Ripple Current, IRIPPLE
Based on an inductor value of 4 µH, the ripple current is approximately 3.1 A.
Peak Current in Low-Side FET, IPEAK
IRIPPLE
3.1 A
IPEAK = IINmax
+
= 6.3 A +
= 7.85 A
2
2
(8)
(9)
Based on this peak current value, calculate the external current-sense resistor RSENSE
.
0.2 V
RSENSE
=
= 25 mW
7.85 A
Select 20 mΩ, allowing for tolerance.
The filter component values RIFLT and CIFLT for current sense are 1.5 kΩ and 1 nF, respectively, which allows for
good noise immunity.
Right Half-Plane Zero RHP Frequency, fRHP
VBATmin
fRHP
=
= 32 kHz
2p´IINmax ´L
(10)
24
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Output Capacitor, COUTx
To ensure stability, choose output capacitor COUTx such that
fRHP
fLC
£
10
VBATmin
10
£
2p´IINmax ´L
2p´ L ´ COUTx
ö2
÷
æ
ö2
10´IINmax
æ
ç
è
10´ 6.3 A
5 V
COUTx ³ ç
÷ ´L =
´ 4 mH
ç
è
÷
ø
VBATmin
ø
COUTx min ³ 635 mF
(11)
Select COUTx = 680 µF.
This capacitor is usually aluminum electrolytic with ESR in the tens-of-milliohms. ESR in this range is good for
loop stability, because it provides a phase boost. The output filter components, L and C, create a double pole
(180-degree phase shift) at a frequency fLC and the ESR of the output capacitor RESR creates a zero for the
modulator at frequency fESR. One can determine these frequencies by Equation 12.
1
fESR
=
Hz, assume RESR = 40 mW
2p´COUTx ´RESR
1
fESR
=
= 6 kHz
2p´ 660 mF´0.04 W
1
1
fLC
=
=
2p´ L´COUTx 2p´ 4 mH´ 660 mF
= 3.1 kHz
(12)
This satisfies fLC ≤ 0.1 fRHP
.
Bandwidth of Boost Converter, fC
Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response:
fLC < fESR< fC< fRHP Zero
fC < fRHP Zero / 3
fC < fSW / 6
fLC < fC / 3
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Output Ripple Voltage Due to Load Transients, ∆VOUTx
Assume a bandwidth of fC = 10 kHz.
DIOUTx
DVOUTx = RESR ´ DIOUTx
+
4´ COUTx ´ fC
2.5 A
= 0.04 W´ 2.5 A +
= 0.19 V
4´ 660 mF´10 kHz
(13)
Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters
are high-voltage tolerant, a higher excursion on the boost output is tolerable in some cases. In such cases,
choose smaller components for the boost output.
Selection of Components for Type II Compensation
The required loop gain for unity-gain bandwidth (UGB) is
æ
ö
fC
fC
æ
ö
G = 40 logç
÷ - 20 log
ç
÷
ç
÷
ç
è
÷
ø
fLC
f ESR
è
ø
æ 10 kHz ö
æ 10 kHz ö
G = 40 log
- 20 log
= 15.9 dB
÷
ç
÷
ç
3.1kHz
6 kHz
è
ø
è
ø
(14)
The boost-converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage, which allows a
constant loop response across the input-voltage range and makes compensation easier by removing the
dependency on VBAT
.
10G/20
85´10-6 A / V2 ´ VOUTx
R3 =
C1=
C2 =
= 7.2 kW
10
10
=
= 22 nF
2p´ fC ´R3 2p´10 kHz ´ 7.2 kW
C1
22 nF
=
= 223 pF
f
200 kHz
2
æ
ö
æ
ö
SW
2p´ 7.2 kW ´ 22 nF´
-1
2p´R3´ C1´
-1
ç
÷
ç
÷
2
è
ø
è
ø
(15)
Input Capacitor, CIN
The input ripple required is lower than 50 mV.
IRIPPLE
DVC1
=
= 10 mV
8´ fSW ´CIN
IRIPPLE
CIN
=
= 194-μF
8´ fSW ´ DVC1
DVESR = IRIPPLE ´RESR = 40 mV
(16)
Therefore, TI recommends 220 µF with 10-mΩ ESR.
26
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Output Schottky Diode D1 Selection
Maximizing efficiency requires a Schottky diode with low forward-conducting voltage VF over temperature and
fast switching characteristics. The reverse breakdown voltage must be higher than the maximum input voltage,
and the component must have low reverse leakage current. Additionally, the peak forward current must be higher
than the peak inductor current. Equation 17 gives the power dissipation in the Schottky diode:
PD = ID(PEAK) ´ VF ´(1- D)
VINMIN
5 V
D = 1-
= 1-
= 0.53
VOUT + VF
10 V + 0.6 V
PD = 7.85 A ´0.6 V ´(1- 0.53) = 2.2 W
(17)
Low-Side MOSFET (BOT_SW3)
V ´I
æ
ö
I
Pk
PBOOSTFET = (IPk )2 ´rDS(on)(1+ TC)´D +
´(t + t )´ f
ç
÷
r
f
SW
ç
÷
2
è
ø
V ´I
æ
ç
è
ö
Pk
I
PBOOSTFET = (7.85 A)2 ´ 0.02 W ´ (1+ 0.4)´ 0.53 +
´(20 ns + 20 ns)´ 200 kHz = 1.07 W
÷
2
ø
(18)
The times tr and tf denote the rising and falling times of the switching node and relate to the gate-driver strength
of the TPS43330A-Q1 and gate Miller capacitance of the MOSFET. The first term, tr, denotes the conduction
losses, which the low on-resistance of the MOSFET minimizes. The second term, tf, denotes the transition losses
which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on
or off. Transition losses are higher at high output currents and low input voltages (due to the large input peak
current), and when the switching time is low.
NOTE
The on-resistance, rDS(on), has a positive temperature coefficient, which produces the (TC
= d × ΔT) term that signifies the temperature dependence. (Temperature coefficient d is
available as a normalized value from MOSFET data sheets and has an assumed starting
value of 0.005 per °C.)
BuckA Component Selection
BuckA Component Selection
VOUTA
3.3 V
tON min
=
=
= 275 ns
VIN max ´ fSW 30 V ´ 400 kHz
(19)
tON
is higher than the minimum duty cycle specified (100 ns typical). Hence, the minimum duty cycle is
min
achievable at this frequency.
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Current-Sense Resistor RSENSE
Based on the typical characteristics for the VSENSE limit with VIN versus duty cycle, the sense limit is
approximately 65 mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple
currents, choose a VSENSE maximum of 50 mV.
50 mV
RSENSE
=
= 17 mW
3 A
(20)
Select 15 mΩ.
Inductor Selection L
As explained in the description of the buck controllers (see DETAILED DESCRIPTION), for optimal slope
compensation and loop response, choose the inductor such that:
RSENSE
15 mW
L = KFLR
´
= 200´
= 7.5 mH
fSW
400 kHz
•
KFLR = coil-selection constant = 200
(21)
Choose a standard value of 8.2 µH. For the buck converter, choose the inductor saturation currents and core to
sustain the maximum currents.
Inductor Ripple Current IRIPPLE
At the nominal input voltage of 12 V, this inductor value causes a ripple current of 30% of IOUT max ≈ 1 A.
Output Capacitor COUTA
Select an output capacitance COUTA of 100 µF with low ESR in the range of 10 mΩ, giving ∆VOUT(Ripple) ≈ 15 mV
and a ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within
the required limits.
2´ DIOUTA
=
fSW ´ DVOUTA 400 kHz ´0.2 V
2´ 2.9 A
COUTA
»
= 72.5 mF
(22)
(23)
(24)
IOUTA(Ripple)
1 A
VOUTA(Ripple)
=
+ IOUTA(Ripple) ´ESR =
+1 A ´10 mW = 13.1mV
8´ fSW ´ COUTA
8´ 400 kHz ´100 mF
DIOUTA
2.9 A
4´ 50 kHz ´100 mF
DVOUTA
=
+ DIOUTA ´ESR =
+ 2.9 A ´10 mW = 174 mV
4´ fC ´ COUTA
Bandwidth of Buck Converter fC
Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between
stability and transient response.
•
•
•
Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz.
Select the zero fz ≈ fC / 10
Make the second pole fP2 ≈ fSW / 2
28
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Selection of Components for Type II Compensation
VOUT
RESR
COUT
R1
R2
VSENSE
RL
COMP
Type 2A
GmBUCK
VREF
R3
R0
C2
C1
Figure 27. Buck Compensation Components
2p´ fC ´ VOUT ´ COUTx
GmBUCK ´KCFB ´ VREF
2p´ 50 kHz ´ 5 V ´100μF
GmBUCK ´KCFB ´ VREF
R3 =
=
= 23.57 kW
where
•
•
•
•
•
VOUT = 5 V
COUT = 100 µF
GmBUCK = 1 mS
VREF = 0.8 V
KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an internal constant)
(25)
(26)
Use the standard value of R3 = 24 kΩ.
10
10
C1=
=
2p´R3 ´ fC 2p´ 24 kW ´ 50 kHz
= 1.33 nF
Use the standard value of 1.5 nF.
C1
1.5 nF
C2 =
=
= 33 pF
f
400 kHz
æ
ç
ö
÷
æ
ö
SW
2p´ 24kW´1.5 nF
-1
2p´R3´ C1
-1
ç
÷
2
2
è
ø
è
ø
(27)
The resulting bandwidth of buck converter fC
GmBUCK ´R3´KCFB VREF
fC =
´
2p´COUTx
VOUT
1mS´ 24 kW´8.33 S´0.8 V
2p´100 μF´ 5 V
fC =
= 50.9 kHz
(28)
(29)
fC is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
1
1
fZ1
=
=
2p´R3´ C1 2p´ 24 kW ´1.5 nF
= 4.42 kHz
fZ1 is close to the fC / 10 guideline of 5 kHz.
The second pole frequency fP2
1
1
fP2
=
=
2p´R3´ C2 2p´ 24 kW ´33 pF
= 201kHz
(30)
29
fP2 is close to the fSW / 2 guideline of 200 kHz. Hence, the design satisfies all requirements for a good loop.
Copyright © 2013, Texas Instruments Incorporated
TPS43330A-Q1
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
Resistor Divider Selection for Setting VOUTA Voltage
VREF
0.8 V
b =
=
= 0.16
VOUTA
5 V
(31)
Choose the divider current through R1 and R2 to be 50 µA. Then
5 V
R1+ R2 =
= 66 kW
50 mA
(32)
(33)
and
R2
= 0.16
R1+ R2
Therefore, R2 = 16 kΩ and R1 = 84 kΩ.
BuckB Component Selection
Using the same method as for VBuckA produces the following parameters and components.
VOUTB
3.3 V
tON min
=
=
= 275 ns
V
IN max ´ fSW 30 V ´ 400 kHz
(34)
(35)
This result is higher than the minimum duty cycle specified (100 ns typical).
60 mV
RSENSE
=
= 30 mW
2 A
30 mW
400 kHz
L = 200´
= 15 mH
∆Iripple current ≈ 0.4 A (approximately 20% of IOUT max
)
Select an output capacitance COUTB of 100 µF with low ESR in the range of 10 mΩ.
Assume fC = 50 kHz.
2´ DIOUTB
=
fSW ´ DVOUTB 400 kHz ´ 0.12 V
2´1.9 A
COUTB
»
= 46 mF
(36)
IOUTB(Ripple)
0.4 A
VOUTB(Ripple)
=
+ IOUTB(Ripple) ´ESR =
+ 0.4 A ´10 mW = 5.3 mV
8´ fSW ´ COUTB
8´ 400 kHz ´100 mF
(37)
(38)
DIOUTB
1.9 A
4´ 50 kHz ´100 mF
DVOUTB
=
+ DIOUTB ´ESR =
+1.9 A ´10 mW = 114 mV
4´ fC ´ COUTB
2p´ fC ´ VOUTB ´ COUTB
GmBUCK ´KCFB ´ VREF
R3 =
2p´ 50 kHz ´ 3.3 V ´100 mF
1mS ´ 4.16 S ´ 0.8 V
=
= 31kW
(39)
(40)
Use the standard value of R3 = 30 kΩ.
10
10
C1=
=
2p´R3 ´ fC 2p´ 30 kW ´ 50 kHz
= 1.1nF
30
Copyright © 2013, Texas Instruments Incorporated
TPS43330A-Q1
www.ti.com.cn
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
C1
C2 =
f
æ
ö
SW
2p´R3 ´ C1´
-1
ç
÷
2
è
ø
1.1nF
=
= 27 pF
400 kHz
2
æ
ç
ö
2p´ 30 kW ´1.1nF´
-1
÷
è
ø
(41)
GmBUCK ´R3 ´KCFB
2p´ COUTB
VREF
fC =
´
VOUTB
1mS ´ 30 kW ´ 4.16 S ´ 0.8 V
2p´100 μF ´ 3.3 V
=
= 48 kHz
(42)
(43)
fC is close to the target bandwidth of 50 kHz.
The resulting zero frequency fZ1
1
1
fZ1
=
=
2p´R3 ´ C1 2p´ 30 kW ´1.1nF
= 4.8 kHz
fZ1 is close to the fC guideline of 5 kHz.
The second pole frequency fP2
1
1
fP2
=
=
2p´R3 ´ C2 2p´ 30 kW ´ 27 pF
= 196 kHz
(44)
fP2 is close to the fSW / 2 guideline of 200 kHz.
Hence, the design satisfies all requirements for a good loop.
Resistor Divider Selection for Setting VOUT Voltage
VREF
=
VOUT 3.3 V
0.8 V
b =
= 0.242
(45)
Choose the divider current through R1 and R2 to be 50 µA. Then
3.3 V
R1+ R2 =
= 66 kW
50 mA
(46)
(47)
and
R2
= 0.242
R1+ R2
Therefore, R2 = 16 kΩ and R1 = 50 kΩ.
Copyright © 2013, Texas Instruments Incorporated
31
TPS43330A-Q1
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
BuckX High-Side and Low-Side N-Channel MOSFETs
An internal supply, which is 5.8 V typical under normal-operating conditions, provides the gate-drive supply for
these MOSFETs. The output is a totem pole, allowing full-voltage drive of VREG to the gate with peak output
current of 1.5 A. The reference for the high-side MOSFET is a floating node at the phase terminal (PHx), and the
reference for the low-side MOSFET is the power-ground (PGNDx) terminal. For a particular application, select
these MOSFETs with consideration for the following parameters: rDS(on), gate charge Qg, drain-to-source
breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.
The times tr and tf denote the rising and falling times of the switching node and have a relationship to the gate-
driver strength of the TPS43330A-Q1 and to the gate Miller capacitance of the MOSFET. The first term, tr,
denotes the conduction losses, which are minimimal when the on-resistance of the MOSFET is low. The second
term, tf, denotes the transition losses, which arise due to the full application of the input voltage across the drain-
source of the MOSFET as it turns on or off. Transition losses are lower at low currents and when the switching
time is low.
V ´I
æ
ö
= (IOUT )2 ´rDS(on)(1+ TC)´D +
´(tr + tf )´ fSW
IN
OUT
P
BuckTOPFET
ç
÷
2
è
ø
(48)
(49)
P
= (IOUT )2 ´rDS(on)(1+ TC)´(1-D) + VF ´IOUT ´(2´ td )´ fSW
BuckLOWERFET
In addition, during the dead time (td) when both the MOSFETs are off, the body diode of the low-side MOSFET
conducts, increasing the losses. The second term in Equation 49 denotes this dead time. Using external Schottky
diodes in parallel with the low-side MOSFETs of the buck converters helps to reduce this loss.
NOTE
rDS(on) has a positive temperature coefficient, and the TC term for rDS(on) accounts for that
fact. TC = d × ΔT[°C]. The temperature coefficient d is available as a normalized value
from MOSFET data sheets and has an assumed starting value of 0.005 per ºC.
32
Copyright © 2013, Texas Instruments Incorporated
TPS43330A-Q1
www.ti.com.cn
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
Schematics
The following section summarizes the previously calculated example and gives schematic and component
proposals.
Table 4. Application Example 1
PARAMETER
VBuckA
VBuckB
BOOST
VIN = 6 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
VBAT = 5 V (cranking pulse
input) to 30 V
Input voltage
Output voltage, VOUTx
5 V
3 A
3.3 V
2 A
10 V
2.5 A
Maximum output current, IOUTx
Load-step output tolerance, ∆VOUT + ∆VOUT(Ripple)
Current output load-step, ∆IOUTx
Converter switching frequency, fSW
±0.2 V
0.1 to 3 A
400 kHz
±0.12 V
0.1 to 2 A
400 kHz
±0.5 V
0.1 to 2.5 A
200 kHz
2.5V to 40V
VBAT
L1
D1
BOOST — 10V, 25W
3.9µH
680µF
COUT1
10µF
CIN
220µF
TOP-SW3
1kΩ
VBAT
DS
VIN
EXTSUP
DIV
BOT-SW3
0.02Ω
1.5kΩ
1nF
GC1
GC2
VREG
CBB
4.7µF
CBA
TOP-SW2
TOP-SW1
0.1µF
0.1µF
L3
VBuckA — 5V, 15W
0.015Ω
VBuckB — 3.3V, 6.6W
L2
0.03Ω
GA1
GB1
8.2µH
15µH
100µF
COUTA
100µF
COUTB
PHA
PHB
BOT-SW2
BOT-SW1
GA2
GB2
PGNDA
SA1
PGNDB
SB1
TPS43330A-Q1
84kΩ
16kΩ
50kΩ
SA2
SB2
FBA
FBB
16kΩ
COMPA
SSA
COMPB
SSB
33pF
27pF
1.5nF
1.1nF
30kΩ
24kΩ
500nF
500nF
PGA
ENA
PGB
5kΩ
5kΩ
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
220pF
22nF
1nF
7.2kΩ
Figure 28. Simplified Application Schematic, Example 1
Table 5. Application Example 1 – Component Proposals
Name
Component Proposal
Value
4 µH
L1
L2
L3
D1
MSS1278T-392NL (Coilcraft)
MSS1278T-822ML (Coilcraft)
MSS1278T-153ML (Coilcraft)
SK103 (Micro Commercial Components)
IRF7416 (International Rectifier)
8.2 µH
15 µH
TOP_SW3
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3
COUT1
IRFR3504ZTRPBF (International Rectifier)
EEVFK1J681M (Panasonic)
ECASD91A107M010K00 (Murata)
EEEFK1V331P (Panasonic)
680 µF
100 µF
220 µF
COUTA, COUTB
CIN
Copyright © 2013, Texas Instruments Incorporated
33
TPS43330A-Q1
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
Table 6. Application Example 2
PARAMETER
VBuckA
VBuckB
BOOST
VIN = 5 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
VBAT = 5 V (cranking pulse
input) to 30V
Input voltage
Output voltage, VOUTx
5 V
2.7 A
3.3 V
5 A
10 V
3 A
Maximum output current, IOUTx
Load-step output tolerance, ∆VOUT + ∆VOUT(Ripple)
Current output load step, ∆IOUTx
Converter switching frequency, fSW
±0.2 V
±0.12 V
0.1 to 5 A
300 kHz
±0.5 V
0.1 to 3 A
150 kHz
0.1 to 2.7 A
300 kHz
5V to 30V
VBAT
L1
D1
BOOST — 10V, 25W
3.9µH
1.5mF
COUT1
10µF
CIN
330µF
TOP-SW3
1kΩ
VBAT
DS
VIN
EXTSUP
DIV
BOT-SW3
0.015Ω
1.5kΩ
560pF
GC1
GC2
VREG
CBB
4.7µF
CBA
TOP-SW2
TOP-SW1
0.1µF
0.1µF
L3
VBuckA — 5V, 13.5W
0.015Ω
VBuckB — 3.3V, 16.5W
L2
0.01Ω
GA1
GB1
10µH
6.8µH
150µF
COUTA
330µF
COUTB
PHA
PHB
BOT-SW2
BOT-SW1
GA2
GB2
PGNDA
SA1
PGNDB
SB1
TPS43330A-Q1
84kΩ
16kΩ
50kΩ
16kΩ
SA2
SB2
FBA
FBB
COMPA
SSA
COMPB
SSB
47pF
47pF
1.8nF
1.5nF
27kΩ
24kΩ
500nF
500nF
PGA
ENA
PGB
5kΩ
5kΩ
AGND
RT
ENB
80kΩ
COMPC
ENC
DLYAB
SYNC
330pF
47nF
1nF
6.2kΩ
Figure 29. Simplified Application Schematic, Example 2
Table 7. Application Example 2 – Component Proposals
Name
Component Proposal
Value
3.9 µH
10 µH
6.8 µH
L1
L2
L3
D1
MSS1278T-392NL (Coilcraft)
MSS1278T-103ML (Coilcraft)
MSS1278T-682ML (Coilcraft)
SK103 (Micro Commercial Components)
IRF7416 (International Rectifier)
TOP_SW3
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3
COUT1
COUTA
COUTB
CIN
IRFR3504ZTRPBF (International Rectifier)
EEVFK1V152M (Panasonic)
1.5 mF
150 µF
330 µF
330 µF
ECASD91A157M010K00 (Murata)
ECASD90G337M008K00 (Murata)
EEEFK1V331P (Panasonic)
34
Copyright © 2013, Texas Instruments Incorporated
TPS43330A-Q1
www.ti.com.cn
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
Table 8. Application Example 3
PARAMETER
VBuckA
VBuckB
BOOST
VIN = 5 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
VBAT = 5 V (cranking pulse
input) to 30 V
Input voltage
Output voltage, VOUTx
5 V
3 A
2.5 V
1 A
10 V
2 A
Maximum output current, IOUTx
Load-step output tolerance, ∆VOUT + ∆VOUT(Ripple)
Current output load-step, ∆IOUTx
Converter switching frequency, fSW
±0.2 V
0.1 to 3 A
400 kHz
±0.12 V
0.1 to 1 A
400 kHz
±0.5 V
0.1 to 2 A
200 kHz
5V to 30V
VBAT
L1
D1
BOOST — 10V, 20W
3.9µH
470µF
COUT1
10µF
CIN
330µF
TOP-SW3
1kΩ
VBAT
DS
VIN
EXTSUP
DIV
BOT-SW3
0.03Ω
1.5kΩ
470pF
GC1
GC2
VREG
CBB
4.7µF
CBA
TOP-SW2
TOP-SW1
0.1µF
0.1µF
L3
0.015Ω
VBuckB — 3.3V, 16.5W
L2
0.045Ω
VBuckA — 5V, 15W
GA1
GB1
10µH
22µH
150µF
COUTA
100µF
COUTB
PHA
PHB
BOT-SW2
BOT-SW1
GA2
GB2
PGNDA
SA1
PGNDB
SB1
TPS43330A-Q1
84kΩ
16kΩ
34kΩ
SA2
SB2
FBA
FBB
16kΩ
COMPA
SSA
COMPB
SSB
20pF
47pF
1nF
1nF
36kΩ
39kΩ
500nF
500nF
PGA
ENA
PGB
5kΩ
5kΩ
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
220pF
18nF
1nF
8.2kΩ
Figure 30. Simplified Application Schematic, Example 3
Table 9. Application Example 3 – Component Proposals
Name
Component Proposal
Value
3.9 µH
8.2 µH
22 µH
L1
L2
L3
D1
MSS1278T-392NL (Coilcraft)
MSS1278T-822ML (Coilcraft)
MSS1278T-223ML (Coilcraft)
SK103 (Micro Commercial Components)
IRF7416 (International Rectifier)
TOP_SW3
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3
COUT1
COUTA
COUTB
CIN
IRFR3504ZTRPBF (International Rectifier)
EEVFK1V471Q (Panasonic)
470 µF
150 µF
100 µF
330 µF
ECASD91A157M010K00 (Murata)
ECASD40J107M015K00 (Murata)
EEEFK1V331P (Panasonic)
Copyright © 2013, Texas Instruments Incorporated
35
TPS43330A-Q1
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD™ Package
Figure 31. Derating Profile for Power Dissipation Based on High-K JEDEC PCB
PCB Layout Guidelines
Grounding and PCB Circuit Layout Considerations
Boost converter
1. The path formed from the input capacitor to the inductor and BOT_SW3 with the low-side current-sense
resistor must have short leads and PC trace lengths. The same applies for the trace from the inductor to
Schottky diode D1 to the COUT1 capacitor. Connect the negative terminal of the input capacitor and the
negative terminal of the sense resistor together with short trace lengths.
2. The overcurrent-sensing shunt resistor requires noise filtering, and the filter capacitor must be close to the IC
pin.
Buck Converter
1. Connect the drain of TOP_SW1 and TOP_SW2 together with the positive terminal of input capacitor COUT1
The trace length between these terminals must be short.
.
2. Connect a local decoupling capacitor between the drain of TOP_SWx and the source of BOT_SWx.
3. The Kelvin-current sensing for the shunt resistor has traces with minimum spacing, routed in parallel with
each other. Place any filtering capacitors for noise near the IC pins.
4. The resistor divider for sensing the output voltage connects between the positive terminal of itherespective
output capacitor and COUTA or COUTB and the IC signal ground. Do not locate these components and their
traces near any switching nodes or high-current traces.
Other Considerations
1. Short PGNDx and AGND to the thermal pad. Use a star-ground configuration if connecting to a non-ground
plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and voltage-sense
feedback ground networks to this star ground.
2. Connect a compensation network between the compensation pins and IC signal ground. Connect the
oscillator resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits must
not be located near nodes showing high dv/dt; these include the gate-drive outputs, phase pins, and boost
circuits (bootstrap).
3. Reduce the surface area of the high-current-carrying loops to a minimum by ensuring optimal component
placement. Locate the bypass capacitors as close as possible to the respective power and ground pins.
36
Copyright © 2013, Texas Instruments Incorporated
TPS43330A-Q1
www.ti.com.cn
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
PCB Layout
POWER
INPUT
Power L ines
Connection to GND P lane ofPCB through vias
Connection to top /bottom ofPCB through vias
Vo ltage Ra ilOutputs
VBOOST
VBAT
DS
V IN
EXTSUP
D IV
GC1
GC2
CBA
VREG
CBB
GA1
PHA
GB1
PHB
GA2
PGNDA
SA1
GB2
PGNDB
SB1
SA2
SB2
FBA
FBB
COMPA
SSA
COMPB
SSB
PGA
ENA
PGB
AGND
RT
ENB
COMPC
ENC
DLYAB
SYNC
Exposed Pad
connected to GND
P lane
M icrocontro ller
Copyright © 2013, Texas Instruments Incorporated
37
TPS43330A-Q1
ZHCSBI5A –AUGUST 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
REVISION HISTORY
Changes from Original (August 2013) to Revision A
Page
•
Changed 文档状态从产品预览改为生成数据 ........................................................................................................................ 1
38
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS43330AQDAPRQ1
ACTIVE
HTSSOP
DAP
38
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS43330A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS43330AQDAPRQ1 HTSSOP
DAP
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DAP 38
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TPS43330AQDAPRQ1
2000
Pack Materials-Page 2
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