TPS3852G18QDRBRQ1 [TI]
具有集成式窗口看门狗计时器的汽车类高精度电压监控器 | DRB | 8 | -40 to 125;型号: | TPS3852G18QDRBRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有集成式窗口看门狗计时器的汽车类高精度电压监控器 | DRB | 8 | -40 to 125 监控 |
文件: | 总34页 (文件大小:1395K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS3852-Q1
ZHCSG27 –FEBRUARY 2017
具有集成式看门狗计时器的 TPS3852-Q1 高精度电压监控器
1 特性
3 说明
1
•
具有符合 AEC-Q100 的下列结果:
TPS3852-Q1 是一款具有集成式窗口看门狗计时器的
高精度电压监控器。TPS3852-Q1 包含一个高精度欠
压监控器,其在 –40°C 至 +125°C 的指定温度范围内
的欠压阈值 (VITN) 精度达 0.8%。此外,TPS3852-Q1
还包含精确磁滞,是小容差系统的理想之选。监控器
RESET 延迟 具有 一个精度为 15% 的高精度延迟定时
器。
–
器件温度 1 级:-40°C 至 125°C 的环境运行温
度范围
–
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 2
–
器件组件充电模式 (CDM) ESD 分类等级 C4B
DD 输入电压范围:1.6V 至 6.5V
•
•
•
•
•
V
0.8% 电压阈值精度
TPS3852-Q1 包含可编程窗口看门狗计时器,广泛适
用于各种 应用。专用的看门狗输出 (WDO) 可提高分
辨率,从而帮助确定出现故障情况的原因。看门狗超时
可通过外部电容器或通过出厂时编制的默认延迟设置进
行编程。在开发过程中,可以将看门狗禁用,从而避免
出现不必要的看门狗超时。
低电源电流:IDD = 10µA(典型值)
用户可编程看门狗超时
经过出厂编程的高精度看门狗和复位定时器:
–
±15% 精确 WDT 和 RST 延迟
•
•
•
漏极开路输出
手动复位输入 (MR)
高精度电压监控:
TPS3852-Q1 可提供小型 3.00mm × 3.00mm、8 引脚
VSON 封装。TPS3852-Q1 包含 可湿性侧面,可轻松
进行光学检查。
–
–
–
支持 1.8V 到 5.0V 常见电压轨
支持 4% 和 7% 阈值
0.5% 迟滞
器件信息(1)
•
•
看门狗禁用功能
器件型号
TPS3852-Q1
封装
VSON (8)
封装尺寸(标称值)
采用 3mm x 3mm、8 引脚超薄小外形尺寸无引线
(VSON) 封装
3.00mm x 3.00mm
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
2 应用
•
•
•
•
•
•
安全型 应用范围
汽车视觉系统
汽车高级驾驶员辅助系统 (ADAS)
远程信息处理控制单元
现场可编程门阵列 (FPGA) 和专用集成电路 (ASIC)
微控制器和数字信号处理器 (DSP)
典型应用电路
欠压阈值 (VITN) 精度与温度间的关系
3.3 V
0.5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
0.3
0.1
TPS3852-Q1
V
DD
Microcontroller
V
RESET
NMI
RESET
WDO
WDI
DD
SET1
-0.1
-0.3
-0.5
MR
GPIO
CWD
GND
GND
Copyright © 2016, Texas Instruments Incorporated
-50
-25
0
25
50
75
100
125
Temperature (èC)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBVS285
TPS3852-Q1
ZHCSG27 –FEBRUARY 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 19
Power Supply Recommendations...................... 22
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 器件和文档支持 ..................................................... 23
11.1 器件支持 ............................................................... 23
11.2 接收文档更新通知 ................................................. 23
11.3 社区资源................................................................ 23
11.4 商标....................................................................... 23
11.5 静电放电警告......................................................... 23
11.6 Glossary................................................................ 23
12 机械、封装和可订购信息....................................... 24
7
4 修订历史记录
日期
修订版本
注释
2017 年2 月
*
最初发布。
2
Copyright © 2017, Texas Instruments Incorporated
TPS3852-Q1
www.ti.com.cn
ZHCSG27 –FEBRUARY 2017
5 Pin Configuration and Functions
DRB Package
8-Pin VSON
Top View
VDD
CWD
MR
1
2
3
4
8
RESET
WDO
WDI
7
Pad
6
5
GND
SET1
Not to scale
Pin Functions
NAME
NO.
I/O
DESCRIPTION
Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and
ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected (NC) further
enables the selection of the preset watchdog timeouts; see the Timing Requirements table.
When using a capacitor, the TPS3852-Q1 determines the window watchdog upper boundary with 公式 1.
See 表 4 and the CWD Functionality section for additional information.
CWD
2
—
GND
MR
4
3
—
I
Ground pin
Manual reset pin. A logical low on this pin issues a RESET. This pin is internally pulled up to VDD
RESET remains low for a fixed reset delay (tRST) time after MR is deasserted (high).
.
Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). RESET goes
low when VDD goes below the undervoltage threshold (VITN). When VDD is within the normal operating range, the
RESET timeout counter starts. At completion, RESET goes high. During startup, the state of RESET is undefined
below the specified power-on-reset (POR) voltage (VPOR). Above POR, RESET goes low and remains low until the
monitored voltage is within the correct operating range (above VITN + VHYST) and the RESET timeout is complete.
RESET
8
O
SET1
VDD
5
1
I
I
Logic input. Grounding the SET1 pin disables the watchdog timer.
Supply voltage pin. For noisy systems, connecting a 0.1-μF bypass capacitor is recommended.
Watchdog input. A falling transition (edge) must occur at this pin between the lower (tWDL(max)) and upper (tWDU(min)
)
window boundaries in order for WDO to not assert.
WDI
6
7
I
When the watchdog is not in use, the SET1 pin can be used to disable the watchdog. The input at WDI is ignored
when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is disabled, then
WDI cannot be left unconnected and must be driven to either VDD or GND.
Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to the desired pullup voltage rail (VPU). WDO goes
low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout
occurs, WDO goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a high-
impedance state.
WDO
O
Thermal pad
—
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
Copyright © 2017, Texas Instruments Incorporated
3
TPS3852-Q1
ZHCSG27 –FEBRUARY 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
Supply voltage range
Output voltage range
VDD
7
RESET, WDO
SET1, WDI, MR
CWD, CRST
7
V
7
VDD + 0.3(2)
±20
Voltage ranges
V
Output pin current
mA
mA
Input current (all pins)
±20
Continuous total power dissipation
See Thermal Information
(3)
Operating junction, TJ
–40
–40
–65
150
150
150
(3)
Temperature
Operating free-air, TA
Storage, Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The absolute maximum rating is VDD + 0.3 V or 7.0 V, whichever is smaller.
(3) Assume that TJ = TA as a result of the low dissipated power in this device.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
6.5
UNIT
V
VDD
Supply pin voltage
1.6
VSET1
VMR
SET1 pin voltage
0
6.5
V
MR pin voltage
0
0.1(1)
9
6.5
1000(1)
V
CCWD
CWD
RPU
Watchdog timing capacitor
Pullup resistor to VDD
Pullup resistor, RESET and WDO
RESET pin current
nF
kΩ
kΩ
mA
mA
°C
10
10
11
1
100
10
IRESET
IWDO
TJ
Watchdog output current
Junction temperature
10
–40
125
(1) Using a CCWD capacitor of 0.1 nF or 1000 nF gives a tWDU(typ) of 62.74 ms or 77.45 seconds, respectively.
4
Copyright © 2017, Texas Instruments Incorporated
TPS3852-Q1
www.ti.com.cn
ZHCSG27 –FEBRUARY 2017
6.4 Thermal Information
TPS3852-Q1
THERMAL METRIC(1)
DRB (VSON)
8 PINS
47.7
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
51.5
22.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.3
ψJB
22.3
RθJC(bot)
4.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at VITN + VHYST ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, T J ≤ +125°C (unless otherwise noted); the
open-drain pullup resistors are 10 kΩ for each output; typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL CHARACTERISTICS
(1)
VDD
IDD
Supply voltage
Supply current
1.6
6.5
19
V
10
µA
RESET FUNCTION
(2)
VPOR
Power-on-reset voltage
IRESET = 15 µA, VOL(MAX) = 0.25 V
0.8
V
V
(3)
VUVLO
Undervoltage lockout voltage
1.35
Undervoltage threshold accuracy,
entering RESET
VITN
VDD falling
VITN – 0.8%
VITN + 0.8%
VHYST
IMR
Hysteresis voltage
VDD rising
VMR = 0 V
0.2%
500
0.5%
620
0.8%
700
MR pin internal pullup current
nA
WINDOW WATCHDOG FUNCTION
ICWD
CWD pin charge current
CWD = 0.5 V
337
375
413
nA
V
VCWD
CWD pin threshold voltage
1.192
1.21
1.228
VDD = 5 V,
IRESET = IWDO = 3 mA
VOL
ID
RESET, WDO output low
0.4
V
RESET, WDO output leakage current,
open-drain
VDD = VITN + VHYST
VRESET = VWDO = 6.5 V
,
1
µA
VIL
Low-level input voltage (MR, SET1)
High-level input voltage (MR, SET1)
Low-level input voltage (WDI)
0.25
V
V
V
V
VIH
0.8
VIL(WDI)
VIH(WDI)
0.3 × VDD
High-level input voltage (WDI)
0.8 × VDD
(1) During power on, VDD must be a minimum of 1.6 V for at least 300 µs before RESET correlates with VDD
.
(2) When VDD falls below VPOR, RESET and WDO are undefined.
(3) When VDD falls below UVLO, RESET is driven low.
Copyright © 2017, Texas Instruments Incorporated
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6.6 Timing Requirements
at VITN + VHYST ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, T J ≤ +125°C (unless otherwise noted); the
open-drain pullup resistors are 10 kΩ for each output; typical values are at TJ = 25°C
MIN
TYP
MAX UNIT
GENERAL
tINIT CWD pin evaluation period
381
1
µs
µs
µs
Minimum MR, SET1 pin pulse duration
Startup delay
300
RESET FUNCTION
tRST
Reset timeout period
170
200
35
230
920
ms
µs
ns
VDD = VITN + VHYST + 2.5%
VDD = VITN – 2.5%
tRST-DEL VDD to RESET delay
17
tMR-DEL MR to RESET delay
200
Watchdog Function
CWD = NC, SET1 = 0(1)
CWD = NC, SET1 = 1(1)
Watchdog disabled
680
800
ms
CWD = 10 kΩ to VDD,
tWDL
Window watchdog lower boundary
Watchdog disabled
SET1 = 0(1)
CWD = 10 kΩ to VDD,
1.48
1.85
2.22
ms
ms
SET1 = 1(1)
CWD = NC, SET1 = 0(1)
CWD = NC, SET1 = 1(1)
Watchdog disabled
1360
1600
1840
CWD = 10 kΩ to VDD,
tWDU
Window watchdog upper boundary
Watchdog disabled
SET1 = 0(1)
CWD = 10 kΩ to VDD,
9.35
11.0
150
12.65
ms
µs
SET1 = 1(1)
tWD-
setup
Setup time required for device to respond to changes on WDI after
being enabled
Minimum WDI pulse duration
50
50
ns
ns
tWD-DEL WDI to WDO delay
(1) SET1 = 0 means VSET1 < VIL, SET1 = 1 means VSET1 > VIH
.
VITN + VHYST
VITN
VDD
VITN
tRST
VPOR
tRST
tRST-DEL
(1)
RESET
tWDL < t < tWDU
t < tWDU
t < tWDU
WDI
X
X
t < tWDL
WDO
tRST
(1) See 图 2 for WDI timing requirements.
图 1. Timing Diagram
6
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TPS3852-Q1
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ZHCSG27 –FEBRUARY 2017
WDI
Early Fault
WDO
Correct Operation
WDI
WDO
Late Fault
WDI
WDO
Valid
Window
Window
Timing
tWDL(min)
tWDL(typ)
tWDL(max)
tWDU(min)
tWDU(typ)
tWDU(max)
= Tolerance Window
图 2. TPS3852-Q1 Window Watchdog Timing
版权 © 2017, Texas Instruments Incorporated
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ZHCSG27 –FEBRUARY 2017
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6.7 Typical Characteristics
all curves are taken at 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless otherwise noted)
16
12
8
0.7
0.6
0.5
0.4
0.3
-40èC
0èC
25èC
105èC
125èC
4
VIL
VIH
0
0
0
1
2
3
4
5
6
7
-50
-25
25
50
75
100
125
VDD (V)
Temperature (èC)
VDD = 1.6 V
图 3. Supply Current vs VDD
图 4. MR Threshold vs Temperature
380
376
372
368
364
0.5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
0.3
0.1
-0.1
-0.3
-0.5
1.6 V
6.5 V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
TPS3852G33-Q1
图 6. VITN + VHYST Accuracy vs Temperature
图 5. CWD Charging Current vs Temperature
45
40
35
30
25
20
15
10
5
0.5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
0.3
0.1
-0.1
-0.3
-0.5
0
-50
-25
0
25
50
75
100
125
-0.8 -0.6 -0.4 -0.2
0
0.2
0.4
0.6
0.8
Temperature (èC)
VITN + VHYST Accuracy (%)
TPS3852G33-Q1
Includes G and H versions with 3.3-V nominal monitored voltage,
total units = 15,536
图 8. VITN + VHYST Accuracy Histogram
图 7. VITN Accuracy vs Temperature
8
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TPS3852-Q1
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ZHCSG27 –FEBRUARY 2017
Typical Characteristics (接下页)
all curves are taken at 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless otherwise noted)
45
40
35
30
25
20
15
10
5
70
60
50
40
30
20
10
0
0
-0.8 -0.6 -0.4 -0.2
0
0.2
0.4
0.6
0.8
0.2
0.35
0.5
0.65
0.8
VITN Accuracy (%)
Hysteresis (%)
Includes G and H versions with 3.3-V nominal monitored voltage,
total units = 15,536
Includes G and H versions with 3.3-V nominal monitored voltage,
total units = 15,536
图 9. VITN Accuracy Histogram
图 10. Hysteresis Histogram
1.6
1.6
-40èC
-40èC
0èC
0èC
1.4
1.2
1
1.4
1.2
1
25èC
105èC
125èC
25èC
105èC
125èC
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
IRESET (mA)
IRESET (mA)
VDD = 1.6 V
VDD = 6.5 V
图 11. Low-Level RESET Voltage vs RESET Current
图 12. Low-Level RESET Voltage vs RESET Current
50
45
40
35
30
25
20
15
10
5
210
205
200
195
190
-40èC
0èC
25èC
105èC
125èC
-40èC
0èC
25èC
105èC
125èC
0
0
2
4
6
8
10
0
2
4
6
8
10
Overdrive (%)
Overdrive (%)
TPS3852G33-Q1 entering undervoltage
TPS3852G33-Q1 exiting undervoltage
图 13. Propagation Delay vs Overdrive
图 14. Propagation Delay (tRST) vs Overdrive
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Typical Characteristics (接下页)
all curves are taken at 25°C with 1.6 V ≤ VDD ≤ 6.5 V (unless otherwise noted)
25
Overdrive = 3%
Overdrive = 5%
Overdrive = 7%
Overdrive = 9%
Overdrive = 10%
20
15
10
5
-50
-25
0
25
50
75
100
125
Temperature (èC)
VITN = 3.168 V
图 15. High-to-Low Glitch Immunity vs Temperature
10
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TPS3852-Q1
www.ti.com.cn
ZHCSG27 –FEBRUARY 2017
7 Detailed Description
7.1 Overview
The TPS3852-Q1 is a high-accuracy voltage supervisor with an integrated window watchdog timer. This device
includes a precision undervoltage supervisor with a threshold that achieves 0.8% accuracy over the specified
temperature range of –40°C to +125°C. In addition, the TPS3852-Q1 includes accurate hysteresis on the
threshold, making the device ideal for use with tight tolerance systems where voltage supervisors must ensure a
RESET before the minimum supply tolerance of the microprocessor or system-on-a-chip (SoC) is reached.
7.2 Functional Block Diagram
VDD
R1
RESET
R2
Precision
Clock
Reference
VDD
WDO
State
Machine
Cap
CWD
Control
WDI
MR
SET1
GND
Copyright © 2016, Texas Instruments Incorporated
NOTE: R1 + R2 = 4.5 MΩ.
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7.3 Feature Description
7.3.1 RESET
Connect RESET to VPU through a 1-kΩ to 100-kΩ pullup resistor. RESET remains high (deasserted) when VDD is
greater than the negative threshold voltage (VITN). If VDD falls below the negative threshold (VITN), then RESET is
asserted, driving the RESET pin to low impedance. When VDD rises above VITN + VHYST, a delay circuit is
enabled that holds RESET low for a specified reset delay period (tRST). When the reset delay has elapsed, the
RESET pin goes to a high-impedance state and uses a pullup resistor to hold RESET high. The pullup resistor
must be connected to the desired voltage rail to allow other devices to be connected at the correct interface
voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor values. The
pullup resistor value is determined by output logic low voltage (VOL), leakage current (ID), and the current through
the RESET pin IRESET
.
7.3.2 Manual Reset (MR)
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR
causes RESET to assert. After MR returns to a logic high and VDD is above VITN + VHYST, RESET is deasserted
after the reset delay time (tRST). If MR is not controlled externally, then MR can either be connected to VDD or left
floating because the MR pin is internally pulled up. When MR is asserted, the watchdog is disabled and all
signals input to WDI are ignored.
7.3.3 Undervoltage Fault Detection
The TPS3852-Q1 features undervoltage detection for common rails between 1.8 V and 5 V. The voltage is
monitored on the input rail of the device. If VDD drops below VITN, then RESET is asserted (driven low). When
VDD is above VITN + VHYST, RESET deasserts after tRST, as shown in 图 16. The internal comparator has built-in
hysteresis that provides some noise immunity and ensures stable operation. Although not required in most
cases, for noisy applications, good analog design practice is to place a 1-nF to 100-nF bypass capacitor close to
the VDD pin to reduce sensitivity to transient voltages on the monitored signal.
VITN + VHYST
VDD
VITN
Undervoltage Limit
tRST + tRST-DEL
RESET
图 16. Undervoltage Detection
12
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Feature Description (接下页)
7.3.4 Watchdog Mode
This section provides information for the watchdog mode of operation.
7.3.4.1 SET1
The SET1 pin can enable and disable the watchdog timer. If SET1 is set to GND, the watchdog timer is disabled
and WDI is ignored. When the watchdog is disabled, WDO is in a high-impedance state. If the watchdog timer is
disabled, drive the WDI pin to either GND or VDD to ensure that there is no increase in IDD. When SET1 is logic
high, the watchdog operates normally. The SET1 pin can be changed dynamically; however, if the watchdog is
going from disabled to enabled there is a setup time tWD-setup where the watchdog does not respond to changes
on WDI, as shown in 图 17.
VDD
RESET
SET1
150 µs
Watchdog
Enabled/Disabled
Enabled
Disabled
Enabled
图 17. Enabling and Disabling the Watchdog
7.3.4.2 Window Watchdog Timer
This section provides information for the window watchdog mode of operation. A window watchdog is typically
employed in safety-critical applications where a traditional watchdog timer is inadequate. In a traditional
watchdog there is a maximum time in which a pulse must be issued to prevent the reset from occurring. In a
window watchdog, the pulse must be issued between a maximum lower window time (tWDL(max)) and the minimum
upper window time (tWDU(min)) set by the CWD pin.
7.3.4.3 Watchdog Input (WDI)
WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of
the input signal. For the first pulse, the watchdog acts as a traditional watchdog timer; thus, the first pulse must
be issued before tWDU(min). After the first pulse, to ensure proper functionality of the watchdog timer, always issue
the WDI pulse within the window of tWDL(max) and tWDU(min). If the pulse is issued in this region, then WDO remains
unasserted. Otherwise the device asserts WDO, putting the WDO pin into a low-impedance state.
The watchdog input (WDI) is a digital pin. In order to ensure there is no increase in IDD, drive the WDI pin to
either VDD or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply
current (IDD) because of the architecture of the digital logic gates. When RESET is asserted, the watchdog is
disabled and all signals input to WDI are ignored. When RESET is no longer asserted, the device resumes
normal operation and no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to
either VDD or GND.
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13
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Feature Description (接下页)
7.3.4.4 CWD
The CWD pin provides the functionality of both high-precision, factory-programmed window watchdog timing
options and user-programmable window watchdog timing. The CWD pin can be either pulled up to VDD through a
resistor, have an external capacitor to ground, or be left floating. Every time that the device issues a reset event
and the supply voltage is above VITN, the device tries to determine which of these three options is connected to
the pin. There is an internal state machine that the device goes through to determine which option is connected
to the CWD pin. The state machine can take up to 381 μs to determine if the CWD pin is left floating, pulled-up
through a resistor, or connected to a capacitor.
If the CWD pin is being pulled up to VDD using a pullup resistor, then use a 10-kΩ resistor.
7.3.4.5 Watchdog Output (WDO)
The TPS3852-Q1 features a window watchdog with an independent watchdog output (WDO). The independent
watchdog output gives the flexibility to flag when there is a fault in the watchdog timing without performing an
entire system reset. For legacy applications, WDO can be tied to RESET. When the RESET output is not
asserted, the WDO signal maintains normal operation. However, when the RESET signal is asserted, the WDO
pin goes to a high-impedance state. This is due to using the standard RESET timing options when a fault occurs
on WDO. When RESET is unasserted, the window watchdog timer resumes normal operation.
14
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7.4 Device Functional Modes
表 1 summarises the functional modes of the TPS3852-Q1.
表 1. Device Functional Modes
VDD
WDI
—
WDO
—
RESET
Undefined
Low
VDD < VPOR
VPOR ≤ VDD < VDD(min)
DD(min) ≤ VDD ≤ VITN + VHYST
Ignored
Ignored
High
High
High
(1)
V
Low
(2)
VDD > VITN
tWDL(max) < tPU(3L)SE
tWDU(min)
<
High
(3)
tPULSE > tWDU(min)
tPULSE < tWDL(max)
(1) Only valid before VDD goes above VITN + VHYST
(2) Only valid after VDD goes above VITN + VHYST
(3) Where tPULSE is the time between the falling edges on WDI.
Low
Low
High
High
(3)
.
.
7.4.1 VDD is Below VPOR (VDD < VPOR
)
When VDD is less than VPOR, RESET is undefined and can be either high or low. The state of RESET largely
depends on the load that the RESET pin is experiencing.
7.4.2 Above Power-On-Reset, But Less Than VDD(min) (VPOR ≤ VDD < VDD(min)
)
When the voltage on VDD is less than VDD(min) and greater than or equal to VPOR, the RESET signal is asserted
(logic low). When RESET is asserted, the watchdog output WDO is in a high-impedance state regardless of the
WDI signal that is input to the device.
7.4.3 Normal Operation (VDD ≥ VDD(min)
)
When VDD is greater than or equal to VDD(min), the RESET signal is determined by VDD. When RESET is asserted,
WDO goes to a high-impedance state. WDO is then pulled high through the pullup resistor.
版权 © 2017, Texas Instruments Incorporated
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 CWD Functionality
The TPS3852-Q1 features three options for setting the watchdog window: connecting a capacitor to the CWD
pin, connecting a pullup resistor to VDD, and leaving the CWD pin unconnected. 图 18 shows a schematic
drawing of all three options. If this pin is connected to VDD through a 10-kΩ pullup resistor or left unconnected
(high impedance), then the factory-programmed watchdog timeouts are enabled; see the Timing Requirements
table. Otherwise, the watchdog timeout can be adjusted by placing a capacitor from the CWD pin to ground.
V
DD
V
V
DD
DD
TPS3852-Q1
TPS3852-Q1
TPS3852-Q1
V
DD
V
DD
V
DD
375 nA
375 nA
375 nA
CWD
CWD
CWD
C
CWD
Cap
Cap
Cap
Control
Control
Control
User Programmable
Capacitor to GND
CWD
Unconnected
10 kΩ Resistor
to VDD
Copyright © 2016, Texas Instruments Incorporated
图 18. CWD Charging Circuit
8.1.1.1 Factory-Programmed Timing Options
If using the factory-programmed timing options (listed in 表 2), the CWD pin must either be unconnected or
pulled up to VDD through a 10-kΩ pullup resistor. Using these options enables high-precision watchdog timing.
表 2. Factory-Programmed Watchdog Timing
INPUT
CWD
WATCHDOG LOWER BOUNDARY (tWDL
)
WATCHDOG UPPER BOUNDARY (tWDU)
UNIT
SET1
MIN
680
TYP
Watchdog disabled
800
MAX
MIN
1360
9.35
TYP
Watchdog disabled
1600
MAX
1840
12.65
0
1
0
1
NC
920
ms
ms
Watchdog disabled
1.85
Watchdog disabled
11.0
10 kΩ to VDD
1.48
2.22
16
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8.1.1.2 Adjustable Capacitor Timing
Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected to
CWD, then a 375-nA current source charges CCWD until VCWD = 1.21 V. The TPS3852-Q1 determines the
window watchdog upper boundary with the formula given in 公式 1, where CCWD is in microfarads (µF) and tWDU
is in seconds.
tWDU(typ)(s) = 77.4 × CCWD(µF) + 0.055 (s)
(1)
The TPS3852-Q1 is limited to using CCWD capacitors between 100 pF and 1 µF. Note that 公式 1 is for ideal
capacitors; capacitor tolerances cause the actual device timing to vary. For the most accurate timing, use
ceramic capacitors with COG dielectric material. As shown in 表 3, when using the minimum capacitance of 100
pF, the watchdog upper boundary is 62.74 ms; whereas with a 1-µF capacitance, the watchdog upper boundary
is 77.455 seconds. If a CCWD capacitor is used, 公式 1 can be used to set the window watchdog upper boundary
(tWDU). 表 4 shows how tWDU can be used to calculate tWDL
.
表 3. tWDU Values for Common Ideal Capacitor Values
WATCHDOG UPPER BOUNDARY (tWDU
)
CCWD
UNIT
MIN(1)
53.32
112.5
704
TYP
62.74
132.4
829
MAX(1)
72.15
152.2
953
100 pF
1 nF
ms
ms
ms
ms
ms
10 nF
100 nF
1 µF
6625
65836
7795
77455
8964
89073
(1) Minimum and maximum values are calculated using ideal capacitors.
表 4. Programmable CWD Timing
INPUT
CWD
WATCHDOG LOWER BOUNDARY (tWDL
)
WATCHDOG UPPER BOUNDARY (tWDU)
UNIT
SET1
MIN
TYP
Watchdog disabled
tWDU x 0.5
MAX
MIN
TYP
MAX
0
1
Watchdog disabled
CCWD
(1)
tWDU(min) x 0.5
tWDU(max) x 0.5
0.85 x tWDU(typ)
tWDU(typ)
1.15 x tWDU(typ)
s
(1) Calculated from 公式 1 using ideal capacitors.
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8.1.2 Overdrive Voltage
Forcing a RESET is dependent on two conditions: the amplitude VDD is beyond the trip point (ΔV1 and ΔV2), and
the length of time that the voltage is beyond the trip point (t1 and t2). If the voltage is just under the trip point for a
long period of time, RESET asserts and the output is pulled low. However, if VDD is just under the trip point for a
few nanoseconds, RESET does not assert and the output remains high. The length of time required for RESET
to assert can be changed by increasing the amount VDD goes under the trip point. If VDD is under the trip point by
10%, the amount of time required for the comparator to respond is much faster and causes RESET to assert
much quicker than when barely under the trip point voltage. 公式 2 shows how to calculate the percentage
overdrive.
Overdrive = |( VDD / VITX – 1) × 100% |
(2)
In 公式 2, VITX corresponds to the threshold trip point. If VDD is exceeding the positive threshold, VITN + VHYST is
used. VITN is used when VDD is falling below the negative threshold. In 图 19, t1 and t2 correspond to the amount
of time that VDD is over the threshold; the propagation delay versus overdrive for VITN and VITN + VHYST is
illustrated in 图 13 and 图 14, respectively.
The TPS3852-Q1 is relatively immune to short positive and negative transients on VDD because of the overdrive
voltage.
ûV1
t1
VITN + VHYST
VDD
VITN
ûV2
t2
Time
Copyright © 2016, Texas Instruments Incorporated
图 19. Overdrive Voltage
18
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ZHCSG27 –FEBRUARY 2017
8.2 Typical Application
A typical application for the TPS3852-Q1 is shown in 图 20. The TPS3852G33-Q1 is used to monitor the
3.3-V, VCORE rail powering the microcontroller.
3.3 V
V
CORE
Microcontroller
TPS3852-Q1
RESET
TPS3890-Q1
SENSE
RESET
V
DD
V
DD
MR
NMI
WDO
WDI
MR
CT
SET1
GPIO
RESET
GND
CWD
6.8 µF
GND
GND
2.2 nF
Copyright © 2016, Texas Instruments Incorporated
图 20. Monitoring Supply Voltage and Watchdog Supervision of a Microcontroller
8.2.1 Design Requirements
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
7.21 seconds (typ)
3.3-V CMOS
Watchdog disable for
initialization period
Watchdog must remain disabled for 7 seconds until
logic enables the watchdog timer
Output logic voltage
3.3-V CMOS
3.3 V with a 5% threshold
250 ms, maximum
50 µA
Worst-case VITN = 3.142 V
(–4.7% threshold)
Monitored rail
Watchdog window
tWDL(max) = 135 ms, tWDU(min) = 181 ms
Maximum device current
consumption
52 µA (worst-case) when RESET or WDO is
asserted(1)
(1) Only includes the TPS3852G33-Q1 current consumption.
8.2.2 Detailed Design Procedure
8.2.2.1 Monitoring the 3.3-V Rail
This application calls for very tight monitoring of the rail with only 5% of variation allowed on the rail. To ensure
this requirement is met, the TPS3852G33-Q1 was chosen for its –4% threshold. To calculate the worst-case for
VITN, the accuracy must also be taken into account. The worst-case for VITN can be calculated by 公式 3:
VITN(Worst-Case) = VITN(typ) × 0.992 = 3.3 × 0.96 × 0.992 = 3.142 V
(3)
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8.2.2.2 Calculating RESET and the WDO Pullup Resistor
The TPS3852-Q1 uses an open-drain configuration for the RESET circuit, as shown in 图 21. When the FET is
off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull
the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to
ensure that VOL is below the maximum value. To choose the proper pullup resistor, there are three key
specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRESET),
and VOL. The maximum VOL is 0.4 V, meaning that the effective resistor divider created must be able to bring the
voltage on the reset pin below 0.4 V with IRESET kept below 10 mA. For this example, with a VPU of 3.3 V, a
resistor must be chosen to keep IRESET below 50 μA because this value is the maximum consumption current
allowed. To ensure this specification is met, a pullup resistor value of 100 kΩ was selected, which sinks a
maximum of 33 μA when RESET or WDO is asserted. As illustrated in 图 11, when the RESET current is at 33
μA the low-level output voltage is approximately zero.
VPU
RESET
RESET
CONTROL
Copyright © 2016, Texas Instruments Incorporated
图 21. RESET Open-Drain Configuration
8.2.2.3 Setting the Window Watchdog
As illustrated in 图 18, there are three options for setting the window watchdog. The design specifications in this
application require the programmable timing option (external capacitor connected to CWD). When a capacitor is
connected to the CWD pin, the window is governed by 公式 4. 公式 4 is only valid for ideal capacitors, any
temperature or voltage derating must be accounted for separately.
tWDU - 0.055
0.25 - 0.055
CCWD mF =
=
= 0.0025 mF
(
)
77.4
77.4
(4)
The nearest standard capacitor value to 2.5 nF is 2.2 nF. Selecting 2.2 nF for the CCWD capacitor gives the
following minimum and maximum timing parameters:
tWDU(MIN) = 0.85ì tWDU(TYP) = 0.85ì 77.4ì2.2ì10-3 + 0.055 = 191 ms
(5)
-3
»
ÿ
tWDL(MAX) = 0.5ìtWDU(MAX) = 0.5ì 1.15ì 77.4ì2.2ì10 + 0.055 =129 ms
⁄
(6)
Capacitor tolerance also influence tWDU(MIN) and tWDL(MAX). Select a ceramic COG dielectric capacitor for high
accuracy. For 2.2 nF, COG capacitors are readily available with a 5% tolerance, which results in a 5% decrease
in tWDU(MIN) and a 5% increase in tWDL(MAX), giving 181 ms and 135 ms, respectively. A falling edge must be
issued within this window.
8.2.2.4 Watchdog Disabled During Initialization Period
The watchdog is often needed to be disabled during startup to allow for an initialization period. When the
initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by
the TPS3852-Q1. To achieve this setup, SET1 must start at GND. In this design, SET1 is controlled by a
TPS3890-Q1 supervisor. In this application, the TPS3890-Q1 was chosen to monitor VDD as well, meaning that
RESET on the TPS3890-Q1 stays low until VDD rises above VITN. When VDD comes up, the delay time can be
adjusted through the CT capacitor on the TPS3890-Q1. With this approach, the RESET delay can be adjusted
from a minimum of 25 µs to a maximum of 30 seconds. For this design, a minimum delay of 7 seconds is needed
until the watchdog timer is enabled. The CT capacitor calculation (see the TPS3890-Q1 data sheet) yields an
ideal capacitance of 6.59 µF, giving a closest standard ceramic capacitor value of 6.8 µF. When connecting a
6.8-µF capacitor from CT to GND, the typical delay time is 7.21 seconds. 图 22 illustrates the typical startup
waveform for this circuit when the watchdog input is off. 图 22 illustrates that when the watchdog is disabled, the
WDO output remains high. See the TPS3890-Q1 data sheet for detailed information on the TPS3890-Q1.
20
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ZHCSG27 –FEBRUARY 2017
8.2.3 Glitch Immunity
图 25 shows the high-to-low glitch immunity for the TPS3852G33-Q1 with a 7% overdrive with VDD starting at 3.3
V. This curve shows that VDD can go below the threshold for 5.2 µs without RESET asserting.
8.2.4 Application Curves
Unless otherwise stated, application curves were taken at TA = 25°C.
VDD
2V/div
VDD
2V/div
128 ms
7.94 s
SET1
WDI
2V/div
2V/div
WDO
2V/div
WDO
2V/div
RESET
2V/div
RESET
2V/div
1s/div
50ms/div
图 22. Startup Without a WDI Signal
图 23. Typical WDI Signal
VDD
1V/div
(yellow)
VDD
1V/div
RESET
1V/div
5.2 µs
(green)
204 ms
RESET
2V/div
2µs/div
50ms/div
图 24. Typical RESET Delay
图 25. High-to-Low Glitch Immunity
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9 Power Supply Recommendations
This device is designed to operate from an input supply with a voltage range between 1.6 V and 6.5 V. An input
supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is
to place a 0.1-µF capacitor between the VDD pin and the GND pin.
10 Layout
10.1 Layout Guidelines
•
•
•
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
If a CCWD capacitor or pull-up resistor is used, place these components as close as possible to the CWD pin.
If the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.
Place the pullup resistors on RESET and WDO as close to the pin as possible.
10.2 Layout Example
Vin
RPU1
CVDD
Vin
RPU2
1
2
3
4
8
7
6
5
Vin
CCWD
VDD
CWD
MR
RESET
WDO
WDI
GND
SET1
GND Plane
Denotes a via
图 26. Typical Layout for the TPS3852-Q1
22
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TPS3852-Q1
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ZHCSG27 –FEBRUARY 2017
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 评估模块
TPS3851EVM-780 评估模块可用于评估此部件。使用此评估模块时,必须将 EVM 上的器件更换为 TPS3852-
Q1。
11.1.2 器件命名规则
表 5. 器件命名规则
说明
命名规则
值
TPS3852
(具有窗口看门狗的高精度监控器)
—
—
G
H
VITN = –4%
VITN = -7%
1.8V
X
(标称阈值,受监视电压标称值的百分比)
yy(y)(1)
(受监视电压标称值选项)
18
33
3.3V
(1) 例如,TPS3852G33QDRBQ1 对应的受监视电压标称值为 3.3V,标称阈值为 -4%。
11.2 接收文档更新通知
如需接收文档更新通知,请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后,即可每周定期收到已更改的产品信息。有关更改的详细信息,请查阅已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
24
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3852G18QDRBRQ1
TPS3852G33QDRBRQ1
TPS3852H18QDRBRQ1
TPS3852H33QDRBRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
SON
SON
DRB
DRB
DRB
DRB
8
8
8
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
852DB
Samples
Samples
Samples
Samples
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
852GB
852LB
852PB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3852-Q1 :
Catalog : TPS3852
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DRB0008F
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
S
C
A
L
E
3
0
.
A
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
1.6 0.05
(0.2) TYP
4
5
A
A
2X
1.95
2.4 0.05
8
1
6X 0.65
0.35
0.25
8X
PIN 1 ID
0.5
0.3
0.1
C A B
C
8X
(OPTIONAL)
0.05
4222121/C 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.55)
(2.8)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222121/C 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.6)
8X (0.3)
1
8
(0.635)
SYMM
(1.07)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222121/C 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DRB0008K
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
0.07 MIN
(0.13)
S
C
A
L
E
3
0
.
A
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
A
A
1.6 0.05
(0.2) TYP
EXPOSED
THERMAL PAD
(0.19) TYP
4
1
5
2X
1.95
9
SYMM
2.4 0.05
8
6X 0.65
0.35
8X
SYMM
PIN 1 ID
(45 X 0.3)
0.25
0.5
0.3
0.1
C A B
8X
0.05
C
4227074/D 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008K
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.8)
(1.6)
8X (0.6)
1
8
8X (0.3)
(2.4)
SYMM
9
(0.95)
6X (0.65)
5
4
(R0.05) TYP
(
0.2) VIA
(0.55)
SYMM
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4227074/D 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008K
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.8)
2X (1.5)
8X (0.6)
8
1
2X
(1.06)
8X (0.3)
9
SYMM
(0.63)
6X (0.65)
5
4
(R0.05) TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4227074/D 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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