TPS3850G33QDRCRQ1 [TI]
用于进行 OV 和 UV 监控的汽车窗口监控器,具有窗口看门狗计时器和可编程延迟 | DRC | 10 | -40 to 125;型号: | TPS3850G33QDRCRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 用于进行 OV 和 UV 监控的汽车窗口监控器,具有窗口看门狗计时器和可编程延迟 | DRC | 10 | -40 to 125 监控 |
文件: | 总42页 (文件大小:2022K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS3850-Q1
ZHCSFY8B –JANUARY 2017 –REVISED SEPTEMBER 2021
TPS3850-Q1 具备可编程窗口看门狗定时器的高精度电压监控器
1 特性
3 说明
• 具有符合AEC-Q100 标准的下列特性:
TPS3850-Q1 将可编程窗口看门狗定时器与高精度电
压监控器相结合。TPS3850-Q1 窗口比较器在 SENSE
引脚上可针对过压 (VIT+(OV)) 和欠压 (VIT–(UV)) 阈值实
现 0.8% 的精度(–40°C 至 +125°C)。TPS3850-Q1
在两种阈值条件下还可提供高精度迟滞,因此非常适用
于容差要求严苛的系统。该监控器的 RESET 延迟可通
过经出厂编程的默认延迟设置进行设定,也可以通过外
部电容以编程方式设定。出厂编程的 RESET 延迟具备
9.5% 精度、高精度延迟时间。
– 器件温度等级1:-40°C 至125°C 环境工作温度
范围
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 提供功能安全
– 可帮助进行功能安全系统设计的文档
• 输入电压范围:VDD = 1.6V 至6.5V
• 0.8% 电压阈值精度(最大值)
• 低电源电流:IDD = 10µA(典型值)
• 用户可编程看门狗超时
• 用户可编程复位延迟
• 出厂编程的精密看门狗和复位计时器
• 开漏输出
TPS3850-Q1 具备适用于多种应用的可编程窗口看门
狗计时器。专用看门狗输出 (WDO) 有助于提高分辨
率,从而帮助确定出现故障情况的根本原因。窗口看门
狗超时可通过经出厂编程的默认延迟设置进行设定,也
可以通过外部电容以编程方式设定。可通过逻辑引脚禁
用看门狗,避免在开发过程中出现意外的看门狗超时。
• 精密过压和欠压监测:
– 支持0.9V 到5.0V 常见电压轨
– 提供4% 和7% 故障窗口
– 0.5% 迟滞
TPS3850-Q1 采用小型3.00mm ×
3.00mm、10 引脚 VSON 封装。TPS3850-Q1 具有可
湿性侧面,可轻松进行光学检查。
• 看门狗禁用功能
• 采用小型3mm × 3mm 10 引脚VSON 封装
器件信息
封装(1)
2 应用
封装尺寸(标称值)
器件型号
TPS3850-Q1
VSON (10)
3.00mm × 3.00mm
• 车载充电器(OBC) 和无线充电器
• 驾驶员监控
• 数字驾驶舱处理单元
• Adas 域控制器
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
• 汽车远程信息处理控制单元
1.8V
0.5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
1.2V
0.3
0.1
V
V
I/O
TPS3850-Q1
CORE
SENSE
SET1
VDD
RESET
WDO
Microcontroller
RESET
NMI
SET0
CRST
CWD
-0.1
-0.3
-0.5
GPIO
WDI
GND
GND
Copyright © 2016, Texas Instruments Incorporated
典型应用电路
-50
-25
0
25
50
75
100
125
Temperature (èC)
过压阈值(VIT+(OV)) 精度与温度间的关系
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBVS264
TPS3850-Q1
ZHCSFY8B –JANUARY 2017 –REVISED SEPTEMBER 2021
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................21
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Applications.................................................. 27
9 Power Supply Recommendations................................33
10 Layout...........................................................................34
10.1 Layout Guidelines................................................... 34
10.2 Layout Example...................................................... 34
11 Device and Documentation Support..........................35
11.1 Device Support........................................................35
11.2 Documentation Support.......................................... 35
11.3 接收文档更新通知................................................... 35
11.4 支持资源..................................................................35
11.5 Trademarks............................................................. 36
11.6 Electrostatic Discharge Caution..............................36
11.7 术语表..................................................................... 36
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements..................................................6
6.7 Timing Diagrams.........................................................7
6.8 Typical Characteristics..............................................10
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagrams....................................... 13
7.3 Feature Description...................................................14
Information.................................................................... 36
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (April 2017) to Revision B (July 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 删除了“±15% 精度的WDT 和RST 延迟”.......................................................................................................1
• 添加了“提供功能安全”要点.............................................................................................................................1
• 更新了“应用”以链接到网站.............................................................................................................................1
• 添加了“在SENSE 引脚上”以进行澄清........................................................................................................... 1
• Updated ESD Ratings.........................................................................................................................................4
• Changed ICWD min and max spec ......................................................................................................................5
• Changed VCWD min and max spec .................................................................................................................... 5
• Added a footnote to for tINIT ............................................................................................................................... 6
• Created a separate section for Timing Diagram................................................................................................. 7
• Added explanation about capacitors for tWDU. ...............................................................................................24
• Changed minimum and maximum limits on tWDU from 0.85 and 1.15 to 0.905 and 1.095 respectively .......... 24
• Changed 0.85 to 0.905 in Equation 14 and 1.15 to 1.05 in Equation 15.......................................................... 31
Changes from Revision * (January 2017) to Revision A (April 2017)
Page
• Changed 0.000381 to 0.000324 in Equation 11 .............................................................................................. 28
• Changed Equation 17 and Equation 18 so that ISENSE is no longer in the denominator ................................. 32
• Deleted J row from Device Nomenclature table............................................................................................... 35
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5 Pin Configuration and Functions
VDD
CWD
SET0
CRST
GND
1
2
3
4
5
10
9
SENSE
RESET
WDO
Pad
8
7
WDI
6
SET1
Not to scale
图5-1. DRC Package
3-mm × 3-mm VSON-10
Top View
表5-1. Pin Functions
PIN
NO.
DESCRIPTION
NAME
I/O
Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout
period. This pin can also be connected by a 10-kΩpullup resistor to VDD, or left unconnected (NC) for various
factory-programmed reset timeout options; see the CRST Delay section.
CRST
4
I
When using an external capacitor, use 方程式3 to determine the reset timeout.
Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin
and ground. Furthermore, this pin can also be connected by a 10-kΩresistor to VDD, or leaving unconnected
(NC) further enables the selection of the preset watchdog timeouts; see the 节6.6 table.
When using a capacitor, the TPS3850-Q1 determines the window watchdog upper boundary with 方程式6.
The lower watchdog boundary is set by the SET pins, see 表8-5 and the CWD Functionality section for
additional information.
CWD
GND
2
5
I
Ground pin
—
Reset output. Connect RESET using a 1-kΩto 100-kΩresistor to VDD. RESET goes low when the voltage at
the SENSE pin goes below the undervoltage threshold (VIT-(UV)) or above the overvoltage threshold (VIT+(OV)).
When the voltage level at the SENSE pin is within the normal operating range, the RESET timeout counter
starts. At timer completion, RESET goes high. During startup, the state of RESET is undefined below the
specified power-on-reset voltage (VPOR). Above VPOR, RESET goes low and remains low until the monitored
voltage is within the correct operating range (between VIT-(UV) and VIT(+OV)) and the RESET timeout is
complete.
RESET
9
O
SENSE
SET0
10
3
I
I
SENSE input to monitor the voltage rail. Connect this pin to the supply rail that must be monitored.
Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog;
see the 节6.6 table.
Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog;
see the 节6.6 table.
SET1
VDD
6
1
I
I
Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended.
Watchdog input. A falling transition (edge) must occur at this pin between the lower (tWDL(max)) and upper
(tWDU(min)) window boundaries in order for WDO to not assert.
WDI
7
8
I
When the watchdog is not in use, the SETx pins can be used to disable the watchdog. The input at WDI is
ignored when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is
disabled, then WDI cannot be left unconnected and must be driven to either VDD or GND.
Watchdog output. Connect WDO with a 1-kΩto 100-kΩresistor to VDD. WDO goes low (asserts) when a
watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs, WDO
goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a high-
impedance state.
WDO
O
Thermal pad
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage
Output voltage
VDD
7
–0.3
–0.3
–0.3
–0.3
RESET, WDO
SET0, SET1, WDI, SENSE
CWD, CRST
7
V
7
VDD + 0.3(3)
±20
Voltage ranges
V
Output pin current
RESET, WDO
mA
mA
Input current (all pins)
±20
Continuous total power dissipation
See 节6.4
(2)
Operating junction, TJ
150
150
150
–40
–40
–65
(2)
Temperature
Operating free-air, TA
°C
Storage, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) TJ = TA as a result of the low dissipated power in this device.
(3) The absolute maximum rating is VDD + 0.3 V or 7.0 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
6.5
UNIT
VDD
VSENSE
VSET0
VSET1
CCRST
CRST
CCWD
CWD
RPU
Supply pin voltage
1.6
V
V
Input pin voltage
0
6.5
SET0 pin voltage
0
6.5
V
SET1 pin voltage
0
0.1(1)
9
6.5
V
RESET delay capacitor
Pullup resistor to VDD
Watchdog timing capacitor
Pullup resistor to VDD
Pullup resistor, RESET and WDO
RESET pin current
1000(1)
nF
kΩ
nF
kΩ
kΩ
mA
mA
°C
10
11
0.1(2)
9
1000(2)
11
10
10
1
100
10
IRST
IWDO
TJ
Watchdog output current
Junction temperature
10
125
–40
(1) Using a CCRST capacitor of 0.1 nF or 1000 nF gives a reset delay of 703 µs or 3.22 seconds, respectively.
(2) Using a CCWD capacitor of 0.1 nF or 1000 nF gives a tWDU(typ) of 62.74 ms or 77.45 seconds, respectively.
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6.4 Thermal Information
TPS3850-Q1
THERMAL METRIC(1)
DRC (VSON)
10 PINS
47.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
52.4
22.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.4
ψJT
22.4
ψJB
RθJC(bot)
4.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at 1.6 V ≤VDD ≤6.5 V over the operating temperature range of –40°C ≤TA, TJ ≤+125°C (unless otherwise noted); the
open-drain pullup resistors are 10 kΩfor each output; typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL CHARACTERISTICS
(1) (2) (3)
VDD
IDD
Supply voltage
Supply current
1.6
6.5
19
V
10
µA
RESET FUNCTION
(2)
VPOR
Power-on-reset voltage
IRESET = 15 µA, VOL(MAX) = 0.25 V
0.8
V
V
(1)
VUVLO
Undervoltage lockout voltage
1.35
Overvoltage SENSE threshold accuracy,
entering RESET
VIT+(OV)
VIT-(UV)
VIT(ADJ)
VIT+(nom)+0.8%
VIT-(nom)+0.8%
0.4032
V
IT+(nom)–0.8%
Undervoltage SENSE threshold accuracy,
entering RESET
V
IT-(nom)–0.8%
Falling SENSE threshold voltage,
adjustable version only
0.3968
0.4
V
VHYST
ICRST
Hysteresis voltage
0.2%
337
0.5%
375
0.8%
413
CRST pin charge current
CRST pin threshold voltage
CRST = 0.5 V
CWD = 0.5 V
nA
V
VCRST
1.192
1.21
1.228
WINDOW WATCHDOG FUNCTION
ICWD
VCWD
VOL
CWD pin charge current
347
375
403
1.224
0.4
nA
V
CWD pin threshold voltage
1.196
1.21
RESET, WDO output low
VDD = 5 V, ISINK = 3 mA
V
ID
RESET, WDO output leakage current
Low-level input voltage (SET0, SET1)
High-level input voltage (SET0, SET1)
Low-level input voltage (WDI)
High-level input voltage (WDI)
VDD = 1.6 V, VRESET, = VWDO = 6.5 V
1
µA
V
VIL
0.25
VIH
0.8
V
VIL(WDI)
VIH(WDI)
0.3 × VDD
V
0.8 × VDD
V
TPS3850Xyy(y), VSENSE = 5.0 V,
VDD = 3.3 V
2.1
2.5
50
µA
nA
ISENSE
SENSE pin idle current
TPS3850H01 only, VSENSE = 5.0 V,
VDD = 3.3 V
–50
(1) When VDD falls below VUVLO, RESET is driven low.
(2) When VDD falls below VPOR, RESET and WDO are undefined.
(3) During power-on, VDD must be a minimum 1.6 V for at least 300 µs before the output corresponds to the SENSE voltage.
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6.6 Timing Requirements
at 1.6 V ≤VDD ≤6.5 V over the operating temperature range of –40°C ≤TA, TJ ≤+125°C (unless otherwise noted); the
open-drain pullup resistors are 10 kΩfor each output; typical values are at TJ = 25°C
MIN
TYP
MAX
UNIT
GENERAL
tINIT
CWD, CRST pin evaluation period(1)
Time required between changing the SET0 and SET1 pins
SET0, SET1 pin setup time
381
500
1
µs
µs
µs
µs
tSET
Startup delay(2)
300
RESET FUNCTION
CRST = NC
170
8.5
200
10
230
ms
ms
tRST
Reset timeout period
11.5
CRST = 10 kΩto VDD
VDD = 5 V, VSENSE = VIT+(OV) + 2.5%
VDD = 5 V, VSENSE = VIT-(UV) –2.5%
35
tRST-DEL
VSENSE to RESET delay
µs
17
WINDOW WATCHDOG FUNCTION
CWD = programmable, SET0 = 0, SET1 = 0(3)
CWD = programmable, SET0 = 1, SET1 = 1(3)
CWD = programmable, SET0 = 0, SET1 = 1(3) (4)
CWD = NC, SET0 = 0, SET1 = 0
1/8
1/2
Window watchdog ratio of
WD ratio lower boundary to upper
boundary
3/4
19.1
1.48
22.5
1.85
25.9
2.22
ms
ms
CWD = NC, SET0 = 0, SET1 = 1
CWD = NC, SET0 = 1, SET1 = 0
Watchdog disabled
CWD = NC, SET0 = 1, SET1 = 1
680
7.65
7.65
800
9.0
9.0
920
ms
ms
ms
Window watchdog lower
boundary
tWDL
10.35
10.35
CWD = 10 kΩto VDD, SET0 = 0, SET1 = 0
CWD = 10 kΩto VDD, SET0 = 0, SET1 = 1
CWD = 10 kΩto VDD, SET0 = 1, SET1 = 0
CWD = 10 kΩto VDD, SET0 = 1, SET1 = 1
CWD = NC, SET0 = 0, SET1 = 0
Watchdog disabled
1.48
1.85
55.0
2.22
63.3
ms
ms
ms
46.8
CWD = NC, SET0 = 0, SET1 = 1
23.375
27.5 31.625
CWD = NC, SET0 = 1, SET1 = 0
Watchdog disabled
CWD = NC, SET0 = 1, SET1 = 1
1360
92.7
1600
109.0
195.0
1840
125.4
224.3
ms
ms
ms
Window watchdog upper
boundary
tWDU
CWD = 10 kΩto VDD, SET0 = 0, SET1 = 0
CWD = 10 kΩto VDD, SET0 = 0, SET1 = 1
CWD = 10 kΩto VDD, SET0 = 1, SET1 = 0
CWD = 10 kΩto VDD, SET0 = 1, SET1 = 1
165.8
Watchdog disabled
9.35
11.0
150
12.65
ms
µs
Setup time required for the device to respond to changes on WDI after being
enabled
tWD-setup
Minimum WDI pulse duration
WDI to WDO delay
50
50
ns
ns
tWD-del
(1) Refer to 节8.1.1.2
(2) During power-on, VDD must be a minimum 1.6 V for at least 300 µs before the output corresponds to the SENSE voltage.
(3) 0 refers to VSET ≤VIL, 1 refers to VSET ≥VIH
(4) If this watchdog ratio is used, then tWDL(max) can overlap tWDU(min)
.
.
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6.7 Timing Diagrams
VDD
VUVLO
VPOR
VIT-(UV) + VHYST
VIT-(UV)
tRST-DEL
SENSE
tRST
tRST
(1)
RESET
WDI
tWDL < t < tWDU
t < tWDU
t < tWDU
X
X
t < tWDL
WDO
tRST
A. See 图6-2 for WDI timing requirements.
图6-1. Timing Diagram
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WDI
Early Fault
WDO
Correct Operation
WDI
WDO
Late Fault
WDI
WDO
Valid
Window
Window
Timing
tWDL(min)
tWDL(typ)
tWDL(max)
tWDU(min)
tWDU(typ)
tWDU(max)
= Tolerance Window
图6-2. TPS3850-Q1 Window Watchdog Timing
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VDD/
SENSE
RESET
tRST-DEL
tRST
SET0
tSET
tWD-setup
SET1
RATIO
1:8
1:2
1:8
Disabled
图6-3. Changing SET0 and SET1 Pins
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6.8 Typical Characteristics
all curves are taken at TA = 25°C with 1.6 V ≤VDD ≤6.5 V (unless otherwise noted)
0.5
0.3
0.5
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
0.3
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
图6-4. VIT+(OV) Accuracy vs Temperature
图6-5. VIT-(UV) Accuracy vs Temperature
0.5
0.3
0.5
0.3
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Average
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
图6-6. VIT-(OV) Accuracy vs Temperature
图6-7. VIT+(UV) Accuracy vs Temperature
25
20
15
10
5
25
20
15
10
5
0
0
-0.5 -0.4 -0.3 -0.2 -0.1
0
VIT+(OV) Accuracy (%)
0.1 0.2 0.3 0.4 0.5
-0.5 -0.4 -0.3 -0.2 -0.1
0
VIT-(UV) Accuracy (%)
0.1 0.2 0.3 0.4 0.5
Includes G and H versions; with 1.2-V, 1.8-V, 3.0-V, 3.3-V, and
5-V thresholds; total units = 41,111
Includes G and H versions; with 1.2-V, 1.8-V, 3.0-V, 3.3-V, and
5-V thresholds; total units = 41,111
图6-8. VIT+(OV) Accuracy Histogram
图6-9. VIT-(UV) Accuracy Histogram
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6.8 Typical Characteristics (continued)
all curves are taken at TA = 25°C with 1.6 V ≤VDD ≤6.5 V (unless otherwise noted)
380
376
372
368
364
16
12
8
-40èC
0èC
25èC
105èC
125èC
4
1.6 V
6.5 V
0
-50
-25
0
25
50
75
100
125
0
1
2
3
4
5
6
7
Temperature (èC)
VDD (V)
图6-11. Supply Current vs Power-Supply Voltage
1.6
图6-10. CWD Charging Current vs Temperature
1.6
1.4
1.2
1
-40èC
0èC
25èC
105èC
125èC
-40èC
0èC
25èC
105èC
125èC
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
1
2
3
IRESET (mA)
4
5
6
0
1
2
3
IRESET (mA)
4
5
6
VDD = 1.6 V
VDD = 6.5 V
图6-12. Low-Level RESET Voltage vs RESET Current
图6-13. Low-Level RESET Voltage vs RESET Current
90
90
-40èC
0èC
25èC
105èC
125èC
-40èC
0èC
25èC
105èC
125èC
70
50
30
10
70
50
30
10
1
2
3
4
Overdrive (%)
5
6
7
1
2
3
4
Overdrive (%)
5
6
7
VDD = 1.6 V, VIT+(OV) = 0.936 V
图6-14. Propagation Delay vs Overdrive
VDD = 6.5 V, VIT+(OV) = 0.936 V
图6-15. Propagation Delay vs Overdrive
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6.8 Typical Characteristics (continued)
all curves are taken at TA = 25°C with 1.6 V ≤VDD ≤6.5 V (unless otherwise noted)
40
30
20
10
0
40
30
20
10
0
-40èC
0èC
25èC
105èC
125èC
-40èC
0èC
25èC
105èC
125èC
1
2
3
4
Overdrive (%)
5
6
7
1
2
3
4
Overdrive (%)
5
6
7
VDD = 1.6 V, VIT-(UV) = 0.864 V
图6-16. Propagation Delay vs Overdrive
VDD = 6.5 V, VIT-(UV) = 0.864 V
图6-17. Propagation Delay vs Overdrive
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
Overdrive = 3%
Overdrive = 4%
Overdrive = 5%
Overdrive = 6%
Overdrive = 7%
Overdrive = 3%
Overdrive = 4%
Overdrive = 5%
Overdrive = 6%
Overdrive = 7%
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
VDD = 1.6 V, VIT+(OV) = 0.936 V
图6-18. SENSE Glitch Immunity vs Temperature
VDD = 6.5 V, VIT+(OV) = 0.936 V
图6-19. SENSE Glitch Immunity vs Temperature
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
Overdrive = 3%
Overdrive = 4%
Overdrive = 5%
Overdrive = 6%
Overdrive = 7%
Overdrive = 3%
Overdrive = 4%
Overdrive = 5%
Overdrive = 6%
Overdrive = 7%
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
VDD = 1.6 V, VIT-(UV) = 0.864 V
图6-20. SENSE Glitch Immunity vs Temperature
VDD = 6.5 V, VIT-(UV) = 0.864 V
图6-21. SENSE Glitch Immunity vs Temperature
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7 Detailed Description
7.1 Overview
The TPS3850-Q1 is a high-accuracy voltage supervisor with an integrated watchdog timer. This device includes
a precision voltage supervisor with both overvoltage (VIT+(OV)) and undervoltage (VIT-(UV)) thresholds that achieve
0.8% accuracy over the specified temperature range of –40°C to +125°C. In addition, the TPS3850-Q1 includes
accurate hysteresis on both thresholds, making the device ideal for use with tight tolerance systems where
voltage supervisors must ensure a RESET before the minimum and maximum supply tolerance of the
microprocessor or system-on-a-chip (SoC) is reached.
7.2 Functional Block Diagrams
VDD
VDD
SENSE
R1
RESET
R2
Precision
Clock
R3
Reference
0.4 V
VDD
WDO
State
Machine
Cap
Control
CWD
VDD
Cap
Control
CRST
WDI SET0 SET1
GND
RTOTAL = R1 + R2 + R3 = 4.5 MΩ.
图7-1. Fixed Version Block Diagram
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VDD
VDD
SENSE
RESET
Reference
0.4 V
Precision
Clock
VDD
WDO
State
Machine
Cap
Control
CWD
VDD
Cap
Control
CRST
WDI SET0 SET1
GND
图7-2. Adjustable Version Block Diagram
7.3 Feature Description
7.3.1 CRST
The CRST pin provides the user the functionality of both high-precision, factory-programmed, reset delay timing
options and user-programmable, reset delay timing. The CRST pin can be pulled up to VDD through a resistor,
have an external capacitor to ground, or can be left unconnected. The configuration of the CRST pin is re-
evaluated by the device every time the voltage on the SENSE line enters the valid window (VIT+(UV) < VSENSE
<
VIT-(OV)). The pin evaluation is controlled by an internal state machine that determines which option is connected
to the CRST pin. The sequence of events takes 381 μs (tINIT) to determine if the CRST pin is left unconnected,
pulled up through a resistor, or connected to a capacitor. If the CRST pin is being pulled up to VDD, then a 10-
kΩpullup resistor is required.
7.3.2 RESET
The RESET pin features a programmable reset delay time that can be adjusted from 703 µs to 3.22 seconds
when using adjustable capacitor timing. RESET is an open-drain output that should be pulled up through a 1-kΩ
to 100-kΩ pullup resistor. When VDD is above VDD (min), RESET remains high (not asserted) when the SENSE
voltage is between the positive threshold (VIT+(OV)) and the negative threshold (VIT-(UV)). If SENSE falls below
VIT-(UV) or rises above VIT+(OV), then RESET is asserted, driving the RESET pin to a low-impedance state. When
SENSE comes back into the valid window, a RESET delay circuit is enabled that holds RESET low for a
specified reset delay period (tRST). This tRST period is determined by what is connected to the CRST pin; see 图
8-1. When the reset delay has elapsed, the RESET pin goes to a high-impedance state and uses a pullup
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resistor to hold RESET high. The pullup resistor must be connected to the proper voltage rail to allow other
devices to be connected at the correct interface voltage. To ensure proper voltage levels, give some
consideration when choosing the pullup resistor values. The pullup resistor value is determined by output logic
low voltage (VOL), capacitive loading, and leakage current (ID); see the 节8.1.1 section for more information.
7.3.3 Over- and Undervoltage Fault Detection
The TPS3850-Q1 features both overvoltage detection and undervoltage detection. This detection is achieved
through the combination of two comparators with a precision voltage reference and a trimmed resistor divider
(fixed versions only). The SENSE pin is used to monitor the critical voltage rail; this configuration optimizes
device accuracy because all resistor tolerances are accounted for in the accuracy and performance
specifications. Both comparators also include built-in hysteresis that provides some noise immunity and ensures
stable operation. If the voltage on the SENSE pin drops below VIT-(UV), then RESET is asserted (driven low).
When the voltage on the SENSE pin is between the positive and negative threshold voltages, RESET deasserts
after the user-defined RESET delay time, as shown in 图7-3.
The SENSE input can vary from GND to 6.5 V, regardless of the device supply voltage used. Although not
required in most cases, for noisy applications, good analog-design practice is to place a 1-nF to 100-nF bypass
capacitor at the SENSE pin to reduce sensitivity to transient voltages on the monitored signal.
VIT+(OV)
Overvoltage Limit
VIT-(OV) = VIT+(OV) - VHYST
VSENSE
VIT+(UV) = VIT-(UV) + VHYST
VIT-(UV)
Undervoltage Limit
tRST
tRST
RESET
图7-3. Window Comparator Timing Diagram
7.3.4 Adjustable Operation Using the TPS3850H01Q1
The adjustable version (TPS3850H01Q1) can be used to monitor any voltage rail down to 0.4 V using the circuit
illustrated in 图 7-4. When using the TPS3850H01Q1, the device does not function as a window comparator;
instead, the device only monitors the undervoltage threshold. To monitor a user-defined voltage, the target
threshold voltage for the monitored supply (VMON) and the resistor divider values can be calculated by using 方
程式1 and 方程式2, respectively:
≈
’
÷
R1
VMON = V
ì 1+
∆
IT(ADJ)
R2 ◊
«
(1)
方程式 1 can be used to calculate either the negative threshold or the positive threshold by replacing VITx with
either VITN or VITN + VHYST, respectively.
RTOTAL = R1 + R2
(2)
Large resistor values minimize current consumption; however, the input bias current of the device degrades
accuracy if the current through the resistors is too low. Therefore, choosing an RTOTAL value so that the current
through the resistor divider is at least 100 times larger than the maximum SENSE pin current (ISENSE) ensures a
good degree of accuracy; see the IQ vs Accuracy Tradeoff In Designing Resistor Divider Input To A Voltage
Supervisor (SLVA450) for more details on sizing input resistors.
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V
MON
VDD
TPS3850-Q1
R
1
2
SENSE
SET1
SET0
CRST
CWD
VDD
RESET
WDO
R
WDI
WDI
GND
Copyright © 2016, Texas Instruments Incorporated
图7-4. Adjustable Voltage Monitor
7.3.5 Window Watchdog
7.3.5.1 SET0 and SET1
When changing the SET0 or SET1 pins, there are two cases to consider: enabling and disabling the watchdog,
and changing the SET0 or SET1 pins when the watchdog is enabled. In case 1 where the watchdog is being
enabled or disabled, the changes take effect immediately. However, in case 2, a RESET event must occur in
order for the changes to take place.
7.3.5.1.1 Enabling the Window Watchdog
The TPS3850-Q1 features the ability to enable and disable the watchdog timer. This feature allows the user to
start with the watchdog timer disabled and then enable the watchdog timer using the SET0 and SET1 pins. The
ability to enable and disable the watchdog is useful to avoid undesired watchdog trips during initialization and
shutdown. When the SETx pins are changed to disable the watchdog timer, changes on the pins are responded
to immediately (as shown in 图 7-5). When the watchdog goes from disabled to enabled, there is a 150 μs
(tWD-setup) transition period where the device does not respond to changes on WDI. After this 150-μs period, the
device begins to respond to changes on WDI again.
VDD/
SENSE
RESET
SET0
tWD-setup
SET1
RATIO
1:8
Disabled
1:8
图7-5. Enabling the Watchdog Timer
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7.3.5.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor
When using the TPS3850-Q1 with fixed timing options, if the watchdog is disabled and reenabled while WDO is
asserted (logic low) the watchdog performs as described in the 节 7.3.5.1.1 section. However, if there is a
capacitor on the CRST pin, and the watchdog is disabled and reenabled when WDO is asserted (logic low), then
the watchdog behaves as shown in 图 7-6. When the watchdog is disabled, WDO goes high impedance (logic
high). However, when the watchdog is enabled again, the tRST period must expire before the watchdog resumes
normal operation.
VDD/
SENSE
RESET
tWDU
tWDU
WDO
tRST
Disabling and
Enabling
watchdog
SET1
SET0
There is no WDI signal in this figure, WDI is always at GND.
图7-6. Enabling and Disabling the Watchdog Timer During a WDO Reset Event
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7.3.5.1.3 SET0 and SET1 During Normal Watchdog Operation
The SET0 and SET1 pins can be used to control the window watchdog ratio of the lower boundary to the upper
boundary. There are four possible modes for the watchdog (see 表 8-5): disabled, 1:8 ratio, 3:4 ratio, and 1:2
ratio. If SET0 = 1 and SET1 = 0, then the watchdog is disabled. When the watchdog is disabled, WDO does not
assert and the TPS3850-Q1 functions as a normal supervisor. The SET0 and SET1 pins can be changed when
the device is operational, but cannot be changed at the same time. If these pins are changed when the device is
operational, then there must be a 500-µs (tSET) delay between switching the two pins. If SET0 and SET1 are
used to change the reset timing, then a reset event must occur before the new timing condition is latched. This
reset can be triggered by SENSE rising above VIT+(OV) or below VIT-(UV), or by bringing VDD below VUVLO. 图 7-7
shows how the SET0 and SET1 pins do not change the watchdog timing option until a reset event has occurred.
VDD/
SENSE
RESET
tRST-DEL
tRST
SET0
tSET
SET1
RATIO
1:2
1:8
图7-7. Changing SET0 and SET1 Pins
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7.3.6 Window Watchdog Timer
This section provides information for the window watchdog modes of operation. A window watchdog is typically
employed in safety-critical applications where a traditional watchdog timer is inadequate. In a traditional
watchdog, there is a maximum time in which a pulse must be issued to prevent the reset from occurring.
However, in a window watchdog the pulse must be issued between a maximum lower window time (tWDL(max)
)
and the minimum upper window time (tWDU(min)) set by the CWD pin and the SET0 and SET1 pins. 表 8-5
describes how tWDU can be used to calculate the timing of tWDL. The tWDL timing can also be changed by
adjusting the SET0 and SET1 pins. 图 7-8 shows the valid region for a WDI pulse to be issued to prevent the
WDO from being triggered and being pulled low.
WDI
Early Fault
WDO
Correct Operation
WDI
WDO
Late Fault
WDI
WDO
Valid
Window
Window
Timing
tWDL(min)
tWDL(typ)
tWDL(max)
tWDU(min)
tWDU(typ)
tWDU(max)
= Tolerance Window
图7-8. TPS3850-Q1 Window Watchdog Timing
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7.3.6.1 CWD
The CWD pin provides the user the functionality of both high-precision, factory-programmed watchdog timing
options and user-programmable watchdog timing. The TPS3850-Q1 features three options for setting the
watchdog window: connecting a capacitor to the CWD pin, connecting a pullup resistor to VDD, and leaving the
CWD pin unconnected. The configuration of the CWD pin is evaluated by the device every time VSENSE enters
the valid window (VIT+(UV) < VSENSE < VIT-(OV)). The pin evaluation is controlled by an internal state machine that
determines which option is connected to the CWD pin. The sequence of events takes 381 μs (tINIT) to determine
if the CWD pin is left unconnected, pulled up through a resistor, or connected to a capacitor. If the CWD pin is
being pulled up to VDD using a pullup resistor, then a 10-kΩresistor is required.
7.3.6.2 WDI Functionality
WDI is the watchdog timer input that controls the WDO output. The WDI input is triggered by the falling edge of
the input signal. For the first pulse, the watchdog functions as a traditional watchdog timer; thus, the first pulse
must be issued before tWDU(min). After the first pulse, to ensure proper functionality of the watchdog timer, always
issue the WDI pulse within the window of tWDL(max) and tWDU(min). If the pulse is issued in this region, then WDO
remains unasserted. Otherwise, the device asserts WDO, putting the WDO pin into a low-impedance state.
The watchdog input (WDI) is a digital pin. To ensure there is no increase in IDD, drive the WDI pin to either VDD
or GND at all times. Putting the pin to an intermediate voltage can cause an increase in supply current (IDD
)
because of the architecture of the digital logic gates. When RESET is asserted, the watchdog is disabled and all
signals input to WDI are ignored. When RESET is no longer asserted, the device resumes normal operation and
no longer ignores the signal on WDI. If the watchdog is disabled, drive the WDI pin to either VDD or GND.
7.3.6.3 WDO Functionality
The TPS3850-Q1 features a window watchdog timer with an independent watchdog output ( WDO). The
independent watchdog output provides the flexibility to flag a fault in the watchdog timing without performing an
entire system reset. When RESET is not asserted (high), the WDO signal maintains normal operation. When
asserted, WDO remains down for tRST. When the RESET signal is asserted (low), the WDO pin goes to a high-
impedance state. When RESET is unasserted, the window watchdog timer resumes normal operation and WDO
can be used again.
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7.4 Device Functional Modes
表7-1 summarizes the functional modes of the TPS3850-Q1.
表7-1. Device Functional Modes
VDD
WDI
WDO
SENSE
RESET
Undefined
Low
VDD < VPOR
—
—
—
—
Ignored
High
V
POR ≤VDD < VUVLO
(1)
(1)
Ignored
Ignored
High
High
High
VSENSE < VIT+(UV)
VSENSE > VIT-(OV)
Low
Low
(2)
(3)
VIT-(UV) < VSENSE < VIT+(OV)
High
t
WDL(max) ≤tpulse
≤
VDD ≥VDD (min)
tWDU(min)
(3)
(2)
(2)
tWDL(max) > tpulse
Low
Low
VIT-(UV) < VSENSE < VIT+(OV)
VIT-(UV) < VSENSE < VIT+(OV)
High
High
(3)
tWDU(min) < tpulse
(1) When VSENSE has not entered the valid window.
(2) When VSENSE is in the valid window.
(3) Where tpulse is the time between falling edges on WDI.
7.4.1 VDD is Below VPOR ( VDD < VPOR
)
When VDD is less than VPOR, RESET is undefined and can be either high or low. The state of RESET largely
depends on the load that the RESET pin is experiencing.
7.4.2 Above Power-On-Reset But Less Than UVLO (VPOR ≤VDD < VUVLO
)
When VDD is less than VUVLO, and greater than or equal to VPOR, the RESET signal is asserted (logic low)
regardless of the voltage on the SENSE pin. When RESET is asserted, the watchdog output WDO is in a high-
impedance state regardless of the WDI signal that is input to the device.
7.4.3 Above UVLO But Less Than VDD (min) (VUVLO ≤VDD < VDD (min)
)
When VDD is less than VDD (min) and greater than or equal to VUVLO, the RESET signal responds to changes on
the SENSE pin, but the accuracy can be degraded.
7.4.4 Normal Operation (VDD ≥VDD (min)
)
When VDD is greater than or equal to VDD (min), the RESET signal is determined by VSENSE. When RESET is
asserted, WDO goes to a high-impedance state. WDO is then pulled high through the pullup resistor.
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
The following sections describe in detail proper device implementation, depending on the final application
requirements.
8.1.1 CRST Delay
The TPS3850-Q1 features three options for setting the reset delay (tRST): connecting a capacitor to the CRST
pin, connecting a pullup resistor to VDD, and leaving the CRST pin unconnected. 图 8-1 shows a schematic
drawing of all three options. To determine which option is connected to the CRST pin, an internal state machine
controls the internal pulldown device and measures the pin voltage. This sequence of events takes 381 μs
(tINIT) to determine which timing option is used. Every time RESET is asserted, the state machine determines
what is connected to the pin.
VDD
VDD
TPS3850-Q1
TPS3850-Q1
TPS3850-Q1
VDD
VDD
VDD
VDD
375 nA
375 nA
375 nA
CRST
CCRST
CRST
CRST
Cap
Control
Cap
Control
Cap
Control
User Programmable
Capacitor to GND
Floating
CRST
10 kΩ Resistor
to VDD
图8-1. CRST Charging Circuit
8.1.1.1 Factory-Programmed Reset Delay Timing
To use the factory-programmed timing options, the CRST pin must either be left unconnected or pulled up to
VDD through a 10-kΩ pullup resistor. Using these options enables a high-precision, 15% accurate reset delay
timing, as shown in 表8-1.
表8-1. Reset Delay Time for Factory-Programmed Reset Delay Timing
RESET DELAY TIME (tRST
)
CRST
UNIT
MIN
TYP
200
10
MAX
230
NC
170
8.5
ms
ms
11.5
10 kΩto VDD
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8.1.1.2 Programmable Reset Delay Timing
The TPS3850-Q1 uses a CRST pin charging current (ICRST) of 375 nA. When using an external capacitor, the
rising RESET delay time can be set to any value between 700 µs (CCRST = 100 pF) and 3.2 seconds (CCRST
=
1 µF). The typical ideal capacitor value needed for a given delay time can be calculated using 方程式 3, where
CCRST is in microfarads and tRST is in seconds:
tRST = 3.22 × CCRST + 0.000381
(3)
To calculate the minimum and maximum-reset delay time use 方程式4 and 方程式5, respectively.
tRST(min) = 2.8862 × CCRST + 0.000324
tRST(max) = 3.64392 × CCRST + 0.000438
(4)
(5)
The slope of 方程式 3 is determined by the time the CRST charging current (ICRST) takes to charge the external
capacitor up to the CRST comparator threshold voltage (VCRST). When RESET is asserted, the capacitor is
discharged through the internal CRST pulldown resistor. When the RESET conditions are cleared, the internal
precision current source is enabled and begins to charge the external capacitor; when VCRST = 1.21 V, RESET is
unasserted. Note that to minimize the difference between the calculated RESET delay time and the actual
RESET delay time, use a use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize
parasitic board capacitance around this pin. 表8-2 lists the reset delay time ideal capacitor values for CCRST
.
表8-2. Reset Delay Time for Common Ideal Capacitor Values
RESET DELAY TIME (tRST
)
CCRST
UNIT
MIN(1)
TYP
0.70
3.61
32.6
323
MAX(1)
0.80
100 pF
1 nF
0.61
3.21
29.2
289
ms
ms
ms
ms
ms
4.08
10 nF
100 nF
1 μF
36.8
364
2886
3227
3644
(1) Minimum and maximum values are calculated using ideal capacitors.
8.1.2 CWD Functionality
The TPS3850-Q1 features three options for setting the watchdog window: connecting a capacitor to the CWD
pin, connecting a pullup resistor to VDD, and leaving the CWD pin unconnected. 图 8-2 shows a schematic
drawing of all three options. If this pin is connected to VDD through a 10-kΩ pullup resistor or left unconnected
(high impedance), then the factory-programmed watchdog timeouts are enabled; see the table. Otherwise, the
watchdog timeout can be adjusted by placing a capacitor from the CWD pin to ground.
VDD
VDD
VDD
TPS3850-Q1
TPS3850-Q1
TPS3850-Q1
VDD
VDD
VDD
375 nA
375 nA
375 nA
10 kꢀ
CWD
CWD
CWD
C
CWD
Cap
Control
Cap
Control
Cap
Control
User Programmable
Capacitor to GND
CWD
Unconnected
10 kΩ Resistor
to VDD
Copyright © 2016, Texas Instruments Incorporated
图8-2. CWD Charging Circuit
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8.1.2.1 Factory-Programmed Timing Options
If using the factory-programmed timing options (listed in 表 8-3), the CWD pin must either be unconnected or
pulled up to VDD through a 10-kΩ pullup resistor. Using these options enables high-precision, factory
programmed watchdog timing.
表8-3. Factory-Programmed Watchdog Timing
INPUT
WATCHDOG LOWER BOUNDARY (tWDL
)
WATCHDOG UPPER BOUNDARY (tWDU)
UNIT
CWD
SET0 SET1
MIN
19.1
1.48
TYP
22.5
1.85
MAX
25.9
2.22
MIN
46.8
TYP
55.0
27.5
MAX
63.3
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ms
ms
23.375
31.625
NC
Watchdog disabled
Watchdog disabled
680
800
9.0
9.0
920
10.35
10.35
1360
1600
109.0
195.0
1840
125.4
224.3
ms
ms
ms
7.65
7.65
92.7
165.8
10 kΩto VDD
Watchdog disabled
1.48 1.85
Watchdog disabled
9.35 11.0
2.22
12.65
ms
8.1.2.2 Adjustable Capacitor Timing
Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected
to CWD, then a 375-nA, constant-current source charges CCWD until VCWD = 1.21 V. The TPS3850-Q1
determines the window watchdog upper boundary with the formula given in 方程式 6, where CCWD is in
microfarads and tWDU is in seconds.
tWDU(typ) = 77.4 × CCWD + 0.055
(6)
The TPS3850-Q1 is designed and tested using CCWD capacitors between 100 pF and 1 µF. Note that 方程式6 is
for ideal capacitors. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWDU
can decrease and the maximum of tWDU can increase by the capacitor tolerance. To allow for a valid watchdog
window, choose a capacitor with tolerance such that tWDU(min) and tWDL(max) do not overlap. For the most
accurate timing, use ceramic capacitors with COG dielectric material. As shown in 表 8-4, when using the
minimum capacitor of 100 pF, the watchdog upper boundary is 62.74 ms; whereas with a 1-µF capacitor, the
watchdog upper boundary is 77.455 seconds. If a CCWD capacitor is used, 方程式 6 can be used to set tWDU the
window watchdog upper boundary. The window watchdog lower boundary is dependent on the SET0 and SET1
pins because these pins set the window watchdog ratio of the lower boundary to upper boundary; 表 8-5 shows
how tWDU can be used to calculate tWDL based on the SET0 and SET1 pins.
8.1.2.3
表8-4. tWDU Values for Common Ideal Capacitor Values
WATCHDOG UPPER BOUNDARY (tWDU
)
CCWD
UNIT
MIN(1)
56.77
119.82
750
TYP
62.74
132.4
829
MAX(1)
68.7
100 pF
1 nF
ms
ms
ms
ms
ms
144.98
908
10 nF
100 nF
1 µF
7054
7795
77455
8536
70096
84814
(1) Minimum and maximum values are calculated using ideal capacitors.
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表8-5. Programmable CWD Timing
INPUT
SET0 SET1
WATCHDOG LOWER BOUNDARY (tWDL
)
WATCHDOG UPPER BOUNDARY (tWDU
MIN TYP
tWDU x 0.125 tWDU(max) x 0.125 0.905 x tWDU(typ)
)
UNIT
CWD
MIN
tWDU(min)x 0.125
tWDU(min) x 0.75
TYP
MAX
MAX
0
0
1
1
0
1
0
1
tWDU(typ) 1.095 x tWDU(typ)
tWDU(typ) 1.095 x tWDU(typ)
s
s
tWDU x 0.75
Watchdog disabled
tWDU x 0.5
tWDU(max) x 0.75 0.905 x tWDU(typ)
CCWD
Watchdog disabled
tWDU(max) x 0.5 0.905 x tWDU(typ) tWDU(typ) 1.095 x tWDU(typ)
tWDU(min) x 0.5
s
8.1.3 Adjustable SENSE Configuration
The TPS3850H01Q1 has an undervoltage supervisor that can monitor voltage rails greater than 0.4 V. 表 8-6
contains 1% resistor values for creating a voltage divider to monitor common rails from 0.5 V to 12 V with a
threshold of 4% and 10%. These resistor values can be scaled to decrease the amount of current flowing
through the resistor divider, but increasing the resistor values also decreases the accuracy of the resistor divider.
General practice is for the current flowing through the resistor divider to be 100 times greater than the current
going into the SENSE pin. This practice ensures the highest possible accuracy. 方程式 7 can be used to
calculate the resistors required in the resistor divider. 图8-3 shows the block diagram for adjustable operation.
≈
’
÷
R1
VMON = V
ì 1+
∆
IT(ADJ)
R2 ◊
«
(7)
表8-6. SENSE Resistor Divider Values
4% THRESHOLD
10% THRESHOLD
INPUT VOLTAGE (V)
THRESHOLD
VOLTAGE (V)
THRESHOLD
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
R1 (kΩ)
R2 (kΩ)
0.5
16.2
75
80.6
80.6
80.6
80.6
80.6
80.6
80.6
80.6
80.6
80.6
0.48
10
64.9
82.5
137
249
374
464
523
825
2100
80.6
80.6
80.6
80.6
80.6
80.6
80.6
80.6
80.6
80.6
0.45
0.72
0.81
1.08
1.64
2.26
2.70
2.99
4.49
10.82
0.8
0.9
1.2
1.8
2.5
3
0.77
93.1
150
267
402
499
562
887
2260
0.86
1.14
1.73
2.40
2.88
3.3
5
3.19
4.80
12
11.62
VDD
Reference
0.4 V
VMON
RESET
R1
RESET
TIMING
SENSE
R2
图8-3. Adjustable Voltage Divider
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8.1.4 Overdrive on the SENSE Pin
The propagation delay from exceeding the threshold to RESET being asserted is dependent on two conditions:
the amplitude of the voltage on the SENSE pin relative to the threshold, (ΔV1 and ΔV2), and the length of time
that the voltage is above or below the trip point (t1 and t2). If the voltage is just over the trip point for a long
period of time, then RESET asserts and the output is pulled low. However, if the SENSE voltage is just over the
trip point for a few nanoseconds, then the RESET does not assert and the output remains high. The time
required for RESET to assert can be changed by increasing the time that the SENSE voltage goes over the trip
point. 方程式8 shows how to calculate the percentage overdrive.
Overdrive = | ( VSENSE / VITx –1) × 100% |
(8)
In 方程式 8, VITx corresponds to the SENSE threshold trip point. If VSENSE exceeds the positive threshold, then
VIT+(OV) is used. VIT-(UV) is used when VSENSE falls below the negative threshold. In 图 8-4, t1 and t2 correspond
to the amount of time that the SENSE voltage is over the threshold. The response time versus overdrive for
V
IT+(OV) and VIT-(UV) is illustrated in 图6-14 and 图6-17, respectively.
The TPS3850-Q1 is relatively immune to short positive and negative transients on the SENSE pin because of
the overdrive voltage curve; see 图6-20 and 图6-21.
ûV1
t1
VIT+(OV)
VSENSE
VIT-(UV)
ûV2
t2
Time
图8-4. Overdrive Voltage on the SENSE Pin
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8.2 Typical Applications
8.2.1 Design 1: Monitoring a 1.2-V Rail with Factory-Programmable Watchdog Timing
A typical application for the TPS3850-Q1 is shown in 图8-5. The TPS3850G12Q1 is used to monitor the
1.2-V, VCORE rail powering the microcontroller.
1.8V
1.2V
V
V
I/O
TPS3850-Q1
CORE
SENSE
SET1
SET0
CRST
CWD
VDD
Microcontroller
RESET
NMI
RESET
WDO
WDI
GPIO
GND
GND
Copyright © 2016, Texas Instruments Incorporated
图8-5. Monitoring Supply Voltage and Watchdog Supervision of a Microcontroller
8.2.1.1 Design Requirements
PARAMETER
Reset delay
DESIGN REQUIREMENT
Minimum reset delay of 250 ms
DESIGN RESULT
Minimum reset delay of 260 ms, reset delay of
322 ms (typical)
Leaving the CWD pin unconnected with SET0 = 0
and SET1 = 1 produces a window with a tWDL(max)
of 2.2 ms and a tWDU(min) of 22 ms
Functions with a 200-Hz pulse-width modulation
(PWM) signal with a 50% duty cycle
Watchdog window
Output logic voltage
Monitored rail
1.8-V CMOS
1.8-V CMOS
Worst-case VIT+(OV) 1.257 V (4.8%)
Worst-case VIT-(UV) 1.142 V (4.7%)
1.2 V within ±5%
Maximum device current
consumption
10 µA of current consumption, typical worst-case of
199 µA when WDO or RESET is asserted
200 µA
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Monitoring the 1.2-V Rail
The window comparator allows for precise voltage supervision of common rails between 0.9 V and 5.0 V. This
application calls for very tight monitoring of the rail with only ±5% of variation allowed on the rail. To ensure this
requirement is met, the TPS3850G12Q1 was chosen for its ±4% thresholds. To calculate the worst-case for
VIT+(OV) and VIT-(UV), the accuracy must also be taken into account. The worst-case for VIT+(OV) can be calculated
by 方程式9:
VIT+(OV)(Worst-Case) = VIT+(OV)typ × 1.048 = 1.2 × 1.048 = 1.257 V
(9)
The worst case for VIT-(UV) can be calculated using 方程式10:
VIT–(UV)(Worst-Case) = VIT–(UV)typ × 0.952 = 1.2 × 0.952 = 1.142 V
(10)
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8.2.1.2.2 Meeting the Minimum Reset Delay
The TPS3850-Q1 features three options for setting the reset delay: connecting a capacitor to the CRST pin,
connecting a pullup resistor, and leaving the CRST pin unconnected. If the CRST pin is either unconnected or
pulled up the minimum timing requirement cannot be met, thus an external capacitor must be connected to the
CRST pin. Because a minimum time is required, the worst-case scenario is a supervisor with a high CRST
charging current (ICRST) and a low CRST comparator threshold (VCRST). For applications with ambient
temperatures ranging from –40°C to +125°C, CCRST can be calculated using ICRST(MAX), VCRST(MIN), and solving
for CCRST in 方程式11:
tRST(min) - 0.000324
0.25 - 0.000324
2.8862
CRST(min)_ideal
=
=
2.8862
(11)
When solving 方程式 11, the minimum capacitance required at the CRST pin is 0.086 μF. If standard capacitors
with ±10% tolerances are used, then the minimum CRST capacitor required can be found in 方程式12:
CRST(min)_ideal
0.086 mF
1- 0.1
CRST(min)
=
=
1- Ctolerance
(12)
Solving 方程式 12 where Ctolerance is 0.1 or 10%, the minimum CCRST capacitor is 0.096 μF. This value is then
rounded up to the nearest standard capacitor value, so a 0.1-μF capacitor must be used to achieve this reset
delay timing. If voltage and temperature derating are being considered, then also include these values in
Ctolerance
.
8.2.1.2.3 Setting the Watchdog Window
In this application, the window watchdog timing options are based on the PWM signal that is provided to the
TPS3850-Q1. A window watchdog setting must be chosen such that the falling edge of the PWM signal always
falls within the window. A nominal window must be designed with tWDL(max) less than 5 ms and tWDU(min) greater
than 5 ms. There are several options that satisfy this window option. An external capacitor can be placed on the
CWD pin and calculated to have a sufficient window. Another option is to use one of the factory-programmed
timing options. An additional advantage of choosing one of the factory-programmed options is the ability to
reduce the number of components required, thus reducing overall BOM cost. Leaving the CWD pin unconnected
(NC) with SET0 = 0 and SET1 = 1 produces a tWDL(max) of 2.22 ms and a tWDU(min) of 23.375 ms; see 图8-10.
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8.2.1.2.4 Calculating the RESET and WDO Pullup Resistor
The TPS3850-Q1 uses an open-drain configuration for the RESET circuit, as shown in 图 8-6. When the FET is
off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull
the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to
ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key
specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST),
and VOL. The maximum VOL is 0.4 V, meaning that the effective resistor divider created must be able to bring the
voltage on the reset pin below 0.4 V with IRST kept below 10 mA. For this example, with a VPU of 1.8 V, a resistor
must be chosen to keep IRST below 200 μA because this value is the maximum consumption current allowed.
To ensure this specification is met, a pullup resistor value of 10 kΩwas selected, which sinks a maximum of 180
μA when RESET or WDO is asserted. As illustrated in 图 6-12, the RESET current is at 180 μA and the low-
level output voltage is approximately zero.
VDD
RESET
RESET
CONTROL
图8-6. Open-Drain RESET Configuration
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8.2.1.3 Application Curves
Unless otherwise stated, application curves were taken at TA = 25°C.
VDD
500mV/div
SENSE
SENSE
1.2578 V
200mV/div
1.1576 V
WDO
RESET
500mV/div
VUVLO = 1.4 V
VDD
RESET
500mV/div
500mV/div
VPOR = .404V
100ms/div
50ms/div
图8-8. Window Comparator Thresholds Entering a
Valid Window
图8-7. Startup Waveform
VDD
VDD
2V/div
2V/div
SENSE
2V/div
SENSE
2V/div
WDO
2V/div
WDO
2V/div
WDI
2V/div
WDI
2V/div
22 ms
2.2 ms
5ms
10ms/div
5ms/div
图8-10. Window Watchdog Timing
图8-9. 200-Hz WDI Pulse
VDD
SENSE
500mV/div
200mV/div
RESET
500mV/div
50ms/div
图8-11. Typical RESET Delay Timing
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8.2.2 Design 2: Using the TPS3850H01Q1 to Monitor a 0.7-V Rail With an Adjustable Window Watchdog
Timing
A typical application for the TPS3850H01Q1 is shown in 图8-12.
3.3 V
0.7 V
TPS3850-Q1
V
V
I/O
CORE
TPS3890-Q1
SENSE
VDD
Microcontroller
VDD
SENSE
RESET
NMI
RESET
WDO
SET1
SET0
CRST
CWD
MR
CT
RESET
3.3 V
WDI
GPIO
6.8 µF
GND
GND
GND
2.2 nF
Copyright © 2016, Texas Instruments Incorporated
图8-12. Monitoring Supply Voltage and Watchdog Supervision of a Microcontroller
8.2.2.1 Design Requirements
PARAMETER
Reset delay
DESIGN REQUIREMENT
DESIGN RESULT
Minimum RESET delay of 150 ms
Minimum RESET delay of 170 ms
Watchdog disable for initialization Watchdog must remain disabled for 7 seconds until
7.21 seconds (typ)
period
logic enables the watchdog timer
Watchdog window
Output logic voltage
250 ms, maximum
tWDL(max) = 135 ms, tWDU(min) = 181 ms
3.3-V CMOS
3.3-V CMOS
VITN (max) 0.667 V (–4.7%)
VITN (typ) 0.65 V (–6.6%)
VITN (min) 0.641 V (–8.5%)
Monitored rail
0.7 V, with 7% threshold
50 µA
10 µA of current consumption typical, worst-case of
52 μA when WDO or RESET is asserted(1)
Maximum device current
consumption
(1) Only includes the current consumption of the TPS3850-Q1.
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Meeting the Minimum Reset Delay
The design goal for the RESET delay time can be achieved by either using an external capacitor or the CRST
pin can be left unconnected. To minimize component count, the CRST pin is left unconnected. For CRST = NC,
the minimum delay is 170 ms, which is greater than the minimum required RESET delay of 150 ms.
8.2.2.2.2 Setting the Window Watchdog
As illustrated in 图8-2, there are three options for setting the window watchdog. The design specifications in this
application require the programmable timing option (external capacitor connected to CWD). When a capacitor is
connected to the CWD pin, the window is governed by 方程式 13. 方程式 13 is only valid for ideal capacitors,
any temperature or voltage derating must be accounted for separately.
tWDU - 0.055
77.4
0.25 - 0.055
77.4
CCWD mF =
=
= 0.0025 mF
(
)
(13)
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The nearest standard capacitor value to 2.5 nF is 2.2 nF. Selecting 2.2 nF for the CCWD capacitor gives the
following minimum and maximum timing parameters:
tWDU(MIN) = 0.905ì tWDU(TYP) = 0.905ì 77.4ì 2.2ì10-3 + 0.055 = 203.88 ms
(14)
(15)
tWDL(MAX) = 0.5ì tWDU(MAX) = 0.5ì 1.05ì 77.4ì 2.2ì10-3+ 0.055 = 118 ms
»
ÿ
⁄
Capacitor tolerance also influences tWDU(MIN) and tWDL(MAX). Select a ceramic COG dielectric capacitor for high
accuracy. For 2.2 nF, COG capacitors are readily available with a 5% tolerance, resulting in a 5% decrease in
tWDU(MIN) and a 5% increase in tWDL(MAX), giving 181 ms and 135 ms, respectively. A falling edge must be issued
within this window.
8.2.2.2.3 Watchdog Disabled During the Initialization Period
The watchdog is often needed to be disabled during startup to allow for an initialization period. When the
initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by
the TPS3850-Q1. To achieve this setup, SET0 must start at VDD and SET1 must start at GND. In this design,
SET0 is simply tied to VDD and SET1 is controlled by a TPS3890-Q1 supervisor. In this application, the
TPS3890-Q1 was chosen to monitor VDD as well, which means that RESET on the TPS3890-Q1 stays low until
VDD rises above VITN. When VDD comes up, the delay time can be adjusted through the CT capacitor on the
TPS3890-Q1. With this approach, the RESET delay can be adjusted from a minimum of 25 µs to a maximum of
30 seconds. For this design, a minimum delay of 7 seconds is needed until the watchdog timer is enabled. The
CT capacitor calculation (see the TPS3890-Q1 data sheet) yields an ideal capacitance of 6.59 µF, giving a
closest standard ceramic capacitor value of 6.8 µF. When connecting a 6.8-µF capacitor from CT to GND, the
typical delay time is 7.21 seconds. 图 8-13 illustrates the typical startup waveform for this circuit when the
watchdog input is off. 图 8-13 illustrates that when the watchdog is disabled, the WDO output remains high. See
the TPS3890-Q1 data sheet for detailed information on the TPS3890-Q1.
8.2.2.2.4 Calculating the Sense Resistor
There are three key specifications to keep in mind when calculating the resistor divider values (R1 and R2, see
图 7-4 or 图 8-3): voltage threshold (VIT(ADJ)), resistor tolerance, and the SENSE pin current (ISENSE). To ensure
that no accuracy is lost because of ISENSE, the current through the resistor divider must be 100 times greater
than ISENSE. Starting with R2 = 80.6 kΩ provides a 5-µA resistor divider current when VSENSE = 0.4 V. To
calculate the nominal resistor values, use 方程式16:
V
IT(ADJ)
V
= V
+ R1
ITN
IT(ADJ)
R2
(16)
where
• VITN is the monitored falling threshold voltage and
• VIT(ADJ) is the threshold voltage on the SENSE pin
Solving 方程式 16 for R1 gives the nearest 1% resistor of 51.1 kΩ. Now, plug R1 back into 方程式 16 to get the
monitored threshold. With these resistor values, the nominal threshold is 0.65 V or 6.6%.
To calculate the minimum and maximum threshold variation including the tolerances of the resistors, threshold
voltage, and sense current, use 方程式17 and 方程式18.
≈
’
÷
◊
V
IT(ADJ)min
V
= V
+ R1(min)
+ISENSE(min) = 0.641V
∆
∆
«
÷
ITN(min)
IT(ADJ)min
R2(max)
(17)
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≈
’
÷
◊
V
IT(ADJ)max
V
= V
+ R1(max)
+ISENSE(max) = 0.667 V
∆
∆
«
÷
ITN(max)
IT(ADJ)max
R2(min)
(18)
where
• VITN is the falling monitored threshold voltage
• VIT(ADJ) is the sense voltage threshold and
• ISENSE is the sense pin current
The calculated tolerance on R1 and R2 is 1%.
8.2.2.3 Application Curves
VDD
VDD
2V/div
158 ms
2V/div
WDI
RESET
2V/div
2V/div
7.6 seconds
WDO
2V/div
SET1
2V/div
RESET
2V/div
WDO
50ms/div
2V/div
1s/div
图8-14. Typical WDI Signal
图8-13. Startup Without a WDI Signal
9 Power Supply Recommendations
This device is designed to operate from an input supply with a voltage range between 1.6 V and 6.5 V. An input
supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is
to place a 0.1-µF capacitor between the VDD pin and the GND pin.
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10 Layout
10.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends
placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the
CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected.
• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
• If a CCRST capacitor or pullup resistor is used, place these components as close as possible to the CRST pin.
If the CRST pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.
• If a CCWD capacitor or pullup resistor is used, place these components as close as possible to the CWD pin. If
the CWD pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin.
• Place the pullup resistors on RESET and WDO as close to the pin as possible.
10.2 Layout Example
CVDD
GND Plane
Vin
RPU1
1
2
3
4
5
10
9
SENSE
RESET
WDO
Vin
CCWD
VDD
CWD
SET0
CRST
GND
8
RPU2
CCRST
7
WDI
6
SET1
Vin
Denotes a via.
图10-1. Typical Layout for the TPS3850-Q1
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
The TPS3850EVM-781 Evaluation Module can be used to evaluate this part.
11.1.2 Device Nomenclature
表11-1. Device Nomenclature
DESCRIPTION
NOMENCLATURE
VALUE
TPS3850
—
—
(high-accuracy supervisor with window watchdog)
X
G
H
VIT+(OV) = 4%; VIT–(UV) = –4%
VIT+(OV) = 7%; VIT–(UV) = –7%
(nominal thresholds as a percent of the nominal
monitored voltage)
01
09
115
12
18
25
30
33
50
0.4 V
0.9 V
1.15 V
1.2 V
1.8 V
2.5 V
3.0 V
3.3 V
5.0 V
yy(y)
(nominal monitored voltage option)
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
• TPS3890-Q1 Low Quiescent Current, 1% Accurate Supervisor with Programmable Delay
• Optimizing Resistor Dividers at a Comparator Input
• TPS3850EVM-781 Evaluation Module
11.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
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11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021,德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3850G09QDRCRQ1
TPS3850G12QDRCRQ1
TPS3850G18QDRCRQ1
TPS3850G25QDRCRQ1
TPS3850G30QDRCRQ1
TPS3850G33QDRCRQ1
TPS3850G50QDRCRQ1
TPS3850H01QDRCRQ1
TPS3850H09QDRCRQ1
TPS3850H12QDRCRQ1
TPS3850H18QDRCRQ1
TPS3850H25QDRCRQ1
TPS3850H30QDRCRQ1
TPS3850H33QDRCRQ1
TPS3850H50QDRCRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
850BB
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
850CB
850DB
850EB
850FB
850GB
850HB
(850AA, 850AB)
850JB
850KB
850LB
850MB
850NB
850PB
850RB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3850-Q1 :
Catalog : TPS3850
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3850G09QDRCRQ1 VSON
TPS3850G12QDRCRQ1 VSON
TPS3850G18QDRCRQ1 VSON
TPS3850G25QDRCRQ1 VSON
TPS3850G30QDRCRQ1 VSON
TPS3850G33QDRCRQ1 VSON
TPS3850G50QDRCRQ1 VSON
TPS3850H01QDRCRQ1 VSON
TPS3850H09QDRCRQ1 VSON
TPS3850H12QDRCRQ1 VSON
TPS3850H18QDRCRQ1 VSON
TPS3850H25QDRCRQ1 VSON
TPS3850H30QDRCRQ1 VSON
TPS3850H33QDRCRQ1 VSON
TPS3850H50QDRCRQ1 VSON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3850G09QDRCRQ1
TPS3850G12QDRCRQ1
TPS3850G18QDRCRQ1
TPS3850G25QDRCRQ1
TPS3850G30QDRCRQ1
TPS3850G33QDRCRQ1
TPS3850G50QDRCRQ1
TPS3850H01QDRCRQ1
TPS3850H09QDRCRQ1
TPS3850H12QDRCRQ1
TPS3850H18QDRCRQ1
TPS3850H25QDRCRQ1
TPS3850H30QDRCRQ1
TPS3850H33QDRCRQ1
TPS3850H50QDRCRQ1
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
VSON
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
DRC
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
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