TPS3840DL32DBVRQ1 [TI]
具有手动复位和可编程复位延时时间的汽车类高输入电压监控器 | DBV | 5 | -40 to 125;型号: | TPS3840DL32DBVRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有手动复位和可编程复位延时时间的汽车类高输入电压监控器 | DBV | 5 | -40 to 125 监控 |
文件: | 总38页 (文件大小:1528K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS3840-Q1
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
具有 MR 和可编程延迟功能的 TPS3840-Q1 汽车类毫微 IQ 电压监控器
1 特性
2 应用
1
•
符合汽车类 应用要求
•
•
•
汽车音响主机和仪表组
•
具有符合 AEC-Q100 标准的下列特性:
汽车显示屏、集成驾驶舱和驾驶员监控
远程信息处理控制单元和紧急呼叫
–
器件温度等级 1:–40°C 至 +125°C 的环境工作
温度范围
3 说明
–
–
器件 HBM ESD 分类等级 2
TPS3840-Q1 系列电压监控器或复位 IC 可在高电压电
平下工作,同时能够在整个 VDD 和温度范围内保持非
常低的静态电流。TPS3840-Q1 可提供低功耗、高精
度和低传播延迟(tp_HL = 30µs 典型值)的最佳组合。
器件 CDM ESD 分类等级 C7B
•
宽工作电压范围:1.5V 至 10V
利用外部电阻器来扩展输入电压范围
–
•
•
毫微电源电流:350nA(典型值)、700nA(最大
值)
当 VDD 上的电压降至负电压阈值 (VIT-) 以下或手动复
位被拉至低逻辑 (VMR_L) 时,复位输出信号会置位。当
固定阈值电压 (VIT-)
–
–
–
阈值范围为 1.6V 至 4.9V(阶跃为 0.1V)
高精度:1%(典型值)、1.5%(最大值)
VDD 升至 VIT- 加迟滞 (VIT+) 以上以及手动复位 (MR) 悬
空或高于 VMR_H、复位延时时间 (tD) 已过期时,复位信
号会清除。可以通过在 CT 引脚和地之间连接一个电容
器对复位延时时间进行编程。对于快速复位,可以将
CT 引脚悬空。
内置的迟滞 (VIT+
)
–
–
1.6V < VIT- ≤ 3.0V = 100mV(典型值)
3.1V ≤ VIT- < 4.9V = 200mV(典型值)
•
•
快速启动延迟 (tSTRT):350µs(最大值)
其他 特性:低上电复位电压 (VPOR)、针对 MR 和
VDD 的内置毛刺抑制保护、内置迟滞、低漏极开路输
出漏电流 (ILKG(OD))。TPS3840-Q1 是一款用于汽车应
用和 电池供电/低功耗 应用的完美电压监控 解决方
案。
基于电容器的可编程复位延时时间:
–
tD:50µs(无电容器)至 6.2s (10µF)
•
•
低电平有效手动复位 (MR)
三种输出拓扑:
–
TPS3840DL-Q1:漏极开路,低电平有效
(RESET)
器件信息(1)
–
–
TPS3840PL-Q1:推挽,低电平有效 (RESET)
TPS3840PH-Q1:推挽,高电平有效 (RESET)
器件型号
封装
封装尺寸(标称值)
TPS3840-Q1
SOT-23 (5) (DBV)
2.90mm × 1.60mm
•
封装:5 引脚 SOT-23 (DBV)
(1) 有关封装详细信息,请参阅数据表末尾的机械制图附录。
典型应用电路
3.3V
1.8V
VCORE
VI/O
Microcontroller
VDD
VDD
MR
RESET
TPS3840PL18
CT GND
RESET
GND
MR
RESET
TPS3840DL30
CT
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNVSBA1
TPS3840-Q1
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements................................................ 7
7.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
9
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 器件和文档支持 ..................................................... 26
12.1 器件命名规则......................................................... 26
12.2 社区资源................................................................ 27
12.3 商标....................................................................... 27
12.4 静电放电警告......................................................... 27
12.5 Glossary................................................................ 27
13 机械、封装和可订购信息....................................... 27
8
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Original (April 2019) to Revision A
Page
•
将“预告信息”更改为“生产数据发布”......................................................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
TPS3840-Q1
www.ti.com.cn
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
5 Device Comparison Table
Device Comparison Table shows the variants planned to release at RTM, however other voltages from 表 3 at
the end of datasheet can be sample upon request, please contact TI sales representative for details.
PART NUMBER
TPS3840DL16DBVRQ1(1)
TPS3840DL25DBVRQ1(1)
TPS3840DL28DBVRQ1(1)
TPS3840DL29DBVRQ1(1)
TPS3840DL30DBVRQ1(1)
TPS3840DL31DBVRQ1(1)
TPS3840DL41DBVRQ1(1)
TPS3840DL42DBVRQ1(1)
TPS3840DL44DBVRQ1(1)
TPS3840DL45DBVRQ1(1)
TPS3840PL25DBVRQ1(2)
TPS3840PH27DBVRQ1(3)
TPS3840PH30DBVRQ1(3)
OUTPUT TOPOLOGY
Open-Drain, Active-Low
Open-Drain, Active-Low
Open-Drain, Active-Low
Open-Drain, Active-Low
Open-Drain, Active-Low
Open-Drain, Active-Low
Open-Drain, Active-Low
Open-Drain, Active-Low
Open-Drain, Active-Low
Open-Drain, Active-Low
Push-Pull, Active-Low
Push-Pull, Active-High
Push-Pull, Active-High
THRESHOLD (Vit-) (V)
HYSTERESIS (mV)
1.6
2.5
2.8
2.9
3.0
3.1
4.1
4.2
4.4
4.5
2.5
2.7
3.0
100
100
100
100
100
200
200
200
200
200
100
100
100
(1) TPS3840DL-Q1: Open-Drain, Active-Low (RESET)
(2) TPS3840PL-Q1: Push-Pull, Active-Low (RESET)
(3) TPS3840PH-Q1: Push-Pull, Active-High (RESET)
Copyright © 2019, Texas Instruments Incorporated
3
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ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
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6 Pin Configuration and Functions
DBV Package
5-Pin
TPS3840PL-Q1, TPS3840DL-Q1 Top View
DBV Package
5-Pin
TPS3840PH-Q1 Top View
RESET
VDD
1
2
3
5
CT
RESET
VDD
1
2
3
5
CT
/ NC
GND
4
MR
GND
4
MR / NC
Not to scale
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
TPS3840PL-Q1,
TPS3840DL-Q1
TPS3840PH-Q1
RESET
N/A
1
O
Active-High Output Reset Signal: This pin is driven high
when either the MR pin is driven to a logic low or VDD
voltage falls below the negative voltage threshold (VIT-).
RESET remains high (asserted) for the delay time period (tD)
after both MR is floating or above VMR_L and VDD voltage
rise above VIT+.
RESET
1
N/A
O
Active-Low Output Reset Signal: This pin is driven logic
when either the MR pin is driven to a logic low or VDD
voltage falls below the negative voltage threshold (VIT-).
RESET remains low (asserted) for the delay time period (tD)
after both MR is floating or above VMR_L and VDD voltage
rise above VIT+.
VDD
2
3
4
2
3
4
I
_
I
Input Supply Voltage. TPS3840-Q1 monitors VDD voltage
GND
Ground
MR / NC
Manual Reset. Pull this pin to a logic low (VMR_L) to assert a
reset signal in the output pin. After the MR pin is left floating
or pull to VMR_H the output goes to the nominal state after the
reset delay time(tD) expires. MR can be left floating when
not in use. NC stands for "No Connection" or floating.
CT
5
5
-
Capacitor Time Delay Pin. The CT pin offers a user-
programmable delay time. Connect an external capacitor on
this pin to adjust time delay. When not in use leave pin
floating for the smallest fixed time delay.
4
Copyright © 2019, Texas Instruments Incorporated
TPS3840-Q1
www.ti.com.cn
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
12
UNIT
VDD
RESET (TPS3840PL)
VDD + 0.3
VDD + 0.3
12
RESET (TPS3840PH)
Voltage
V
RESET (TPS3840DL)
MR(2)
12
CT
5.5
Current
RESET pin and RESET pin
Operating junction temperature, TJ
Storage, Tstg
±70
mA
°C
–40
–65
150
Temperature(3)
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
(3) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-
001(1)
± 2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
± 750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.5
0
NOM
MAX
10
UNIT
V
VDD
Input supply voltage
VRESET, VRESET
IRESET, IRESET
TJ
RESET pin and RESET pin voltage
RESET pin and RESET pin current
Junction temperature (free air temperature)
Manual reset pin voltage
10
V
0
±5
mA
°C
V
–40
0
125
VDD
(1)
VMR
(1) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
7.4 Thermal Information
TPS3840
THERMAL METRIC(1)
DBV (SOT23-5)
5 PINS
187.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
109.2
92.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
35.4
ψJB
92.5
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2019, Texas Instruments Incorporated
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TPS3840-Q1
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7.5 Electrical Characteristics
At 1.5 V ≤ VDD ≤ 10 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF
and over the operating free-air temperature range – 40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
COMMON PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDD
Input supply voltage
Negative-going input threshold accuracy(1)
1.5
–1.5
175
75
10
1.5
V
VIT-
-40°C to 125°C
1
200
100
%
VHYS
VHYS
Hysteresis on VIT- pin
VIT- = 3.1 V to 4.9 V
225
125
mV
mV
Hysteresis on VIT- pin
VIT- = 1.6 V to 3.0 V
VDD = 1.5 V < VDD < 10 V
(2)
IDD
Supply current into VDD pin
VDD > VIT+
300
700
600
nA
TA = -40°C to 125°C
VMR_L
VMR_H
RMR
Manual reset logic low input(3)
Manual reset logic high input(3)
Manual reset internal pull-up resistance
CT pin internal resistance
mV
V
0.7VDD
350
100
500
kΩ
kΩ
RCT
650
TPS3840PL (Push-Pull Active-Low)
VOL(max) = 200 mV
IOUT(Sink) = 200 nA
VPOR
Power on Reset Voltage(4)
300
200
mV
mV
1.5 V < VDD < 5 V
VDD < VIT-
Low level output voltage
VOL
IOUT(Sink) = 2 mA
1.5 V < VDD(2)< 5 V
VDD > VIT+
IOUT(Source) = 2 mA
0.8VDD
0.8VDD
V
V
High level output voltage
VOH
5 V < VDD < 10 V
(2)
VDD > VIT+
IOUT(Source) = 5 mA
TPS3840PH (Push-Pull Active-High)
VPOR
Power on Reset Voltage(4)
VOH, IOUT(Source) = 500 nA
950
200
mV
mV
1.5 V < VDD(2)< 5 V
VDD > VIT+
IOUT(Sink) = 2 mA
Low level output voltage
VOL
1.5 V < VDD(2)< 5 V
VDD > VIT+
200
mV
V
IOUT(Sink) = 5 mA
High level output voltage
1.5 V < VDD < 5 V, VDD < VIT-
IOUT(Source) = 2 mA
,
VOH
0.8VDD
TPS3840DL(Open-Drain)
Power on Reset Voltage(4)
VOL(max) = 0.2 V
IOUT (Sink) = 5.6 uA
VPOR
950
200
mV
mV
1.5 V < VDD < 5 V
VDD < VIT-
Low level output voltage
VOL
IOUT(Sink) = 2 mA
RESET pin in High Impedance,
VDD = VRESET = 5.5 V
VIT+ < VDD
Ilkg(OD) Open-Drain output leakage current
90
nA
(1) VIT- threshold voltage range from 1.6 V to 4.9 V in 100 mV steps, for released versions see Device Voltage Thresholds table.
(2) VIT+ = VHYS + VIT-
(3) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR
(4) VPOR is the minimum VDD voltage level for a controlled output state. VDD slew rate ≤ 100mV/µs
6
Copyright © 2019, Texas Instruments Incorporated
TPS3840-Q1
www.ti.com.cn
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
7.6 Timing Requirements
At 1.5 V ≤ VDD ≤ 10 V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF
and over the operating free-air temperature range – 40°C to 125°C, VDD slew rate < 100mV / us, unless otherwise noted.
Typical values are at TJ = 25°C.
PARAMETER
Startup Delay(1)
TEST CONDITIONS
CT pin open
MIN
TYP
MAX
UNIT
tSTRT
tP_HL
100
220
350
µs
Propagation detect delay for VDD falling
below VIT-
VDD = VIT+ to (VIT-) - 10%(2)
CT pin = open
15
30
50
µs
µs
tD
Reset time delay
CT pin = 10 nF
CT pin = 1 µF
5% VIT- overdrive(3)
6.2
619
10
ms
ms
µs
ns
tGI_VIT-
tMR_PW
tMR_RES
Glitch immunity VIT-
MR pin pulse duration to initiate reset
Propagation delay from MR low to reset
300
700
VDD = 4.5 V, MR < VMR_L
ns
VDD = 4.5 V,
MR = VMR_L to VMR_H
tMR_tD
Delay from release MR to deasert reset
tD
ms
(1) When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is release after the startup delay (tSTRT), a
capacitor at CT pin will add tD delay to tSTRT time
(2) tP_HL measured from threhold trip point (VIT-) to VOL for active low variants and VOH for active high variants.
(3) Overdrive % = [(VDD/ VIT-) - 1] × 100%
VIT+
VIT-
VDD(MIN)
VDD
VPOR
tSTRT + tD
tP_HL
tD
tP_HL
tSTRT + tD
VOH
RESET
VOL
(1) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then
tD programmed time will be added to the startup time, VDD slew rate = 100 mV / µs.
(2) Open-Drain timing diagram assumes pull-up resistor is connected to RESET
图 3. Timing Diagram TPS3840DL-Q1 (Open-Drain Active-Low)
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TPS3840-Q1
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
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VIT+
VIT-
VDD(MIN)
VDD
VPOR
tP_HL
tSTRT + tD
tD
tP_HL
tSTRT + tD
VOH
RESET
VOL
(3) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then
tD programmed time will be added to the startup time. VDD slew rate = 100 mV / µs.
图 4. Timing Diagram TPS3840PL-Q1 (Push-Pull Active-Low)
VIT+
VIT-
VDD(MIN)
VDD
VPOR
tSTRT + tD
tP_HL
tD
tP_HL
tSTRT + tD
VOH
RESET
VOL
(4) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then
tD programmed time will be added to the total startup time. VDD slew rate = 100 mV / µs.
图 5. Timing Diagram TPS3840PH-Q1 (Push-Pull Active-High)
8
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TPS3840-Q1
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ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
7.7 Typical Characteristics
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
0.6
0.55
0.5
0.6
0.55
0.5
25°C
-40°C
125°C
25°C
-40°C
125°C
0.45
0.4
0.45
0.4
0.35
0.3
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0.05
1
2
3
4
5
VDD (V)
6
7
8
9
10
1
2
3
4
5
VDD (V)
6
7
8
9
10
IDDv
IDDv
图 6. Supply Current vs Supply Voltage for TPS3840DL49-Q1
图 7. Supply Current vs Supply Voltage for TPS3840PL49-Q1
0.6
0.6
25°C
0.55
DL16
DL29
DL49
0.5
-40°C
125°C
0.4
0.3
0.2
0.1
0
0.5
0.45
0.4
0.35
0.3
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0.25
0.2
0.15
0.1
0.05
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
1
2
3
4
5 6
VDD (V)
7
8
9
10
VIT_
IDDv
图 8. Supply Current vs Supply Voltage for TPS3840PH49-
图 9. Negative-going Input Threshold Accuracy over
Q1
Temperature for TPS3840DL-Q1
0.6
0.6
0.5
0.4
0.3
0.2
0.1
0
PL16
PL28
PL49
PH16
PH30
PH49
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
VIT_
VIT_
图 10. Negative-going Input Threshold Accuracy over
图 11. Negative-going Input Threshold Accuracy over
Temperature for TPS3840PL-Q1
Temperature for TPS3840PH-Q1
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Typical Characteristics (接下页)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
20
15
10
5
20
15
10
5
DL16
DL29
DL49
PL16
PL28
PL49
0
0
-5
-5
-10
-15
-20
-10
-15
-20
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Vhys
Vhys
图 12. Input Threshold VIT- Hysteresis Accuracy for
图 13. Input Threshold VIT- Hysteresis Accuracy for
TPS3840DL-Q1
TPS3840PL-Q1
20
15
10
5
10
9
PH16
PH30
PH49
25°C
-40°C
125°C
8
7
6
5
0
4
-5
3
2
-10
-15
-20
1
0
-1
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
1
2
3
4
5
VDD (V)
6
7
8
9
10
Vhys
VRES
图 14. Input Threshold VIT- Hysteresis Accuracy for
图 15. Output Voltage vs Input Voltage for TPS3840DL49-Q1
TPS3840PH-Q1
10
9
5.5
25°C
-40°C
125°C
25°C
-40°C
125°C
5
8
4.5
4
7
6
3.5
3
5
4
2.5
2
3
2
1.5
1
1
0
0.5
0
-1
0
1
2
3
4
5
VDD (V)
6
7
8
9
10
0
1
2
3
4
5
VDD (V)
6
7
8
9
10
VRES
VRES
图 16. Output Voltage vs Input Voltage for TPS3840PL49-Q1
图 17. Output Voltage vs Input Voltage for TPS3840PH49-Q1
10
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Typical Characteristics (接下页)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
0.055
0.05
140
120
100
80
25°C
-40°C
125°C
25°C
-40°C
125°C
0.045
0.04
0.035
0.03
60
40
0.025
0.02
20
0.015
0
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
IRESET (mA)
3
3.5
4
4.5
5
VDD (V)
VOLv
VOL_
图 19. Low Level Output Voltage vs VDD for TPS3840DL49-
图 18. Low Level Output Voltage vs IRESET for TPS3840DL49-
Q1
Q1
0.055
140
25°C
-40°C
125°C
25°C
-40°C
125°C
0.05
0.045
0.04
120
100
80
60
40
20
0
0.035
0.03
0.025
0.02
0.015
-20
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
IRESET (mA)
3
3.5
4
4.5
5
VDD (V)
VOLv
VOL_
图 21. Low Level Output Voltage vs VDD for TPS3840PL49-
图 20. Low Level Output Voltage vs IRESET for TPS3840PL49-
Q1
Q1
0.09
0.085
0.08
80
70
60
50
40
30
20
10
0
25°C
-40°C
125°C
0.075
0.07
0.065
0.06
0.055
0.05
0.045
0.04
0.035
0.03
25°C
-40°C
125°C
0.025
0.02
0.015
0
0.5
1
1.5
2
2.5
IRESET (mA)
3
3.5
4
4.5
5
5
5.5
6
6.5
7
7.5 8
VDD (V)
8.5
9
9.5 10 10.5
VOL_
VOLv
图 23. Low Level Output Voltage vs VDD for TPS3840PH49-
图 22. Low Level Output Voltage vs IRESET for TPS3840PH49-
Q1
Q1
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Typical Characteristics (接下页)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
5
4.5
4
10
9.975
9.95
25°C
-40°C
125°C
25°C
-40°C
125°C
9.925
9.9
3.5
3
9.875
9.85
2.5
2
9.825
9.8
1.5
1
9.775
9.75
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
IRESET (mA)
3
3.5
4
4.5
5
VDD (V)
VOHv
VOH_
图 25. High Level Output Voltage over Temperature for
图 24. High Level Output Voltage vs IRESET for TPS3840PL49-
TPS3840PL49-Q1
Q1
5
1.6
25°C
-40°C
125°C
25°C
-40°C
125°C
4.5
4
1.55
1.5
3.5
3
1.45
1.4
2.5
2
1.35
1.3
1.5
1
1.25
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
IRESET (mA)
3
3.5
4
4.5
5
VDD (V)
VOHv
VOH_
图 27. High Level Output Voltage Over Temperature for
图 26. High Level Output Voltage vs IRESET for
TPS3840PH49-Q1
TPS3840PH49-Q1
2.75
2.5
2.25
2
2.75
DL16
DL29
DL49
PL16
PL28
PL49
2.5
2.25
2
1.75
1.5
1.25
1
1.75
1.5
1.25
1
0.75
0.75
0.5
0.5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
MR_L
MR_L
图 28. Manual Reset Logic Low Voltage Threshold Over
图 29. Manual Reset Logic Low Voltage Threshold Over
Temperature for TPS3840DL-Q1
Temperature for TPS3840PL-Q1
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Typical Characteristics (接下页)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
2.75
2.5
2.25
2
2.75
2.5
2.25
2
DL16
DL29
DL49
PH16
PH230
PH49
1.75
1.5
1.25
1
1.75
1.5
1.25
1
0.75
0.5
0.75
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
MR_L
MR_H
图 30. Manual Reset Logic Low Voltage Threshold Over
图 31. Manual Reset Logic High Voltage Threshold Over
Temperature for TPS3840PH-Q1
Temperature for TPS3840DL-Q1
2.75
2.75
PL16
PL28
PL49
PH16
PH30
PH49
2.5
2.25
2
2.5
2.25
2
1.75
1.5
1.25
1
1.75
1.5
1.25
1
0.75
0.75
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
MR_H
MR_H
图 32. Manual Reset Logic High Voltage Threshold Over
图 33. Manual Reset Logic High Voltage Threshold Over
Temperature for TPS3840PL-Q1
Temperature for TPS3840PH-Q1
22
478
25°C
-40°C
125°C
DL49
PL49
PH49
21
20
19
18
17
16
15
14
13
12
476
474
472
470
468
466
464
462
460
458
5
10
15
20
25 30
Overdrive (%)
35
40
45
50
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Glit
RCTv
图 34. Glitch Immunity on VIT- vs Overdrive (Data Taken with
图 35. CT Pin Internal Resistance Over Temperature
TPS3840PL28-Q1)
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Typical Characteristics (接下页)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
15
12
9
215
210
205
200
195
190
185
180
175
170
DL49
PL49
PH49
DL49
PL49
PH49
6
3
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Star
Dela
图 36. Startup Delay Over Temperature
图 37. Reset Time Delay with No Capacitor Over
Temperature
600
500
400
300
200
100
0
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
25°C
-40°C
125°C
25°C
-40°C
125°C
0
0.01 0.02
0.05 0.1 0.2 0.3 0.5
Capacitor (µF)
1
2
3 4 567 10
0.01
0.02 0.03 0.050.07 0.1
0.2 0.3
Capacitor Value (µF)
0.5 0.7
1
Dela
Dela
图 38. Reset Time Delay vs Capacitor Value (Data Taken
图 39. Reset Time Delay vs Small Capacitor Values (Data
with TPS3840PL16-Q1)
Taken with TPS3840PL16-Q1)
5
17.25
25°C
-40°C
125°C
DL49
PL49
PH49
17
16.75
16.5
16.25
16
4.5
4
3.5
3
2.5
2
15.75
15.5
15.25
15
1.5
1
0.5
14.75
1
2
3
4
Capacitor Value (µF)
5
6
7
8
9 10
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Dela
TPHL
图 40. Reset Time Delay vs Large Capacitor Values (Data
图 41. Propagation Detect Time Delay for VDD Falling Below
Taken with TPS3840PL16-Q1)
VIT- (High-to-Low) Over Temperature
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ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
Typical Characteristics (接下页)
Typical characteristics show the typical performance of the TPS3840-Q1 device. Test conditions are TJ = 25°C, VDD = 3.3 V,
Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
465
460
455
450
445
440
435
430
425
420
415
3.55
3.5
DL49
PL49
PH49
DL49
PL49
PH49
3.45
3.4
3.35
3.3
3.25
3.2
3.15
3.1
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
MR_r
MRde
图 42. Propagation Time Delay from MR Asserted to Reset
图 43. Propagation Time Delay from MR Release to
Over Temperature
Deasserted Reset Over Temperature
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8 Detailed Description
8.1 Overview
The TPS3840-Q1 is a family of wide VDD and nano-quiescent current voltage detectors with fixed threshold
voltage. TPS3840-Q1 features include programable reset time delay using external capacitor, active-low manual
reset, 1% typical monitor threshold accuracy with hysteresis and glitch immunity.
Fixed negative threshold voltages (VIT-) can be factory set from 1.6 V to 4.9 V (see 表 3 for available options).
TPS3840-Q1 is available in SOT-23 5 pin industry standard package.
8.2 Functional Block Diagram
VDD
Push-Pull variants
VDD
RMR
VDD
MR / NC
RESET
RESET
RCT
Subreg
Voltage
Divider
+
VDD
œ
VREF
GND
GND
CT / NC
Copyright © 2019, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Input Voltage (VDD)
VDD pin is monitored by the internal comparator to indicate when VDD falls below the fixed threshold voltage.
VDD also functions as the supply for the internal bandgap, internal regulator, state machine, buffers and other
control logic blocks. Good design practice involve placing a 0.1 uF to 1 uF bypass capacitor at VDD input for
noisy applications to ensure enough charge is available for the device to power up correctly.
16
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TPS3840-Q1
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Feature Description (接下页)
8.3.1.1 VDD Hysteresis
The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD
pin falls below VIT- the output reset is asserted. When the voltage at the VDD pin goes above VIT- plus hysteresis
(VHYS) the output reset is deasserted after tD delay.
Hystersis Width
Hystersis Width
RESET
RESET
VIT-
VIT-
VIT+
VIT+
VDD
VDD
图 44. Hysteresis Diagram
8.3.1.2 VDD Transient Immunity
The TPS3840-Q1 is immune to quick voltage transients or excursion on VDD. Sensitivity to transients depends
on both pulse duration and overdrive. Overdrive is defined by how much VDD deviates from the specified
threshold. Threshold overdrive is calculated as a percent of the threshold in question, as shown in 公式 1.
Overdrive = | (VDD / VIT- – 1) × 100% |
(1)
VDD
VIT+
VIT-
Overdrive
Pulse
Duration
图 45. Overdrive vs Pulse Duration
8.3.2 User-Programmable Reset Time Delay
The reset time delay can be set to a minimum value of 50 µs by leaving the CT pin floating, or a maximum value
of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (tD) can be programmed
by connecting a capacitor no larger than 10 µF between CT pin and GND.
The relationship between external capacitor (CCT_EXT) in F at CT pin and the time delay (tD) in seconds is given
by 公式 2.
tD = -ln (0.29) x RCT x CCT_EXT + tD (no cap)
(2)
(3)
(4)
公式 2 is simplified to 公式 3 by plugging RCT and tD(no cap) given in Electrical Characteristics section:
tD = 618937 x CCT_EXT + 50 µs
公式 4 solves for external capacitor value (CCT_EXT) in units of F where tD is in units of seconds
CCT_EXT = (tD- 50 µs) ÷ 618937
The reset delay varies according to three variables: the external capacitor variance (CCT), CT pin internal
resistance (RCT) provided in the Electrical Characteristics table, and a constant. The minimum and maximum
variance due to the constant is shown in Equation 5 and Equation 6.
s tD (minimum) = -ln (0.36) x RCT (min) x CCT (min) + tD (no cap, min)
tD (maximum) = -ln (0.26) x RCT (max) x CCT (max) + tD (no cap, max)
(5)
(6)
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Feature Description (接下页)
The recommended maximum delay capacitor for the TPS3840 is limited to 10 µF as this ensures there is enough
time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the
previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before
the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above zero and
the reset delay will be shorter than expected. Larger delay capacitors can be used so long as the capacitor has
enough time to fully discharge during the duration of the voltage fault.
8.3.3 Manual Reset (MR) Input
The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR
with pulse duration longer than tMR_RES will causes reset output to assert. After MR returns to a logic high (VMR_H
)
and VDD is above VIT+, reset is deasserted after the user programmed reset time delay (tD) expires.
If MR is not controlled externally, then MR can be left disconnected. If the logic signal controlling MR is less than
VDD, then additional current flows from VDD into MR internally. For minimum current consumption, drive MR to
either VDD or GND. VMR must not be higher than VDD voltage.
VDD
VIT+
VHYS
VIT-
VIT+
VHYS
VIT-
RESET
tP_HL
tD
tMR_tD
tMR_RES
MR
VMR_H
VMR_L
Reset not asserted
tMR_PW
Pulse width less than tMR_PW
图 46. Timing Diagram MR and RESET (TPS3840DL-Q1)
8.3.4 Output Logic
8.3.4.1 RESET Output, Active-Low
RESET (Active-Low) applies to TPS3840DL-Q1 (Open-Drain) and TPS3840PL-Q1 (Push-Pull) hence the "L" in
the device name. RESET remains high (deasserted) as long as VDD is above the negative threshold (VIT-) and
the MR pin is floating or above VMR_H. If VDD falls below the negative threshold (VIT-) or if MR is driven low, then
RESET is asserted.
When MR is again logic high or floating and VDD rise above VIT+, the delay circuit will hold RESET low for the
specified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to logic high
voltage (VOH).
The TPS3840DL-Q1 (Open-Drain) version, denoted with "D" in the device name, requires a pull-up resistor to
hold RESET pin high. Connect the pull-up resistor to the desired pull-up voltage source and RESET can be
pulled up to any voltage up to 10 V independent of the VDD voltage. To ensure proper voltage levels, give some
consideration when choosing the pull-up resistor values. The pull-up resistor value determines the actual VOL, the
output capacitive loading, and the output leakage current (ILKG(OD)).
The Push-Pull variants (TPS3840PL and TPS3840PH), denoted with "P" in the device name, does not require a
pull-up resistor.
18
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TPS3840-Q1
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Feature Description (接下页)
8.3.4.2 RESET Output, Active-High
RESET (active-high), denoted with no bar above the pin label, applies only to TPS3840PH-Q1 push-pull active-
high version. RESET remains low (deasserted) as long as VDD is above the threshold (VIT-) and the manual
reset signal (MR) is logic high or floating. If VDD falls below the negative threshold (VIT-) or if MR is driven low,
then RESET is asserted driving the RESET pin to high voltage (VOH).
When MR is again logic high and VDD is above VIT+ the delay circuit will hold RESET high for the specified reset
time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to low voltage (VOL ).
8.4 Device Functional Modes
表 1 summarizes the various functional modes of the device. Logic high is represented by "H" and logic low is
represented by "L".
表 1. Truth Table
VDD
VDD < VPOR
VPOR < VDD < VIT-
VDD ≥ VIT-
MR
Ignored
Ignored
L
RESET
RESET
Undefined
Undefined
(1)
H
H
L
L
L
VDD ≥ VIT-
H
H
H
VDD ≥ VIT-
Floating
L
(1) When VDD falls below VDD(MIN), undervoltage-lockout (UVLO) takes effect and output reset is held asserted until VDD falls below VPOR
.
8.4.1 Normal Operation (VDD > VDD(min)
)
When VDD is greater than VDD(min), the reset signal is determined by the voltage on the VDD pin with respect to
the trip point (VIT-) and the logic state of MR.
•
•
MR high: the reset signal corresponds to VDD with respect to the threshold voltage.
MR low: in this mode, the reset is asserted regardless of the threshold voltage.
8.4.2 VDD Between VPOR and VDD(min)
When the voltage on VDD is less than the VDD(min) voltage, and greater than the power-on-reset voltage (VPOR),
the reset signal is asserted.
8.4.3 Below Power-On-Reset (VDD < VPOR
)
When the voltage on VDD is lower than VPOR, the device does not have enough bias voltage to internally pull the
asserted output low or high and reset voltage level is undefined.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.2 Typical Application
9.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
A typical application for the TPS3840-Q1 is voltage rail monitoring and power-up sequencing as shown in 图 47.
The TPS3840-Q1 can be used to monitor any rail above 1.6 V. In this design application, two TPS3840-Q1
devices monitor two separate voltage rails and sequences the rails upon power-up. The TPS3840PL30-Q1 is
used to monitor the 3.3-V main power rail and the TPS3840DL16-Q1 is used to monitor the 1.8-V rail provided by
the LDO for other system peripherals. The RESET output of the TPS3840PL30-Q1 is connected to the ENABLE
input of the LDO. A reset event is initiated on either voltage supervisor when the VDD voltage is less than VIT- or
when MR is driven low by an external source.
LDO
VDD
EN
1.8 V
3.3V
1 µF
1 µF
VI/O
VCORE
10kΩ
Microcontroller
VDD
VDD
RESET
RESET
MR
RESET
MR
TPS3840PL30
CT GND
TPS3840DL16
CT
NC
GND
0.047µF
图 47. TPS3840-Q1 Voltage Rail Monitor and Power-Up Sequencer Design Block Diagram
9.2.1.1 Design Requirements
This design requires voltage supervision on two separate rails: 3.3-V and 1.8-V rails. The voltage rail needs to
sequence upon power up with the 3.3-V rail coming up first followed by the 1.8-V rail at least 25 ms after.
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Two TPS3840-Q1 devices provide voltage monitoring with 1%
accuracy with device options available in 0.1 V variations
Two Rail Voltage Supervision
Monitor 3.3-V and 1.8-V rails
Power up the 3.3-V rail first followed
by 1.8-V rail 25 ms after
The CT capacitor on TPS38240PL28 is set to 0.047 µF for a
reset time delay of 29 ms typical
Voltage Rail Sequencing
Output logic voltage
3.3-V Open-Drain
3.3-V Open-Drain
Maximum device current
consumption
1 µA
Each TPS3840-Q1 requires 350 nA typical
20
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ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
9.2.1.2 Detailed Design Procedure
The primary constraint for this application is choosing the correct device to monitor the supply voltage of the
microprocessor. The TPS3840-Q1 can monitor any voltage between 1.6 V and 10 V and is available in 0.1 V
increments. Depending on how far away from the nominal voltage rail the user wants the voltage supervisor to
trigger determines the correct voltage supervisor variant to choose. In this example, the first TPS3840-Q1
triggers when the 3.3-V rail falls to 3.0 V. The second TPS3840-Q1 triggers a reset when the 1.8-V rail falls to
1.6 V. The secondary constraint for this application is the reset time delay that must be at least 25 ms to allow
the microprocessor, and all other devices using the 3.3-V rail, enough time to startup correctly before the 1.8-V
rail is enabled via the LDO. Because a minimum time is required, the user must account for capacitor tolerance.
For applications with ambient temperatures ranging from –40°C to +125°C, CCT can be calculated using RCT and
solving for CCT in 公式 2. Solving 公式 2 for 25 ms gives a minimum capacitor value of 0.04 µF which is rounded
up to a standard value 0.047 µF to account for capacitor tolerance.
A 1-µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor
is only required for the Open-Drain device variants and is calculated to maintain the RESET current within the ±5
mA limit found in the Recommended Operating Conditions: RPull-up = VPull-up ÷ 5 mA. For this design, a standard
10-kΩ pull-up resistor is selected to minimize current draw when RESET is asserted. Keep in mind the lower the
pull-up resistor, the higher VOL. The MR pin can be connected to an external signal if desired or left floating if not
used due to the internal pull-up resistor to VDD.
9.2.1.3 Application Curves
VDD
30ms delay from VDD (3.3V) to LDO Enable set by 0.047µF on CT of TPS3840PL30
RESET
(LDO Enable)
VOUT (LDO)
Negligible delay from LDO Enable to 1.8V VOUT
图 48. Startup Sequence Highlighting the Delay Between 3.3V and 1.8V Rails
版权 © 2019, Texas Instruments Incorporated
21
TPS3840-Q1
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
www.ti.com.cn
9.2.2 Design 2: Automotive Off-Battery Monitoring
The initial power stage in automotive applications starts with the 12 V battery. Variation of the battery voltage is
common between 9 V and 16 V. Furthermore, If cold-cranking and load dump conditions are considered, voltage
transients can occur as low as 3 V and as high as 42V. In this design example, we are highlighting the ability for
low power , direct off-battery voltage supervision. 图 49 illustrates an example of how the TPS3840-Q1 is
monitoring the battery voltage while being powered by it as well. For more information, read this application
report on how to achieve nano-amp IQ voltage supervision in automotive, wide-vin applications.
图 49. Fast Start Undervoltage Supervisor with Level-Shifted Input
22
版权 © 2019, Texas Instruments Incorporated
TPS3840-Q1
www.ti.com.cn
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
9.2.2.1 Design Requirements
This design requires voltage supervision on a 12-V power supply voltage rail with possibility of the 12-V rail rising
up as high as 42 V. The undervoltage fault occurs when the power supply voltage drops below 7.7 V.
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
TPS3840-Q1 provides voltage monitoring with 1%
accuracy with device options available in 0.1 V
variations. Resistor dividers are calculated based
on device variant and desired threshold voltage.
Monitor 12-V power supply for undervoltage
condition, trigger a undervoltage fault at 7.7 V.
Power Rail Voltage Supervision
The TPS3840-Q1 limits VDD to 10 V but can
monitor voltages higher than the maximum VDD
voltage with the use of an external resistor divider.
Maximum Input Power
Output logic voltage
Operate with power supply input up to 42 V.
Open-Drain Output Topology
Due to large variance in battery voltage, an open-
drain output is recommended to provide the correct
reset signal.
TPS3840-Q1 requires 350 nA (typical) and the
external resistor divider will also consume current.
There is a tradeoff between current consumption
and voltage monitor accuracy but generally set the
resistor divider to consume 100 times current into
VDD.
Maximum system current
consumption
35 uA when power supply is at 12 V typical
The TPS3840-Q1 has 1% typical voltage monitor
accuracy. By decreasing the ratio of resistor
values, the resistor divider will consume more
current but the accuracy will increase. The resistor
tolerance also needs to be accounted for.
Voltage Monitor Accuracy
Typical voltage monitor accuracy of 2.5%.
Delay when returning from fault
condition
RESET delay of at least 200 ms when returning
from a undervoltage fault.
CCT = 0.33 µF sets 204 ms delay
9.2.2.2 Detailed Design Procedure
The primary constraint for this application is monitoring a 12-V rail while preventing the VDD pin on TPS3840-Q1
from exceeding the recommended maximum of 10 V. This is accomplished by sizing the resistor divider so that
when the 12-V rail drops to 7.7 V, the VDD pin for TPS3840-Q1 will be at 1.6 V which is the VIT- threshold for
triggering a undervoltage condition for TPS3840DL16-Q1 as shown in 公式 7. Reasonably sized resistors were
selected for the voltage divider. While selecting lower resistor values may increase current, this allows for
additional accuracy from the resistor divider.
Vrail_trigger = VIT- x (R2 ÷ (R1 + R2))
(7)
where Vrail_trigger is the trigger voltage of the rail being monitored, VIT- is the falling threshold on the VDD pin of
TPS3840, and R1 and R2 are the top and bottom resistors of the external resistor divider. VIT- is fixed per device
variant and is 1.6 V for TPS3840DL16-Q1. Substituting in the values from 图 49, the undervoltage trigger
threshold for the rail is set to 7.7 V. Given that R1 = 100 kΩ, R2 = 26.2 kΩ.
Because the undervoltage trigger of 10 V on the rail corresponds to 1.6 V undervoltage threshold trigger of the
TPS3840-Q1 device, there is room for the rail to rise up while maintaining less than 10 V on the VDD pin of the
TPS3840-Q1. 公式 8 shows the maximum rail voltage that still meets the 10 V maximum at the VDD pin for
TPS3840-Q1.
Vrail_max = 10 V x (26.2 kΩ ÷ (100 kΩ + 26.2 kΩ)) = 48.168 V
(8)
This means the monitored voltage rail can go as high as 48.168 V and not violate the recommended maximum
for the VDD pin on TPS3840-Q1. This is useful when monitoring a voltage rail that has a wide range that may go
much higher than the nominal rail voltage such as in this case. Notice that the resistor values chosen are less
than 100kΩ to preserve the accuracy set by the internal resistor divider. Good design practice recommends using
a 0.1-µF capacitor on the VDD pin and this capacitance may need to increase when using an external resistor
divider.
版权 © 2019, Texas Instruments Incorporated
23
TPS3840-Q1
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
www.ti.com.cn
9.2.2.3 Application Curves: TPS3840EVM
These application curves are taken with the TPS3840EVM using the TPS3840-Q1. Please see the TPS3840EVM
User Guide for more information. The scope of the test below was to ensure that normal operation was
maintained under typical cold crank and load dump conditions. This was verified by observing the input changing
to its minimum and maximum value and the output remained both defined and accurate.
图 50. TPS3840-Q1 Warm-Start Test Pulse
图 51. TPS3840-Q1 Cold-Start Test Pulse
图 52. TPS3840-Q1 Cold Crank Test Pulse
图 53. TPS3840-Q1 Load Dump Test Pulse
24
版权 © 2019, Texas Instruments Incorporated
TPS3840-Q1
www.ti.com.cn
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.5 V and 10 V. TI
recommends an input supply capacitor between the VDD pin and GND pin. This device has a 12-V absolute
maximum rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage
transient that can exceed 12 V, additional precautions must be taken.
11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends
placing a minimum 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected
to the CT pin, then minimize parasitic capacitance on this pin so the rest time delay is not adversely affected.
•
•
•
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
>0.1-µF ceramic capacitor as near as possible to the VDD pin.
If a CCT capacitor is used, place these components as close as possible to the CT pin. If the CT pin is left
unconnected, make sure to minimize the amount of parasitic capacitance on the pin to <5 pF.
Place the pull-up resistors on RESET pin as close to the pin as possible.
11.2 Layout Example
The layout example in shows how the TPS3840-Q1 is laid out on a printed circuit board (PCB) with a user-
defined delay.
Pull-up resistor required for Open-Drain
(TPS3840DLXX) only
CT
RESET
CCT
Rpull-up
VDD
GND
CIN
MR
VDD
GND
Vias used to connect pins for application-specific connections
图 54. TPS3840-Q1 Recommended Layout
版权 © 2019, Texas Instruments Incorporated
25
TPS3840-Q1
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
www.ti.com.cn
12 器件和文档支持
12.1 器件命名规则
表 2 显示了如何根据器件型号来解译器件的功能。
表 2. 器件命名约定
说明
命名规则
值
工程原型预发布样片
器件型号
P
工程原型样片
TPS3840
TPS3840-Q1
型号代码(输出拓扑)
DL
漏极开路,低电平有效
推挽,高电平有效
推挽,低电平有效
示例:16 表示 1.6V 阈值
SOT23-5
PH
PL
检测电压选项
封装
##(两个字符)
DBV
R
卷带
大卷带
汽车后缀
Q1
表示器件符合 AEC-Q100 标准
表 3 显示了 TPS3840-Q1 的可能型号。有关所显示的其他选项的详细信息和供货情况,请联系德州仪器 (TI);最
低订购量适用。
表 3. 器件阈值
产品
电压阈值 (VIT-
典型值 (V)
1.6
)
迟滞 (VHYST
典型值 (V)
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.100
0.200
0.200
0.200
0.200
0.200
0.200
0.200
0.200
0.200
0.200
0.200
0.200
)
漏极开路,低电平有效
TPS3840DL16-Q1
推挽,低电平有效
推挽,高电平有效
TPS3840PH16-Q1
TPS3840PL16-Q1
TPS3840DL17-Q1
TPS3840DL18-Q1
TPS3840DL19-Q1
TPS3840DL20-Q1
TPS3840DL21-Q1
TPS3840DL22-Q1
TPS3840DL23-Q1
TPS3840DL24-Q1
TPS3840DL25-Q1
TPS3840DL26-Q1
TPS3840DL27-Q1
TPS3840DL28-Q1
TPS3840DL29-Q1
TPS3840DL30-Q1
TPS3840DL31-Q1
TPS3840DL32-Q1
TPS3840DL33-Q1
TPS3840DL34-Q1
TPS3840DL35-Q1
TPS3840DL36-Q1
TPS3840DL37-Q1
TPS3840DL38-Q1
TPS3840DL39-Q1
TPS3840DL40-Q1
TPS3840DL41-Q1
TPS3840DL42-Q1
TPS3840PL17-Q1
TPS3840PL18-Q1
TPS3840PL19-Q1
TPS3840PL20-Q1
TPS3840PL21-Q1
TPS3840PL22-Q1
TPS3840PL23-Q1
TPS3840PL24-Q1
TPS3840PL25-Q1
TPS3840PL26-Q1
TPS3840PL27-Q1
TPS3840PL28-Q1
TPS3840PL29-Q1
TPS3840PL30-Q1
TPS3840PL31-Q1
TPS3840PL32-Q1
TPS3840PL33-Q1
TPS3840PL34-Q1
TPS3840PL35-Q1
TPS3840PL36-Q1
TPS3840PL37-Q1
TPS3840PL38-Q1
TPS3840PL39-Q1
TPS3840PL40-Q1
TPS3840PL41-Q1
TPS3840PL42-Q1
TPS3840PH17-Q1
TPS3840PH18-Q1
TPS3840PH19-Q1
TPS3840PH20-Q1
TPS3840PH21-Q1
TPS3840PH22-Q1
TPS3840PH23-Q1
TPS3840PH24-Q1
TPS3840PH25-Q1
TPS3840PH26-Q1
TPS3840PH27-Q1
TPS3840PH28-Q1
TPS3840PH29-Q1
TPS3840PH30-Q1
TPS3840PH31-Q1
TPS3840PH32-Q1
TPS3840PH33-Q1
TPS3840PH34-Q1
TPS3840PH35-Q1
TPS3840PH36-Q1
TPS3840PH37-Q1
TPS3840PH38-Q1
TPS3840PH39-Q1
TPS3840PH40-Q1
TPS3840PH41-Q1
TPS3840PH42-Q1
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
26
版权 © 2019, Texas Instruments Incorporated
TPS3840-Q1
www.ti.com.cn
ZHCSJM9A –APRIL 2019–REVISED SEPTEMBER 2019
表 3. 器件阈值 (接下页)
产品
推挽,低电平有效
TPS3840PL43-Q1
电压阈值 (VIT-
)
迟滞 (VHYST
典型值 (V)
0.200
)
漏极开路,低电平有效
推挽,高电平有效
TPS3840PH43-Q1
典型值 (V)
4.3
TPS3840DL43-Q1
TPS3840DL44-Q1
TPS3840DL45-Q1
TPS3840DL46-Q1
TPS3840DL47-Q1
TPS3840DL48-Q1
TPS3840DL49-Q1
TPS3840PL44-Q1
TPS3840PL45-Q1
TPS3840PL46-Q1
TPS3840PL47-Q1
TPS3840PL48-Q1
TPS3840PL49-Q1
TPS3840PH44-Q1
TPS3840PH45-Q1
TPS3840PH46-Q1
TPS3840PH47-Q1
TPS3840PH48-Q1
TPS3840PH49-Q1
4.4
0.200
4.5
0.200
4.6
0.200
4.7
0.200
4.8
0.200
4.9
0.200
12.2 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
25-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3840DL16DBVRQ1
TPS3840DL18DBVRQ1
TPS3840DL20DBVRQ1
TPS3840DL25DBVRQ1
TPS3840DL28DBVRQ1
TPS3840DL29DBVRQ1
TPS3840DL30DBVRQ1
TPS3840DL31DBVRQ1
TPS3840DL32DBVRQ1
TPS3840DL37DBVRQ1
TPS3840DL40DBVRQ1
TPS3840DL41DBVRQ1
TPS3840DL42DBVRQ1
TPS3840DL44DBVRQ1
TPS3840DL45DBVRQ1
TPS3840DL46DBVRQ1
TPS3840DL47DBVRQ1
TPS3840PH27DBVRQ1
TPS3840PH30DBVRQ1
TPS3840PL16DBVRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DQ16
DQ18
DQ20
DQ25
DQ28
DQ29
DQ30
DQ31
DQ32
DQ37
DQ40
DQ41
DQ42
DQ44
DQ45
DQ46
DQ47
QH27
QH30
QL16
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Dec-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3840PL25DBVRQ1
TPS3840PL28DBVRQ1
TPS3840PL29DBVRQ1
TPS3840PL30DBVRQ1
TPS3840PL31DBVRQ1
TPS3840PL40DBVRQ1
TPS3840PL43DBVRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
QL25
QL28
QL29
QL30
QL31
QL40
QL43
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Dec-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3840-Q1 :
Catalog : TPS3840
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3840DL16DBVRQ1 SOT-23
TPS3840DL18DBVRQ1 SOT-23
TPS3840DL20DBVRQ1 SOT-23
TPS3840DL25DBVRQ1 SOT-23
TPS3840DL28DBVRQ1 SOT-23
TPS3840DL29DBVRQ1 SOT-23
TPS3840DL30DBVRQ1 SOT-23
TPS3840DL31DBVRQ1 SOT-23
TPS3840DL32DBVRQ1 SOT-23
TPS3840DL37DBVRQ1 SOT-23
TPS3840DL40DBVRQ1 SOT-23
TPS3840DL41DBVRQ1 SOT-23
TPS3840DL42DBVRQ1 SOT-23
TPS3840DL44DBVRQ1 SOT-23
TPS3840DL45DBVRQ1 SOT-23
TPS3840DL46DBVRQ1 SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3840PH27DBVRQ1 SOT-23
TPS3840PH30DBVRQ1 SOT-23
TPS3840PL16DBVRQ1 SOT-23
TPS3840PL25DBVRQ1 SOT-23
TPS3840PL28DBVRQ1 SOT-23
TPS3840PL29DBVRQ1 SOT-23
TPS3840PL30DBVRQ1 SOT-23
TPS3840PL31DBVRQ1 SOT-23
TPS3840PL43DBVRQ1 SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3840DL16DBVRQ1
TPS3840DL18DBVRQ1
TPS3840DL20DBVRQ1
TPS3840DL25DBVRQ1
TPS3840DL28DBVRQ1
TPS3840DL29DBVRQ1
TPS3840DL30DBVRQ1
TPS3840DL31DBVRQ1
TPS3840DL32DBVRQ1
TPS3840DL37DBVRQ1
TPS3840DL40DBVRQ1
TPS3840DL41DBVRQ1
TPS3840DL42DBVRQ1
TPS3840DL44DBVRQ1
TPS3840DL45DBVRQ1
TPS3840DL46DBVRQ1
TPS3840PH27DBVRQ1
TPS3840PH30DBVRQ1
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS3840PL16DBVRQ1
TPS3840PL25DBVRQ1
TPS3840PL28DBVRQ1
TPS3840PL29DBVRQ1
TPS3840PL30DBVRQ1
TPS3840PL31DBVRQ1
TPS3840PL43DBVRQ1
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 4
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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