TPS3435 [TI]
纳安级静态电流精密看门狗计时器;
| 型号： | TPS3435 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 纳安级静态电流精密看门狗计时器 |
| 文件： | 总33页 (文件大小：1693K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS3435
ZHCSRF8 –DECEMBER 2022
TPS3435 具有精密超时看门狗计时器的毫微级IQ
1 特性
3 说明
• 出厂编程或用户可编程的看门狗超时
– ±10% 精确计时器（最大值）
– 出厂编程：1 毫秒至100 秒
• 出厂编程或用户可编程的复位延迟
– ±10% 精确计时器（最大值）
– 出厂编程选项：2 毫秒至10 秒
• 输入电压范围：VDD = 1.04 V 至6.0 V
• 超低电源电流：IDD = 250nA（典型值）
• 开漏、推挽；低电平有效输出
• 各种可编程选项：
TPS3435 是一款超低功耗（典型值为 250nA）器件，
可提供具有可编程超时看门狗计时器的。
TPS3435 可提供具有多种功能的高精度超时看门狗计
时器，广泛适用于各种应用。该超时看门狗计时器可以
进行出厂编程或由用户使用外部电容器进行编程。计时
器值可以使用逻辑引脚的组合来动态更改。可以使用专
用引脚或计时器扩展引脚的组合来启用或禁用看门狗功
能。该器件还提供启动延迟选项，可在主机上电后立即
禁用看门狗监控并保持固定时间。
WDO 延迟可设定为出厂编程的默认延迟设置或通过外
部电容器进行编程。该器件还提供锁存输出操作，看门
狗故障清除之前会锁存输出。
– 看门狗启用/禁用
– 看门狗启动延迟：无延迟至10 秒
– 动态计时器扩展：1X 至256X
– 锁存输出选项
TPS3435 提供了 TPS3431 器件系列的性能升级替代
产品。TPS3435 采用小型 6 引脚 WSON 和 8 引脚
SOT23 封装。
• MR 功能支持
2 应用
器件信息
• 机器人伺服驱动器
• 混合模块（AI、AO、DI、DO）
• HVAC 控制器
• 电表
封装(1)
DDF (8)
DSE (6) (2)
封装尺寸（标称值）
2.90mm × 1.60mm
1.50mm x 1.50mm
器件型号
TPS3435
TPS3435
• 输液泵
• 外科手术设备
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 预发布封装。
10
Supply
Device lot 1
Device lot 2
Device lot 3
VDD
MR
VDD
5
0
WDO
RESET / NMI
µC
TPS3435
WDI
GPIO
GPIO
CRST
CWD
WD-EN
-5
SET[0:1]
GPIO
GND
GND
GND
-10
-40
TPS3435 offers various pinout options to support different features.
Choose suitable pinout based on application needs
-7
26
59
92
125
Ambient Temperature (C)
典型应用电路
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSCF7
TPS3435
ZHCSRF8 –DECEMBER 2022
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Table of Contents
8.2 Functional Block Diagrams....................................... 14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................21
9 Application and Implementation..................................22
9.1 Application Information............................................. 22
9.2 Typical Applications.................................................. 23
10 Power Supply Recommendations..............................24
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 接收文档更新通知................................................... 26
12.2 支持资源..................................................................26
12.3 Trademarks.............................................................27
12.4 Electrostatic Discharge Caution..............................27
12.5 术语表..................................................................... 27
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 器件比较............................................................................ 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics ............................................8
7.6 Timing Requirements .................................................9
7.7 Switching Characteristics .........................................10
7.8 Timing Diagrams....................................................... 11
7.9 Typical Characteristics..............................................12
8 详细说明.......................................................................... 14
8.1 Overview...................................................................14
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2022
*
Initial Release
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5 器件比较
图5-1 显示了TPS3435 的器件命名规则。对于所有可能的输出类型、看门狗时间选项和输出断言延迟选项，请参
阅节8 了解更多详细信息。有关其他选项的详细信息和可用性，请联系TI 销售代码或访问TI 的E2E 论坛。
TPS3435 X X X X X XXX X
Tape/Reel
R: Reel
T: Tape
Pinout Op on
Package
DDF: SOT23-8
DSE: WSON-6
A
B
C
J
Output
K
Assert Time
A: External
Capacitor
B: 2 msec
C: 10 msec
D: 25 msec
E: 50 msec
F: 100 msec
G: 200 msec
H: 1 sec
Output Topology,
Watchdog
Watchdog
Time
Startup Delay
A: DL, No Delay
B: DL, 200 msec
C: DL, 500 msec
D: DL, 1 sec
Time Scaling
A: 1, 2, 4
B: 1, 4 , 8
A: External
Capacitor
B: 1 msec
C: 5 msec
D: 10 msec
E: 20 msec
F: 50 msec
G: 100 msec
H: 200 msec
I: 1 sec
J = 1.4 sec
K = 1.6 sec
L = 10 sec
M = 50 sec
N = 100 sec
C: 1, 8, 16
D: 1, 16, 32
E: 1, 32, 64
F: 1, 64, 128
G: 1, 128, 256
E: DL, 5 sec
F: DL, 10 sec
G: PL, No Delay
H: PL, 200 msec
I: PL, 500 msec
J: PL, 1 sec
I: 10 sec
J = Latched
output
K: PL, 5 sec
L: PL, 10 sec
Refer ‘Mechanical, Packaging and Orderable Informa on’ sec on for list of released orderable.
For any other orderable, contact local TI support.
图5-1. 器件命名规则
TPS3435 属于引脚兼容的器件系列，提供了不同的功能集，详见表5-1。
表5-1. 引脚兼容的器件系列
器件
电压监控器
看门狗类型
TPS35
Timeout
是
是
否
否
TPS36
窗口
TPS3435
TPS3436
Timeout
窗口
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6 Pin Configuration and Functions
8
7
VDD
8
7
VDD
SET0
CWD
1
2
1
2
MR
CWD
WDO
WDO
CRST
GND
3
6
5
WDI
CRST
GND
3
6
5
WDI
4
SET0
4
SET1
Not to scale
Not to scale
图6-1. Pin Configuration Option A
DDF Package, 8-Pin SOT-23,
TPS3435 Top View
图6-2. Pin Configuration Option B
DDF Package, 8-Pin SOT-23,
TPS3435 Top View
VDD
SET0
WD_EN
WDI
1
2
6
5
8
7
VDD
SET0
MR
1
2
WDO
WDO
3
4
GND
WDI
3
6
5
WD-EN
SET1
Not to scale
GND
4
图6-4. Pin Configuration Option J
DSE Package, 6-Pin WSON,
TPS3435 Top View
Not to scale
图6-3. Pin Configuration Option C
DDF Package, 8-Pin SOT-23,
TPS3435 Top View
VDD
CWD
CRST
WDI
1
2
6
5
WDO
3
4
GND
Not to scale
图6-5. Pin Configuration Option K
DSE Package, 6-Pin WSON,
TPS3435 Top View
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PIN
表6-1. Pin Functions
PIN NUMBER
I/O
DESCRIPTION
PINOUT PINOUT PINOUT PINOUT PINOUT
NAME
A
B
C
J
K
Programmable WDO assert time pin. Connect a capacitor between
this pin and GND to program the WDO assert time period. See 节
8.3.3 for more details.
CRST
3
3
2
I
I
—
—
Programmable watchdog timeout input. Watchdog timeout is set by
connecting a capacitor between this pin and ground. See 节8.3.1.1
for more details.
CWD
2
2
1
—
—
GND
MR
4
1
4
4
2
4
4
Ground pin
—
Manual reset pin. A logic low on this pin asserts the WDO output.
See 节8.3.2 for more details.
I
—
—
—
Watchdog output. Connect WDO to VDD using pull up resistance
when using open drain output. WDO is asserted when a watchdog
error occurs or MR pin is driven LOW. See 节8.3.3 for more details.
WDO
SET0
SET1
7
5
7
1
5
7
1
5
5
1
5
O
I
Logic input. SET0, SET1, and WD-EN pins select the watchdog timer
scaling and enable-disable the watchdog; see 节8.3.1.4 for more
details.
—
—
Logic input. SET0, SET1, and WD-EN pins select the watchdog timer
scaling and enable-disable the watchdog; see 节8.3.1.4 for more
details.
I
—
—
Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass
capacitor is recommended.
VDD
8
8
8
6
6
2
6
I
I
Logic input. Logic high input enables the watchdog monitoring
feature. See 节8.3.1.2 for more details.
WD-EN
—
—
—
Watchdog input. A falling transition (edge) must occur at this pin
before the timeout expires in order for WDO to not assert. See 节
8.3.1 for more details.
WDI
6
6
3
3
3
I
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted(1)
MIN
–0.3
–0.3
–0.3
–20
–40
–65
MAX
6.5
UNIT
Voltage
Voltage
VDD
V
VDD+0.3 (3)
6.5
CWD, CRST, WD–EN, SETx, WDI, MR (2), WDO (Push Pull)
V
WDO (Open Drain)
WDO pin
Current
20
mA
℃
Temperature (4)
Temperature (4)
Operating ambient temperature, TA
Storage, Tstg
125
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
(3) The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller
(4) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
± 2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
± 750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.9
0
NOM
MAX
6
UNIT
VDD (Active Low output)
CWD, CRST, WD–EN, SETx, WDI, MR (1)
WDO(Open Drain)
VDD
6
Voltage
V
0
WDO (Push Pull)
0
VDD
5
Current
CRST
CWD
TA
WDO pin current
mA
nF
nF
–5
1.5
1.5
–40
CRST pin capacitor range
CWD pin capacitor range
Operating ambient temperature
1800
1000
125
℃
(1) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
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7.4 Thermal Information
TPS3435
THERMAL METRIC(1)
DDF (SOT23-8)
8 PINS
175.3
94.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
92.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.4
ψJT
91.9
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At 1.04 V ≤VDD ≤6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩto VDD, output load (CLOAD) = 10 pF and over
operating free-air temperature range –40℃to 125℃, unless otherwise noted. VDD ramp rate ≤1 V/µs. Typical values are
at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
VDD
IDD
Input supply voltage
Active LOW output
1.04
6
0.8
3
V
0.25
0.25
TA = –40℃to 85℃
Supply current into VDD pin (1)
µA
Low level input voltage WD–EN, WDI,
VIL
0.3VDD
V
SETx, MR (1)
High level input voltage WD–EN, WDI,
VIH
0.7VDD
V
SETx, MR (1)
RMR
Manual reset internal pull-up resistance
100
kΩ
WDO (Open-drain active-low)
VDD =1.5 V
IOUT(Sink) = 500 µA
300
300
Low level output voltage
VOL
mV
VDD = 3.3 V
IOUT(Sink) = 2 mA
VDD = VPULLUP = 6V
TA = –40℃to 85℃
10
10
30
60
nA
nA
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6V
WDO (Push-pull active-low)
VOH(min) = 0.8 VDD
Iout (source) = 15 µA
VPOR
Power on WDO voltage (2)
900
300
300
mV
mV
VDD = 1.5 V
IOUT(Sink) = 500 µA
Low level output voltage
High level output voltage
VOL
VDD = 3.3 V
IOUT(Sink) = 2 mA
VDD = 1.8 V
IOUT(Source) = 500 µA
0.8VDD
0.8VDD
0.8VDD
VDD = 3.3 V
IOUT(Source) = 500 µA
VOH
V
VDD = 6 V
IOUT(Source) = 2 mA
(1) If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
(2) VPOR is the minimum VDD voltage level for a controlled output state
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7.6 Timing Requirements
At 1.04 V ≤VDD ≤6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩto VDD, output RESET / WDO load (CLOAD) =
10 pF and over operating free-air temperature range –40℃to 125℃, unless otherwise noted. VDD ramp rate ≤1 V/µs.
Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tMR_PW
tP-WD
MR pin pulse duration to assert output
WDI pulse duration to start next frame (1)
100
ns
500
200
ns
WD–EN hold time to enable or disable WD
tHD-WDEN
tHD-SETx
µs
µs
operation (1)
SETx hold time to change WD timer setting
150
(1)
Orderable Option TPS3435xxB
Orderable Option TPS3435xxC
Orderable Option TPS3435xxD
Orderable Option TPS3435xxE
Orderable Option TPS3435xxF
Orderable Option TPS3435xxG
Orderable Option TPS3435xxH
Orderable Option TPS3435xxI
Orderable Option TPS3435xxJ
Orderable Option TPS3435xxK
Orderable Option TPS3435xxL
Orderable Option TPS3435xxM
Orderable Option TPS3435xxN
0.8
4
1
5
1.2
6
9
10
11
18
20
22
ms
45
50
55
90
100
200
1
110
220
1.1
1.54
1.76
11
tWD
Watchdog timeout period
180
0.9
1.26
1.44
9
1.4
1.6
10
s
45
50
55
90
100
110
(1) Not production tested
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7.7 Switching Characteristics
At 1.04 V ≤VDD ≤6 V, MR = Open, WDO pull-up resistor (Rpull-up) = 100 kΩto VDD, output RESET / WDO load (CLOAD) =
10 pF and over operating free-air temperature range –40℃to 125℃, unless otherwise noted. VDD ramp rate ≤1 V/µs.
Typical values are at TA = 25℃
PARAMETER
Startup delay (1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSTRT
500
µs
Orderable part number
TPS3435xA, TPS3435xG
0
200
500
1
Orderable part number
TPS3435xB, TPS3435xH
180
450
0.9
4.5
9
220
550
1.1
5.5
11
ms
Orderable part number
TPS3435xC, TPS3435xI
tSD
Watchdog startup delay
Orderable part number
TPS3435xD, TPS3435xJ
Orderable part number
TPS3435xE, TPS3435xK
5
s
Orderable part number
TPS3435xF, TPS3435xL
10
2
Orderable part number
TPS3435xxxxB
1.6
9
2.4
11
ms
ms
ms
ms
ms
ms
s
Orderable part number
TPS3435xxxxC
10
25
50
100
200
1
Orderable part number
TPS3435xxxxD
22.5
45
27.5
55
Orderable part number
TPS3435xxxxE
tWDO
Watchdog assert time delay
Orderable part number
TPS3435xxxxF
90
110
220
1.1
11
Orderable part number
TPS3435xxxxG
180
0.9
9
Orderable part number
TPS3435xxxxH
Orderable part number
TPS3435xxxxI
10
100
s
Propagation delay from MR low to WDO
assertion
VDD ≥1.25 V,
MR = VMR_H to VMR_L
tMR_WDO
ns
(1) Specified by design parameter.
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7.8 Timing Diagrams
VDDMIN
VDD
tSTRT
tSTRT
VPOR
ttSD
t
ttSD
t
ttSD
t
ttWD
t
ttWD
t
ttWD
t
ttWDO
t
WDO
tP-WD
Ignore
Ignore
WDI
Ignore
图7-1. Functional Timing Diagram
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7.9 Typical Characteristics
all curves are taken at TA = 25°C (unless otherwise noted)
10
60
48
36
24
12
0
Device lot 1
Device lot 2
Device lot 3
5
0
-5
-10
-40
-7
26
59
92
125
-5
-4
-3
-2
-1
0
1
2
3
4
5
Ambient Temperature (C)
Time Accuracy (%)
图7-2. Timer Accuracy vs Temperature
图7-3. Timer Accuracy Histogram
10
8
10
8
TA = 25C
TA = 125C
TA = −40C
6
6
4
4
2
2
TA = 25C
TA = 125C
TA = −40C
0
0
200
400
600
800
1000
0
CWD Capacitance (nF)
0
300
600
900
1200
1500
1800
CRST capacitance (nF)
图7-4. tWD vs Capacitance
图7-5. tWDO vs Capacitance
1
0.5
0.4
0.3
0.2
0.1
0
TA = −40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
TA = −40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
0.8
0.6
0.4
0.2
0
1
2
3
4
5
1
2
3
4
5
Sink current (mA)
Sink current (mA)
图7-6. WDO VOL vs I sink, VDD = 1.5 V
图7-7. WDO VOL vs I sink, VDD = 3.3 V
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2
6
5.6
5.2
4.8
4.4
4
1.6
1.2
0.8
0.4
TA = −40C
TA = 0C
TA = 85C
TA = −40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
TA = 125C
TA = 25C
0
1
2
3
4
5
1
2
3
4
5
Source current (mA)
Source current (mA)
图7-8. WDO VOH vs I source, VDD = 2.0 V
图7-9. WDO VOH vs I source, VDD = 6.0 V
图7-10. Supply Current vs Power-Supply Voltage
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8 详细说明
8.1 Overview
The TPS3435 is a high-accuracy timeout watchdog timer device. The device family supports multiple features
related to watchdog operation in a compact 6 pin WSON and 8 pin SOT23 package. The devices are available in
5 different pinout configurations. Each pinout offers access to different features to meet the various application
requirements.
8.2 Functional Block Diagrams
VDD
WDO
WDO
Logic
MR
Oscillator
Capacitance
Detection
Watchdog Timer
Logic
GND
CRST
CWD
WDI
SET0
图8-1. Pinout Option A
VDD
WDO
WDO
Logic
Oscillator
Capacitance
Detection
Watchdog Timer
Logic
GND
CRST
CWD
WDI
SET1
SET0
图8-2. Pinout Option B
VDD
WDO
WDO
Logic
MR
Oscillator
Watchdog Timer
Logic
GND
WDI
SET0 SET1 WD-EN
图8-3. Pinout Option C
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VDD
WDO
WDO
Logic
Oscillator
Watchdog Timer
Logic
GND
WD_EN
WDI
SET0
图8-4. Pinout Option J
VDD
WDO
WDO
Logic
Oscillator
Capacitance
Detection
Watchdog Timer
Logic
GND
CRST
CWD
WDI
图8-5. Pinout Option K
8.3 Feature Description
8.3.1 Timeout Watchdog Timer
The TPS3435 offers high precision timeout watchdog timer monitoring. The device is available in multiple pinout
options A to K which support multiple features to meet ever expanding needs of various applications. Ensure a
correct pinout is selected to meet the application needs.
The timeout watchdog is active when the VDD voltage is higher than the VDDMIN, MR voltage is held higher than
0.7 x VDD and watchdog is enabled. TPS3435 family offers various startup time delay options to ensure enough
time is available for the host to complete boot operation. Please refer 节8.3.1.3 for additional details.
The timeout watchdog timer monitors the WDI pin for falling edge in the time frame defined by tWD time period.
Refer 节 8.3.1.1 section to arrive at the relevant tWD value needed for application. The timer value is reset when
a valid falling edge is detected on WDI pin in the tWD time duration. When a valid WDI transition is not detected
in tWD time, the device asserts WDO output. The WDO is asserted for time tWDO. Refer 节 8.3.3 to arrive at the
relevant tWDO value needed for application.
图 8-6 shows the basic operation for timeout watchdog timer operation. The TPS3435 watchdog functionality
supports multiple features. Details are available in following sub sections.
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tP-WD
ttWD
t
ttWD
t
ttSD
t
tWD
ttWDO
t
ttWD
t
WDO
WDI
Ignore
图8-6. Timeout Watchdog Timer Operation
8.3.1.1 tWD Timer
The tWD timer for TPS3435 can be set using an external capacitor connected between CWD pin and GND pin.
This feature is available with pinout options A or B or K. Applications which are space constrained or need timer
values which meet offered timer options, can benefit when using pinout options C or J. The TPS3435 offers
multiple fixed timer options ranging from 1 msec up-to 100 sec.
The TPS3435, when using capacitance based timer, senses the capacitance value during the power up. The
capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance
value. The sensed value is used to arrive at tWD timer for the watchdog operation. This unique implementation
helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current
consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor
functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique
implementation of TPS3435 helps avoid the dead time as the capacitance is not continuously charging or
discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. 方程
式 1 highlights the relationship between tWD in second and CWD capacitance in farad. The tWD timer is 20%
accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWD time. Ensure
the capacitance meets the recommended operating range. Capacitance outside the recommended range can
lead to incorrect operation of the device.
tWD (sec) = 4.95 x 106 x CCWD (F)
(1)
The TPS3435 also offers wide selection of high accuracy fixed timer options starting from 1 msec to 100 sec
including various industry standard values. The TPS3435 fixed time options are ±10% accurate for tWD ≥ 10
msec. For tWD < 10 msec, the accuracy is ±20%. tWD value relevant to application can be identified from the
orderable part number. Refer 节5 section to identify mapping of orderable part number to tWD value.
The TPS3435 offers flexibility to change the tWD value on the fly by controlling the logic levels on the SETx pins.
节 8.3.1.4 section explains the advantages offered by this feature and the device behavior with various SETx pin
combinations.
8.3.1.2 Watchdog Enable Disable Operation
The TPS3435 supports watchdog enable or disable functionality. This functionality is critical for different use
cases as listed below.
• Disable watchdog during firmware update to avoid host RESET.
• Disable watchdog during software step-by-step debug operation.
• Disable watchdog when performing critical task to avoid watchdog error interrupt.
• Keep watchdog disabled until host boots up.
The TPS3435 supports watchdog enable or disable functionality through either WD-EN pin or SET[1:0] = 0b'01
logic combination or by keeping WDI pin in the floating state. For a given pinout only one of these three methods
is available for the user to disable watchdog operation.
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For a pinout which offers a WD-EN pin, the watchdog enable disable functionality is controlled by the logic state
of WD-EN pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable the watchdog
operation. The WD-EN pin can be toggled any time during the device operation. The 图 8-7 diagram shows
timing behavior with WD-EN pin control.
VPOR
tWD
VDD
ttWD
t
WD-EN
ttWD
t
WDO
WDI
ttWDO
t
Ignore
Ignore
图8-7. Watchdog Enable: WD-EN Pin Control
SET[1:0] = 0b'01 combination can be used to disable watchdog operation with a pinout which offers SET1 and
SET0 pins, but does not include WD-EN pin. The SET pin logic states can be changed at any time during
watchdog operation. Refer 节8.3.1.4 section for additional details regarding SET[1:0] pin behavior.
A pinout which does not offer WD-EN or SET[1:0] pins uses WDI float pin status to disable the watchdog
operation. Users can float the WDI pin during normal operation to disable the watchdog. To enable watchdog,
drive the WDI pin and apply a valid edge to trigger the watchdog. It is recommended to drive HIGH and then
LOW when exiting the WDI float state.
Pinout options A, B, K offer watchdog timer control using a capacitance connected between CWD and GND pin.
A capacitance value higher than recommended or connect to GND leads to watchdog functionality getting
disabled. Note, capacitance value is detected and latched during start-up or after an error event. Changing
capacitance on the fly does not enable or disable watchdog operation. A power supply recycle is needed to
detect change in capacitance.
When watchdog is disabled the ongoing frame will be terminated and WDO will stay deasserted. When enabled
the device will immediately enter tWD frame and start watchdog monitoring operation.
8.3.1.3 tSD Watchdog Start Up Delay
The TPS3435 supports watchdog startup delay feature. This feature is activated after power up or after WDO
assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted.
This feature allows time for the host complete boot process before watchdog monitoring can take over. The start
up delay helps avoid unexpected WDO assert events during boot. The tSD time is predetermined based on the
device part number selected. Refer 节 5 section for details to map the part number to tSD time. Pinout option A,
B, K are available only in no delay or 10 sec start up delay options.
The tSD frame is complete when the time duration selected for tSD is over or host provides a valid transition on
the WDI pin. The host must provide a valid transition on the WDI pin during tSD time. The device exits the tSD
frame and enters watchdog monitoring phase after valid WDI transition. Failure to provide valid transition on WDI
pin triggers the watchdog error by asserting the WDO output pin.
The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin or
WDI float functionality as described in 节8.3.1.2 section.
图8-8 diagram shows the operation for tSD time frame.
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VDDMIN
VDD
VPOR
tSTRT
ttSD
t
ttWD
t
ttSD
t
ttWD
t
ttWDO
t
WDO
WDI
Ignore
Ignore
图8-8. tSD Frame Behavior
8.3.1.4 SET Pin Behavior
The TPS3435 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the
user to program the tWD timer on the fly to meet various application requirements. Typical use cases where SET
pin can be used are:
• Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is
operational. Watchdog can be used to wake up the host after long duration to perform the application related
activities before going back to sleep.
• Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not
interrupt the critical task. Change timer to application specified interval after the critical task is complete.
The tWD timer value for the device is combination of timer selection based on the CWD pin or fixed timer value
along with SET pin logic level. The base tWD timer value is decided based on the Watchdog Time selector in the
节5 section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed
any time during the operation. SETx pin change which leads to change of watchdog timer value or enable
disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO
output is asserted as well. The updated tWD timer value will be applied after output is deasserted and the tSD
timer is over or terminated.
For a pinout which offers only SET0 pin to the user, the tWD multiplier value is decided based on the Watchdog
Time Scaling selector in the 节 5 section. 表 8-1 showcases an example of the tWD values for different SET0
logic levels when using Watchdog Time setting as option D = 10 msec.
表8-1. tWD Scaling with SET0 Pin Only
tWD
WATCHDOG TIME SCALING SELECTION
SET0 = 0
10 msec
10 msec
10 msec
10 msec
10 msec
10 msec
10 msec
SET0 = 1
20 msec
A
B
C
D
E
F
40 msec
80 msec
160 msec
320 msec
640 msec
1280 msec
G
For pinouts which offer both SET0 & SET1 pins to the user, the tWD multiplier value is decided based on the
Watchdog Time Scaling selector in the 节 5 section. Two SETx pins offer 3 different time scaling options. The
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SET[1:0] = 0b'01 combination disables the watchdog operation. 表 8-2 showcases an example of the tWD values
for different SET[1:0] logic levels when using Watchdog Time setting as option G = 100 msec. The package pin
out selected does not offer WD-EN pin.
表8-2. tWD Scaling with SET0 & SET1 Pins, WD-EN Pin Not Available
tWD
WATCHDOG TIME
SCALING SELECTION
SET[1:0] = 0b'00
100 msec
100 msec
100 msec
100 msec
100 msec
100 msec
100 msec
SET[1:0] = 0b'01
Watchdog disable
Watchdog disable
Watchdog disable
Watchdog disable
Watchdog disable
Watchdog disable
Watchdog disable
SET[1:0] = 0b'10
200 msec
SET[1:0] = 0b'11
400 msec
A
B
C
D
E
F
400 msec
800 msec
800 msec
1600 msec
3200 msec
6400 msec
12800 msec
25600 msec
1600 msec
3200 msec
6400 msec
12800 msec
G
Selected pinout option can offer WD-EN pin along with SET[1:0] pins. With this pinout, the WD-EN pin controls
watchdog enable and disable operation. The SET[1:0] = 0b'01 combination operates as SET[1:0] = 0b'00.
Make sure the tWD value with SETx multiplier does not exceed 640 sec. If a selection of timer and multiplier
results in tWD > 640 sec, the timer value will be restricted to 640 sec.
图8-9 to 图8-11 diagrams show the timing behavior with respect to SETx status changes.
WD_EN = 1
WD multiplier = n
ttWD X nt
WD multiplier = m
WD multiplier = 1
SETx
ttWD X mt
ttWD
t
ttWD
t
ttWD X nt
ttWD X mt
ttWD
t
WDO
WDI
图8-9. Watchdog Behavior with SETx Pin Status
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SET Pin (2 Pins) Operation; WD_EN Pin Not Available
00 = WD multiplier = 1
01 = WD Disabled
10 = WD multiplier = n
11 = WD multiplier = m
SET[1:0]
tWD
WD Disabled
tWD X n
tWD X m
WD time value
SET Pin (2 Pins) Operation; WD_EN Available = 1
SET[1:0]
00 or 01 = WD multiplier = 1
10 = WD multiplier = n
tWD X n
11 = WD multiplier = m
tWD X m
tWD
WD time value
tWD = Fixed based on OPN or programmable using capacitor
n,m = Fixed based on timeset multiplier chosen
图8-10. Watchdog Operation with 2 SET Pins
SET0
1 = WD multiplier = n
tWD X n
0 = WD multiplier = 1
1 = WD multiplier = n
tWD X n
0 = WD multiplier = 1
WD time
value
tWD
tWD
tWD = Fixed based on OPN or programmable using capacitor
n = Fixed based on timeset multiplier chosen
图8-11. Watchdog Operation with 1 SET Pin
8.3.2 Manual RESET
The TPS3435 supports manual reset functionality using MR pin. MR pin when driven with voltage lower than 0.3
x VDD, asserts the WDO output. The MR pin has 100 kΩ pull up to VDD. The MR pin can be left floating. The
internal pull up will ensure the output is not asserted due to MR pin trigger.
The output is deasserted after MR pin voltage rises above 0.7 x VDD voltage. Refer 图8-12 for more details.
0.7 x VDD
MR
0.3 x VDD
tP-HL
ttSD
t
WDO
图8-12. MR Pin Response
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8.3.3 WDO Output
The TPS3435 device offers WDO output pin. WDO output is asserted when MR pin voltage is lower than 0.3 X
VDD or watchdog timer error is detected.
The output will be asserted for tWDO time when any relevant events described above are detected, except for MR
event. The time tWDO can be programmed by connecting a capacitor between CRST pin and GND or device will
assert tWDO for fixed time duration as selected by orderable part number. Refer 节 5 section for all available
options.
方程式 2 describes the relationship between capacitor value and the time tWDO. Ensure the capacitance meets
the recommended operating range. Capacitance outside the recommended range can lead to incorrect
operation of the device.
tWDO (sec) = 4.95 x 106 x CCRST (F)
(2)
TPS3435 also offers a unique option of latched output. An orderable with latched output will hold the output in
asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is
latched due to MR pin low voltage, the output latch will be released when MR pin voltage rises above 0.7 x VDD
level. If the output is latched due to watchdog timer error, the output latch will be released when a WDI negative
edge is detected or the device is shutdown and powered up again.
8.4 Device Functional Modes
表8-3 summarizes the functional modes of the TPS3435.
表8-3. Device Functional Modes
VDD
Watchdog Status
Not Applicable
Not Applicable
Disabled
WDI
WDO
Undefined
High
VDD < VPOR
—
Ignored
V
POR ≤VDD < VDDmin
Ignored
High
Enabled
tpulse (1) < tWD(min)
tpulse (1) > tWD(max)
High
VDD ≥VDDmin
Enabled
Low
(1) Where tpulse is the time between falling edges on WDI.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail proper device implementation, depending on the final application
requirements.
9.1.1 Output Assert Delay
The TPS3435 features two options for setting the output assert delay (tWDO): using a fixed timing and
programming the timing through an external capacitor.
9.1.1.1 Factory-Programmed Output Assert Delay Timing
Fixed output assert delay timings are available using pinout C and J. Using these timings enables a high-
precision, 10% accurate output assert delay timing.
9.1.1.2 Adjustable Capacitor Timing
The TPS3435 also utilizes a programmable output assert delay, using a precision current source to charge an
external capacitor upon device startup. By monitoring the voltage on the CRST pin, the TPS3435 can be
programmed to have a desired output assert delay. The typical delay time resulting from a given external
capacitance on the CRST pin can be calculated by 方程式 3, where tWDO is the output assert delay time in
seconds and CCRST is the capacitance in microfarads.
tWDO (sec) = 4.95 × 106 × CCRST (F)
(3)
Note that in order to minimize the difference between the calculated output assert delay time and the actual
output assert delay time, use a high-quality ceramic dielectric COG, X5R, or X7R capacitor and minimize
parasitic board capacitance around this pin. 表 9-1 lists the output assert delay time ideal capacitor values for
CCRST
.
表9-1. Output Assert Delay Time for Common Ideal Capacitor Values
OUTPUT ASSERT
DELAY TIME (tWDO
)
CCRST
UNIT
MIN(1)
39.6
TYP
MAX(1)
10 nF
100 nF
1 μF
49.5
59.4
ms
ms
ms
396
495
594
3960
4950
5940
(1) Minimum and maximum values are calculated using ideal capacitors.
9.1.2 Watchdog Timer Functionality
The TPS3435 features two options for setting the watchdog timer (tWD): using a fixed timing and programming
the timing through an external capacitor.
9.1.2.1 Factory-Programmed Timing Options
Fixed watchdog timeout options are available using pinout C and J. Using these timings enables a high-
precision, 10% accurate watchdog timer tWD
.
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9.1.2.2 Adjustable Capacitor Timing
Adjustable tWD timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please
consult 方程式 1 for calculating typical tWD values using ideal capacitors. Capacitor tolerances cause the actual
device timing to vary such that the minimum of tWD can decrease and the maximum of tWD can increase by the
capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material.
9.2 Typical Applications
9.2.1 Design 1: Monitoring a Standard Microcontroller for Timeouts
This example application uses the TPS3435CDDBBDDFR to monitor a microcontroller to ensure it is not stalled
during operation.
3.3V
V
TPS3435
CC
SET1
SET0
WD-EN
MR
VDD
WDO
WDI
Microcontroller
RESET
GPIO
GND
GND
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图9-1. Microcontroller Watchdog Monitoring Circuit
9.2.1.1 Design Requirements
PARAMETER
Watchdog Timeout Period
Watchdog Output Assert Delay
Startup Delay
DESIGN REQUIREMENT
Typical timeout period of 40 ms
DESIGN RESULT
Typical timeout period of 40 ms
Typical output assert of 2 ms
Minimum startup delay of 900 ms
Open-drain
Typical output assert of 2 ms
Minimum startup delay of 700 ms
Open-drain
Output logic voltage
Maximum device current
consumption
250 nA typical, 3.0 μA maximum(1)
20 µA
(1) Only includes the current consumption of the TPS3435.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Setting the Watchdog Timeout Period
The watchdog timeout design requirement can be met either by using a fixed-timeout version of the TPS3435 or
by connecting a capacitor between the CWD pin and GND. The typical values can be met with preprogrammed
fixed time options, hence a pinout offering fixed time options is selected. Please see the 节 7.6 for a list of fixed
timeouts. If using the CWD feature, please refer to 节 8.3.1.1 for instructions on how to program the timout
period. In this application example, the 40 ms timeout watchdog period is achieved by using watchdog time of
10ms (option D) and watchdog time scaling of 4 (option B). Connect SET[1:0] = 0b'10 to select watchdog time
scaling of 4.
9.2.1.2.2 Setting Output Assert Delay
Please see the 节 7.7 for a list of fixed timeouts. Timeout option B was chosen in order to meet the design
requirement for a 2 ms typical timeout.
9.2.1.2.3 Setting the Startup Delay
Startup delay option D is chosen, which offers a startup delay of 1 s. This accounts for the minimum specification
of 700 ms.
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9.2.1.2.4 Calculating the WDO Pullup Resistor
The TPS3435 uses an open-drain configuration for the WDO output, as shown in 图 9-2. When the FET is off,
the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to
ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL
is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in
mind: the pullup voltage (VPU), the recommended maximum WDO pin current (ISink), and VOL. The maximum VOL
is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin
below 0.3 V with ISink kept below 2 mA for VDD ≥3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU
=VDD = 1.5 V, a resistor must be chosen to keep ISink below 500 μA because this value is the maximum
consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected,
which sinks a maximum of 150 μA when WDO is asserted.
VDD
WDO
WDO
CONTROL
图9-2. Open-Drain WDO Configuration
9.2.1.3 Application Curves
图9-3. Typical WDI Pulse
图9-4. Watchdog Timeout Fault
10 Power Supply Recommendations
This device is designed to operate from an input supply with a voltage range between 1.04 V and 6.5 V. An input
supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is
to place a 0.1-µF capacitor between the VDD pin and the GND pin.
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11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends
placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the
CRST pin, then minimize parasitic capacitance on this pin so the WDO delay time is not adversely affected.
• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
• Place CCRST capacitor as close as possible to the CRST pin.
• Place CCWD capacitor as close as possible to the CWD pin.
• Place the pullup resistor on the WDO pin as close to the pin as possible.
11.2 Layout Example
TPS3435
8
7
VDD
SET0
MR
1
2
WDO
WDI
3
6
5
WD-EN
SET1
GND
4
Not to scale
图11-1. Typical Layout for the TPS3435
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
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12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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27
Product Folder Links: TPS3435
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS3435CAIEGDDFR
TPS3435CAKAGDDFR
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDF
DDF
8
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
NLHOG
NLHOA
Samples
Samples
NIPDAU
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2023
OTHER QUALIFIED VERSIONS OF TPS3435 :
Automotive : TPS3435-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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