TPS2835PWPRG4 [TI]
SYNCHRONOUS-BUCK MOSFET DRIVERS WITH DEAD-TIME CONTROL; 同步降压MOSFET和死区时间控制驱动器
| 型号： | TPS2835PWPRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS-BUCK MOSFET DRIVERS WITH DEAD-TIME CONTROL |
| 文件： | 总23页 (文件大小：988K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ
ꢂꢉ ꢊꢋꢌꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏꢋꢒ ꢓ ꢎꢂ ꢔꢕ ꢀ ꢖ ꢍꢗ ꢘ ꢕꢍ ꢂ
ꢙ ꢗꢀ ꢌ ꢖꢕꢚ ꢖꢐꢀ ꢗꢓ ꢕ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
D PACKAGE
(TOP VIEW)
D
Floating Bootstrap or Ground-Reference
High-Side Driver
D
D
D
D
D
D
D
Adaptive Dead-Time Control
1
2
3
4
5
6
7
14
13
12
11
10
9
ENABLE
IN
CROWBAR
NC
BOOT
NC
HIGHDR
BOOTLO
LOWDR
NC
50-ns Max Rise/Fall Times With 3.3-nF Load
2.4-A Typical Output Current
4.5-V to 15-V Supply Voltage Range
TTL-Compatible Inputs
SYNC
DT
PGND
8
V
Internal Schottky Bootstrap Diode
CC
SYNC Control for Synchronous or
Nonsynchronous Operation
PWP PACKAGE
(TOP VIEW)
D
CROWBAR for OVP, Protects Against
Faulted High-Side Power FETs
1
2
3
4
5
6
7
14
13
12
11
10
9
ENABLE
IN
CROWBAR
NC
BOOT
NC
HIGHDR
BOOTLO
LOWDR
NC
D
Low Supply Current....3 mA Typical
D
Ideal for High-Current Single or Multiphase
Power Supplies
Thermal
Pad
SYNC
DT
PGND
D
D
−40°C to 125°C Operating Virtual Junction
Temperature Range
8
V
CC
Available in SOIC and TSSOP PowerPAD
Packages
NC − No internal connection
description
The TPS2834 and TPS2835 are MOSFET drivers for synchronous-buck power stages. These devices are ideal
for designing a high-performance power supply using switching controllers that do not include on-chip MOSFET
drivers. The drivers are designed to deliver minimum 2-A peak currents into large capacitive loads. The
high-side driver can be configured as ground-reference or as floating-bootstrap. An adaptive dead-time control
circuit eliminates shoot-through currents through the main power FETs during switching transitions, and
provides high efficiency for the buck regulator. The TPS2834 and TPS2835 have additional control functions:
ENABLE, SYNC, and CROWBAR. Both high-side and low-side drivers are off when ENABLE is low. The driver
is configured as a nonsynchronous-buck driver disabling the low-side driver when SYNC is low. The CROWBAR
function turns on the low-side power FET, overriding the IN signal, for overvoltage protection against faulted
high-side power FETs.
The TPS2834 has a noninverting input, while the TPS2835 has an inverting input. These drivers are available
in 14-terminal SOIC and thermally enhanced TSSOP PowerPAD packages and operate over a junction
temperature range of −40°C to 125°C.
Related Synchronous MOSFET Drivers
DEVICE NAME
TPS2830
TPS2831
TPS2832
TPS2833
TPS2836
TPS2837
ADDITIONAL FEATURES
INPUTS
Noninverted
ENABLE, SYNC, and CROWBAR
CMOS
CMOS
TTL
Inverted
Noninverted
Inverted
W/O ENABLE, SYNC, and CROWBAR
W/O ENABLE, SYNC, and CROWBAR
Noninverted
Inverted
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
ꢁ
ꢁ
ꢍ
ꢎ
ꢫ
ꢖ
ꢦ
ꢏ
ꢋ
ꢤ
ꢀ
ꢥ
ꢗ
ꢟ
ꢎ
ꢝ
ꢊ
ꢞ
ꢖ
ꢚ
ꢀ
ꢚ
ꢜ
ꢝ
ꢧ
ꢞ
ꢟ
ꢥ
ꢠ
ꢡ
ꢢ
ꢢ
ꢣ
ꢣ
ꢜ
ꢜ
ꢟ
ꢟ
ꢝ
ꢝ
ꢜ
ꢤ
ꢤ
ꢨ
ꢥ
ꢦ
ꢠ
ꢠ
ꢧ
ꢧ
ꢝ
ꢣ
ꢢ
ꢡ
ꢤ
ꢤ
ꢟ
ꢞ
ꢨ
ꢀꢧ
ꢦ
ꢩ
ꢤ
ꢪ
ꢜ
ꢥ
ꢢ
ꢤ
ꢣ
ꢜ
ꢣ
ꢟ
ꢠ
ꢝ
ꢦ
ꢫ
ꢢ
ꢝ
ꢣ
ꢣ
ꢧ
ꢤ
ꢬ
Copyright 2002, Texas Instruments Incorporated
ꢠ
ꢟ
ꢥ
ꢣ
ꢟ
ꢠ
ꢡ
ꢣ
ꢟ
ꢤ
ꢨ
ꢜ
ꢞ
ꢜ
ꢥ
ꢧ
ꢠ
ꢣ
ꢭ
ꢣ
ꢧ
ꢠ
ꢟ
ꢞ
ꢮ
ꢢ
ꢗ
ꢝ
ꢡ
ꢧ
ꢤ
ꢣ
ꢢ
ꢝ
ꢫ
ꢢ
ꢠ
ꢫ
ꢯ
ꢢ
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ
ꢠ
ꢠ
ꢢ
ꢝ
ꢣ
ꢰ
ꢬ
ꢁ
ꢠ
ꢟ
ꢫ
ꢦ
ꢥ
ꢣ
ꢜ
ꢟ
ꢝ
ꢨ
ꢠ
ꢟ
ꢥ
ꢧ
ꢤ
ꢤ
ꢜ
ꢝ
ꢱ
ꢫ
ꢟ
ꢧ
ꢤ
ꢝ
ꢟ
ꢣ
ꢝ
ꢧ
ꢥ
ꢧ
ꢤ
ꢤ
ꢢ
ꢠ
ꢜ
ꢪ
ꢰ
ꢜ
ꢝ
ꢥ
ꢪ
ꢦ
ꢫ
ꢧ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈ
ꢂ ꢉꢊꢋ ꢌ ꢍ ꢎꢊꢎꢏ ꢂꢐꢑ ꢏꢋꢒ ꢓꢎ ꢂ ꢔꢕ ꢀ ꢖꢍ ꢗ ꢘꢕ ꢍꢂ
ꢙꢗ ꢀ ꢌ ꢖ ꢕꢚ ꢖꢐ ꢀ ꢗꢓ ꢕ ꢋꢎ ꢊꢀ ꢍꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
AVAILABLE OPTIONS
PACKAGED DEVICES
T
J
SOIC
(D)
TSSOP
(PWP)
TPS2834D
TPS2835D
TPS2834PWP
TPS2835PWP
− 40°C to 125°C
The D and PWP packages are available taped and reeled. Add R
suffix to device type (e.g., TPS2834DR)
functional block diagram
8
V
CC
14
BOOT
1 MΩ
(TPS2834 Only)
12
11
HIGHDR
BOOTLO
250 kΩ
2
IN
V
CC
(TPS2835 Only)
10
LOWDR
PGND
250 kΩ
7
6
DT
1
5
3
ENABLE
SYNC
CROWBAR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ
ꢂꢉ ꢊꢋꢌꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏꢋꢒ ꢓ ꢎꢂ ꢔꢕ ꢀ ꢖ ꢍꢗ ꢘ ꢕꢍ ꢂ
ꢙ ꢗꢀ ꢌ ꢖꢕꢚ ꢖꢐꢀ ꢗꢓ ꢕ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
Terminal Functions
TERMINAL
NAME NO.
BOOT
I/O
DESCRIPTION
14
I
Bootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTLO to develop the floating
bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 µF and 1 µF.
BOOTLO
11
3
O
I
This terminal connects to the junction of the high-side and low-side MOSFETs.
CROWBAR
CROWBAR can to be driven by an external OVP circuit to protect against a short across the high-side
MOSFET. If CROWBAR is driven low, the low-side driver will be turned on and the high-side driver will be
turned off, independent of the status of all other control terminals.
DT
6
I
I
Dead-time control terminal. Connect DT to the junction of the high-side and low-side MOSFETs.
If ENABLE is low, both drivers are off.
ENABLE
HIGHDR
IN
1
12
O
I
Output drive for the high-side power MOSFET
2
Input signal to the MOSFET drivers (noninverting input for the TPS2834; inverting input for the TPS2835).
Output drive for the low-side power MOSFET
LOWDR
NC
10
O
4, 9, 13
No internal connection
PGND
SYNC
7
5
Power ground. Connect to the FET power ground.
I
I
Synchronous rectifier enable terminal. If SYNC is low, the low-side driver is always off; If SYNC is high, the
low-side driver provides gate drive to the low-side MOSFET.
V
CC
8
Input supply. Recommended that a 1-µF capacitor be connected from V to PGND.
CC
detailed description
low-side driver
The low-side driver is designed to drive low r
source and sink.
N-channel MOSFETs. The current rating of the driver is 2 A,
N-channel MOSFETs. The current rating of the driver is 2 A,
DS(on)
high-side driver
The high-side driver is designed to drive low r
DS(on)
source and sink. The high-side driver can be configured as a GND-reference driver or as a floating bootstrap
driver. The internal bootstrap diode is a Schottky, for improved drive efficiency. The maximum voltage that can
be applied from BOOT to ground is 30 V.
dead-time (DT) control
Dead-time control prevents shoot-through current from flowing through the main power FETs during switching
transitions by controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn
on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until
the voltage at the junction of the power FETs (Vdrain) is low; the TTL-compatible DT terminal connects to the
junction of the power FETs.
ENABLE
The ENABLE terminal enables the drivers. When enable is low, the output drivers are low. ENABLE is a
TTL-compatible digital terminal.
IN
The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The TPS2834
has a noninverting input; the TPS2835 has an inverting input.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈ
ꢂ ꢉꢊꢋ ꢌ ꢍ ꢎꢊꢎꢏ ꢂꢐꢑ ꢏꢋꢒ ꢓꢎ ꢂ ꢔꢕ ꢀ ꢖꢍ ꢗ ꢘꢕ ꢍꢂ
ꢙ
ꢗ
ꢀ
ꢌ
ꢖ
ꢕ
ꢚ
ꢖ
ꢐ
ꢀ
ꢗ
ꢓ
ꢕ
ꢋ
ꢎ
ꢊ
ꢀ
ꢍ
ꢎ
ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
detailed description (continued)
SYNC
The SYNC terminal controls whether the drivers operate in synchronous or nonsynchronous mode. In
synchronous mode, the low-side FET is operated as a synchronous rectifier. In nonsynchronous mode, the
low-side FET is always off. SYNC is a TTL-compatible digital terminal.
CROWBAR
The CROWBAR terminal overrides the normal operation of the driver. When CROWBAR is low, the low-side
FET turns on to act as a clamp, protecting the output voltage of the dc/dc converter against overvoltages due
to a short across the high-side FET. V should be fused to protect the low-side FET. CROWBAR is a
IN
TTL-compatible digital terminal.
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
CC
Input voltage range:BOOT to PGND (high-side driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V
BOOTLO to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
ENABLE, SYNC, and CROWBAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V
DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to PGND.
DISSIPATION RATING TABLE
PACKAGE
T
A
≤ 25°C
DERATING FACTOR
26.68 mW/°C
T
A
= 70°C
T = 85°C
A
‡
PWP with solder
2668
1024
749
1467
563
1067
409
‡
PWP without solder
10.24 mW/°C
D
7.49 mW/°C
412
300
JUNCTION-CASE THERMAL RESISTANCE TABLE
PWP
Junction-case thermal resistance
2.07 °C/W
‡
Test Board Conditions:
1. Thickness: 0.062I
2. 3I × 3I (for packages <27 mm long)
3. 4I × 4I (for packages >27 mm long)
4. 2-oz copper traces located on the top of the board (0.071 mm thick)
5. Copper areas located on the top and bottom of the PCB for soldering
6. Power and ground planes, 1-oz copper (0.036 mm thick)
7. Thermal vias, 0.33 mm diameter, 1.5 mm pitch
8. Thermal isolation of power plane
For more information, refer to TI technical brief literature number SLMA002.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ
ꢂꢉ ꢊꢋꢌꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏꢋꢒ ꢓ ꢎꢂ ꢔꢕ ꢀ ꢖ ꢍꢗ ꢘ ꢕꢍ ꢂ
ꢙ ꢗꢀ ꢌ ꢖꢕꢚ ꢖꢐꢀ ꢗꢓ ꢕ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
recommended operating conditions
MIN NOM
MAX
15
UNIT
V
Supply voltage, V
Input voltage
4.5
4.5
CC
BOOT to PGND
28
V
electrical characteristics over recommended operating virtual junction temperature range,
= 6.5 V, ENABLE = High, C = 3.3 nF (unless otherwise noted)
V
CC
L
supply current
PARAMETER
Supply voltage range
TEST CONDITIONS
MIN
TYP
MAX
15
UNIT
V
V
4.5
V
CC
V
V
V
= LOW,
= HIGH,
= HIGH,
V
V
V
=15 V
=15 V
=12 V,
100
400
(ENABLE)
(ENABLE)
(ENABLE)
CC
CC
CC
µA
300
3
Quiescent current
CC
f
C
= 200 kHz,
BOOTLO grounded,
C = 50 pF,
(LOWDR)
(SWX)
mA
= 50 pF,
(HIGHDR)
See Note 2
NOTE 2: Ensured by design, not production tested.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈ
ꢂ ꢉꢊꢋ ꢌ ꢍ ꢎꢊꢎꢏ ꢂꢐꢑ ꢏꢋꢒ ꢓꢎ ꢂ ꢔꢕ ꢀ ꢖꢍ ꢗ ꢘꢕ ꢍꢂ
ꢙꢗ ꢀ ꢌ ꢖ ꢕꢚ ꢖꢐ ꢀ ꢗꢓ ꢕ ꢋꢎ ꢊꢀ ꢍꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
electrical characteristics over recommended operating virtual junction temperature range,
= 6.5 V, ENABLE = High, C = 3.3 nF (unless otherwise noted) (continued)
V
CC
L
output drivers
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
– V
= 4.5 V,
= 6.5 V,
= 12 V,
= 4.5 V,
= 6.5 V,
= 12 V,
(BOOT)
(BOOTLO)
0.7
1.1
= 4 V
(HIGHDR)
Duty cycle < 2%,
V
V
– V
(BOOTLO)
= 5 V
(BOOT)
(HIGHDR)
1.1
2
1.5
2.4
1.4
1.6
2.7
High-side sink (see Note 3)
A
t
< 100 µs
pw
(see Note 2)
V
V
– V
(BOOTLO)
= 10.5 V
(BOOT)
(HIGHDR)
V
V
– V
(BOOTLO)
= 0.5V
(BOOT)
(HIGHDR)
1.2
1.3
2.3
Duty cycle < 2%,
V
V
– V
(BOOTLO)
= 1.5 V
High-side source
(see Note 3)
(BOOT)
(HIGHDR)
Peak output
current
A
t
< 100 µs
pw
(see Note 2)
V
V
– V
(BOOTLO)
= 1.5 V
(BOOT)
(HIGHDR)
V
V
V
V
V
V
= 4.5 V, V
= 4 V
1.3
2
1.8
2.5
3.5
1.7
2.4
3
CC
(LOWDR)
(LOWDR)
(LOWDR)
Duty cycle < 2%,
= 6.5 V, V
= 5 V
t
< 100 µs
Low-side sink (see Note 3)
A
A
CC
CC
CC
CC
CC
pw
(see Note 2)
= 12 V, V
= 10.5 V
= 0.5V
= 1.5 V
3
= 4.5 V, V
= 6.5 V, V
1.4
2
LOWDR))
Duty cycle < 2%,
Low-side source
(see Note 3)
t
< 100 µs
(LOWDR))
(LOWDR0)
pw
(see Note 2)
= 12 V, V
= 1.5 V
2.5
V
V
– V
= 4.5 V,
= 6.5 V,
= 12 V,
= 4.5 V,
= 6.5 V,
= 12 V,
(BOOT)
(BOOTLO)
5
5
= 0.5 V
(HIGHDR)
V
V
– V
(BOOTLO)
= 0.5 V
(BOOT)
(HIGHDR)
High-side sink (see Note 3)
Ω
Ω
V
V
– V
(BOOTLO)
= 0.5 V
(BOOT)
(HIGHDR)
5
V
V
– V
(BOOTLO)
= 4 V
(BOOT)
(HIGHDR)
75
75
75
V
V
– V
(BOOTLO)
= 6 V
(BOOT)
(HIGHDR)
Output
resistance
High-side source (see Note 3)
V
V
– V
(BOOTLO)
=11.5 V
(BOOT)
(HIGHDR)
V
V
V
V
V
V
= 4.5 V, V
= 0.5 V
9
7.5
6
(DRV)
(DRV)
(DRV)
(DRV)
(DRV)
(DRV)
(LOWDR)
= 6.5 V, V
= 0.5 V
= 0.5 V
= 4 V
Low-side sink (see Note 3)
Ω
Ω
(LOWDR)
= 12 V, V
(LOWDR)
= 4.5 V, V
= 6.5 V, V
75
75
75
(LOWDR)
Low-side source (see Note 3)
)= 6 V
(LOWDR
= 12 V, V
= 11.5 V
(LOWDR)
NOTES: 2: Ensured by design, not production tested.
3. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the r of the MOSFET transistor when
DS(on)
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ
ꢂꢉ ꢊꢋꢌꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏꢋꢒ ꢓ ꢎꢂ ꢔꢕ ꢀ ꢖ ꢍꢗ ꢘ ꢕꢍ ꢂ
ꢙ ꢗꢀ ꢌ ꢖꢕꢚ ꢖꢐꢀ ꢗꢓ ꢕ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
electrical characteristics over recommended operating virtual junction temperature range,
= 6.5 V, ENABLE = High, C = 3.3 nF (unless otherwise noted) (continued)
V
CC
L
dead-time control
PARAMETER
High-level input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
IH
V
IL
V
IH
V
IL
0.7V
CC
LOWDR
DT
Over the V
range (see Note 2)
range
V
CC
CC
Low-level input voltage
High-level input voltage
Low-level input voltage
1
1
2
V
V
Over the V
NOTE 2: Ensured by design, not production tested.
digital control terminals (IN, CROWBAR, SYNC, ENABLE)
PARAMETER
High-level input voltage
Low-level input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
2
IH
Over the V
CC
range
1
V
IL
switching characteristics over recommended operating virtual junction temperature range,
ENABLE = High, C = 3.3 nF (unless otherwise noted)
L
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
60
50
50
40
30
30
50
40
40
40
30
30
95
80
70
80
70
60
80
70
60
170
135
85
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 4.5 V,
= 6.5 V,
= 12 V,
V
V
V
= 0 V
= 0 V
= 0 V
(BOOT)
(BOOT)
(BOOT)
(BOOTLO)
(BOOTLO)
(BOOTLO)
HIGHDR output (see Note 2)
ns
Rise time
= 4.5 V
CC
CC
CC
= 6.5 V
= 12 V
LOWDR output (see Note 2)
HIGHDR output (see Note 2)
LOWDR output (see Note 2)
ns
ns
ns
ns
ns
= 4.5 V,
= 6.5 V,
= 12 V,
V
= 0 V
= 0 V
= 0 V
(BOOT)
(BOOT)
(BOOT)
(BOOTLO)
(BOOTLO)
(BOOTLO)
V
V
Fall time
= 4.5 V
CC
CC
CC
= 6.5 V
= 12 V
= 4.5 V,
= 6.5 V,
= 12 V,
= 4.5 V,
= 6.5 V,
= 12 V,
V
V
V
V
V
V
= 0 V
= 0 V
= 0 V
= 0 V
= 0 V
= 0 V
(BOOT)
(BOOT)
(BOOT)
(BOOT)
(BOOT)
(BOOT)
(BOOTLO)
(BOOTLO)
(BOOTLO)
(BOOTLO)
(BOOTLO)
(BOOTLO)
HIGHDR going low (excluding
dead time) (see Note 2)
Propagation delay time
LOWDR going high (excluding
dead time) (see Note 2)
= 4.5 V
CC
CC
CC
CC
CC
CC
LOWDR going low (excluding
dead time) (see Note 2)
= 6.5 V
Propagation delay time
Driver nonoverlap time
ns
ns
= 12 V
= 4.5 V
= 6.5 V
= 12 V
40
25
15
DT to LOWDR and LOWDR to
HIGHDR (see Note 2)
NOTE 2: Ensured by design, not production tested.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈ
ꢂ ꢉꢊꢋ ꢌ ꢍ ꢎꢊꢎꢏ ꢂꢐꢑ ꢏꢋꢒ ꢓꢎ ꢂ ꢔꢕ ꢀ ꢖꢍ ꢗ ꢘꢕ ꢍꢂ
ꢙꢗ ꢀ ꢌ ꢖ ꢕꢚ ꢖꢐ ꢀ ꢗꢓ ꢕ ꢋꢎ ꢊꢀ ꢍꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
TYPICAL CHARACTERISTICS
FALL TIME
vs
RISE TIME
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
50
45
40
50
45
40
C
T
= 3.3 nF
= 25°C
C
T
= 3.3 nF
= 25°C
L
J
L
J
High Side
Low Side
35
30
35
30
High Side
Low Side
25
20
25
20
15
10
15
10
4
5
6
7
8
9
10 11 12 13 14 15
4
5
6
7
8
9
10 11 12 13 14 15
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 1
Figure 2
RISE TIME
vs
JUNCTION TEMPERATURE
FALL TIME
vs
JUNCTION TEMPERATURE
50
45
40
50
45
40
V
C
= 6.5 V
= 3.3 nF
CC
L
V
C
= 6.5 V
= 3.3 nF
CC
L
High Side
High Side
Low Side
35
30
35
30
Low Side
25
20
25
20
15
10
15
10
−50
−25
0
25
50
75
100
125
0
25
50
75
100
125
−50
−25
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 3
Figure 4
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ
ꢂꢉ ꢊꢋꢌꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏꢋꢒ ꢓ ꢎꢂ ꢔꢕ ꢀ ꢖ ꢍꢗ ꢘ ꢕꢍ ꢂ
ꢙ ꢗꢀ ꢌ ꢖꢕꢚ ꢖꢐꢀ ꢗꢓ ꢕ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
TYPICAL CHARACTERISTICS
HIGH-TO-LOW PROPAGATION DELAY TIME
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
vs
SUPPLY VOLTAGE, HIGH TO LOW LEVEL
SUPPLY VOLTAGE, LOW TO HIGH LEVEL
150
150
140
130
C
T
= 3.3 nF
= 25°C
C
T
= 3.3 nF
= 25°C
L
J
140
130
L
J
120
110
100
120
110
100
90
80
90
80
70
60
50
40
70
60
50
40
High Side
Low Side
Low Side
30
20
30
20
4
5
6
7
8
9
10 11 12 13 14 15
4
5
6
7
8
9
10 11 12 13 14 15
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 5
Figure 6
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
150
150
140
130
V
C
= 6.5 V
= 3.3 nF
V
C
= 6.5 V
140
130
CC
L
CC
= 3.3 nF
L
120
110
100
120
110
100
High Side
90
80
90
80
High Side
70
60
50
40
70
60
50
40
Low Side
Low Side
30
20
30
20
−50
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 7
Figure 8
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈ
ꢂ ꢉꢊꢋ ꢌ ꢍ ꢎꢊꢎꢏ ꢂꢐꢑ ꢏꢋꢒ ꢓꢎ ꢂ ꢔꢕ ꢀ ꢖꢍ ꢗ ꢘꢕ ꢍꢂ
ꢙꢗ ꢀ ꢌ ꢖ ꢕꢚ ꢖꢐ ꢀ ꢗꢓ ꢕ ꢋꢎ ꢊꢀ ꢍꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
TYPICAL CHARACTERISTICS
DRIVER-OUTPUT FALL TIME
vs
DRIVER-OUTPUT RISE TIME
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1000
1000
V
T
= 6.5 V
= 25°C
V
T
= 6.5 V
CC
J
CC
= 25°C
J
100
10
100
10
High Side
Low Side
High Side
Low Side
1
1
0.01
0.1
1
10
100
0.01
0.1
1
10
100
C
− Load Capacitance − nF
C
− Load Capacitance − nF
L
L
Figure 9
Figure 10
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
25
6000
T
C
= 25°C
= 50 pF
T
C
= 25°C
= 50 pF
J
L
J
L
5500
5000
4500
4000
20
15
500 kHz
2 MHz
300 kHz
200 kHz
3500
3000
2500
2000
1500
1000
100 kHz
50 kHz
25 kHz
10
5
1 MHz
500
0
0
4
6
8
10
12
14
16
4
6
8
10
12
14
16
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 11
Figure 12
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ
ꢂꢉ ꢊꢋꢌꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏꢋꢒ ꢓ ꢎꢂ ꢔꢕ ꢀ ꢖ ꢍꢗ ꢘ ꢕꢍ ꢂ
ꢙ ꢗꢀ ꢌ ꢖꢕꢚ ꢖꢐꢀ ꢗꢓ ꢕ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
TYPICAL CHARACTERISTICS
PEAK SOURCE CURRENT
PEAK SINK CURRENT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
4
3.5
3
4
3.5
3
T
J
= 25°C
T
J
= 25°C
Low Side
Low Side
2.5
2
2.5
2
High Side
High Side
1.5
1
1.5
1
0.5
0
0.5
0
4
6
8
10
12
14
16
4
6
8
10
12
14
16
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 13
Figure 14
INPUT THRESHOLD VOLTAGE
INPUT THRESHOLD VOLTAGE
vs
vs
SUPPLY VOLTAGE
JUNCTION TEMPERATURE
2.0
1.8
1.6
1.4
1.2
1.0
2.0
1.8
1.6
1.4
1.2
1.0
T
J
= 25°C
V
CC
= 6.5 V
4
6
8
10
12
14
16
−50
−25
0
25
50
75
100
125
V
CC
− Supply Voltage − V
T
J
− Junction Temperature − °C
Figure 15
Figure 16
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢈ
ꢂ ꢉꢊꢋ ꢌ ꢍ ꢎꢊꢎꢏ ꢂꢐꢑ ꢏꢋꢒ ꢓꢎ ꢂ ꢔꢕ ꢀ ꢖꢍ ꢗ ꢘꢕ ꢍꢂ
ꢙꢗ ꢀ ꢌ ꢖ ꢕꢚ ꢖꢐ ꢀ ꢗꢓ ꢕ ꢋꢎ ꢊꢀ ꢍꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
APPLICATION INFORMATION
Figure 17 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A
pulse-width-modulation (PWM) controller and a TPS2835 driver. The converter operates over an input range from
4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3 A continuous load. The converter achieves an efficiency
of 94% for V = 5 V, I
=1 A, and 93% for V = 5 V, I = 3 A.
IN
load
IN load
V
IN
+
C10
C5
100 µF
100 µF
+
C11
0.47 µF
U1
R6
R5
R1
1 kΩ
TPS2835
ENABLE
IN
1 MΩ
0 Ω
1
2
3
4
5
6
7
14
13
12
11
10
9
BOOT
NC
C15
1.0 µF
Q1
Si4410
L1
27 µH
CROWBAR HIGHDR
NC
BOOTLO
3.3 V
SYNC
DT
LOWDR
NC
C13
R7
3.3 Ω
10 µF
R11
4.7 Ω
8
PGND
V
CC
C7
100 µF
+
C12
100 µF
+
Q2
C14
Si4410
C6
1 µF
1000 pF
RTN
GND
C8
0.1 µF
C3
0.0022 µF
U2
TL5001A
C2
0.033 µF
2
C4
0.022 µF
R3
180 Ω
V
CC
COMP
R2
1.6 kΩ
3
1
6
OUT
DTC
4
7
FB
RT
R4
2.32 kΩ
C9
0.22 µF
5
SCP
R8
121 kΩ
GND
8
R9
90.9 kΩ
R10
1.0 kΩ
C1
1 µF
Figure 17. 3.3-V 3-A Synchronous-Buck Converter Circuit
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀꢁ ꢂ ꢃꢄ ꢅꢈ
ꢂꢉ ꢊꢋꢌꢍꢎ ꢊꢎ ꢏꢂ ꢐꢑꢏꢋꢒ ꢓ ꢎꢂ ꢔꢕ ꢀ ꢖ ꢍꢗ ꢘ ꢕꢍ ꢂ
ꢙ ꢗꢀ ꢌ ꢖꢕꢚ ꢖꢐꢀ ꢗꢓ ꢕ ꢋ ꢎꢊ ꢀꢍ ꢎ ꢛ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
APPLICATION INFORMATION
Great care should be taken when laying out the PC board. The power-processing section is the most critical
and will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very
tight. The connection from Q1 drain to the positive sides of C5, C10, and C11 and the connection from Q2 source
to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and
C12 should also be connected to Q2 source.
Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from
the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive
traces. The bypass capacitor (C14) should be tied directly across V
and PGND.
CC
The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A). This node is very
sensitive to noise pickup and should be isolated from the high-current power stage and be as short as possible.
The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these
three areas are properly laid out, the rest of the circuit should not have other EMI problems and the power supply
will be relatively free of noise.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TPS2834D
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
D
14
14
14
14
14
14
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
2834
TPS2834DG4
TPS2834DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
50
2500
2500
90
Green (RoHS
& no Sb/Br)
2834
SOIC
Green (RoHS
& no Sb/Br)
2834
TPS2834DRG4
TPS2834PWP
TPS2834PWPG4
TPS2834PWPR
TPS2834PWPRG4
TPS2835D
SOIC
D
Green (RoHS
& no Sb/Br)
2834
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
PWP
PWP
PWP
D
Green (RoHS
& no Sb/Br)
TPS2834
TPS2834
TPS2834
TPS2834
2835
90
Green (RoHS
& no Sb/Br)
2000
2000
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS2835DG4
TPS2835PWP
TPS2835PWPG4
SOIC
D
50
Green (RoHS
& no Sb/Br)
2835
HTSSOP
HTSSOP
PWP
PWP
90
Green (RoHS
& no Sb/Br)
TPS2835
TPS2835
TPS2835
90
Green (RoHS
& no Sb/Br)
TPS2835PWPR
OBSOLETE HTSSOP
OBSOLETE HTSSOP
PWP
PWP
14
14
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
TPS2835PWPRG4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2834DR
SOIC
D
14
14
2500
2000
330.0
330.0
16.4
12.4
6.5
6.9
9.0
5.6
2.1
1.6
8.0
8.0
16.0
12.0
Q1
Q1
TPS2834PWPR
HTSSOP PWP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS2834DR
SOIC
D
14
14
2500
2000
367.0
367.0
367.0
367.0
38.0
35.0
TPS2834PWPR
HTSSOP
PWP
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明