TPS26632RGET [TI]
具有输出功率限制和浪涌保护功能的 4.5V 至 60V、31mΩ、0.6A 至 6A 电子保险丝 | RGE | 24 | -40 to 125;
| 型号： | TPS26632RGET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有输出功率限制和浪涌保护功能的 4.5V 至 60V、31mΩ、0.6A 至 6A 电子保险丝 | RGE | 24 | -40 to 125 电子 |
| 文件： | 总52页 (文件大小：5291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS2663
ZHCSIU6F –SEPTEMBER 2018 –REVISED JUNE 2021
TPS2663x 60V 6A 功率限制浪涌保护工业电子保险丝
1 特性
3 说明
• 工作电压为4.5V 至60V，绝对最大值为67V
• 集成式60V、31mΩRON 热插拔FET
• 通过外部N 沟道FET 提供反极性保护和反向电流
阻断支持
• 可调电流限制为0.6A 至6A (± 7%)
• 浪涌期间具有电气快速瞬变(IEC61000-4-4) 抗扰性
和负载保护(IEC 61000-4-5) 并提供A 类系统性能
• 快速反向电流阻断(0.17µs)
• 具有可调节输出功率限制功能(± 6%) 的型号
• 可调节UVLO、OVP 切断、输出压摆率控制，用于
浪涌电流限制
• 通过在器件加电期间进行热调节，为大型及未知容
性负载充电
TPS2663x 器件是易于使用的正极 60V 和 6A 电子保
险丝，其中包含一个 31mΩ 的集成式 FET。该器件具
有一个 B-FET 驱动器，用于在需要输入反极性故障和
反向电流阻断保护的系统设计中控制外部 N 沟道
FET。该器件集成了强大的保护功能， 可简化在
IEC61000-4-5 工业浪涌测试等系统测试期间需要保护
的系统设计。该器件具有可调节输出功率限制 (PLIM)
功能，从而简化需要符合 IEC61010-1 和UL1310 等标
准的系统设计。其他保护功能包括可调节过流保护、快
速短路保护、输出压摆率控制、过压保护和欠压锁定。
为实现系统状态监视和下游负载控制，该器件提供了故
障和精确的电流监视器输出。可以使用 PGOOD 来启
用和禁用下游直流/直流转换器控制。MODE 引脚可用
于在两种限流故障响应（闭锁和自动重试）之间灵活地
对器件进行配置。
• 具有最大35V 和39V 过压钳位的型号
• 电源正常输出(PGOOD)
• 可选过流故障响应选项（自动重试和闭锁模式）
• 具有2x 脉冲过流支持的型号
器件信息(1)
封装尺寸（标称值）
器件型号
TPS26630
封装
• 模拟电流监控器(IMON) 输出(± 6%)
• 通过UL 2367 认证
TPS26631
TPS26632
TPS26633
TPS26635
– 文件编号E169910
– RILIM ≥3kΩ
• 通过IEC 62368-1 认证
VQFN (24)
4.00mm × 4.00mm
6.50mm x 4.40mm
TPS26631
TPS26633
TPS26636
2 应用
HTSSOP (20)
• 工厂自动化和控制–PLC、DCS、HMI、I/O 模
块、传感器集线器
• 电机驱动器–CNC、编码器电源
• 电子断路器
Optional components
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VIN_SYS
VOUT
for RCB and RPP
4.5V-60V
IN
OUT
COUT
R4
R5
B_GATE
D1*
PGTH
Protected supply
To Load
DRV
PGOOD
FLT
TPS26630/31
IN_SYS
PGOOD
ISURGE
R1
R2
R3
ON/OFF Control
SHDN
UVLO
IMON
ILIM
Load Monitor
RILON
OVP
dVdT
RILIM
MODE
GND
CdVdT
* TVS for Surge Suppression Only
简化版原理图
24V 电源下的IEC61000-4-5 浪涌性能
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSE94
TPS2663
www.ti.com.cn
ZHCSIU6F –SEPTEMBER 2018 –REVISED JUNE 2021
Table of Contents
10 Application and Implementation................................30
10.1 Application Information........................................... 30
10.2 Typical Application: Power Path Protection in a
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements..................................................9
7.7 Typical Characteristics.............................................. 11
8 Parameter Measurement Information..........................14
9 Detailed Description......................................................16
9.1 Overview...................................................................16
9.2 Functional Block Diagram.........................................17
9.3 Feature Description...................................................18
9.4 Device Functional Modes..........................................29
PLC System................................................................ 30
10.3 System Examples................................................... 35
10.4 Do's and Don'ts.......................................................37
11 Power Supply Recommendations..............................37
11.1 Transient Protection................................................ 37
12 Layout...........................................................................39
12.1 Layout Guidelines................................................... 39
12.2 Layout Example...................................................... 40
13 Device and Documentation Support..........................42
13.1 Documentation Support.......................................... 42
13.2 接收文档更新通知................................................... 42
13.3 支持资源..................................................................42
13.4 Trademarks.............................................................42
13.5 Electrostatic Discharge Caution..............................42
13.6 术语表..................................................................... 42
14 Mechanical, Packaging, and Orderable
Information.................................................................... 42
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision E (March 2020) to Revision F (June 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
Changes from Revision D (August 2019) to Revision E (March 2020)
Page
• 将UL 2367 从“认证正在处理中”更改为“已认证”........................................................................................1
• 向特性部分添加了“通过IEC 62368-1 认证”................................................................................................... 1
Changes from Revision C (March 2019) to Revision D (August 2019)
Page
• 将器件信息表中的TPS26632 器件替换为TPS26636 器件................................................................................1
• Added the TPS26636 device to the Pin Configuration and Functions table.......................................................3
• Added the TPS26636 device to the Pin Functions table.................................................................................... 3
• Updated the Input Voltage in the Absolute Maximum Ratings table...................................................................6
• Updated the PLIM Input and Output Ramp Control in the Electrical Characteristics table.................................7
Changes from Revision B (January 2019) to Revision C (March 2019)
Page
• 将“预告信息”更改为“量产数据”.................................................................................................................. 1
Changes from Revision A (December 2018) to Revision B (January 2019)
Page
• Updated the Pin Configuration and Functions section .......................................................................................3
• Updated Layout Example ................................................................................................................................ 40
Changes from Revision * (September 2018) to Revision A (December 2018)
Page
• Updated the Pin Configuration and Functions section........................................................................................3
• Updated Functional Block Diagram ................................................................................................................. 17
• Updated Layout Example ................................................................................................................................ 40
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ZHCSIU6F –SEPTEMBER 2018 –REVISED JUNE 2021
5 Device Comparison Table
ADJUSTABLE OUTPUT POWER
PART NUMBER
TPS26630
OVERVOLTAGE PROTECTION
OVERLOAD FAULT RESPONSE
LIMITING
Overvoltage cut-off, adjustable
Overvoltage cut-off, adjustable
Active Current Limiting (1x)
No
Active Current Limiting with Pulse
current support (2x)
TPS26631
No
Yes
Yes
TPS26632
Overvoltage clamp, fixed (35-V max)
Overvoltage clamp, fixed (35-V max)
Active Current Limiting (1x)
Active Current Limiting with Pulse
current support (2x)
TPS26633
Active Current Limiting with Pulse
current support (2x)
TPS26635
TPS26636
Overvoltage clamp, fixed (39-V max)
Overvoltage clamp, fixed (35-V max)
Yes
Yes
Active Current Limiting with Pulse
current support (2x)
6 Pin Configuration and Functions
IN
IN
1
2
3
4
20
OUT
OUT
19
18
17
OUT
IN
18
17
OUT
OUT
1
2
3
4
5
6
IN
IN
PGOOD
B_GATE
PGTH
FLT
5
6
16
DRV
IN_SYS
UVLO
PowerPAD™
B_GATE
DRV
16
15
PGOOD
PGTH
FLT
PowerPadTM
15
14
13
7
8
IMON
IN_SYS
14
13
OVP
GND
SHDN
MODE
IMON
UVLO
12
11
9
10
dVdT
ILIM
图6-2. TPS26631 PWP Package 20-Pin HTSSOP
Top View
图6-1. TPS26630, TPS26631 RGE Package 24-Pin
VQFN Top View
IN
IN
1
2
3
4
20
OUT
OUT
19
18
17
OUT
IN
18
17
OUT
OUT
1
2
3
4
5
6
IN
IN
PGOOD
B_GATE
PGTH
FLT
5
6
16
DRV
IN_SYS
UVLO
PowerPAD™
B_GATE
DRV
16
15
PGOOD
PGTH
FLT
PowerPadTM
15
14
13
7
8
IMON
IN_SYS
14
13
PLIM
GND
SHDN
MODE
IMON
UVLO
12
11
9
10
dVdT
ILIM
图6-4. TPS26633, TPS26636 PWP Package 20-Pin
HTSSOP Top View
图6-3. TPS26632, TPS26633, TPS26635 RGE
Package 24-Pin VQFN Top View
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ZHCSIU6F –SEPTEMBER 2018 –REVISED JUNE 2021
表6-1. Pin Configuration and Functions
PIN
TPS26630, TPS26631,
TPS26632, TPS26633,
TPS26635, TPS26636
TYPE
DESCRIPTION
NAME
VQFN
HTSSOP
1
2
1
2
3
IN
P
Power input. Connects to the DRAIN of the internal FET
—
Blocking FET gate driver output. Connect B_GATE to GATE of the external
NFET. If external FET is not used then leave B_GATE pin floating. See the Input
Reverse Polarity Protection (B_GATE, DRV) section.
B_GATE
DRV
3
4
5
4
5
6
O
O
P
Blocking FET fast pull down switch drive. Connect DRV to the GATE of external
pull down switch. Leave this pin floating if external N-FET is not used.
Power input and supply voltage of the device. When an external Blocking FET is
used then connect IN_SYS to source of the FET. Short IN_SYS to IN in case
blocking FET is not used.
IN_SYS
Input for setting the programmable undervoltage lockout threshold. An
undervoltage event turns off the internal FET and asserts FLT to indicate the
power-failure. Connect UVLO pin to GND pin to select the internal default
threshold.
UVLO
OVP
6
7
7
8
I
I
Input for setting the programmable overvoltage protection threshold (For
TPS26630 and TPS26631 Only). An overvoltage event turns off the internal FET
and asserts FLT to indicate the overvoltage fault. Connect OVP pin to GND pin
externally to select the internal default threshold.
Input for setting the programmable output power limiting threshold (For
TPS26632, TPS26633, TPS26635 and TPS26636 Only). Connect a resistor
across PLIM to GND to set the output power limit. Connect PLIM to GND if PLIM
feature is not used. See the tput power limit. Connect PLIM to GND if PLIM
feature is not used. See the Output Power Limiting, PLIM (TPS26632,
TPS26633, TPS26635 and TPS26636 Only) section.
PLIM
7
8
I
GND
dVdT
8
9
9
Connect GND to system ground
—
A capacitor from this pin to GND sets output voltage slew rate. See the Hot Plug-
In and In-Rush Current Control section.
10
I/O
A resistor from this pin to GND sets the overload and short-circuit current limit.
See the Overload and Short Circuit Protection section.
ILIM
10
11
11
12
I/O
I
Mode selection pin for overload fault response. See the Device Functional
Modes section.
MODE
Shutdown pin. Pulling SHDN low makes the device to enter into low power
shutdown mode. Cycling SHDN pin voltage resets the device that has latched off
due to a fault condition.
SHDN
IMON
12
13
13
14
I
Analog current monitor output. This pin sources a scaled down ratio of current
through the internal FET. A resistor from this pin to GND converts current to
proportional voltage. If unused, leave it floating.
O
Fault event indicator. It is an open drain output. If unused, leave floating or
connect to GND.
FLT
14
15
15
16
O
I
PGTH
PGOOD comparator input.
Active High. A high indicates PGTH has crossed the V(PGTHR) threshold and the
internal FET is enhanced. PGOOD goes low when V(PGTH) hits V(PGTHF)
threshold. If PGOOD is unused then connect to GND or leave it floating.
PGOOD
OUT
16
17
O
P
17
18
—
18
19
20
Power output of the device
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表6-1. Pin Configuration and Functions (continued)
PIN
TPS26630, TPS26631,
TPS26632, TPS26633,
TPS26635, TPS26636
TYPE
DESCRIPTION
NAME
VQFN
19
HTSSOP
20
21
N. C
No Connect
—
—
—
22
23
24
Connect PowerPad to GND plane for heat sinking. Do not use PowerPad as the
only electrical connection to GND.
PowerPadTM
—
—
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–60
–60
–0.3
MAX
67
UNIT
IN_SYS
V
V
V
75
IN_SYS (10ms transient), TA = 25 ℃
IN, OUT, UVLO, FLT, PGOOD, PGTH
67
IN_SYS –OUT (10ms transient), with
a Blocking FET
V
–85
75
81
14
72
20
V
V
V
V
V
IN (10ms transient), TA = 25 ℃
–0.3
–60
–0.3
–60
–0.3
Input Voltage
BGATE
BGATE –IN_SYS
DRV
DRV –IN_SYS
OVP, dVdT, IMON, MODE, SHDN,
ILIM, PLIM
5.5
10
V
–0.3
IFLT, IdVdT, IPGOOD
Sink current
mA
IdVdT, IILIM, IPLIM, IMODE, ISHDN
Source current
Internally limited
Operating Junction temperature
Transient junction temperature
Storage temperature
150
T(TSD)
150
–40
–65
–65
TJ
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
IN_SYS, IN
4.5
60
OUT, UVLO, PGTH, PGOOD,
FLT
0
60
Input Voltage
V
OVP, dVdT, IMON, MODE
0
0
4
5
SHDN
ILIM
Resistance
Resistance
Resistance
3
30
IMON
1
kΩ
PLIM
60.4
0.1
10
150
IN, IN_SYS, OUT
dVdT
µF
nF
External Capacitance
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over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
TJ
Operating Junction temperature
25
125
°C
–40
7.4 Thermal Information
TPS2663
THERMAL METRIC(1)
RGE (VSON)
24 PINS
31.4
PWP (HTSSOP)
UNIT
20 PINS
32.2
23.4
10
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
23.2
10.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
0.3
ΨJT
10.2
9.9
ΨJB
RθJC(bot)
2.8
3.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
–40°C ≤TA = TJ ≤+125°C, 4.5 V < V(IN_SYS) = V(IN) < 60 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT =
OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE
V(IN_SYS)
Operating input voltage
Supply current
4.5
60
1.7
60
V
IQ(ON)
Enabled: V( SHDN) = 2 V
1.38
21
mA
µA
IQ(OFF)
V( SHDN) = 0 V
V(IN_SYS) = –24V, V(IN) = Floating,
V(OUT) = 0 V
I(GND)
Ground current during reverse polarity
Over voltage clamp
144
32.8
36.6
200
35
µA
V
TPS26632, TPS26633, TPS26636
Only, V(IN_SYS) > 35 V, I(OUT) = 1 mA
32
V(OVC)
TPS26635 Only, V(IN_SYS) > 40 V,
I(OUT) = 1 mA
35.7
39
V
UNDERVOLTAGE LOCKOUT (UVLO) INPUT
V(IN_SYS) rising, V(UVLO) = 0 V
V(IN_SYS) falling, V(UVLO) = 0 V
15.1
14
15.46
14.47
210
15.9
15.1
240
V
V
Factory set V(IN_SYS) undervoltage trip
level trip level
V(INSYS_UVLO)
V(SEL_UVLO)
V(UVLOR)
V(UVLOF)
I(UVLO)
Internal UVLO select threshold
UVLO threshold voltage, rising
UVLO threshold voltage, falling
UVLO Input leakage current
180
mV
V
1.176
1.09
–150
1.2
1.224
1.15
150
1.122
8
V
nA
0 V ≤V(UVLO) ≤60 V
OVERVOLTAGE PROTECTION (OVP) INPUT
V(IN_SYS) rising, V(OVP) = 0 V
V(IN_SYS) falling, V(OVP) = 0 V
33.2
32.7
34.33
33.89
210
35.4
35
V
V
Factory set V(IN_SYS) overvoltage trip
level trip level
V(IN_SYS_OVP)
V(SEL_OVP)
V(OVPR)
V(OVPF)
I(OVP)
Internal OVP select threshold
180
240
mV
V
over-voltage threshold voltage, rising
over-voltage threshold voltage, falling
OVP Input leakage current
1.176
1.09
1.2
1.224
1.15
150
1.122
0
V
nA
0 V ≤V(OVP) ≤4 V
–150
CURRENT LIMIT PROGRAMMING (ILIM)
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7.5 Electrical Characteristics (continued)
–40°C ≤TA = TJ ≤+125°C, 4.5 V < V(IN_SYS) = V(IN) < 60 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT =
OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
0.6
2
MAX UNIT
0.54
0.66
2.16
A
A
A
A
R(ILIM) = 30 kΩ, V(IN) –V(OUT) = 1 V
R(ILIM) = 9 kΩ, V(IN) – V(OUT) = 1 V
R(ILIM) = 4.02 kΩ, V(IN) –V(OUT) = 1 V
R(ILIM) = 3 kΩ, V(IN) –V(OUT) = 1 V
1.84
I(OL)
Over Load current limit
4.185
5.58
4.5
6
4.815
6.42
3 kΩ< R(ILIM) < 30 kΩ, TPS26631,
TPS26633, TPS26635 and TPS26636
Only
I(OL_Pulse)
Transient Pulse Over current limit
2xI(OL)
A
I(FASTRIP)
I(FASTRIP)
I(SCP)
Fast-trip comparator threshold
Fast-trip comparator threshold
Short Circuit Protect current
TPS26630 and TPS26632 Only
2xI(OL)
3xI(OL)
45
A
A
A
TPS26631, TPS26633,TPS26635 and
TPS26636 Only
OUTPUT POWER LIMITING CONTROL (PLIM) INPUT –TPS26632, TPS26633, TPS26635 and TPS26636 ONLY
V(SEL_PLIM)
I(PLIM)
Power Limit Feature select threshold
PLIM sourcing current
160
4.4
217
5.02
100
151
240
5.6
mV
µA
W
V(PLIM) = 0 V
94
106
R(PLIM) = 100 kΩ
R(PLIM) = 150 kΩ (1)
P(PLIM)
Max Output power
141.9
160.1
W
B_GATE (BLOCKING FET GATE DRIVER)
V(B_GATE)
I(B_GATE)
B_GATE clamp voltage
8.3
16
10.23
19.4
14
23
V
µA
kΩ
V
V
V
(B_GATE) –V(IN_SYS)
Blocking FET Gate drive current
B_GATE Pull down resistance
DRV logic high level
(B_GATE) –V(IN_SYS) = 1 V
Rpd_BGATE
V(DRV_OH)
800
3
1010
4.25
1200
5.2
V
(DRV) –V(IN_SYS), C(DRV) ≤50 pF
PASS FET OUTPUT (OUT)
RON
RON
IN to OUT total ON resistance
26
33
30.44
30.44
34.5
45
0.6 A ≤I(OUT) ≤6 A,TJ = 25°C
0.6 A ≤I(OUT) ≤6 A,TJ = 85°C
mΩ
mΩ
IN to OUT total ON resistance
IN to OUT total ON resistance
0.6 A ≤I(OUT) ≤6 A, –40°C ≤TJ ≤
+125°C
RON
19
–100
–20
45
53
mΩ
µA
OUT leakage during input supply
brownout
V(IN_SYS) = 0 V, V(OUT) = 24 V, V(IN)
Floating, V( SHDN) = 2V, Sinking
=
Ilkg(OUT)
V(REVTH)
V(FWDTH)
V
(IN_SYS) –V(OUT) threshold for
mV
mV
–15
–9
reverse protection comparator, rising
V
(IN_SYS) –V(OUT) threshold for
57
67
reverse protection comparator, falling
OUTPUT RAMP CONTROL (dVdT)
I(dVdT)
dVdT charging current
V(dVdT) = 0 V
1.775
23.5
3.8
2
25
2.225
26
µA
V/V
V
GAIN(dVdT)
V(dVdTmax)
R(dVdT)
dVdT to OUT gain
V(OUT) /V(dVdT)
dVdT maximum capacitor voltage
dVdT discharging resistance
4.17
16.6
4.75
26.6
10
Ω
LOW IQ SHUTDOWN ( SHDN) INPUT
V( SHDN)
V(SHUTF)
Open circuit voltage
I( SHDN) = 0.1 µA
2.48
0.8
2.7
3.3
2
V
V
SHDN threshold voltage for low IQ
shutdown, falling
V(SHUTR)
I( SHDN)
SHDN threshold rising
Leakage current
V
V( SHDN) = 0 V
µA
–10
CURRENT MONITOR OUTPUT (IMON)
GAIN(IMON) Gain factor I(IMON):I(OUT)
25.66
27.9
30.14 µA/A
0.6 A ≤I(OUT) ≤2 A
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7.5 Electrical Characteristics (continued)
–40°C ≤TA = TJ ≤+125°C, 4.5 V < V(IN_SYS) = V(IN) < 60 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT =
OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
26.22
27.9
29.58 µA/A
2 A ≤I(OUT) ≤6 A
FAULT FLAG ( FLT): ACTIVE LOW
R( FLT)
I( FLT)
POWER GOOD (PGOOD)
R(PGOOD) PGOOD Pull-down resistance
I(PGOOD) PGOOD Input leakage current
FLT Pull-down resistance
36
70
6
130
150
Ω
FLT Input leakage current
nA
0 V ≤V( FLT) ≤60 V
–150
36
70
130
150
Ω
nA
0 V ≤V(PGOOD) ≤60 V
–150
POSITIVE INPUT FOR POWER GOOD COMPARATOR (PGTH)
V(PGTHR)
V(PGTHF)
I(PGOOD)
PGTH threshold voltage, rising
PGTH threshold voltage, falling
PGTH input leakage current
1.176
1.09
1.2
1.224
1.15
150
V
V
1.123
nA
0 V ≤V(PGTH) ≤60 V
–150
THERMAL PROTECTION
T(J_REG) Thermal regulation set point
136
145
165
11
154
°C
°C
°C
Thermal shutdown (TSD) threshold,
rising
T(TSD)
T(TSDhyst)
TSD hysteresis
Mode selection
MODE
MODE = Open
Latch
MODE_SEL
Auto –
Retry
MODE = Short to GND
(1) Parameter guaranteed by design and characterization, not tested in production
7.6 Timing Requirements
–40°C ≤TA = TJ ≤+125°C, 4.5 V < V(IN_SYS) = V(IN) < 60 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT =
OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
UVLO INPUT (UVLO)
UVLO↑(100 mV above V(UVLOR)) to
742 +
49.5 x
C(dVdT)
V(OUT) = 100 mV with V(PGTH
<
UVLO_ton(dly)
UVLO switch turnon delay
µs
V(PGTHF), C(dVdT) ≥10 nF, [C(dVdT) in
nF]
UVLO↑ (100 mV above V(UVLOR)) to
FET ON with V(PGTH) > V(PGTHF)
UVLO_ton(fast_dly) UVLO switch turnon delay (fast)
70
150
251
µs
UVLO↓(20 mV below V(UVLOF)) to FLT
↓
UVLO_toff(dly)
tUVLO_FLTdly)
UVLO switch turnoff delay
9
11
16
µs
µs
UVLO to fault de-assertion delay
500
617
700
UVLO↑ to FLT ↑delay
OVER VOLTAGE PROTECTION INPUT (OVP)
OVP↑(20 mV above V(OVPR)) to FLT
↓
OVP_tOFF(dly)
OVP switch turnoff delay
8.5
58
11
14
µs
µs
OVP↓(100 mV below V(OVPF)) to FET
ON with V(PGTH ) > V(PGTHF)
OVP_ton(fast_dly)
OVP switch turnon delay (fast)
129
225
OVP↓(100 mV below V(OVPF)) to FET
150 +
49.5 x
C(dVdT)
OVP_ton(dly)
OVP switch disable delay
µs
ON with V(PGTH ) < V(PGTHF), C(dVdT)
10 nF, [C(dVdT) in nF]
≥
Maximum duration in over voltage
clamp operation
TPS26632, TPS26633,TPS26635 and
TPS26636 Only
tOVC(dly)
162
ms
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7.6 Timing Requirements (continued)
–40°C ≤TA = TJ ≤+125°C, 4.5 V < V(IN_SYS) = V(IN) < 60 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT =
OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
FLT assertion delay in over voltage
clamp operation
TPS26632, TPS26633,TPS26635 and
TPS26636 Only
OVC_tFLT(dly)
617
µs
SHUTDOWN CONTROL INPUT ( SHDN)
tSD(dly)
SHUTDOWN entry delay
0.8
1
1.5
µs
SHDN↓(below V(SHUTF)) to FET OFF
CURRENT LIMIT
Hot-short response time
Soft short response
I(OUT) > I(SCP)
1
µs
µs
tFASTTRIP(dly)
I(FASTTRIP) < I(OUT) < I(SCP)
2.2
3.2
4.5
Maximum duration in current & (power
limiting: TPS26632, TPS26633,
TPS26635 and TPS26636 Only)
tCL_PLIM(dly)
129
162
25.5
670
202
ms
ms
ms
Maximum duration in 2x current
limiting
tCB(dly)
20
31
I(OL) < I(OUT) ≤I(2xOL)
MODE = GND, TPS26631,
TPS26633,TPS26635 and TPS26636
Only
Retry delay in Pulse over current
limiting
tCBRetry(dly)
550
800
FLT delay in current & (power limiting:
TPS26632, TPS26633, TPS26635 and
TPS26636 Only)
tCL_PLIM_FLT(dly)
1.09
1.3
1.6
ms
µs
REVERSE CURRENT BLOCKING (RCB) COMPARATOR
(V(IN_SYS) –V(OUT))↓(1 V overdrive
below V(REVTH)) to V(DRV) –V(IN_SYS)
tRCB(fast_dly)
0.17
0.37
=
V(DRV_OH)
Reverse protection comparator
dectection delay (reverse)
(V(IN_SYS) –V(OUT))↓(10 mV
tRCB(dly)
0.48
617
3
µs
µs
overdrive below V(REVTH)) to V(DRV)
V(IN_SYS) = V(DRV_OH)
–
(V(IN_SYS) –V(OUT))↓(10 mV
overdrive below V(REVTH)) to FLT↓
tRCB(flt_dly)
Fault assertion Delay
500
800
(V(IN_SYS) –V(OUT))↑(10 mV
Reverse protection comparator
dectection delay (forward)
overdrive above V(FWDTH)) to
0.87
605
ms
µs
V
(BGATE) –V(IN_SYS) = 5 V, C(BFET-
tFWD_FLT(dly)
IN_SYS) = 4.7 nF
(V(IN_SYS) –V(OUT))↑(10 mV
overdrive above V(FWDTH)) to FLT↑
Fault de-assertion Delay
434
350
800
700
OUTPUT RAMP CONTROL (dVdT)
t(FASTCHARGE) Output ramp time in fast charging
t(dVdT) Output ramp time
POWER GOOD (PGOOD)
C(dVdT) = Open, 10% to 90%
V(OUT), C(OUT) = 1 µF; V(IN) = 24V
495
µs
C(dVdT) = 22 nF, 10% to 90%
V(OUT), V(IN) = 24V
8.35
ms
tPGOODR
PGOOD delay (deglitch) time
Rising edge
1.07
1.3
1.3
1.6
4
ms
µs
Falling edge, PGTH↓(10mV below
tPGOODF
PGOOD delay (deglitch) time
2.12
V(PGTHF)
)
FAULT FLAG ( FLT)
Delay from I(OUT) > I(OL) to FLT↓.
TPS26631, TPS26633, TPS26635 and
TPS26636 Only
FLT assertion delay in Pulse over
current limiting
tCB_FLT(dly)
22
25.5
30
ms
THERMAL PROTECTION
t(TSD_retry)
Retry delay in TSD
Thermal Regulation Timeout
MODE = GND
500
2.3
648
800
2.9
ms
s
t(Treg_timeout)
2.54
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7.7 Typical Characteristics
–40°C ≤TA = TJ ≤+125°C, V(IN_SYS) = V(IN) = 24 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN,
C(OUT) = 1 μF, C(dVdT) = OPEN. (Unless stated otherwise)
75
60
45
30
15
0
42
40
38
36
34
32
30
ILOAD = 0.6 A
ILOAD = 6 A
TPS26632, TPS26633, TPS26636
TPS26635
-60
-30
0
30
60
90
120
150
-50
0
50
Temperature (èC)
100
150
Temperature (èC)
D002
D006
图7-1. On-Resistance vs Temperature Across Load Current
图7-2. Overvoltage Clamp Threshold vs Temperature
11
20.5
V(IN_SYS) = 4.5 V
V(IN_SYS) = 24 V
V(IN_SYS) = 60 V
V(IN_SYS) = 4.5 V
V(IN_SYS) = 24 V
V(IN_SYS) = 60 V
10.5
20
19.5
19
10
9.5
9
8.5
18.5
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D014
D015
图7-3. B_GATE Drive Voltage vs Temperature
图7-4. B_GATE Drive Current vs Temperature
48
45
42
39
36
33
30
27
24
21
18
15
12
9
TA = 125èC
TA = 85èC
TA = 25èC
TA = -40èC
4.75
4.5
4.25
4
V(IN_SYS) = 4.5 V
V(IN_SYS) = 24 V
V(IN_SYS) = 60 V
3.75
6
0
5
10 15 20 25 30 35 40 45 50 55 60
Supply Voltage (V)
3.5
-50
0
50
Temperature (èC)
100
150
D023
D016
图7-6. Input Supply Current vs Supply Voltage in Shutdown
图7-5. B_GATE Pull Down Drive Voltage vs Temperature
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7.7 Typical Characteristics (continued)
–40°C ≤TA = TJ ≤+125°C, V(IN_SYS) = V(IN) = 24 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN,
C(OUT) = 1 μF, C(dVdT) = OPEN. (Unless stated otherwise)
1600
1400
1200
1000
800
600
400
200
0
0
-20
-40
-60
-80
-100
-120
-140
-160
TA = -40 èC
TA = 25 èC
TA = 85 èC
TA = 125 èC
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
-65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
Reverse Supply Voltage (V)
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Supply Voltage (V)
D041
D026
V(OUT) = 0 V
图7-7. Input Supply Current vs Supply Voltage During Normal
Operation
图7-8. Input Supply Current vs Reverse Supply Voltage, –
V(IN_SYS)
10
1.25
R(ILIM) = 9 kW
R(ILIM) = 4.02 kW
R(ILIM) = 3 kW
R(ILIM) = 30 kW
R(ILIM) = 18 kW
7.5
5
1
0.75
0.5
2.5
0
-50
0
50
Temperature (èC)
100
150
-50
0
50
Temperature (èC)
100
150
D020
D025
图7-9. Overload Current Limit vs Temperature
图7-10. Overload Current Limit vs Temperature
7
6
5
4
3
2
1
150
8
7
6
5
CURRENT LIMIT
POWER LIMIT
125
100
75
50
25
0
0
10
20
30
Supply Voltage (V)
40
50
60
60
80
100
120
140
160
D052
PLIM (W)
D042
TPS26632
R(PLIM) = 100 kΩ
R(ILIM) = 3 kΩ
图7-11. Output Power Limiting Accuracy vs PLIM
图7-12. Power Limit, Current limit vs Supply Voltage
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7.7 Typical Characteristics (continued)
–40°C ≤TA = TJ ≤+125°C, V(IN_SYS) = V(IN) = 24 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN,
C(OUT) = 1 μF, C(dVdT) = OPEN. (Unless stated otherwise)
160
140
120
100
80
160
140
120
100
80
TA = 125èC
TA = 85èC
TA = 25èC
TA = -40èC
60
60
40
40
20
20
0
0
0
0.6 1.2 1.8 2.4
3
Output Current (A)
3.6 4.2 4.8 5.4
6
6.6
0
0.1
0.2
0.3
Output Current (A)
0.4
0.5
0.6
D021
D033
图7-13. Current Monitor Output vs Output Current
180
图7-14. IMON Gain Accuracy at < 0.6-A Output Current
190
tUVLO_ON(fast_dly)
tOVP_ON(fast_dly)
160
140
120
100
80
180
170
160
150
140
-60
-30
0
30
60
90
120
150
-50
0
50
Temperature (èC)
100
150
Temperature (èC)
D008
D029
图7-16. Maximum Duration in Current and Power Limiting vs
A.
V(PGTH) > V(PGTHF)
Temperature
图7-15. UVLO, OVP Fast Turn ON Delay vs Temperature
200
3000
2000
TA = -40èC
1000
TA = 0èC
500
TA = 25èC
190
180
170
160
150
TA = 85èC
200
TA = 125èC
100
50
20
10
5
2
1
0.5
0.2
0.1
-50
0
50
Temperature (èC)
100
150
3
4
5 6 7 8 10
20 30 4050 70 100
Power Dissipation (W)
200 300400
D019
D040
图7-17. Reverse Current Blocking Response vs Temperature
Taken on VQFN device on EVM Board
图7-18. Thermal Shutdown Time vs Power Dissipation
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8 Parameter Measurement Information
V(OUT)
VUVLO
V(UVLOF)-0.02 V
0.1 V
VUVLO
FLT
V(UVLOR)+0.1V
10%
time
0
time
0
UVLO_tON(dly)
UVLO_toff(dly)
V(OVPR)+0.02V
V(OVP)
V(OUT)
0.1 V
FLT
VOVP
V(OVPF)-0.02 V
10%
0
0
time
time
OVP_tOFF(dly)
OVP_tON(dly)
VPGTH
VPGTH
VPGTHF
VPGTHF
V(OUT)
V(OUT)
V(OVPF)
-0.02V
V(UVLOR)
+0.1V
VUVLO
VUVLO
time
time
0
0
UVLO_tON(fast_dly)
OVP_tON(fast_dly)
图8-1. Timing Waveforms
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-1V
67 mV
V(IN_SYS) -V(OUT)
V(IN_SYS) -V(OUT)
V(DRV_OH)
V(DRV) -V(IN_SYS)
90%
V(B_GATE) -V(IN_SYS)
0
time
0
time
tFWD(dly)
tRCB(fast_dly)
I(FASTRIP)
V(OUT)
I(OL)
I(OUT)
I(OUT)
I(OL)
0
time
tCL_PLIM(dly)
time
0
tCB(dly)
tCL_PLIM(dly)
tFASTRIP(dly)
P(PLIM)
P(OUT)
V(OUT)
V(OUT)
2xI(OL)
I(OUT)
I(OL)
I(OUT)
time
0
tCB(dly)
tCL_PLIM(dly)
tCL_PLIM(dly)
0
time
图8-2. Timing Waveforms
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9 Detailed Description
9.1 Overview
The TPS2663x devices are a family of 60-V industrial eFuses. The devices provides robust protection for all
systems and applications powered from 4.5 V to 60 V. With an external N-channel FET the devices can be used
to protect the loads from negative supply voltages down to –60 V. For hot-pluggable boards, the devices
provides hot-swap power management with in-rush current control and programmable output voltage slew rate
features using the dVdT pin. Load, source and device protections are provided with many programmable
features including overcurrent, overvoltage and undervoltage. The precision overcurrent limit (±7% at 6 A) helps
to minimize over design of the input power supply, while the fast response short circuit protection 1-µs (typical)
immediately isolates the faulty load from the input supply when a short circuit is detected. The device features
fast reverse current blocking response (0.17 µs). The internal robust protection control blocks of the TPS2663x
along with its ±60-V rating, helps to simplify the system designs for the industrial surge compliance ensuring
complete protection of the load and the device. The 60-V maximum DC operating and 70-V absolute maximum
voltage rating enables system protection from 60-V DC input supply faults and from industrial SELV power
supplies.
By monitoring the output (Load) voltage through the PGTH pin, the device distinguishes between real system
faults and system transients and the turn ON delay during a fault recovery is controlled accordingly. The valid
load voltage detection threshold can be adjusted using a resistor ladder network from OUT, PGTH and GND.
This scheme ensures fast recovery during system tests like voltage interruption and brown-out tests, EMC
testing like Electrical Fast Transients (IEC61000-4-4) and Surge (IEC61000-4-5).
The TPS26632, TPS26633, TPS26635 and TPS26636 devices integrate adjustable output power limiting (PLIM)
functionality that simplifies the system design requiring compliance in accordance to standards like IEC61010-1
and UL1310.
The devices provides precise monitoring of voltage bus for brown-out, overvoltage conditions and asserts fault
signal for the downstream system. Its overall threshold accuracy of 2% ensures tight supervision of bus,
eliminating the need for a separate supply voltage supervisor chip. The devices monitors V(IN_SYS) and V(OUT) to
provide true reverse current blocking when a reverse condition or input power failure condition is detected.
Additional features of the TPS2663x devices include:
• ±6% Current monitor output (IMON) for health monitoring of the system
• A choice of latch off or automatic restart mode response during current limit, power Limit and thermal fault
using MODE pin
• PGOOD indicator output with ±2% accurate adjustable valid load voltage detection threshold (PGTH)
• Over temperature protection to safely shutdown in the event of an overcurrent event
• De-glitched fault reporting for supply brown-out and overvoltage faults
• Enable and disable control from an MCU using SHDN pin
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9.2 Functional Block Diagram
OUT
IN
IN_SYS
31 mΩ
20 µA
Charge
Pump (12 V)
Current
Sense
B_GATE
DRV
IN_SYS
+
+
PORb
Fast_Charge
_EN
+
IN_SYS
-15mV
+57mV
X27.9 µ
4.3 V
4.2 V
œ
IMON
CP
SWEN
Gate Control Logic
5 V
UVLOb
REVERSE
1.2 V
Power Limit Amp
Current Limit Amp
1.12 V
I(OUT) = I(OL)
P(OUT) = P(LIM)
162 msec
timer
Timeout
Fast-Trip Comp
(Threshold= 45A)
ILIM
TSD
Thermal
Shutdown
VSEL_UVLO
+
+
OLR
Open/ Short
detect
OVP
1.2 V
SHDNb
UVLO
œ
1.12 V
I(OUT) = I(OL)
Ramp Control
VSEL_OVP
SWEN
FLT
+
25x
* Only for Latch Mode
I(OUT) > I(CB)
OVP
œ
65 Ω
SET
Timeout
25.5 msec
timer
S
Q
*TPS26631
Only
4.17V
1.2 Meg Ω
CLR
R
Q
2 µA
3V
MODE
PORb
Fault Latch
Overload fault response
(Auto-Retry/Latch-off)
select detection
dVdT
OLR
UVLOb
14 Ω
PORb
PGOOD
Gate Enhanced (HS_FET)
SET
1.3msec
S
R
Q
Q
TSD
1.2V
SHDNb
2.7V
GND
+
2 µs
65 Ω
1.12V
0.8 V
SHDNb
CLR
SHDNb
+
Fast_Charge
_EN
TPS26630 & TPS26631
SHDN
PGTH
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OUT
IN
IN_SYS
31 mΩ
20 µA
Charge
Pump
Current
Sense
B_GATE
DRV
P_IN
+
PORb
Fast_Charge
_EN
+
IN_SYS
-15mV
+57mV
X27.9 µ
4.3 V
œ
IMON
4.2 V
CP
SWEN
+
Gate Control Logic
5 V
UVLOb
REVERSE
1.2 V
Power Limit Amp
Current Limit Amp
1.12 V
I(OUT) = I(OL)
P(OUT) = P(LIM)
VSEL_UVLO
+
162 msec
timer
Timeout
Fast-Trip Comp
(Threshold= 45A)
ILIM
TSD
Thermal
Shutdown
UVLO
œ
OLR
Open/ Short
detect
4.17V
SHDNb
5 µA
Ramp Control
SWEN
FLT
25x
PLIM
* Only for Latch Mode
4.17V
I(OUT) > I(CB)
65 Ω
SET
Timeout
25.5 msec
timer
S
Q
2 µA
*TPS26631,
TPS26633, TPS26635
and TPS26636 Only
dVdT
1.2 Meg Ω
CLR
R
Q
3V
MODE
PORb
UVLOb
PORb
14 Ω
Fault Latch
Overload fault response
(Auto-Retry/Latch-off)
select detection
OLR
TSD
SHDNb
GND
PGOOD
Gate Enhanced (HS_FET)
SET
1.3 msec
S
R
Q
Q
1.2V
2.7 V
+
2 µs
65 Ω
1.12V
0.8 V
SHDNb
CLR
SHDNb
+
Fast_Charge
_EN
TPS26632, TPS26633, TPS26635 and TPS26636
SHDN
PGTH
9.3 Feature Description
9.3.1 Hot Plug-In and In-Rush Current Control
The devices are designed to control the inrush current upon insertion of a card into a live backplane or other
"hot" power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended
resets of the system power. The controlled start-up also helps to eliminate conductive and radiative
interferences. An external capacitor connected from the dVdT pin to GND defines the slew rate of the output
voltage at power-on. The fastest output slew rate of 24 V/500 µs can be achieved by leaving dVdT pin floating.
The inrush current can be calculated using 方程式1.
dV
dT
V(IN)
tdVdT
I = Cì
where
í I(INRUSH) = C(OUT) ì
(1)
tdVdT = 20.8 × 103 × V(IN) × C(dVdT)
(2)
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Figure 8-1 illustrates in-rush current control performance of the device during Hot Plug-In.
VIN_SYS
VOUT
PGOOD
IIN
CdVdT = 100 nF
COUT = 1000 µF
RILIM = 4.02 kΩ
图9-1. Hot Plug In and Inrush Current Control at 24-V Input
9.3.1.1 Thermal Regulation Loop
The average power dissipation within the eFuse during power up with a capacitive load can be calculated using
方程式3.
PD(INRUSH) = 0.5ì V(IN) ìI(INRUSH)
(3)
System designs requiring to charge large output capacitors rapidly may result in an operating point that exceeds
the power dissipation versus time boundary limits of the device defined by 图7-18 characteristic curve. This may
result in increase in junction temperature beyond the device's maximum allowed junction temperature. To keep
the junction temperature within the operating range, the thermal regulation control loop regulates the junction
temperature at T(J_REG), 145°C (typical) by controlling the inrush current profile and thereby limiting the power
dissipation within the device automatically. An internal 2.5 seconds (typical) timer starts from the instance the
thermal regulation operation kicks in. If the output does not power up within this time then the internal FET is
turned OFF. Subsequent operation of the device depends on the MODE configuration (Auto-Retry or latch OFF)
setting as shown in 表 9-1. The maximum time-out of 1.25 seconds (typical) in thermal regulation loop operation
ensures that the device and the system board does not heat up during steady fault conditions such as wake up
with output short-circuit. This scheme ensures reliable power up operation.
Thermal regulation control loop is internally enabled during power up by V(IN), UVLO cycling and turn ON using
SHDN control. Figure 8-2 illustrates performance of the device operating in thermal regulation loop during power
up by V(IN) with a large output capacitor. The Thermal regulation loop gets disabled internally after the power up
sequence when the internal FET's gate gets fully enhanced or when the t(Treg_timeout) of 2.5 seconds (typical)
time is elapsed.
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VIN_SYS
VOUT
PGOOD
IIN
CdVdT = Open
COUT = 30 mF
RILIM = 4.02 kΩ
图9-2. Thermal Regulation Loop Response During Power Up with Large Capacitive Load
9.3.2 PGOOD and PGTH
The devices feature an open drain Power good (PGOOD) indicator output. PGOOD can be used for enable and
disable of the downstream loads like DC-DC converters. Connect a resistor ladder network from VOUT, PGTH
and GND to set the PGOOD threshold level. PGOOD goes high when the internal FET’s gate is enhanced and
V(PGTH) is above V(PGTHR). PGOOD goes low when V(PGTH) goes below V(PGTHF). There is a deglitch of tPGOODR
,
1.2 msec (typical) at the rising edge and tPGOODR, 2.1 μs (typical) deglitch on the falling edge of PGOOD
indication. PGOOD is a rated for 60 V and can be pulled to IN_SYS or OUT through a resistor. PGTH can be
used for setting downstream’s supply UVLO levels and PGOOD as enable and disable control.
9.3.2.1 PGTH as VOUT Sensing Input
The devices use PGTH as the output (Load) voltage monitor input and to set the down stream loads UVLO
threshold. To set the input PGTH threshold, connect a resistor divider network from VOUT to PGTH terminal to
GND as shown in the Simplified Schematic. During a system fault recovery (example: OVP high to low or UVLO
low to high) when the internal FET gate control is enabled, the device samples the PGTH information and
decides whether to turn ON the FET with fast slew rate or dVdT mode based on the sampled V(PGTH)
information.
图 8-1 shows the turn ON behavior based on V(PGTH) information. During the fault recovery instance if the
V(PGTH) level is above(PGTHF) then the internal FET turns ON within a delay of tOVP(dly_fast) with fast slew rate
(ignores the capacitance connected at dVdT pin) with thermal regulation loop enabled for a duration of
tCL_PLIM(dly). Maximum current through the device during this operation is limited at I(OL) in TPS26630 and
TPS26632 devices and at 2 x I(OL) in TPS26631, TPS26633, TPS26635 and TPS26636 devices for a maximum
duration of tCB(dly). During the fault recovery instance if the V(PGTH) level is below V(PGTHF) then the device turns
ON the internal FET in dVdT mode and the slew rate will depend on the dVdT capacitor value and maximum
current through the devices is limited at I(OL). This way the device distinguishes between real system faults and
system transients and the turn ON delay is controlled accordingly. This scheme ensures fast recovery during
system tests like voltage interruption and brown-out tests, EMC testing like Electrical Fast Transients
(IEC61000-4-4) and Surge (IEC61000-4-5). The fast turn ON during transient recovery feature can be disabled
by connecting PGTH to GND. In this case, PGOOD will be pulled low.
9.3.3 Undervoltage Lockout (UVLO)
The TPS2663x devices feature an accurate ± 2% adjustable undervoltage lockout functionality. When the
voltage at UVLO pin falls below V(UVLOF) during input undervoltage fault, the internal FET quickly turns off and
FLT is asserted. The UVLO comparator has a hysteresis of 78 mV (typical). To set the input UVLO threshold,
connect a resistor divider network from IN supply to UVLO terminal to GND as shown in the Simplified
Schematic. The TPS2663x devices also features a factory set 15-V input supply undervoltage lockout
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V(IN_SYS_UVLO) threshold with 1-V hysteresis. This feature can be enabled by connecting the UVLO terminal
directly to the GND terminal. If the Undervoltage Lock-Out function is not needed, the UVLO terminal must be
connected to the IN_SYS terminal. UVLO terminal must not be left floating. In the applications where reverse
polarity protection is required connect a minimum of 300-kΩresistor between UVLO and IN_SYS.
图8-1 shows the turn ON behavior when UVLO pin voltage exceeds V(UVLOR) threshold.
9.3.4 Overvoltage Protection (OVP)
The TPS2663x devices incorporate circuitry to protect the system during overvoltage conditions. The TPS26630
and TPS26631 feature an accurate ± 2% adjustable overvoltage cut off functionality. A voltage more than
V(OVPR) on OVP pin turns off the internal FET and protects the downstream load. To program the OVP threshold
externally, connect a resistor divider from IN_SYS supply to OVP terminal to GND as shown in the Simplified
Schematic.
The TPS26630 and TPS26631 also feature a factory set 34.3-V input overvoltage cut off V(IN_SYS_OVP) threshold
with a 440 mV hysteresis. This feature can be enabled by connecting the OVP terminal directly to the GND
terminal. The TPS26632, TPS26633 and TPS26636 feature an internally fixed 35-V maximum overvoltage
clamp V(OVC) functionality. The TPS26632 and TPS26633 clamps the output voltage to V(OVC), when the input
voltage exceeds 35 V. TPS26635 features a fixed 39-V maximum overvoltage clamp level. During the output
voltage clamp operation, the power dissipation in the internal MOSFET is PD = (V(IN_SYS) – V(OVC)) × I(OUT)
.
Excess power dissipation for a prolonged period can increase the device temperature. To avoid this, the internal
FET is operated in overvoltage clamp for a maximum duration of tOVC(dly), 162 msec (typical). After this duration,
the internal FET is turned OFF and the subsequent operation of the device depends on the MODE configuration
(Auto-Retry or latch OFF) setting as shown in 表9-1.
图8-1 shows the turn ON behavior when OVP pin voltage falls below V(OVPF) threshold.
图 9-3 illustrates the overvoltage cut-off functionality and 图 9-4 illustrates the overvoltage clamp functionality.
FLT is asserted after a delay of 617 µs (typical) after entering in overvoltage clamp mode and remains asserted
until the overvoltage fault is removed.
VIN_SYS
VOUT
FLTb
IIN
TPS26630 and TPS26631
TPS26635
RLOAD = 30 Ω, FLT
图9-3. Overvoltage Cut-off Response at 33-V Level
connected to VOUT
图9-4. Overvoltage Clamp Response with
TPS26635
9.3.5 Input Reverse Polarity Protection (B_GATE, DRV)
The TPS2663x devices support the reverse input polarity protection feature. Connect an N-channel power FET
(Q1) with the source to IN_SYS, drain to IN and GATE to B-GATE as shown in 图9-5. This forms a back to back
FET topology in power path that is required to protect the load from input reverse polarity faults. Connect an
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external signal FET (Q2) across BGATE, DRV and IN_SYS. Q2 acts as a pull down gate switch for Q1. In the
applications where reverse polarity protection and reverse current blocking is not required then connect IN_SYS
and IN together. Leave BGATE and DRV open as shown in 图9-6.
Figure 8-7 illustrates the reverse input polarity protection functionality.
The TPS2663x devices support a maximum differential voltage across V(IN_SYS) – V(OUT) upto –85 V. This high
voltage transients generally appear during the IEC61000-4-5 surge testing at the V(IN_SYS). This voltage stress
appears across the external N-channel FET. The TPS2663x provides a gate drive (B_GATE) of 10.2 V (typical).
The fast pull down gate switch Q2 pulls down the GATE of the Q1 during reverse current and reverse polarity
fault events. Q2 should be at least 15-V, VDS rated FET with a maximum VGS rating of 20-V, Ciss ≤50 pF and
VGTH(min) ≤3 V.
N-FET
V(IN_SYS)
V(OUT)
OUT
V(IN_SYS)
V(OUT)
IN
IN
OUT
Q1
B_GATE
B_GATE
DRV
31mΩ
31 mΩ
Q2
DRV
TPS2663x
IN_SYS
IN_SYS
TPS2663x
GND
GND
图9-6. Configuration for Applications Without
Input Reverse Polarity Protection and Reverse
Current Blocking Requirement
图9-5. Configuration for Input Reverse Polarity
Protection and Reverse Current Blocking
VIN_SYS
VOUT
IIN
图9-7. Input Reverse Polarity Response at –60-V Input
9.3.6 Reverse Current Protection
The device monitors V(IN_SYS) and V(OUT) to provide true reverse current blocking when a reverse condition or
input power failure condition is detected. The reverse comparator turns OFF the external blocking FET Q1
quickly as soon as V(IN_SYS) – V(OUT) falls below –1 V. The total time taken to turn OFF the FET Q1 in this
condition is tRCB(fast_dly) + t(Driver). The delay due to the driver stage t(Driver) can be calculated using 方程式4.
t(Driver) = -RDSON(Q2)xCiss(Q1)xln(VGTH
)
(Q1)
VBGATE
(4)
where
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• RDSON(Q2) is the on resistance of the fast pull down switch Q2
• Ciss(Q1) is the input capacitance of the blocking FET Q1
• VGTH(Q1) is the GATE threshold voltage of the blocking FET Q1
• VBGATE = 10.2 V (typical)
In a typical system design, t(Driver) is generally 10% to 20% of tRCB(fast_dly) of 120 nsec (typical).
图 9-8 and 图 9-9 illustrates the behavior of the system during input hot short circuit condition. The blocking FET
Q1 is turned ON within 1.6 ms (typical) once the differential forward voltage V(IN_SYS) – V(OUT) exceeds 67 mV
(typical).
图9-8. Input Hot Short Functionality at 24-V Supply
图9-9. Input Hot-Short: Fast Trip Response
(Zoomed)
The reverse comparator architecture has a supply line noise immunity resulting in a robust performance in noisy
environments. This is achieved by controlling the turn OFF time of the internal FET based on the over-drive
differential voltage V(IN_SYS) –V(OUT) over V(REVTH). Higher the over-drive, faster the turn OFF time, tRCB(dly)
.
9.3.7 Overload and Short Circuit Protection
The device monitors the load current by sensing the voltage across the internal sense resistor. The FET current
is monitored during start-up and normal operation.
9.3.7.1 Overload Protection
Set the current limit using 方程式5
18
IOL
=
R(ILIM
)
(5)
where
• I(OL) is the overload current limit in Ampere
• R(ILIM) is the current limit resistor in kΩ
9.3.7.1.1 Active Current Limiting at 1x IOL, (TPS26630 and TPS26632 Only)
The TPS2663x devices feature accurate overload current limiting and fast short circuit protection feature. With
TPS26630 and TPS26632 if the load current exceeds the programmed current limit IOL, the device regulates the
current through it at IOL eventually reducing the output voltage. The power dissipation across the device during
this operation will be (VIN –VOUT) x IOL and this could heat up the device and eventually enter into thermal
shutdown. The maximum duration for the overcurrent through the FET tCL_PLIM(dly), 162 msec (typical). If the
thermal shutdown occurs before this time the internal FET turns OFF and the subsequent operation (auto-retry
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or latch OFF) will depend on the MODE pin configuration in 表 9-1. Figure 9-10 and Figure 9-11 illustrate
overload current limiting performance.
VOUT
VOUT
FLT
FLT
IIN
IIN
VIN_SYS = 24 V
MODE connected
to GND (Auto-
Retry)
VIN_SYS = 24 V
MODE connected
to GND (Auto-
Retry)
RILIM = 9 kΩ
RILIM = 9 kΩ
图9-10. Overload Performance with TPS26630,
TPS26632 during Load Step from 19 Ωto 9 Ω
图9-11. Response During Coming Out of Overload
Fault
9.3.7.1.2 Active Current Limiting with 2x IOL Pulse Current Support, (TPS26631, TPS26633, TPS26635 and TPS26636
Only)
TPS26631,TPS26633,TPS26635 and TPS26636 after the start-up and with PGOOD high, if the load current
exceeds IOL, then an internal fixed tCB(dly), 25.5 msec (typical) timer starts. During this time the device will pass
through the over current demanded by the load not more than 2 x IOL above which the device will regulate at 2 x
IOL. After tCB(dly) time, the device regulates the current at IOL. The power dissipation across the device during this
operation will be (VIN–VOUT) x IOL and this could heat up the device and eventually enter into thermal shutdown.
The maximum duration for the internal FET in current regulation is tCL_PLIM(dly). The subsequent operation will be
based on the MODE setting (either auto-retry or latch OFF) in 表9-1.
The 2 x I(OL) pulse current support is activated only after PGOOD goes high. If PGOOD is in low state such as
during start-up operation or during auto-retry cycles, the 2 x I(OL) pulse current support is not activated and the
device limits the current at I(OL) level.
图9-12 and 图9-13 illustrate overload current limiting performance.
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VOUT
VOUT
FLT
FLT
IIN
IIN
VIN_SYS = 24 V
MODE connected
to GND (Auto-
Retry)
VIN_SYS = 24 V
MODE connected
to GND (Auto-
Retry)
RILIM = 9 kΩ
RILIM = 9 kΩ
图9-12. Overload Performance with TPS26631,
TPS26633, TPS26635 and TPS26636 during Load
Step from 19 Ωto 9 Ω
图9-13. Response during Coming Out of Overload
Fault
The TPS2663x devices feature ILIM pin short and open fault detection and protection. The internal FET is turned
OFF when ILIM pin is detected short or open to GND and it remains OFF till the ILIM pin fault is removed.
Refer to 图8-2 for more information on tCB(dly) and tCL_PLIM(dly) parameter measurement information.
9.3.7.2 Short Circuit Protection
During a transient output short circuit event, the current through the device increases rapidly. As the current-limit
amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip
comparator. The fast-trip comparator architecture is designed for fast turn OFF tFASTTRIP(dly) = 1 µs (typical) with
I(SCP) = 45 A of the internal FET during an output short circuit event. The fast-trip threshold is internally set to
I(FASTTRIP). The fasttrip circuit holds the internal FET off for only a few microseconds, after which the device turns
back on slowly, allowing the current-limit loop to regulate the output current to I(OL). Then the device functions
similar to the overload condition. Figure 8-14 illustrates output hot-short performance of the device.
VIN_SYS = 24 V
RILIM = 9.09 kΩ
图9-14. Output Hot-Short Response
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The fast-trip comparator architecture has a supply line noise immunity resulting in a robust performance in noisy
environments. This is achieved by controlling the turn OFF time of the internal FET based on the overcurrent
level, I(FASTTRIP) through the device. Higher the overcurrent, faster the turn OFF time, tFASTTRIP(dly). At overload
current level in the range of IFASTTRIP < IOUT < ISCP the fast-trip comparator response is 3.2 μs (typical).
9.3.7.2.1 Start-Up With Short-Circuit On Output
When the device is started with short-circuit on the output, the current begins to limit at I(OL). Due to high power
dissipation of VIN x I(OL) within the device the junction temperature increases. Subsequently, the thermal
regulation control loop limits the load current to regulate the junction temperature at T(J_REG) , 145°C (typical) for
a duration of t(Treg_timeout), 2.5 sec (typical). Subsequent operation of the device depends on the MODE
configuration (Auto-Retry or latch OFF) setting as per the 表 9-1. FLT gets asserted after t(Treg_timeout) and
remains asserted till the output short-circuit is removed. 图 9-15 illustrates the behavior of the device in this
condition.
VIN_SYS
FLTb
IIN
A.
VIN = 24V
RILIM = 3 kΩ
图9-15. Start-Up With Short on Output
9.3.8 Output Power Limiting, PLIM (TPS26632, TPS26633, TPS26635 and TPS26636 Only)
The TPS26630 and TPS26631 devices with a fixed overcurrent limit threshold the maximum output power limit
increases linearly with supply input. Electrical industrial process control equipment such as PLC CPU needs to
comply with standards like IEC61010-1 and UL1310 for fire safety, which require limited energy and power
circuits. Limiting the output power becomes a challenge in such high power applications where the operating
supply voltage range is wide. The TPS26632, TPS26633, TPS26635 and TPS26636 devices integrate
adjustable output power limiting functionality that simplifies the system design requiring compliance in
accordance to this standard.
Connect a resistor from PLIM to GND as shown in 图 9-16 to set the output power limiting value. If output power
limiting is not required then connect PLIM to GND directly. This disables the PLIM functionality.
During an over power load event the TPS26632 limits the output power at the programmed value set by PLIM
resistor. This indirectly results in the device operation in current limiting mode with steady state output voltage
and current set by the load characteristics and PLIM = VOUT × IOUT. 图 7-12 shows the output power limit and
current limit characteristics of TPS26632 with 100 W power limit setting. The maximum duration for the device in
power limiting mode is 162 msec (typical), tCL_PLIM(dly). After this time, the device operates either in auto-retry or
latch off mode based on MODE pin configuration in 表9-1.
During an over power load event the TPS26633, TPS26635 and TPS26636 allows the extra power for a
maximum duration of tCB(dly), 25.5 msec (typical). The maximum power during this time is limited to VOUT x 2 x
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IOL where IOL is the overload current limit set by the R(ILIM) resistor. After the tCB(dly) time, the output power gets
limited to the value programmed by the PLIM resistor. Set the power limit using 方程式6.
P(PLIM) = 1 x R(PLIM)
(6)
Here P(PLIM) is output power limit in watts, R(PLIM) is the power limit setting resistor in kΩ. Figure 9-17 and Figure
9-18 illustrate output power limiting performance of TPS26632 and TPS26633 devices respectively.
Refer to 图8-2 for more information on tCB(dly) and tCL_PLIM(dly) parameter measurement information.
Optional components
for RCB and RPP
4.5 V - 60 V
IN
OUT
COUT
R4
R5
31 mΩ
B_GATE
PGTH
Protected supply
To Load
DRV
PGOOD
FLT
TPS26632/33/35/36
IN_SYS
R1
R2
ON/OFF Control
SHDN
UVLO
IMON
ILIM
Load Monitor
RIMON
PLIM
dVdT
RILIM
MODE
GND
CdVdT
R3
图9-16. TPS26632, TPS26633, TPS26635 and TPS26636 Typical Application Schematic
RPLIM = 100 kΩ
RILIM = 3 kΩ
RPLIM = 100 kΩ
RILIM = 3 kΩ
图9-17. 100 W Class 2, Output Power Limiting
图9-18. 100 W Class 2, Output Power Limiting
Response of TPS26632
Response of TPS26633
9.3.9 Current Monitoring Output (IMON)
The TPS2663x devices feature an accurate analog current monitoring output. A current source at IMON terminal
is internally configured to be proportional to the current flowing from IN to OUT. This current can be converted
into a voltage using a resistor R(IMON) from IMON terminal to GND terminal. The IMON voltage can be used as a
means of monitoring current flow through the system. The maximum voltage (V(IMONmax) for monitoring the
current is limited to 4 V. This puts a limitation on maximum value of R(IMON) resistor and is determined by 方程式
7.
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V
(
IMON
)
= I
[
(
OUT
)
ìGAIN
(
IMON
)
ìR
(
IMON
)
]
(7)
Where,
• GAIN(IMON) is the gain factor I(IMON):I(OUT) = 27.9 μA/A (Typical)
• I(OUT) is the load current
Refer to Figure 6-13 for IMON output versus load current plot. 图9-19 illustrates IMON performance.
VIN_SYS
VOUT
IMON
IIN
图9-19. IMON Response During a Load Step
The IMON pin must not have a bypass capacitor to avoid delay in the current monitoring information.
9.3.10 FAULT Response ( FLT)
The FLT open-drain output asserts (active low) under the faults events such as undervoltage, overvoltage,
overload, power limiting, reverse current, ILIM pin short and thermal shutdown conditions. The device is
designed to eliminate false reporting by using an internal "de-glitch" circuit for fault conditions without the need
for an external circuitry. FLT can be left open or connected to GND when not used.
9.3.11 IN_SYS, IN, OUT and GND Pins
Connect a minimum of 0.1uF capacitor across IN_SYS and GND. For systems and applications where reverse
polarity protection and/or reverse current blocking feature is required
• Connect a N-channel FET between IN_SYS and IN with source of the FET connected to IN_SYS, Drain at IN
and GATE to B_GATE.
• Connect a N-channel signal FET with GATE to DRV, Drain to B_GATE, Source to IN_SYS
If the external N-channel FET is not used then connect IN_SYS and IN together and leave B_GATE and DRV
pins floating as shown in Figure 8-7. Do not leave any of the IN and OUT pins un-connected.
9.3.12 Thermal Shutdown
The device has a built-in overtemperature shutdown circuitry designed to protect the internal FET, if the junction
temperature exceeds T(TSD), 165°C (typical). After the thermal shutdown event, depending upon the mode of
fault response configured as per the 表 9-1, the device either latches off or commences an auto-retry cycle of
648 msec (typical), t(TSD_retry) after TJ < [T(TSD) –11°C]. During the thermal shutdown, the fault pin FLT pulls low
to indicate a fault condition.
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9.3.13 Low Current Shutdown Control (SHDN)
The internal, external FET and hence the load current can be switched off by pulling the SHDN pin below 0.8-V
threshold with a micro-controller GPIO pin or can be controlled remotely with an opto-isolator device. The device
quiescent current reduces to 21 μA (typical) in shutdown state. To assert SHDN low, the pull down must have
sinking capability of at least 10 µA. To enable the device, SHDN must be pulled up to at least 2 V. Once the
device is enabled, the internal FET turns on with dVdT mode. 图 9-20 and 图 9-13 illustrate the performance of
SHDN control.
SHDN
VOUT
SHDN
VOUT
PGOOD
PGOOD
IIN
IIN
VIN = 24 V
C(dVdT) = 22 nF
VIN = 24 V
C(dVdT) = 22 nF
RLOAD = 24 Ω
RLOAD = 24 Ω
图9-20. Turnon Control With SHDN
图9-21. Turnoff Control With SHDN
9.4 Device Functional Modes
The TPS2663x devices respond differently to overload with MODE pin configurations. The operational
differences are explained in 表9-1.
表9-1. Device Operational Differences Under Different MODE Configurations
MODE Pin Configuration
Overload Protection Operation
Device
Active Current limiting at 1x for a maximum duration of tCL_PLIM(dly)
.
There after Latches OFF. Latch reset by toggling SHDN low to high
or UVLO low to high or power cycling IN_SYS.
TPS26630, TPS26632
Open
Active Current limiting at 2x for tCB(dly) duration followed with 1x
current limiting for a maximum duration of tCL_PLIM(dly). There after
Latches OFF. Latch reset by toggling SHDN low to high or UVLO low
to high or power cycling IN_SYS.
TPS26631, TPS26633,
TPS26635, TPS26636
Active Current limiting at 1x for a maximum duration of tCL_PLIM(dly)
There after auto-retries after a delay of t(TSD_retry)
.
TPS26630, TPS26632
.
Shorted to GND
Active Current limiting at 2x for tCB(dly) duration followed with 1x
current limiting for a maximum duration of tCL_PLIM(dly). There after
auto-retries after a delay of t(TSD_retry)
TPS26631, TPS26633,
TPS26635
.
Refer to 图8-2 for more information on tCB(dly) and tCL_PLIM(dly) parameter measurement information.
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The TPS2663x is an industrial eFuse, typically used for Hot-Swap and Power rail protection applications. It
operates from 4.5 V to 60 V with adjustable current limit, output power limit, overvoltage, undervoltage and
reverse polarity protections. The device aids in controlling in-rush current and provides robust protection against
reverse current and filed miss-wiring conditions for systems such as PLCs, Industrial PCs, Control and
Automation and Sensors. The device also provides robust protection for multiple faults on the system rail
The Detailed DesignProcedure section can be used to select component values for the device. Additionally, a
spreadsheet design tool TPS2663 Design Calculator is available in the web product folder.
10.2 Typical Application: Power Path Protection in a PLC System
图10-1. A Typical CPU (PLC Controller) System Block Diagram
The PLC system is usually connected to an external 24-V DC power supply to provide power to the controller
unit, backplane, and I/O modules. Input protection circuits are required to protect the PLC from faults such as
overvoltage, undervoltage, and overload. Because input supply connectors are screw type, there can always be
a possibility of reverse supply connections. Protection circuits should block the reverse polarity to protect the
PLC from possible negative voltages. At the same time, every PLC is tested for electrostatic discharge (ESD)
according to IEC 61000-4-2, burst pulses (EFT) according to IEC 61000- 4-4, energy single pulse (surge)
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according to IEC 61000-4-5, voltage drops and interruptions. 图 10-1 shows a system block diagram of PLC
controller unit along with the input protection socket. The TPS2663x devices offer a plug and play input
protection solution for such applications. For more information about this end equipment refer to the TI
application site on Programmable Logic Controller (PLC), DCS & PAC: CPU (PLC Controller).
Q1
CSD19537Q3
V(IN_SYS): 18 V œ 33 V
IN
OUT
R4
499 k
COUT
1 mF
VIN
CIN
1 µF
B_GATE
PGTH
RPGOOD
24 k
Q2
BSS138
R5
56 k
DC-DC
Converter
DRV
PGOOD
FLT
TPS26630/31
D1
SMCJ36CA
IN_SYS
EN
R1
ON/OFF Control
SHDN
887 k
UVLO
IMON
ILIM
R2
29.4 k
OVP
dVdT
RILIM
R3
MODE
GND
CdVdT
9.09 k
34 k
100 nF
图10-2. 24-V, 2-A eFuse Input Protection Circuit for Industrial PLC, CNC CPU
10.2.1 Design Requirements
表10-1 shows the Design Requirements for TPS2663x.
表10-1. Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
V(IN)
Typical input voltage
24 V
V(UV)
Undervoltage lockout set point
Overvoltage cutoff set point
Overload Current limit
Inrush Current limit
18 V
V(OV)
33 V
I(LIM)
2 A
500 mA
I(INRUSH)
P(OUT)
T(FAIL_TR)
P(Surge)
Output Load
15 W (DC-DC) with 15 V VINminDC-DC
10 msec
Power Interruption time
IEC61000-4-5 Surge test level
± 500 V, 2 Ωgenerator impedance
10.2.2 Detailed Design Procedure
10.2.2.1 Programming the Current-Limit Threshold—R(ILIM) Selection
The R(ILIM) resistor at the ILIM pin sets the overload current limit, this can be set using 方程式8.
18
R(ILIM
=
= 9kW
)
IOL
(8)
where
• ILIM = 2 A
Choose the closest standard 1% resistor value : R(ILIM) = 9.09 kΩ
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10.2.2.2 Undervoltage Lockout and Overvoltage Set Point
The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using an external voltage divider
network of R1, R2 and R3 connected between IN_SYS, UVLO, OVP and GND pins of the device. The values
required for setting the undervoltage and overvoltage are calculated by solving 方程式9 and 方程式10.
R3
V(OVPR) =
ì V(OV)
R1+ R2 + R3
(9)
R2 + R3
R1+ R2 + R3
V(UVLOR) =
ì V(UV)
(10)
For minimizing the input current drawn from the power supply {I(R123) = V(IN) / (R1 + R2 + R3)}, it is recommended
to use higher value resistance for R1, R2 and R3.
However, the leakage current due to external active components connected at resistor string can add error to
these calculations. So, the resistor string current, I(R123) must be chosen to be 20x greater than the leakage
current of UVLO and OVP pins.
From the device electrical specifications, V(OVPR) = 1.2 V and V(UVLOR) = 1.2 V. From the design requirements,
V(OV) is 33 V and V(UV) is 18 V. To solve the equation, first choose the value of R3 = 34 kΩ and use 方程式 9 to
solve for (R1 + R2) = 916 kΩ. Use 方程式 10 and value of (R1 + R2) to solve for R2 = 29.4 kΩ and finally R1= 887
kΩ.
Choose the closest standard 1% resistor values: R1 = 887 kΩ, R2 = 29.4 kΩ, and R3 = 34 kΩ.
The UVLO and the OVP pins can also be connected to the GND pin to enable the internal default V(OV) = 34.2 V
and V(UV) = 15.6 V.
10.2.2.3 Output Buffer Capacitor –COUT
During the power interruption time TFAIL_TR the output capacitor COUT of the TPS26630 provides energy to the
15 W DC-DC converter load. Use 方程式11 to compute the required buffer capacitor COUT
2ìP(DC-DC)ìTFAIL _ TR
COUT
=
V
2 -V
2
(IN_ SYS)
(UV _DC-DC)
(11)
where
• P(DC-DC) = 15 W/η. Assuming efficiency of 95%, P(DC-DC) = 15.8 W
• TFAIL_TR = 10 msec
• V(IN_SYS) = 24 V
• V(UV_DC-DC) = 15 V
COUT = 0.9 mF. Choose a capacitor with ±10% tolerance, COUT = 1 mF/35 V electrolytic capacitor. Figure 9-4 and
图 10-5 illustrate the performance during the power interruption tests on TPS26630. Figure 9-8 illustrate the
performance on TPS26631.
10.2.2.4 PGTH Set Point
Set the VPGTHF threshold at the down-stream DC-DC converter UVLO falling threshold. VIN minimum operating
voltage of the DC-DC converter is at 15 V. Assuming UVLO to be at 20% lower level, VUVLO_DC-DC = 12 V. Use
方程式12 to calculate R4 and R5.
R5
V
=
x VUVLO_DC-DC
(PGTHF)
R4 +R5
(12)
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V(PGTHF) = 1.14 V. Assuming R5 = 56 kΩ, R4 comes out to be approximately 499 kΩ.
10.2.2.5 Setting Output Voltage Ramp Time—(tdVdT
)
Use 方程式 1 and 方程式 2 to calculate required C(dVdT) for achieving an inrush current of 500 mA. C(dVdT) = 0.1
µF. Figure 9-3 illustrates the inrush current limiting performance during 24-V hot-plug in condition.
10.2.2.5.1 Support Component Selections—RPGOOD and C(IN)
The RPGOOD serves as pull-up for the open-drain output. The current sink by this pin must not exceed 10 mA
(see the Absolute Maximum Ratings table). Typical resistance value in the range of 10 kΩ to 100 kΩ is
recommended for RPGOOD. Connect PGOOD directly to the EN pin of the DC-DC converter. 图 10-6 and Figure
9-8 illustrate the power up and power down performance of the system respectively. The CIN is a local bypass
capacitor to suppress noise at the input. A minimum of 1 µF is recommended for C(IN) for limit the slew rates
during the surge test.
10.2.2.6 Selecting Q1, Q2 and TVS Clamp for Surge Protection
For ±500-V, 2-Ωsurge, typically a SMC sized TVS like SMCJ36CA clamps the voltage around ±55 V. During the
negative surge strike, the input voltage VIN_SYSspikes to –55 V. This results in a voltage stress of –(55 V + 24
V) = –79 V across the external blocking FET Q1. Choose at least a 80-V rated N-channel FET. B_GATE drive is
in the range of 10 V to 14 V. Select a suitable FET with the target RDSON specified at this gate drive voltage.
The fast pull down gate switch Q2 pulls down the GATE of the Q1 during the reverse current event appearing
during the surge test. Q2 should be at least 15-V VDS rated FET with a maximum VGS rating of 20-V , Ciss <=
50 pF and VGTH(min) ≤ 3 V. CSD19537Q3 and BSS138 are selected for Q1 and Q2 respectively. Figure 9-9
and Figure 9-10 illustrate the performance of the system during the surge testing.
10.2.3 Application Curves
VIN_SYS
VOUT
PGOOD
IIN
图10-4. Voltage Interruption Response With
图10-3. Hot-Plug In at 24-V Supply
TPS26630
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VIN_SYS
VOUT
PGOOD
IIN
图10-5. Voltage Interruption Response With
图10-6. Power Up Followed With Voltage
TPS26630 (Zoomed)
Interruption With TPS26630
VIN_SYS
VOUT
PGOOD
VOUT_DC/DC
图10-7. Voltage Interruption Performance With
图10-8. Power Down Response
TPS26631
VIN_SYS
VOUT
VIN_SYS
VOUT
PGOOD
ISURGE
PGOOD
ISURGE
图10-9. 500-V, 2-ΩSurge Response
图10-10. –500-V, 2-ΩSurge Response
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10.3 System Examples
10.3.1 Simple 24-V Power Supply Path Protection
With the TPS2663x devices, a simple 24-V power supply path protection can be realized using a minimum of five
external components as shown in the schematic diagram in 图 10-11. The external components required are: a
N–Channel Power FET Q1, a N–Channel signal FET Q2 and a R(ILIM) resistor to program the current limit, C(IN)
and C(OUT) capacitors.
Optional components
for RCB and RPP
Q1
V(IN_SYS): 18 V œ 33 V
IN
OUT
COUT
CIN
31 mΩ
B_GATE
PGTH
Q2
DRV
Load Enable /
Disable Control
PGOOD
FLT
TPS26630
IN_SYS
Health Monitor
ON/OFF Control
SHDN
IMON
ILIM
UVLO
OVP
dVdT
RILIM
MODE
GND
图10-11. TPS26630 Configured for a Simple 24-V Supply Path Protection
Protection features with this configuration include:
• Load and device protection from reverse input polarity fault down to –60 V (with a 60-V rated Q1)
• Overvoltage Protection at 34 V
• Inrush current control with 24-V/240-µs output voltage slew rate
• Reverse Current Blocking
• Accurate current limiting with Auto-Retry
10.3.2 Priority Power MUX Operation
Applications having two energy sources such as Portable battery powered equipment require preference of one
source to another. For example, mains power (wall-adapter) has the priority over the internal back-up power or
auxiliary power. These applications demand for switch over from mains power to backup power only when main
input voltage falls below a user defined threshold. The TPS2663x devices provide a simple solution for priority
power multiplexing needs.
图 10-12 shows a typical priority power multiplexing implementation using devices. When the MAIN power is
present, the device in VIN_MAIN path powers the OUT bus irrespective of whether auxiliary power VIN_AUX is
greater than or less than VIN_MAIN. Once the voltage on the VIN_MAIN rail falls below the user-defined
threshold, the device VIN_MAIN issues a signal to switch over to auxiliary power VIN_AUX. The transition
happens seamlessly in tOVP(dly_fast), with minimal voltage droop on the output. The voltage droop during
transition is a function of load current and output capacitance. See 方程式13.
I(LOAD)xtOVP fast _ dly
(
C(OUT)
)
V
=
(DROOP)
(13)
where
• V(DROOP) is in volts, I(LOAD) is load current in Ampere, C(OUT) is output capacitance in µF, tOVP(fast_dly) = 140 µs
(typical)
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Figure 9-13, Figure 9-14, Figure 9-15 and figure 9-16 show typical switch-over waveforms of Priority Muxing
implementation using the TPS26630 or TPS26631 for 20-V Primary and 24-V Auxiliary Bus.
Q1
VIN_MAIN
IN
OUT
R4
R5
31 mΩ
B_GATE
PGTH
PGTH
Q2
DRV
PGOOD
FLT
TPS26630
IN_SYS
R1
R2
R3
ON/OFF Control
SHDN
UVLO
VOUT
IMON
ILIM
Main Load
Monitor
OVP
dVdT
RILIM
RIMON
MODE
GND
CdVdT
Q3
VIN_AUX
IN
OUT
COUT
31 mΩ
B_GATE
PGTH
PGTH
Q4
DRV
PGOOD
FLT
TPS26630
IN_SYS
R6
ON/OFF Control
SHDN
UVLO
Aux
Load Monitor
IMON
ILIM
R7
Q5
RILIM
OVP
dVdT
RILIM
CdVdT
GND
MODE
R8
图10-12. Priority Power Mux Implementation
图10-13. VIN_MAIN Power Recovery: Change Over 图10-14. VIN_MAIN Brownout Condition: Change
from Auxiliary VIN_AUX to Primary Power
VIN_MAIN
Over from Main VIN_MAIN to Auxiliary Power
VIN_AUX
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图10-15. VIN_AUX Brownout Condition
图10-16. VIN_AUX Power Recovery
10.3.3 Input Protection for a Compact 24-V Auxiliary Power Supply for Servo Drives
TPS2663x eFuse protects the system from common faults such as reverse polarity, reverse power flow,
overvoltage, undervoltage and overcurrents along with a robust EMC immunity performance. Refer to, Compact,
efficient, 24-V input auxiliary power supply reference design for servo drives TI Design Guide for further
information.
10.4 Do's and Don'ts
• In the applications where reverse polarity protection is required use external FETs Q1 and Q2.
• Connect at least a 300-kΩresistor across UVLO and IN_SYS in the applications where reverse polarity
protection is required.
11 Power Supply Recommendations
The TPS2663x eFuse is designed for the supply voltage range of 4.5 V ≤ VIN ≤ 60 V. If the input supply is
located more than a few inches from the device, an input ceramic bypass capacitor higher than 0.1 μF is
recommended. Power supply must be rated higher than the current limit set to avoid voltage droops during
overcurrent and short circuit conditions.
11.1 Transient Protection
In case of short circuit and overload current limit, when the device interrupts current flow, input inductance
generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the
output. The peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the
input or output of the device. These transients can exceed the Absolute Maximum Ratings of the device if steps
are not taken to address the issue.
Typical methods for addressing transients include:
• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Use of a Schottky diode across the output and GND to absorb negative spikes
• A low value ceramic capacitor (C(IN) to approximately 0.1 μF) to absorb the energy and dampen the
transients.
The approximate value of input capacitance can be estimated with 方程式14
L IN
( )
Vspike Absolute = V IN + I Load
( ) )
´
(
)
(
C IN
( )
(14)
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where
• V(IN) is the nominal supply voltage
• I(LOAD) is the load current
• L(IN) equals the effective inductance seen looking into the source
• C(IN) is the capacitance present at the input
Some applications may require additional Transient Voltage Suppressor (TVS) to prevent transients from
exceeding the Absolute Maximum Ratings of the device. These transients can occur during positive and
negative surge tests on the supply lines. In such applications it is recommended to place at least 1 µF of input
capacitor.
The circuit implementation with optional protection components (a ceramic capacitor, TVS and schottky diode) is
shown in Figure 10-1.
Input
Output
*
IN
OUT
R4
COUT
31 mΩ
B_GATE
PGTH
*
DRV
PGOOD
FLT
TPS2663x
IN_SYS
R1
R2
R3
ON/OFF Control
SHDN
UVLO
IMON
ILIM
OVP
dVdT
RILIM
MODE
GND
CdVdT
* Optional components needed for suppression of transients
图11-1. Circuit Implementation with Optional Protection Components for TPS2663x
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12 Layout
12.1 Layout Guidelines
• For all the applications, a 0.1 µF or higher value ceramic decoupling capacitor is recommended between
IN_SYS terminal and GND.
• The external FET Q1 should be placed with DRAIN close to the VIN pins of the IC and connected through a
plane. The fast pull down switch Q2 DRAIN and SOURCE should be placed very close to the GATE and
SOURCE terminals of Q1 with very short loop. See 图12-1 and 图12-2 for a typical PCB layout example.
• The optimum placement of decoupling capacitor is closest to the IN_SYS and GND terminals of the device.
Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN_SYS
terminal, and the GND terminal of the IC.
• High current carrying power path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
• Locate all the TPS2663x family support components R(ILIM), C(dVdT), R(IMON), UVLO, OVP and PGTH resistors
close to their connection pin. Connect the other end of the component to the GND with shortest trace length.
• The trace routing for the RILIM component to the device must be as short as possible to reduce parasitic
effects on the current limit and current monitoring accuracy. These traces must not have any coupling to
switching signals on the board.
• Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, a
protection Schottky diode is recommended to address negative transients due to switching of inductive loads,
and it must be physically close to the OUT and GND pins.
• Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater
cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board GND plane
directly under the device. Other planes, such as the bottom side of the circuit board can be used to increase
heat sinking in higher current applications.
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12.2 Layout Example
Top Layer
Bottom layer GND plane
Top Layer GND Plane
Via to Bottom Layer
BOTTOM Layer GND Plane
High
Frequency
Bypass cap
Q1
D2
D1
S
D
D
D
VIN_SYS PLANE
S
VOUT PLANE
S
G
OUT
OUT
IN
IN
D
G
D
S
BGATE
PGOOD
Q2
DRV
IN_SYS
UVLO
PGTH
FLT
IMON
TOP Layer
GND Plane
BOTTOM Layer GND Plane
图12-1. Typical PCB Layout Example With QFN Package With a 2 Layer PCB
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Top Layer
Bottom layer GND plane
Top Layer GND Plane
Via to Bottom Layer
BOTTOM Layer GND Plane
High
Frequency
Bypass cap
Q1
D2
D1
S
D
D
D
VIN_SYS PLANE
S
VOUT PLANE
S
IN
OUT
G
S
OUT
OUT
IN
D
G
D
IN
PGOOD
PGTH
BGATE
DRV
IN_SYS
UVLO
Q2
FLT
IMON
OVP
GND
SHDN
MODE
dVdT
ILIM
TOP Layer
GND Plane
BOTTOM Layer GND Plane
图12-2. Typical PCB Layout Example With HTSSOP Package With a 2 Layer PCB
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
• TPS2663 Design Calculator
• CPU (PLC Controller)
• Compact, efficient, 24-V input auxiliary power supply reference design for servo drives
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
42
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Product Folder Links: TPS2663
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OUTLINE
PWP0020T
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
3
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
0.1 C
A
PIN 1 INDEX
AREA
18X 0.65
SEATING
20
PLANE
1
2X
6.6
6.4
5.85
NOTE 3
10
11
0.30
20X
4.5
4.3
0.19
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 1.15 MAX
NOTE 5
11
10
2X 0.3 MAX
NOTE 5
0.25
1.2 MAX
GAGE PLANE
21
2.96
2.21
0.15
0.05
0.75
0.50
THERMAL
PAD
0 -8
A
15
DETAIL A
TYPICAL
1
20
2.96
2.16
4224598/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0020T
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(2.96)
METAL COVERED
BY SOLDER MASK
20X (1.5)
SYMM
1
20
20X (0.45)
(R0.05) TYP
(1.3)
TYP
(6.5)
NOTE 9
21
SYMM
(2.96)
SOLDER MASK
DEFINED PAD
18X (0.65)
10
11
(1.3) TYP
SEE DETAILS
(
0.2) TYP
VIA
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
15.000
SOLDER MASK DETAILS
4224598/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0020T
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.96)
BASED ON
0.125 THICK
STENCIL
METAL COVERED
BY SOLDER MASK
20X (1.5)
1
20
20X (0.45)
(R0.05) TYP
SYMM
21
(2.96)
BASED ON
0.125 THICK
STENCIL
18X (0.65)
11
10
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.31 X 3.31
2.96 X 2.96 (SHOWN)
2.70 X 2.70
0.125
0.15
0.175
2.50 X 2.50
4224598/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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