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TPS25810A-Q1

ZHCSGW8 –APRIL 2017

具有数字电缆补偿功能的 TPS25810A-Q1 USB Type-C DFP 控制器和电源

开关

1 特性

•

固定 3.4A I_LIM(±7.1%)

数字电缆补偿，I_OUT≥ 1.95A

封装：20 引脚 WQFN (3mm × 4mm)

1

•

符合汽车应用要求

具有符合 AEC-Q100 标准的下列特性：

(1)

–

器件温度等级 T：环境工作温度范围为 –40°C

至 105°C

2 应用

•

汽车信息娱乐系统

汽车后座 USB 充电

器件人体模型 (HBM) 静电放电 (ESD) 分类等级

2

器件组件充电模式 (CDM) ESD 分类等级 C4B

3 说明

•

兼容 USB Type-C 版本 1.2 的下行数据端口 (DFP)

控制器

TPS25810A-Q1 器件一款 USB Type-C 下行端口

(DFP) 控制器，集成了一个额定电流为 3A 的 USB 电

源开关。此器件通过监测 Type-C 配置通道 (CC) 线路

来发现连接的 USB 设备。如果连接了上行端口 (UFP)

器件，它会向 V_BUS供电，并将可选 V_BUS拉电流能力

通过直通 CC 线路传达给 UFP。如果使用电子标记电

缆连接了 UFP，它还会将 V_CONN电源施加于电缆 CC

引脚。当连接 Type-C 音频附件或调试附件

•

连接器连接或断开的检测

配置通道 (CC) STD、1.5A、3A 电流能力通告

超高速极性的确定

V_BUS应用和放电

V_CONN应用于电子标记电缆

音频和调试附件的识别

端口未连接时，I_DDQ的典型值为 0.7µA

三个输入电源选项

时，TPS25810A-Q1 可以识别并报告此连接。

–

IN1：USB 充电电源

IN2：V_CONN电源

AUX：器件电源

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

超薄四方扁平无引线

(WQFN) (20)

TPS25810A-Q1

3.00mm x 4.00mm

•

电源唤醒可保证系统冬眠 (S4) 和关闭 (S5) 功耗状

态下的低功耗

(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

(1) CC 引脚符合 IEC-61000-4-2 标准

34mΩ（典型值）高侧金属氧化物半导体场效应晶

体管 (MOSFET)

简化原理图

6 ´ 100 kW

TPS25810A-Q1

(optional)

V_BUS

Bus Power

CC Power

4.5 V– 6.5 V

4.5 V– 5.5 V

2.9 V– 5.5 V

120 µF

IN1

OUT

IN2

FAULT

Power-Switch

Status Signals

Auxiliary Power

AUX

CS

CC1

CC2

UFP

EN

10 µF

Control Signals

CHG

CHG_HI

REF

POL

Type-C DFP

Status Signals

AUDIO

100 kW (1%)

DEBUG

REF_RTN

GND

Thermal Pad

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSE37

TPS25810A-Q1

ZHCSGW8 –APRIL 2017

www.ti.com.cn

8.4 Device Functional Modes........................................ 22

Application and Implementation ........................ 24

9.1 Application Information............................................ 24

9.2 Typical Applications ................................................ 24

1

2

3

4

5

6

7

特性.......................................................................... 1

9

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 6

7.6 Switching Characteristics.......................................... 8

7.7 Typical Characteristics............................................ 10

Detailed Description ............................................ 12

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram ....................................... 14

8.3 Feature Description................................................. 14

10 Power Supply Recommendations ..................... 29

11 Layout................................................................... 30

11.1 Layout Guidelines ................................................. 30

11.2 Layout Example .................................................... 31

12 器件和文档支持 ..................................................... 32

12.1 器件支持 ............................................................... 32

12.2 文档支持 ............................................................... 32

12.3 接收文档更新通知 ................................................. 32

12.4 社区资源................................................................ 32

12.5 商标....................................................................... 32

12.6 静电放电警告......................................................... 32

12.7 Glossary................................................................ 32

13 机械、封装和可订购信息....................................... 32

8

4 修订历史记录

日期

修订版本

注

2017 年 4 月

*

初始发行版

2

TPS25810A-Q1

www.ti.com.cn

ZHCSGW8 –APRIL 2017

5 说明（续）

未连接 USB 负载时，TPS25810A-Q1 器件从 AUX 引脚上消耗的电流小于 0.7μA（典型值）。未连接 UFP 时，此

器件通过使用 UFP 输出对 5V 高功率电源进行禁用，从而可在 S4 和 S5 系统功耗状态下进一步实现系统节能。在

此模式下，该器件能够由电压较低 (3.3V) 的辅助电源 (AUX) 供电运行，该电源通常在低功耗状态（S4 和 S5）下

为系统微控制器供电。

TPS25810A-Q1 器件集成了一个 34mΩ 电源开关，且无论 Type-C 电流通告级别为何，均具有固定的 3.4A 电流限

制。FAULT 输出在开关处于过流和过热条件时发出信号。CS 输出用于实现负载电流大于 1.95A 的数字电缆补偿。

电缆补偿也称为线路压降补偿，是将 USB 电源的电压降补偿到 UFP 负载的一种手段。

3

TPS25810A-Q1

ZHCSGW8 –APRIL 2017

www.ti.com.cn

6 Pin Configuration and Functions

TPS25810A-Q1 RVC Package

20-Pin WQFN With Exposed Thermal Pad

Top View

FAULT

IN1

1

2

3

4

5

6

16

15

14

13

12

11

DEBUG

OUT

Thermal

Pad

IN1

OUT

IN2

CC2

AUX

EN

GND

CC1

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

AUDIO

NO.

Open-drain logic output that asserts when a Type-C audio accessory is identified on

the CC lines

17

O

I

Auxiliary input supply. Connect to an always-alive system rail to use the power-wake

feature. Short to IN1 and IN2 if only one supply is used.

AUX

5

CC1

CC2

11

13

I/O

Analog input/output that connects to the Type-C receptacle CC1 pin

Analog input/output that connects to the Type-C receptacle CC2 pin.

Charge-logic input to select between standard USB (500 mA for a Type-C receptacle

supporting only USB 2.0, and 900 mA for Type-C receptacle supporting USB 3.1) or a

Type-C current-sourcing ability.

CHG

7

I

High-charge logic input to select between 1.5-A and 3-A Type-C current sourcing

capability. Valid when CHG is set to Type-C current.

CHG_HI

CS

8

I

Open-drain output enabling digital cable compensation when load current is greater

than 1.95 A, nominal.

20

O

Open-drain logic output that asserts when a Type-C debug accessory is identified on

the CC lines

DEBUG

EN

16

6

O

I

Enable logic input. Turns the device on and off

Fault event indicator. Open-drain logic output that asserts low to indicate a current-

limit or thermal-shutdown event due to overtemperature.

FAULT

1

O

GND

IN1

12

—

I

Power ground

2, 3

V_BUSinput supply. Internal power switch connects IN1 to OUT.

V_CONNinput supply. Internal power switch connects IN2 to CC1 or CC2. Short to IN1 if

only one supply is used.

IN2

4

I

OUT

14, 15

O

Power switch output

Polarity open-drain logic output that signals which Type-C CC pin is connected to the

CC line. This gives the information needed to multiplex the super-speed lines.

Asserted when the CC2 pin is connected to the CC line in the cable.

POL

18

O

Analog input used to generate the internal current reference. Connect a 1% or better,

100-ppm, 100-kΩ resistor between this pin and REF_RTN.

REF

10

I

REF_RTN

UFP

9

I

Precision signal-reference return. Connect to the REF pin via a 100-kΩ, 1% resistor.

19

O

Open-drain logic output that asserts when a Type-C UFP is identified on the CC lines.

Thermal pad on the bottom of the package. The thermal pad is internally connected to

GND and is used to heat-sink the device to the circuit board. Connect the thermal pad

to the GND plane.

Thermal

pad

—

4

TPS25810A-Q1

www.ti.com.cn

ZHCSGW8 –APRIL 2017

7 Specifications

7.1 Absolute Maximum Ratings

(1)

over operating ambient temperature range, voltages are with respect to GND (unless otherwise noted)

MIN

MAX

UNIT

AUDIO, AUX, CC1, CC2, CHG, CHG_HI, CS, DEBUG, EN,

FAULT, IN1, IN2, OUT, POL, REF, UFP,

–0.3

7

V

Pin voltage, V

Internally

connected

to GND

REF_RTN

V

Internally

limited

Pin positive source current, I_SRC

Pin positive sink current, I_SNK

CC1, CC2, OUT, REF

A

OUT (while applying V_BUS

)

5

1

A

CC1, CC2 (while applying V_CONN

)

Internally

limited

AUDIO, CS, DEBUG, FAULT, POL, UFP

mA

Operating junction temperature, T_J

Storage temperature range, T_stg

–40

–65

180

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2 000

±500

UNIT

Human-body model (HBM), per per AEC Q100-002⁽²⁾

Charged-device model (CDM), per per AEC Q100-011

61000-4-2 contact discharge, CC1 and CC2⁽³⁾IEC

IEC 61000-4-2 air discharge, CC1 and CC2⁽³⁾

Electrostatic

discharge

(1)

V_(ESD)

V

±8 000

±15 000

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

into the device.

(2) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(3) Surges per IEC61000-402, 1999 applied between CC1, CC2 and output ground of the TPS25810EVM-745.

7.3 Recommended Operating Conditions

Voltages are with respect to GND (unless otherwise noted)

MIN NOM

MAX UNIT

IN1

4.5

2.9

0

6.5

V_IN

Supply voltage

IN2

5.5

V

AUX

V_I

Input voltage

CHG, CHG_HI, EN

V

V_IH

V_IL

V_PU

High-level input voltage

Low-level voltage

Pullup voltage

CHG, CHG_HI, EN

1.17

CHG, CHG_HI, EN

0.63

5.5

3

V

Used on AUDIO, CS, DEBUG, FAULT, POL, UFP,

OUT

0

V

A

I_SRC

I_SNK

Positive source current

CC1 or CC2 when supplying V_CONN

250

mA

Positive sink current (10 ms moving

average)

AUDIO, CS, DEBUG, FAULT, POL, UFP

10

mA

Internally

limited

I_{SNK_PULSE}Positive repetitive pulse sink current AUDIO, CS, DEBUG, FAULT, POL, UFP

R_REF

T_J

Reference resistor

98

100

102

125

kΩ

Operating junction temperature

–40

°C

5

TPS25810A-Q1

ZHCSGW8 –APRIL 2017

www.ti.com.cn

7.4 Thermal Information

TPS25810A-Q1

THERMAL METRIC⁽¹⁾

RVC (WQFN)

UNIT

20 PINS

39.3

43.4

13

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.7

ψ_JB

13

R_θJC(bot)

4.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Electrical Characteristics

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF

=

100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined as positive out of the indicated

pin (unless otherwise noted)

PARAMETER

OUT – POWER SWITCH

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_J= 25°C, I_OUT= 3 A

34

37

46

55

r_DS(on)

On-resistance⁽¹⁾

–40°C ≤ T_J≤ 85°C, I_OUT= 3 A

–40°C ≤ T_J≤ 125°C, I_OUT= 3 A

V_OUT= 6.5 V, V_IN1= V_EN= 0 V,

mΩ

I_REV

OUT to IN reverse leakage current –40°C ≤ T_J≤ 85°C,

0

3

µA

I_REVis current out of IN1 pin

OUT – CURRENT LIMIT

3.16

3.4

3.64

7

(1)

I_OS

Short-circuit current limit

A

R_REF= 10 Ω

OUT – DISCHARGE

V_OUT= 4 V, UFP signature removed from

CC lines, time < t_{w_DCHG}

Discharge resistance

400

100

500

150

600

250

Ω

V_OUT= 4 V, No UFP signature on CC lines,

time > t_{w_DCHG}

Bleed discharge resistance

kΩ

REF

V_O

Output voltage

0.78

9.5

0.8

0.82

15.3

V

I_OS

Short circuit current

R_REF= 10 Ω

µA

FAULT

V_OL

I_OFF

CS

Output low voltage

Off-state leakage

I_FAULT= 1 mA

V_FAULT= 5.5 V

350

1

mV

µA

V_OL

I_OFF

Output low voltage

Off-state leakage

I_CS= 1 mA

V_CS= 5.5 V

350

1

mV

µA

OUT sourcing, rising threshold

current for load detect

Hysteresis⁽²⁾

I_TH

1.8

1.95

125

2.1

A

mA

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account

separately.

(2) These parameters are provided for reference only and do not constitute part of TI’s published specifications for purposes of TI’s product

warranty.

6

TPS25810A-Q1

www.ti.com.cn

ZHCSGW8 –APRIL 2017

Electrical Characteristics (continued)

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF

=

100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined as positive out of the indicated

pin (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CC1, CC2 – V_CONNPOWER SWITCH

T_J= 25°C, I_OUT= 250 mA

365

420

530

600

r_DS(on)

On-resistance

–40°C ≤ T_J≤ 85°C, I_OUT= 250 mA

–40°C ≤ T_J≤ 125°C, I_OUT= 250 mA

mΩ

CC1, CC2 – V_CONNPOWER SWITCH – CURRENT LIMIT

300

355

410

800

I_OS

Short-circuit current limit⁽¹⁾

mA

µA

R_REF= 10 Ω

CC1, CC2 – CONNECT MANAGEMENT – DANGLING ELECTRONICALLY MARKED CABLE MODE

Sourcing current on the pass-

0 V ≤ V_CCx≤ 1.5 V

64

80

96

through CC Line

I_SRC

Sourcing current on the Ra CC

0 V ≤ V_CCx≤ 1.5 V

line

CC1, CC2 – CONNECT MANAGEMENT – ACCESSORY MODE

CCx sourcing current

0 V ≤ V_CCx≤ 1.5 V

64

80

0

96

(CC2 – audio, CC1-debug)

I_SRC

µA

CCx sourcing current

0 V ≤ V_CCx≤ 1.5 V

(2)

(CC1 – audio, CC2-debug)

CC1, CC2 – CONNECT MANAGEMENT – UFP MODE

0 V ≤ V_CCx≤ 1.5 V

V_IN1< V_{TH_UVLO_IN1}or V_IN2< V_{TH_UVLO_IN2}

Sourcing current with either IN1 or

IN2 in UVLO

I_SRC

64

75

80

96

85

V_CHG= 0 V and V_{CHG_HI}= 0 V

0 V ≤ V_CCx≤ 1.5 V

V_CHG= V_AUXand V_{CHG_HI}= 0 V

0 V ≤ V_CCx≤ 1.5 V

I_SRC

Sourcing current

170

312

180

330

190

348

V_CHG= V_AUXand V_{CHG_HI}= V_AUX

0 V ≤ V_CCx≤ 2.45 V

UFP, POL, AUDIO, DEBUG

V_OL

I_OFF

Output low voltage

Off-state leakage

I_{SNK_PIN}= 1 mA

V_PIN= 5.5 V

250

1

mV

µA

EN, CHG, CHG_HI – LOGIC INPUTS

V_TH

Rising threshold voltage

Falling threshold voltage

Hysteresis⁽²⁾

0.925

0.875

50

1.15

0.5

V

0.65

–0.5

mV

µA

I_IN

Input current

V_EN= 0 V or 6.5 V

OVERTEMPERATURE SHUTDOWN

Rising threshold temperature for

device shutdown

Hysteresis⁽²⁾

T_{TH_OTSD2}

155

135

°C

20

Rising threshold temperature for

OUT/ V_CONNswitch shutdown in

current limit

Hysteresis⁽²⁾

T_{TH_OTSD1}

°C

IN1

V_{TH_UVLO_IN1}Rising threshold voltage for UVLO

Hysteresis⁽²⁾

3.9

4.1

4.3

V

100

mV

µA

I_IN1(DIS)

Disabled supply current

V_EN= 0 V, –40°C ≤ T_J≤ 85°C

–40°C ≤ T_J≤ 85°C

1

Enabled supply current with CC

lines open

I_{IN1(CC_OPEN)}

µA

7

TPS25810A-Q1

ZHCSGW8 –APRIL 2017

www.ti.com.cn

Electrical Characteristics (continued)

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF

=

100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined as positive out of the indicated

pin (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Enabled supply current with

accessory or dangling

electronically marked cable

signature on CC lines

I_IN1(Ra)

2

µA

V_CHG= 0 V, or V_CHG= V_AUXand V_{CHG_HI}

0 V

=

75

85

100

110

Enabled supply current with UFP

attached

I_IN1(Rd)

µA

IN2

V_{TH_UVLO_IN2}Rising threshold voltage for UVLO

Hysteresis⁽²⁾

3.9

4.1

4.3

V

100

mV

µA

I_IN2(DIS)

Disabled supply current

V_EN= 0 V, –40°C ≤ T_J≤ 85°C

–40°C ≤ T_J≤ 85°C

1

I_{IN2(CC_OPEN)}Enabled supply current with CC

lines open

µA

Enabled supply current with

accessory or dangling

electronically marked cable

I_IN2(Ra)

2

µA

signature on CC lines

Enabled supply current with UFP

signature on CC lines

(Includes IN current that provides

the CC output current to the UFP

Rd resistor)

V_CHG= 0 V, 0 V ≤ V_CCx≤ 1.5 V

98

198

348

110

215

373

V_CHG= V_INand V_{CHG_HI}= 0 V, 0 V ≤ V_CCx

1.5 V

≤

I_IN2(Rd)

µA

0 V ≤ V_CCx≤ 2.45 V

AUX

V_{TH_UVLO_AUX}Rising threshold voltage for UVLO

Hysteresis⁽²⁾

2.65

2.75

100

2.85

V

mV

µA

I_AUX(DIS)

Disabled supply current

V_EN= 0 V, –40°C ≤ T_J≤ 85°C

–40°C ≤ T_J≤ 85°C

1

3

Enabled internal supply current

with CC lines open

I_{AUX(CC_OPEN)}

0.7

µA

Enabled supply current with

accessory or dangling active cable

signature on CC lines

I_AUX(Ra)

140

185

µA

Enabled supply current with UFP

termination on CC lines and with

either IN1 or IN2 in UVLO

I_{AUX(Rd_noIN)}

V_IN1< V_{TH_UVLO_IN1}or V_IN2< V_{TH_UVLO_IN2}

145

55

190

82

µA

Enabled supply current with UFP

termination on CC lines

I_AUX(Rd)

7.6 Switching Characteristics

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF

=

100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined as positive out of the indicated

pin (unless otherwise noted)

PARAMETER

OUT – POWER SWITCH

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_r

t_f

Output-voltage rise time

Output-voltage fall time

V_IN1= 5 V, C_L= 1 µF, R_L= 100 Ω

(measured from 10% to 90% of final

value)

1.2

1.8

2.5

ms

0.35

0.55

0.75

t_on

t_off

Output-voltage turnon time

Output-voltage turnoff time

2.5

2

3.5

3

5

ms

V_IN1= 5 V, C_L= 1 µF, R_L= 100 Ω

4.5

OUT – CURRENT LIMIT

Current-limit response time to short V_IN1– V_OUT= 1 V, R_L= 10 mΩ, see

circuit Figure 1

t_ios

1.5

4

µs

8

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www.ti.com.cn

ZHCSGW8 –APRIL 2017

Switching Characteristics (continued)

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF

=

100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined as positive out of the indicated

pin (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FAULT

Asserting deglitch time due to

overcurrent

t_DEGA

5.5

8.2

10.7

ms

Asserting deglitch time due to

t_DEGA(OC)

0

ms

overtemperature in current limit⁽¹⁾

t_DEGA(OT)

CS

t_DEGA

t_DEGD

Deasserting deglitch time

5.5

8.2

10.7

Asserting deglitch time

5.5

8.2

10.7

ms

Deasserting deglitch time

OUT – DISCHARGE

R_DCHGdischarge time

CC1, CC2 - V_CONNPOWER SWITCH

V_OUT= 1 V, time I_{SNK_OUT}> 1 mA

after UFP signature removed from

CC lines

39

65

96

ms

t_r

t_f

Output-voltage rise time

Output-voltage fall time

V_IN2= 5 V, C_L= 1 µF, R_L= 100 Ω

(measured from 10% to 90% of final

value)

0.15

0.18

0.25

0.22

0.35

0.26

ms

t_on

t_off

Output-voltage turnon time

Output-voltage turnoff time

1

1.5

0.4

2

ms

V_IN2= 5 V, C_L= 1 µF, R_L= 100 Ω

0.3

0.55

CC1, CC2 – V_CONNPOWER SWITCH – CURRENT LIMIT

Current-limit response time to short V_IN2– V_CONN= 1 V, R = 10 mΩ, see

t_res

1

3

µs

circuit

Figure 1

UFP, POL, AUDIO, DEBUG

t_DEGR

t_DEGF

Asserting deglitch time

Deasserting deglitch time

100

7.9

150

200

ms

12.5

17.7

(1) These parameters are provided for reference only and do not constitute part of TI’s published specifications for purposes of TI’s product

warranty.

I_OS

I_OUT

t_ios

Figure 1. Output Short-Circuit Timing Diagram

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7.7 Typical Characteristics

50

500

450

400

350

300

250

40

30

20

10

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

Figure 2. V_BUSCurrent-Limiting Switch On-Resistance vs

Temperature

Figure 3. V_CONNCurrent-Limiting Switch On-Resistance vs

Temperature

0.25

0.2

0.15

0.1

0.05

0

4000

3500

3000

VBUS ILIM 3 A

VBUS ILIM 1.5 A

VCONN_ILIM

2500

2000

1500

1000

500

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

Device disabled

(V_OUT– V_IN) = 6.5

V

Figure 5. I_LIMfor V_BUSand V_CONNvs Temperature

Figure 4. OUT Reverse Leakage Current vs Temperature

350

300

250

200

150

100

50

2010

CS Threshold, Rising

CS Threshold, Falling

1990

1970

1950

1930

1910

1890

1870

1850

1830

1810

1790

1770

1750

UFP 3 A

UFP 1.5 A

UFP 0.5 A/0.9 A

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

T_J- Junction Temperature (^oC)

D001

D005

Figure 7. CC Sourcing Current to UFP vs Temperature

Figure 6. CS Threshold vs Temperature

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Typical Characteristics (continued)

100

400

350

300

250

200

150

100

50

IN1 UFP 3 A

IN1 UFP 0.5 A/1.5 A

95

IN2 UFP 3 A

IN2 UFP 1.5 A

IN2 UFP 0.5 A

90

85

80

75

70

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

Figure 8. IN1 Current With UFP vs Temperature

Figure 9. IN2 Current With UFP vs Temperature

70

65

60

55

50

45

40

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

V_AUX= 5 V

Figure 10. AUX Current With UFP vs Temperature

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8 Detailed Description

8.1 Overview

The TPS25810A-Q1 device is a highly integrated USB Type-C™ downstream-facing port (DFP) controller,

developed with a built-in power switch for the new USB Type-C connector and cable. The device provides all of

the functionality needed to support a USB Type-C DFP in a system where USB power delivery (PD) source

capabilities (for example, V_BUS> 5 V) are not implemented. It is designed to be compliant with the Type‑C

specification, revision 1.2.

8.1.1 USB Type-C Basic

For a detailed description of the Type-C specification, see the USB-IF Web site to download the latest released

version. Some of the basic concepts of the Type-C specification that pertain to understanding the operation of

the TPS25810A-Q1 (DFP device) are described as follows.

USB Type-C removes the need for different plug and receptacle types for host and device functionality. The

Type-C receptacle replaces both Type-A and Type-B receptacles because the Type-C cable is pluggable in

either direction between host and device. A host-to-device logical relationship is maintained via the configuration

channel (CC). Optionally, hosts and devices can be either providers or consumers of power when USB PD

communication is used to swap roles.

All USB Type-C ports operate in one of the following three data modes:

•

Host mode: the port can only be host (provider of power).

Device mode: the port can only be device (consumer of power).

Dual-role mode: the port can be either host or device.

Port types:

•

DFP (downstream facing port): Host

UFP (upstream facing port): Device

DRP (dual-role port): Host or device

Valid DFP-to-UFP connections:

•

Table 1 describes valid DFP-to-UFP connections.

Host-to-host and device-to-device have no functions.

Table 1. DFP-to-UFP Connections

DEVICE-MODE

PORT

HOST-MODE PORT

DUAL-ROLE PORT

Host-mode port

Device-mode port

Dual-role port

No function

Works

No function

Works

Works⁽¹⁾

Works

(1) This may be automatic or manually driven.

8.1.2 Configuration Channel

The function of the configuration channel (CC) is to detect connections and configure the interface across the

USB Type-C cables and connectors.

Functionally, the configuration channel serves the following purposes:

•

Detect connection to the USB ports

Resolve cable orientation and twist connections to establish USB data-bus routing

Establish DFP and UFP roles between two connected ports

Discover and configure power: USB Type-C current modes or USB power delivery

Discover and configure optional alternate and accessory modes

Enhance flexibility and ease of use

Typical flow of DFP-to-UFP configuration is shown in Figure 11:

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Detect Valid

Connection

Establish USB

Power Method

USB Device

Enumeration

Figure 11. Flow of DFP-to-UFP Configuration

8.1.3 Detecting a Connection

DFPs and DRPs fulfill the role of detecting a valid connection over USB Type-C. Figure 12 shows a DFP-to-UFP

connection made with Type-C cable. As shown in Figure 12, the detection concept is based on being able to

detect terminations in the product that has been attached. A pullup and pulldown termination model is used. A

pullup termination can be replaced by a current source.

•

In the DFP-to-UFP connection, the DFP monitors both CC pins for a voltage lower than the unterminated

voltage.

•

A UFP advertises Rd on both of its CC pins (CC1 and CC2).

A powered cable advertises Ra on only one of the CC pins of the plug. Ra is used to inform the source to

apply V_CONN

.

•

An analog audio device advertises Ra on both CC pins of the plug, which identifies it as an analog audio

device. V_CONNis not applied on either CC pin in this case.

UFP monitors for

connection

DFP monitors for

connection

Cable

CC

Rp

Rds

Ra

DFP monitors for

connection

UFP monitors for

connection

Figure 12. DFP-to-UFP Connection

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8.2 Functional Block Diagram

Current Sense

IN1

IN2

OUT

Current Sense

UVLO

CC1

CC2

CS

AUX

CC

Monitor

UVLO

Charge

Pump

Current

Limit

FAULT

Gate

Control

OTSD

Thermal

Sense

POL

UFP

EN

CHG

Control

Logic

DEBUG

AUDIO

CHG_HI

REF

REF_RTN

8.3 Feature Description

TheTPS25810A-Q1 device is a DFP Type-C port controller with integrated power switches for V_CONNand V_BUS. It

does not support BC 1.2 charging modes inherently, because it does not interact with USB D+ and D– data lines.

The TPS25810A-Q1 device can be used in conjunction with a BC 1.2 controller like the TPS2514A-Q1 device to

support BC1.2 and Type-C charging modes in a single Type-C DFP port. See the TPS25810 EVM User's Guide

and Application and Implementation section of this data sheet for more details. The TPS25810A-Q1 device can

be used in a USB 2.0 only or in a USB 3.1 port implementation. When used in a USB 3.1 port, the POL pin can

control an external super-speed MUX to handle the Type-C flippable feature.

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Feature Description (continued)

8.3.1 Configuration Channel Pins CC1 and CC2

Each device has two pins, CC1 and CC2, that serve to detect an attachment to the port and to resolve cable

orientation. These pins are also used to establish the current broadcast to a valid UFP, configure V_CONN, and

detect attachment of a debug or audio-adapter accessory.

Table 2 lists the response to various attachments to its port.

Table 2. TPS25810A-Q1 Response

TPS25810A-Q1 RESPONSE⁽¹⁾

TPS25810A-Q1 TYPE-C

V_CONN

on CC1 or

CC2

CC1

CC2

PORT

OUT

POL

UFP

AUDIO

DEBUG

Nothing attached

UFP connected

OPEN

Rd

OPEN

Rd

OPEN

IN1

NO

Hi-Z

LOW

Hi-Z

LOW

Hi-Z

LOW

Hi-Z

LOW

OPEN

Ra

IN1

NO

Ra

OPEN

IN1

NO

Powered cable, no UFP

connected

OPEN

Ra

NO

Hi-Z

Rd

CC2

CC1

NO

LOW

Hi-Z

Powered cable, UFP

connected

Ra

Rd

IN1

Debug accessory connected

Rd

OPEN

Audio-adapter accessory

connected

Ra

OPEN

NO

Hi-Z

LOW

Hi-Z

(1) POL, UFP, AUDIO, and DEBUG are open-drain outputs; pull high with 100 kΩ to AUX when used. Tie to GND or leave open when not

used.

8.3.2 Current Capability Advertisement and Overload Protection

The TPS25810A-Q1 device supports all three Type-C current advertisements as defined by the USB Type-C

standard. Current broadcast to a connected UFP is controlled by the CHG and CHG_HI pins. For each broadcast

level, the device protects itself from a UFP that draws current in excess of the USB Type-C current

advertisement of that port by setting the current limit as shown in Table 3.

Table 3. USB Type-C Current Advertisement

CC CAPABILITY

BROADCAST

CHG

CHG_HI

CURRENT LIMIT (TYP)

CS THRESHOLD (TYP)

0

1

0

1

0

1

STD

3.4 A

1.95 A

STD

1.5 A

3 A

Under OUT overload conditions, an internal OUT current-limit regulator limits the output current to the selected

I_LIMbased on CHG and CHG_HI selection. In applications where V_CONNis supplied via CC1 or CC2, separate

fixed current-limit regulators protect these pins from overload at the level indicated in the Electrical

Characteristics table. When an overload condition is present, the device maintains a constant output current, with

the output voltage determined by (I_OS× R_LOAD). Two possible overload conditions can occur. The first overload

condition occurs when either: 1) input voltage is first applied, enable is true, and a short circuit is present (load

which draws I_OUT> I_OS), or 2) input voltage is present and the TPS25810A-Q1 device is enabled into a short

circuit. The output voltage is held near zero potential with respect to ground and the TPS25810A-Q1 device

ramps the output current to I_OS. Both limit the current to I_OSuntil the overload condition is removed or the device

begins to thermal cycle. This is demonstrated in Figure 23 where the device was enabled into a short, and

subsequently cycles current off and on as the thermal protection engages.

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The second condition is when an overload occurs while the device is enabled and fully turned on. The device

responds to the overload condition within time t_ios(see Figure 1) when the specified overload (per Electrical

Characteristics) is applied. The response speed and shape vary with the overload level, input circuit, and rate of

application. The current-limit response can be either simply settling to I_OSor turnoff and controlled return to I_OS

.

Similar to the previous case, the TPS25810A-Q1 device limits the current to I_OSuntil the overload condition is

removed or the device begins to thermal cycle.

The TPS25810A-Q1 device thermal cycles if an overload condition is present long enough to activate thermal

limiting in any of the above cases. This is due to the relatively large power dissipation [(V_IN– V_OUT) × I_OS] driving

the junction temperature up. The device turns off when the junction temperature exceeds 135°C (minimum) while

in current limit. The device remains off until the junction temperature cools 20°C and then restarts. The current-

limit profile is shown in Figure 13.

V_OUT

Slope = -r _DS(on)

0 V

I_OUT

0 A

I_OS

Figure 13. Current-Limit Profile

8.3.3 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO

turnon threshold. Built-in hysteresis prevents unwanted on-off cycling due to input voltage droop during turnon.

8.3.3.1 Device Power Pins (IN1, IN2, AUX, OUT, and GND)

The device has multiple input power pins: IN1, IN2 and AUX. IN1 is connected to OUT by the internal power FET

and serves as the supply for the Type-C charging current. IN2 is the supply for V_CONNand ties directly between

the V_CONNpower switch on its input and CC1 or CC2 on its output. AUX, the auxiliary input supply, provides

power to the device. See the Functional Block Diagram.

In the simplest implementation where multiple supplies are not available, IN1, IN2, and AUX can be tied together.

However, in mobile systems (battery powered) where system power savings is paramount, IN1 and IN2 can be

powered by the high-power dc-dc supply (>3-A capability), and AUX can be connected to the low-power supply

that typically powers the system microcontroller when the system is in the hibernate or sleep power state. Unlike

IN1 and IN2, AUX can operate directly from a 3.3-V supply commonly used to power the microcontroller when

the system is put in low-power mode. Ceramic bypass capacitors close to the device from the INx and AUX pins

to GND are recommended to alleviate bus transients.

The recommended operating voltage range for IN1 and IN2 is 4.5 V to 5.5 V, whereas AUX can be operated

from 2.9 V to 5.5 V. However IN1, the high-power supply, can operate up to 6.5 V. This higher input voltage

affords a larger IR loss budget in systems where a long cable harness is used, and results in high IR losses with

3-A charging current. Increasing IN1 beyond 5.5 V enables longer cable and board trace lengths between the

device and the Type-C receptacle while meeting the USB specification for V_BUS≥ 4.75 V at the connector.

Figure 14 illustrates the point. In this example IN1 is at 5 V, which restricts the IR loss budget from the dc-dc

converter to the connector to 250 mV.

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Total IR Drop Budget = 250 mV

Trace IR Drop Budget at 3 A

= 250 – 165 = 85 mV

V_Trace1

V_Trace2

V_TPS25810A-Q1

V_DC-DC = 5 V

V_Connector

= 4.75 V (MIN)

IN1

OUT

5-V DC-DC

MaxRds_On = 55 mΩ

165-mV Drop at 3 A

82.5-mV Drop at 1.5 A

Figure 14. Total IR Loss Budget

8.3.3.2 FAULT Response

The FAULT pin is an open-drain output asserted low when the device OUT current exceeds its programmed

value and the overtemperature threshold (T_{TH_OTSD1}) is crossed. See the Electrical Characteristics for overcurrent

and overtemperature values. The FAULT signal remains asserted until the fault condition is removed and the

device resumes normal operation. An internal deglitch circuit eliminates false overcurrent-fault reporting.

Connect FAULT with a pullup resistor to AUX. FAULT can be left open or tied to GND when not used.

8.3.3.3 Thermal Shutdown

The device has two internal overtemperature shutdown thresholds, T_{TH_OTSD1}and T_{TH_OTSD2}, to protect the

internal FET from damage and assist with overall safety of the system. T_{TH_OTSD2}is greater than T_{TH_OTSD1}

.

FAULT is asserted low to signal a fault condition when the device temperature exceeds T_{TH_OTSD1}and the

current-limit switch is disabled. However, when T_{TH_OTSD2}is exceeded, all open-drain outputs are left open and

the device is disabled such that minimum power is dissipated. The device attempts to power up when the die

temperature decreases by 20°C.

8.3.3.4 REF

A 100-kΩ (1% or better recommended) resistor is connected from this pin to REF_RTN. The REF pin sets the

reference current required to bias the internal circuitry of the device. The overload current-limit tolerance and CC

currents depend upon the accuracy of this resistor. Using a ±1% or better low-temperature-coefficient resistor

yields the best current-limit accuracy and overall device performance.

8.3.3.5 Audio Accessory Detection

The USB Type-C specification defines an audio-adapter decode state which allows implementation of an analog

USB Type-C to 3.5-mm headset adapter. An audio accessory device is detected when both CC1 and CC2 pins

detect V_Ravoltage (when pulled to ground by an Ra resistor). The open-drain AUDIO pin is asserted low to

indicate the detection of such a device.

Table 4. Audio Accessory Detection

CC1

CC2

AUDIO

STATE

Ra

Asserted (pulled low)

Audio-adapter accessory connected

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Platforms supporting the audio accessory function can be triggered by the AUDIO pin to enable accessory mode

circuits to support the audio function. When the Ra pulldown is removed from the CC2 pin, AUDIO is deasserted

or pulled high. The TPS25810A-Q1 device monitors the CC2 pin for audio device detach. When this function is

not needed (for example in a data-less port), AUDIO can be tied to GND or left open.

8.3.3.6 Debug Accessory Detection

The Type-C spec supports an optional debug-accessory mode, used for debug only and not to be used for

communicating with commercial products. When the TPS25810A-Q1 device detects V_Rdvoltage on both CC1

and CC2 pins (when pulled to ground by an Rd resistor), it asserts DEBUG low. With DEBUG asserted, the

system can enter debug mode for factory testing or a similar functional mode. DEBUG deasserts or pulls high

when Rd is removed from CC1. The CC1 pin is monitored for debug-accessory detach.

If the debug-accessory mode is not used, tie DEBUG to GND or leave it open.

Table 5. Debug Accessory Detection

CC1

CC2

POL

STATE

Rd

Asserted (pulled low)

Debug accessory connected

8.3.3.7 Plug Polarity Detection

Reversible Type-C plug orientation is reported by the POL pin when a UFP is connected. However, when no

UFP is attached POL remains deasserted, irrespective of cable plug orientation. Table 6 describes the POL state

based on which of the device CC pins detects V_Rdfrom an attached UFP pulldown.

Table 6. Plug Polarity Detection

CC1

Rd

CC2

Open

Rd

POL

Hi-Z

STATE

UFP connected

Open

Asserted (pulled low)

UFP connected with reverse plug orientation

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Figure 15 shows an example implementation which uses the POL terminal to control the SEL terminal on the

HD3SS3212 device. The HD3SS3212 device provides switching on the differential channels between Port B and

Port C to Port A, depending on cable orientation. For details on the HD3SS3212 device, see HD3SS3212x Two-

Channel Differential 2:1/1:2 USB3.1 Mux/Demux.

3.3 V

HD3SS3212

USB C

SSTXp2

0.1 µF

B0+

Dp1

Dp2

USB Host

SSTXp

V_CC

Dp

B0–

C0+

C0–

B1+

B1–

C1+

C1–

SSTXn2

SSTXp1

SSTXn1

SSRXp2

SSRXn2

SSRXp1

SSRXn1

A0+

A0–

Dm

Dm1

Dm2

SSTXn

SSRXp

A1+

A1–

SSRXn

Dp

GND

Dp

Dm

OEn

SEL

3.3 V

GND

TPS25810A-Q1

OUT

5 V

POL

UFP

OUT

CC1

CC2

IN1

5 V

IN2

CHG

AUX

EN

CHG H_I

FAULT

CS

REF

REF_RTN

AUDIO

DEBUG

GND

Thermal Pad

Figure 15. Example Implementation

8.3.3.8 Device Enable Control

The logic enable pin (EN) controls the power switch and device supply current. The supply current is reduced to

less than 1 μA when a logic low is present on EN. The EN pin provides a convenient way to turn on or turn off

the device while it is powered. The enable input threshold has built-in hysteresis. When this pin is pulled high, the

device is turned on or enabled. When the device is disabled (EN pulled low) the internal FETs tied to IN1 and

IN2 are disconnected, all open-drain outputs are left open (Hi-Z), and the monitor block for CC1 and CC2 is

turned off. The EN terminal should not be left floating.

8.3.3.9 Cable Compensation (CS)

The TPS25810A-Q1 device monitors the current to a UFP, and if the load current exceeds 1.95 A (typ), the CS

pin asserts. This can be useful for implementing a digital droop-compensation scheme by altering the feedback

resistor ratio of the IN1 power source.

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Figure 16 shows a USB charging design using the TPS25810A-Q1 device. The 5-V (typical) nominal output of

the USB power supply, designated 5 V_OUTherein, is often a dc-dc converter in automotive applications. V_{UFP_IN}

refers to the voltage across the inside contacts of the USB connector of a UFP device. Official USB

specifications should be consulted for the most up-to-date requirements. For illustration purposes, it is assumed

the minimum and maximum voltages allowed for V_{UFP_IN}are 4 V and 5.25 V, respectively. In general, when

V_{UFP_IN}is 5 V, the UFP draws optimum current and requires the minimum amount of time to recharge its battery.

V_{UFP_IN}

5 ´ 100 kW

(optional)

TPS25810A-Q1

V_BUS

5 VOUT

Bus Power 4.5 V– 6.5 V

CC Power 4.5 V– 5.5 V

I_OUT

5 V

IN1

OUT

5-V

LDO

IN2

FAULT

Auxiliary Power 2.9 V– 5.5 V

AUX

R₁

CC1

CC2

CS

DC-DC

Converter

R₄

C_OUT

EN

R₂

Cable

Control Signals

CHG

CHG_HI

UFP

POL

FB

10 µF

R₃

REF

AUDIO

100 kW (1%)

REF_RTN

DEBUG

GND

Thermal Pad

Type-C DFP

Status Signals

Figure 16. TPS25810A-Q1 Charging System Schematic

In a practical system, there are voltage drops from the dc-dc output, 5 V_OUT, to V_{UFP_IN}which include the on-

resistance of the TPS25810A-Q1 device power switch, USB cabling and connector contact resistances.

Under rated UFP load current, these drops can be several hundred millivolts, decreasing V_{UFP_IN}below the

optimal 5-V level. In addition, as V_{UFP_IN}decreases below 5 V, most modern UFPs decrease their load

current to prevent possible overload conditions and to maintain V_{UFP_IN}above 4 V. Lower-than-optimum load

current increases the time required to recharge the UFP battery. For example, in Figure 16, assuming that

the loss resistance is 113 mΩ (includes 79 mΩ of USB cable resistance and 34 mΩ of power switch

resistance) and 5 V_OUTis 5 V, the input voltage of UFP (V_{UFP_IN}) is about 4.66 V at 3 A. The TPS25810A-Q1

device provides the CS pin to report high-charging-current conditions and increase the 5 V_OUTvoltage as

shown in Figure 17

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5.25

5.00

4.75

4.50

5 VOUT with compensation

VUFP_IN with compensation

5 VOUT without compensation

VUFP_IN without compensation

3

1

2

Output Current (A)

Figure 17. TPS25810A-Q1 CS Function

Equation 1 through Equation 4 refer to Figure 16

The power supply output voltage is calculated in Equation 1.

R +R +R ´ V

FB

(

)

1

2

3

5V

=

OUT

R

3

(1)

5 V_OUTand V_FBare known. If R₃is given and R₁is fixed, R₂can be calculated. The 5 V_OUTvoltage change with

compensation is shown in Equation 2 and Equation 3.

R +R ´R ´ V

FB

(

)

R ´R

2

3

1

DV =

3

4

(2)

(3)

æ 5V

R ö R ´ V

1 1 FB

OUT

ΔV =

-

ç

÷

V

R

4

è

FB

³ø

If R₁is less than R₃, then Equation 3 can be simplified as Equation 4.

5V ´ R

OUT

1

DV »

R

4

(4)

8.3.3.10 Power Wake

The power-wake feature offers the mobile-systems designer a way to save on system power when no UFP is

attached to the Type-C port. See Figure 18. To enable power wake, the UFP pins from any combination of two

TPS25810A-Q1 devices are tied together (each with its own 100-kΩ pullup) to the enable pin of a 5-V, 6-A dc-dc

buck converter. When no UFP is detected on both Type-C ports, the EN pin of the dc-dc converter is pulled high,

thereby disabling it. Because the TPS25810A-Q1 device is powered by an always-on 3.3-V LDO, turning off the

supply to IN1 and IN2 does not affect its operation in the detach state. Anytime a UFP is detected on either port,

the corresponding UFP pin is pulled low, enabling the dc-dc converter to provide charging current to the attached

UFP. Turning off the high-power dc-dc converter when ports are unattached saves on system power. This

method can save a significant amount of power, because the TPS25810A-Q1 device requires only 0.7 µA

(typical) via the AUX pin when no UFP device is connected.

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Both UFP High

Converters

Disabled

OUT

CC1

CC2

IN1

TPS54620

Buck

Converter

No UFP

Attached

I

IN2

AUX

TPS25810A-Q1

No. 1

EN

CHG

UFP_1

CHG_HI

12 V

UFP_1

(High)

UFP_2

(High)

OUT

CC1

CC2

IN1

No UFP

Attached

IN2

LP2950-33

LDO

AUX

TPS25810A-Q1

No. 2

CHG

UFP_2

CHG_HI

One UFP Low

Converter

Enabled

OUT

CC1

CC2

IN1

TPS54620

Buck

Converter

UFP

Attached

IN2

AUX

TPS25810A-Q1

No. 1

EN

CHG

UFP_1

-

CHG_HI

12 V

UFP_1

(High)

UFP_2

(High)

IN1

IN2

OUT

CC1

CC2

No UFP

Attached

LP2950-33

LDO

AUX TPS25810A-Q1

No. 2

CHG

UFP_2

CHG_HI

Figure 18. Power-Wake Implementation

8.4 Device Functional Modes

The TPS25810A-Q1 device is a Type-C controller with integrated power switches that supports all Type-C

functions in a downstream facing port. The device manages current advertisement and protection for a

connected UFP and active cable. Each device starts its operation by monitoring the AUX bus. When V_AUX

exceeds the undervoltage-lockout threshold, the device samples the EN pin. A high level on this pin enables the

device, and normal operation begins. Having successfully completed its start-up sequence, the device now

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Device Functional Modes (continued)

actively monitors its CC1 and CC2 pins for attachment to a UFP. When a UFP is detected on either the CC1 or

CC2 pin, the internal MOSFET starts to turn on after the required deglitch time is met. The internal MOSFET

starts conducting and allows current to flow from IN1 to OUT. If Ra is detected on the other CC pin (not

connected to the UFP), V_CONNis applied to allow current to flow from IN2 to the CC pin connected to Ra. For a

complete listing of various device operational modes, see Table 2.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS25810A-Q1 device is a Type-C DFP controller that supports all Type-C DFP required functions. It

applies power to V_BUSwhen a UFP attach is detected and removes power when it detects the UFP is detached.

The device exposes its identity via its CC pin, advertising its current capability based on the CHG and CHG_HI

pin settings. The TPS25810A-Q1 device also limits its advertised current internally and provides robust protection

to a fault on the system V_BUSpower rail.

After a connection is established, either device is capable of providing V_CONNto power circuits in the cable plug

on the CC pin that is not connected to the CC wire in the cable. V_CONNis internally current-limited and has its

own supply pin, IN2. Apart from providing charging current to a UFP, the TPS25810A-Q1 device also supports

audio and debug accessory modes.

The following design procedure can be used to implement a full-featured Type-C DFP.

NOTE

BC 1.2 is not supported in the TPS25810A-Q1 device. To support BC 1.2 with Type-C

charging modes in a single Type-C connector, a dedicated charging port (DCP) controller

something like a TPS2514A-Q1 device must be used.

9.2 Typical Applications

9.2.1 Type-C DFP Port Implementation Without BC 1.2 Support

Figure 19 shows a minimal Type-C DFP implementation capable of supporting 5-V and 3-A charging.

USB Type-C

Receptacle

5 V

2

3

4

5

6

7

8

V_BUS

IN1

14

15

13

11

1

OUT

CC2

CC1

IN1

IN2

AUX

EN

FAULT

CS

20

19

18

17

16

10 µF

CHG

CHG_HI

UFP

POL

AUDIO

DEBUG

10

9

REF

100 kW

(1%)

12

GND

REF_RTN

Figure 19. Type-C DFP Port Implementation Without BC 1.2 Support

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Typical Applications (continued)

9.2.1.1 Design Requirements

9.2.1.1.1 Input and Output Capacitance

Input and output capacitance improves the performance of the device. The actual capacitance should be

optimized for the particular application. For all applications, a 0.1-μF or greater ceramic bypass capacitor

between INx and GND is recommended as close to the device as possible for local noise decoupling.

All protection circuits, including those of the TPS25810A-Q1 device, have the potential for input voltage

overshoots and output voltage undershoots. Input voltage overshoots can be caused by either of two effects. The

first cause is an abrupt application of input voltage in conjunction with input power-bus inductance and input

capacitance when the INx pin is high-impedance (before turnon). Theoretically, the peak voltage is 2 times the

applied voltage. The second cause is due to the abrupt reduction of output short-circuit current when the device

turns off and energy stored in the input inductance drives the input voltage high. Input voltage droops may also

occur with large load steps and as the output is shorted. Applications with large input inductance (for instance,

connecting the evaluation board to the bench power supply through long cables) may require large input

capacitance to prevent the voltage overshoot from exceeding the absolute maximum voltage of the device.

The fast current-limit speed of the TPS25810A-Q1 device to hard output short circuits isolates the input bus from

faults. However, ceramic input capacitance in the range of 1 μF to 22 μF adjacent to the input aids in both

response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are

permitted. Output voltage undershoot is caused by the inductance of the output power bus just after a short has

occurred and the device has abruptly reduced the OUT current. Energy stored in the inductance drives the OUT

voltage down, and potentially negative, as it discharges. An application with large output inductance (such as

from a cable) benefits from the use of a high-value output capacitor to control voltage undershoot.

When implementing a USB-standard application, 120-μF minimum output capacitance is required. Typically, a

150-μF electrolytic capacitor is used, which is sufficient to control voltage undershoots. Because in Type-C

applications, DFP is a cold socket when no UFP is attached, the output capacitance should be placed at the INx

pin versus the OUT pin, as is done in USB Type-A ports. It is also recommended to put a 10-μF ceramic

capacitor on the OUT pin for better voltage bypass.

9.2.1.2 Detailed Design Procedure

The TPS25810A-Q1 device supports up to three different input voltages, based on the application. In the

simplest implementation, all input pins are tied to a single voltage source set to 5 V, as shown in Figure 19.

However, it is recommended to set a slightly higher (100 mV to 200 mV) input voltage, when possible, to

compensate for IR loss from the source to the Type-C connector.

Other design considerations are listed as follows:

•

Place at least 120 µF of bypass capacitance close to the INx pins rather than the OUT pin, as Type-C is a

cold-socket connector.

A 10-µF bypass capacitor is recommended to be placed near a Type-C receptacle V_BUSpin to handle load

transients.

Depending on the maximum current-level advertisement supported by the Type-C port in the system, set the

CHG and CHG_HI levels accordingly. Advertisement of 3 A is shown in Figure 19.

The EN, CHG, and CHG_HI pins can be tied directly to GND or V_AUXwithout a pullup resistor.

–

CHG and CHG_HI can also be dynamically controlled by a microcontroller to change the current

advertisement level to the UFP.

•

When an open-drain output of the TPS25810A-Q1 device is not used, it can be left open or tied to GND.

Use a 1% 100-kΩ resistor to connect between the REF and REF_RTN pins, placing it close to the device pin

and keeping it isolated from switching noise on the board.

25

TPS25810A-Q1

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Typical Applications (continued)

9.2.1.3 Application Curves

VIN

CC1

VIN

VBUS

CC2

CC1

IN

Time 20 ms/div

Time 50 ms/div

Basic start-up: IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V

CC1 = Rd

CC2 = open

CC1 = open

CC2 = open → Rd

Figure 20. Basic Start-Up

Figure 21. Start-Up

VBUS VIN

VIN

VBUS

IN

CC1

IN

CC1

Time 50 ms/div

Time 200 ms/div

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V

CC1 = Rd CC2 = open OUT = shorted

IN1 = IN2 = AUX = EN = 5 V; CHG = CHG_HI = 0 V

CC1 = open

CC2 = Rd

OUT = open → 5

Ω

Figure 23. Hot-Plug to Short

Figure 22. Load Step

VIN

VBUS

VOUT

CC1

IN

CC1

CC2

Time 20 ms/div

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V

CC1 = short

CC2 = Rd

CC1 = Rd → open

CC2 = open

Figure 24. Short On CC1

Figure 25. Remove Rd

26

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Typical Applications (continued)

VIN

VBUS

CC2

CC1

Time 50 ms/div

V_IN5 V → 3.5 V (100 ms) → 5 V (1 V/ms)

CC1 = Rd

CC2 = Ra

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V

Figure 26. Brown-Out Test

27

TPS25810A-Q1

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Typical Applications (continued)

9.2.2 Type-C DFP Port Implementation With BC 1.2 (DCP Mode) Support

Figure 27 shows a Type-C DFP implementation capable of supporting 5-V, 3-A charging in a Type-C port that is

also able to support charging of legacy devices when used with a Type-C µB cable assembly for charging

phones and handheld devices equipped with a µB connector.

This implementation requires the use of a TPS2514A-Q1 device, a USB dedicated charging-port (DCP) controller

with auto-detect feature to charge not only BC 1.2-compliant handheld devices but also popular phones and

tablets that incorporate their own propriety charging algorithm. See TPS2513A-Q1, TPS2514A-Q1 USB

Dedicated Charging Port Controller for more details.

TPS2514A-Q1

IN

DM1

DP1

NC

0.1 µF

NC

GND

USB Type-C

Receptacle

TPS25810A-Q1

5 V

2

3

4

5

6

7

8

V_BUS

IN1

14

15

13

11

1

OUT

CC2

CC1

IN1

D–

D+

IN2

AUX

EN

FAULT

CS

20

19

18

17

16

12

10 µF

CHG

CHG_HI

UFP

POL

10

REF

AUDIO

DEBUG

GND

100 kW

(1%)

9

REF_RTN

Figure 27. Type-C DFP Port Implementation With BC 1.2 (DCP Mode) Support

9.2.2.1 Design Requirements

See Design Requirements for the design requirements.

9.2.2.2 Detailed Design Procedure

See Detailed Design Procedure for the detailed design procedure.

9.2.2.3 Application Curves

See Application Curves for the application curves.

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10 Power Supply Recommendations

The device has three power supply inputs. IN1, which is directly connected to OUT via the power MOSFET, is

tied to the V_BUSpin in the Type-C receptacle. IN2 has a current-limiting switch and is multiplexed either to the

CC1 or CC2 pin in the Type-C receptacle, depending on cable plug polarity. AUX is the device supply. In most

applications, all three supplies are tied together. In a special implementation like power wake, IN1 and IN2 are

tied to a single supply, whereas AUX is powered by a supply that is always ON and can be as low as 2.9 V.

USB Specification Revisions 2.0 and 3.1 require V_BUSvoltage at the connector to be between 4.75 V and 5.5 V.

Depending on layout and routing from the supply to the connector, the voltage drop on V_BUSmust be tightly

controlled. Locate the input supply close to the device. For all applications, a 10-μF or greater ceramic bypass

capacitor between OUT and GND is recommended, located as close to the Type-C connector of the device as

possible for local noise decoupling. The power supply should be rated higher than the current limit setting to

avoid voltage droops during overcurrent and short-circuit conditions.

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11 Layout

11.1 Layout Guidelines

Layout best practices as they apply to the TPS25810A-Q1 device are listed as follows.

•

For all applications, a 10-µF ceramic capacitor is recommended near the Type-C receptacle and another

120‑µF ceramic capacitor close to the IN1 pin.

–

The optimum placement of the 120-µF capacitor is closest to the IN1 and GND pins of the device.

Care must be taken to minimize the loop area formed by the bypass capacitor connection, the IN1 pin,

and the GND pin of the device. See Figure 28 for a PCB layout example.

•

High-current-carrying power-path connections to the device should be as short as possible and should be

sized to carry at least twice the full-load current.

–

Have the input and output traces as short as possible. The most common cause of voltage loss failure in

USB power delivery is the resistance associated with the V_BUStrace. Trace length, maximum current being

supplied for normal operation, and total resistance associated with the V_BUStrace must be taken into

account while budgeting for voltage loss.

–

For example, a power-carrying trace that supplies 3 A, at a distance of 20 inches, 0.1-in. wide, with 2‑oz.

copper on the outer layer has a total resistance of approximately 0.046 Ω and voltage loss of 0.14 V. The

same trace at 0.05 in. wide has a total resistance of approximately 0.09 Ω and voltage loss of 0.28 V.

Make power traces as wide as possible.

•

The resistor attached to the REF pin of the device has several requirements:

–

It is recommended to use a 1% 100-kΩ low-temperature-coefficient resistor.

It should be connected to the REF and REF_RTN pins (pins 9 and pin 10, respectively).

The REF_RTN pin should be isolated from the GND plane. See Figure 28.

The trace routing between the REF and REF_RTN pins of the device should be as short as possible to

reduce parasitic effects on current-limit and current-advertisement accuracy. These traces should not have

any coupling to switching signals on the board.

Locate all TPS25810A-Q1 pullup resistors for open-drain outputs close to their connection pin. Pullup

resistors should be 100 kΩ.

–

When a particular open-drain output is not used or needed in the system, leave the associated pin open or

tied to GND.

•

Keep the CC lines close to the same length.

Thermal considerations:

–

When properly mounted, the thermal-pad package provides significantly greater cooling ability than an

ordinary package. To operate at rated power, the thermal pad must be soldered to the board GND plane

directly under the device. The thermal pad is at GND potential and can be connected using multiple vias

to inner-layer GND. Other planes, such as the bottom side of the circuit board, can be used to increase

heat sinking in higher-current applications. See PowerPad™ Thermally Enhanced Package and

PowerPAD™ Made Easy for more information on using this thermal pad package.

Obtaining acceptable performance with alternate layout schemes is possible; however, the layout example

in the following section has been shown to produce good results and is intended as a guideline.

•

ESD considerations:

–

The TPS25810A-Q1 device has built-in ESD protection for CC1 and CC2. Keep trace length to a minimum

from the Type-C receptacle to the TPS25810A-Q1 device on CC1 and CC2.

–

A 10-µF output capacitor should be placed near the Type-C receptacle.

See the TPS25810EVM-745 evaluation module for an example of a double-layer board that passes

IEC61000-4-2 testing.

–

Do not create stubs or test points on the CC lines. Keep the traces short if possible, and use minimal vias

along the traces [1–2 inches (2.54 cm–5.08 cm) or less].

–

See ESD Protection Layout Guide for additional information.

Have a dedicated ground plane layer, if possible, to avoid differential voltage buildup.

30

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11.2 Layout Example

Top Layer Signal Trace

Top Layer Signal Ground Plane

Bottom Layer Signal Trace

Bottom Layer Signal Ground Plane

Via to Bottom Layer Signal Ground Plane

Via to Bottom Layer Signal

AUX

1

16

15

2

Thermal

Pad

IN1

OUT

3

14

13

12

11

4

5

6

IN2

CC2

GND

CC1

AUX

EN

Signal Ground

Bottom Layer

Signal Ground

Top Layer

Figure 28. Layout Example

31

TPS25810A-Q1

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www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 文档支持

12.2.1 相关文档

《PowerPad™ 热增强型封装》

《PowerPAD™ 速成》

《TPS25810EVM-745 用户指南》

《TPS25810 高压 DFP 保护》

12.2.2 相关链接

下面的表格中列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链

接。

12.3 接收文档更新通知

要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品信

息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.5 商标

E2E is a trademark of Texas Instruments.

USB Type-C is a trademark of USB Implementers Forum, Inc..

All other trademarks are the property of their respective owners.

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。本数据随时可能发生变更并

且不对本文档进行修订，恕不另行通知。要获得这份数据表的浏览器版本，请查阅左侧的导航窗格。

32

PACKAGE OUTLINE

RVC0020B

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

B

A

PIN 1 INDEX AREA

4.1

3.9

0.1 MIN

(0.05)

E

SCAL

C

T

SECTION A-A

TYPICAL

C

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

1.6 0.1

2X 1.5

(0.2) TYP

EXPOSED

THERMAL PAD

10

7

16X 0.5

11

6

SYMM

21

A

2X

2.6 0.1

2.5

1

16

0.25

20X

0.15

PIN 1 ID

(OPTIONAL)

20

17

0.1

C A B

C

SYMM

20X

0.05

0.5

0.3

4222724/B 02/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RVC0020B

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.6)

SYMM

17

20

20X (0.6)

1

16

20X (0.2)

4X (1)

(3.8)

SYMM

21

(2.6)

16X (0.5)

(R0.05) TYP

11

6

(

0.2) TYP

VIA

7

10

6X (0.55)

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222724/B 02/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RVC0020B

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

2X (1.47)

SYMM

20

17

20X (0.6)

1

21

16

20X (0.2)

2X

(1.15)

SYMM

(3.8)

(0.675)

TYP

16X (0.5)

METAL

TYP

11

6

(R0.05) TYP

10

7

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD

81.3% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4222724/B 02/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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型号：	TPS25810A-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 USB Type-C™ DFP 控制器和电源开关开关控制器电源开关
文件：	总38页 (文件大小：1192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS25810A-Q1 [TI]

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