TPS25750 [TI]
TPS25750 USB Type-C and USB PD Controller with Integrated Power Switches Optimized for Power Applications;型号: | TPS25750 |
厂家: | TEXAS INSTRUMENTS |
描述: | TPS25750 USB Type-C and USB PD Controller with Integrated Power Switches Optimized for Power Applications 光电二极管 |
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TPS25750
SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020
TPS25750 USB Type-C® and USB PD Controller with Integrated Power Switches
Optimized for Power Applications
1 Features
2 Applications
•
Integrated fully managed power paths
– Integrated 5-V, 3-A, 36-mΩ sourcing switch
(TPS25750S/D)
– Integrated 28-V, 7-A, 16-mΩ bi-directional load
switch (TPS25750D only)
•
Power tools, power banks, retail automation and
payment
Wireless speakers, headphones
Other personal electronics and industrial
applications
•
•
•
•
Standalone USB Type-C PD solution
– No firmware development or external micro-
controller needed
3 Description
The TPS25750 is a highly integrated stand-alone USB
Type-C and Power Delivery (PD) controller optimized
for applications supporting USB-C PD Power. The
TPS25750 integrates fully managed power paths with
robust protection for a complete USB-C PD solution.
The TPS25750 also integrates control for external
battery charger ICs for added ease of use and
reduced time to market. The intuitive web based GUI
will ask the user a few simple questions on the
applications needs using clear block diagrams and
simple multiple-choice questions. As a result, the GUI
will create the configuration image for the user’s
application, reducing much of the complexity
associated with competitive USB PD solutions.
Integrated robust power path protection
– Integrated reverse current protection,
overvoltage protection, and slew rate control
the high-voltage bi-directional power path
– Integrated undervoltage and overvoltage
protection and current limiting for inrush current
protection for the 5V/3A source power path
– 26-V tolerant CC pins for robust protection
when connected to non-compliant devices
Optimized for power applications
– Integrated I2C control for TI battery chargers
– Web-based GUI and pre-configured firmware
– Optimized for power consumer only (sink)
(UFP) applications
•
•
Device Information
PART NUMBER(1)
TPS25750D
PACKAGE
QFN (RJK)
QFN (RSM)
BODY SIZE (NOM)
4.0 mm x 6.0 mm
4.0 mm x 4.0 mm
– Optimized for power provider (source) and
power consumer (sink) (DRP) applications
USB Type-C power delivery (PD) controller
– 10 configurable GPIOs
TPS25750S
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
– BC1.2 charging support
5 A
– USB PD 3.0 compliant
5-20 V
– USB Type-C specification complaint
– Cable attach and orientation detection
– Integrated VCONN switch
3.3 V
LDO
TPS25750D
5 V
3.3 V
VBUS
3 A
– Physical layer and policy engine
– 3.3-V LDO output for dead battery support
– Power supply from 3.3 V or VBUS source
CC1/2
2
CC
VCONN
Type-C Rp/Rd & state
machine,
VCONN switches,
USB PD policy engine,
protocol and physical layer
Optional
Embedded
Controller
USB
Type-C
Connector
I2C
Slave
BQ
Battery
Charger
GND
I2C
Master
10 GPIO
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS25750
www.ti.com
SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 ESD Ratings............................................................... 8
7.3 Recommeded Operating Conditions...........................8
7.4 Recommended Capacitance.......................................9
7.5 Thermal Information..................................................10
7.6 Power Supply Characteristics................................... 11
7.7 Power Consumption..................................................11
7.8 PP_5V Power Switch Characteristics....................... 11
7.9 PPHV Power Switch Characteristics - TPS25750D..12
7.10 PP_EXT Power Switch Characteristics -
TPS25750S.................................................................14
7.11 Power Path Supervisory..........................................16
7.12 CC Cable Detection Parameters.............................16
7.13 CC VCONN Parameters......................................... 17
7.14 CC PHY Parameters...............................................18
7.15 Thermal Shutdown Characteristics.........................18
7.16 ADC Characteristics................................................19
7.17 Input/Output (I/O) Characteristics........................... 19
7.18 BC1.2 Characteristics............................................. 19
7.19 I2C Requirements and Characteristics................... 20
7.20 Typical Characteristics ...........................................22
8 Parameter Measurement Information..........................24
9 Detailed Description......................................................25
9.1 Overview...................................................................25
9.2 Functional Block Diagram.........................................26
9.3 Feature Description...................................................28
9.4 Device Functional Modes..........................................45
10 Application and Implementation................................49
10.1 Application Information........................................... 49
10.2 Typical Application.................................................. 49
11 Power Supply Recommendations..............................54
11.1 3.3-V Power............................................................ 54
11.2 1.5-V Power............................................................ 54
11.3 Recommended Supply Load Capacitance..............54
12 Layout...........................................................................55
12.1 TPS25750D - Layout.............................................. 55
12.2 TPS25750S - Layout...............................................60
13 Device and Documentation Support..........................67
13.1 Device Support....................................................... 67
13.2 Documentation Support.......................................... 67
13.3 Support Resources................................................. 67
13.4 Trademarks.............................................................67
13.5 Electrostatic Discharge Caution..............................67
13.6 Glossary..................................................................67
14 Mechanical, Packaging, and Orderable
Information.................................................................... 67
4 Revision History
Changes from Revision * (July 2020) to Revision A (November 2020)
Page
•
Changed data sheet status from "Advance Information" to "Production Data"...................................................1
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SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020
5 Device Comparison Table
INTEGRATED HIGH
HIGH VOLTAGE GATE DRIVER
DEVICE NUMBER
5-V SOURCE LOAD SWITCH
VOLTAGE BI-DIRECTIONAL FOR BI-DIRECTIONAL EXTERNAL
LOAD SWITCH (PPHV)
PATH (PP_EXT)
TPS25750D
TPS25750S
Yes
Yes
Yes
No
No
Yes
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SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020
6 Pin Configuration and Functions
37
36
35
34
33
32
31
30
29
28
27
38
26
LDO_3V3
ADCIN1
VBUS_IN
VBUS_IN
1
2
25
24
23
22
21
20
ADCIN2
LDO_1V5
GPIO0
VBUS_IN
PPHV
3
4
5
Thermal Pad
(GND)
Thermal Pad (DRAIN)
PPHV
GPIO1
PPHV
6
8
9
10
11
12
13
18
19
7
14
15
16
17
Not to Scale
Figure 6-1. Top View of the TPS25750D 38-pin QFN RJK Package
LDO_3V3
ADCIN1
ADCIN2
LDO_1V5
GPIO0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CC1
GPIO5/USB_N
GPIO4/USB_P
GATE_VBUS
GATE_VSYS
VSYS
Thermal
Pad
(GND)
GPIO1
GPIO2
GPIO3
I2Cs_SDA
I2Cm_IRQ
Not to Scale
Figure 6-2. Top View of the TPS25750S 32-pin QFN RSM Package
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Table 6-1. TPS25750D Pin Functions
PIN
TYPE(1) RESET DESCRIPTION
NAME
NO.
2
ADCIN1
ADCIN2
I
I
Hi-Z
Hi-Z
Configuration Input. Connect to a resistor divider to LDO_3V3.
Configuration Input. Connect to a resistor divider to LDO_3V3.
3
I/O for USB Type-C. Filter noise with recommended capacitor to GND
(CCCy).
CC1
CC2
28
29
I/O
I/O
Hi-Z
Hi-Z
I/O for USB Type-C. Filter noise with recommended capacitor to GND
(CCCy).
GND
11, 12, 14, 31
—
GPIO
GPIO
O
—
Ground. Connect to ground plane.
GPIO0
GPIO1
GPIO2
GPIO3
5
6
Hi-Z
Hi-Z
Hi-Z
Hi-Z
General purpose digital I/O. Tie to ground when unused.
General purpose digital I/O. Tie to ground when unused.
General purpose digital I/O. Tie to ground when unused.
General purpose digital I/O. Tie to ground when unused.
7
19
O
General purpose digital I/O. Tie to ground when unused.This may be
connected to D+ for BC1.2 support.
GPIO4(USB_P)
GPIO5(USB_N)
26
27
I/O
I/O
Hi-Z
Hi-Z
General purpose digital I/O. Tie to ground when unused. This may be
connected to D- for BC1.2 support.
GPIO6
GPIO7
37
36
O
O
Hi-Z
Hi-Z
General purpose digital I/O. Tie to ground when unused.
General purpose digital I/O. Tie to ground when unused.
I2C slave serial clock input. Tie to pullup voltage through a resistor. May be
grounded if unused.
I2Cs_SCL
I2Cs_SDA
I2Cs_IRQ
9
8
I
Hi-Z
Hi-Z
Hi-Z
I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a
resistor. May be grounded if unused.
I/O
O
I2C slave interrupt. Active low. Connect to external voltage through a pull-up
resistor. This can be re-configured to GPIO10. Tie to ground if unused.
10
I2C master serial clock. Open-drain output. Tie to pullup voltage through a
resistor. Can be grounded if unused.
I2Cm_SCL
GPIO11
17
13
16
O
O
Hi-Z
Hi-Z
Hi-Z
General purpose digital I/O. Tie to ground when unused.
I2C master serial data. Open-drain input/output. Tie to pullup voltage through
a resistor. Can be grounded if unused.
I2Cm_SDA
I/O
I2C master interrupt. Active low. Connect to external voltage through a pull-up
resistor.Tie to ground when unused. This can be re-configured to GPIO12.
I2Cm_IRQ
LDO_1V5
LDO_3V3
18
4
I
Hi-Z
—
Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This
pin cannot source current to external circuits.
O
O
Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with
capacitance CLDO_3V3 to GND.
1
—
DRAIN
PP5V
PPHV
15, 30
34, 35
N/A
I
—
—
Connects to drain of internal FET.
5-V System Supply to VBUS, supply for CCy pins as VCONN.
High-voltage sinking node in the system.
20, 21, 22
I/O
VBUS_IN
23, 24, 25
5-V to 20-V input.
I/O
VBUS
32, 33
38
O
I
5-V output from PP5V input to LDO. Bypass with capacitance CVBUS to GND.
Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
VIN_3V3
—
(1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output
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SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020
Table 6-2. TPS25750S Pin Functions
PIN
TYPE(1) RESET DESCRIPTION
NAME
NO.
2
ADCIN1
ADCIN2
I
I
Hi-Z
Hi-Z
Configuration Input. Connect to a resistor divider to LDO_3V3.
Configuration Input. Connect to a resistor divider to LDO_3V3.
3
I/O for USB Type-C. Filter noise with recommended capacitor to GND
(CCCy).
CC1
CC2
24
25
I/O
I/O
Hi-Z
Hi-Z
I/O for USB Type-C. Filter noise with recommended capacitor to GND
(CCCy).
GATE_VSYS
GATE_VBUS
GND
20
O
Hi-Z
Hi-Z
—
Connect to the N-ch MOSFET that has source tied to VSYS.
Connect to the N-ch MOSFET that has source tied to VBUS.
Ground. Connect to ground plane.
21
O
11, 12, 14
—
GPIO0
5
6
I/O
I/O
I/O
I/O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
General purpose digital I/O. Tie to ground when unused.
General purpose digital I/O. Tie to ground when unused.
General purpose digital I/O. Tie to ground when unused.
General purpose digital I/O. Tie to ground when unused.
GPIO1
GPIO2
7
GPIO3
18
General purpose digital I/O. Tie to ground when unused. This may be
connected to D+ for BC1.2 support.
GPIO4 (USB_P)
GPIO5 (USB_N)
22
23
I/O
I/O
Hi-Z
Hi-Z
General purpose digital I/O. Tie to ground when unused. This may be
connected to D- for BC1.2 support.
GPIO6
GPIO7
31
30
I/O
I/O
Hi-Z
Hi-Z
General purpose digital I/O. Tie to ground when unused.
General purpose digital I/O. Tie to ground when unused.
I2C slave serial clock input. Tie to pullup voltage through a resistor. May be
grounded if unused.
I2Cs_SCL
I2Cs_SDA
I2Cs_IRQ
9
8
I
Hi-Z
Hi-Z
Hi-Z
I2C slave serial data. Open-drain input/output. Tie to pullup voltage through a
resistor. May be grounded if unused.
I/O
O
I2C slave interrupt. Active low. Connect to external voltage through a pull-up
resistor. This can be re-configured to GPIO10. Tie to ground when unused.
10
I2C master serial clock. Open-drain output. Tie to pullup voltage through a
resistor when used or unused.
I2Cm_SCL
GPIO11
16
13
15
O
O
Hi-Z
Hi-Z
Hi-Z
General purpose digital I/O. Tie to ground when unused.
I2C master serial data. Open-drain input/output. Tie to pullup voltage through
a resistor when used or unused.
I2Cm_SDA
I/O
I2C master interrupt. Active low. Connect to external voltage through a pull-up
resistor. Tie to ground when unused. This can be re-configured to GPIO12.
I2Cm_IRQ
LDO_1V5
17
4
I
Hi-Z
—
Output of the CORE LDO. Bypass with capacitance CLDO_1V5 to GND. This
pin cannot source current to external circuits.
O
Output of supply switched from VIN_3V3 or VBUS LDO. Bypass with
capacitance CLDO_3V3 to GND.
LDO_3V3
PP5V
1
O
I
—
—
28, 29
5-V System Supply to VBUS, supply for CCy pins as VCONN.
High-voltage sinking node in the system. It is used to implement reverse-
current-protection (RCP) for the external sinking paths controlled by
GATE_VSYS.
VSYS
19
I
—
VBUS
26, 27
32
I/O
I
5-V to 20-V input. Bypass with capacitance CVBUS to GND.
VIN_3V3
—
Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND.
(1) I = input, O = output, I/O = input and output, GPIO = general purpose digital input and output
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7 Specifications
7.1 Absolute Maximum Ratings
7.1.1 TPS25750D and TPS25750S - Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
-0.3
–0.3
–0.5
-0.3
MAX
6
UNIT
PP5V
VIN_3V3
4
V
ADCIN1, ADCIN2
VBUS_IN, VBUS(4)
CC1, CC2 (4)
4
28
26
6.0
Input voltage range (2)
V
V
GPIOx
I2Cm_SDA, I2Cm_SCL, I2Cm_IRQ,
I2Cs_IRQ,I2Cs_SCL, I2Cs_SDA
LDO_1V5(3)
LDO_3V3(3)
–0.3
4
–0.3
–0.3
2
Output voltage range (2)
4
internally limited
1
Source or sink current VBUS
Positive source current on CC1, CC2
Positive sink current on CC1, CC2 while VCONN
1
Source current
Source current
switch is enabled
A
Positive sink current for I2Cm_SDA, I2Cm_SCL,
I2Cm_IRQ, I2Cs_IRQ,I2Cs_SCL, I2Cs_SDA
internally limited
Positive source current for LDO_3V3, LDO_1V5
GPIOx
internally limited
0.005
175
A
TJ Operating junction temperature
TSTG Storage temperature
–40
–55
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.
(3) Do not apply voltage to these pins.
(4) A TVS with a break down voltage falling between the Recommended max and the Abs max value is recommended such as TVS2200.
7.1.2 TPS25750D - Absolute Maximum Ratings
MIN
MAX
28
UNIT
Input voltage range (1)
VPPHV_VBUS_IN
PPHV
Source-to-source voltage
–0.3
V
28
V
Sink current
Continuous current to/from
VBUS_IN to PPHV
A
7
Pulsed current to/from
VBUS_IN to PPHV(2)
10
TJ_PPHV Operating
junction temperature
PP_HV switch
–40
175
°C
(1) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.
(2) Pulse duration ≤ 100 µs and duty-cycle ≤ 1%.
7.1.3 TPS25750S - Absolute Maximum Ratings
MIN
MAX
UNIT
GATE_VBUS,
GATE_VSYS(2)
Output voltage range (1)
–0.3
40
V
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UNIT
SLVSFR7A – JULY 2020 – REVISED NOVEMBER 2020
7.1.3 TPS25750S - Absolute Maximum Ratings (continued)
MIN
MAX
VGATE_VBUS - VVBUS, V
GATE_SYS - VVSYS
VGS
–0.5
12
V
(1) All voltage values are with respect to network GND. Connect the GND pin directly to the GND plane of the board.
(2) Do not apply voltage to these pins.
7.2 ESD Ratings
PARAMETER
TEST CONDITIONS
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per
JEDEC specificationJESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommeded Operating Conditions
7.3.1 TPS25750D - Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
3.0
MAX
UNIT
VIN_3V3
PP5V
3.6
5.5
4.9
VI
Input voltage range (1)
V
ADCIN1, ADCIN2,VBUS_IN,
VBUS (2)
4
0
0
22
22
PPHV
I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ,
ADCIN1, ADCIN2
3.6
VIO
I/O voltage range (1)
V
GPIOx
0
0
5.5
5.5
3
CC1, CC2
VBUS
A
IO
Output current (from PP5V)
CC1, CC2
315
7
mA
A
IPP_HV
IO
Current from VBUS_IN to PPHV
Output current (from LDO_3V3)
GPIOx
1
mA
mA
IO
Output current (from VBUS LDO) Current from LDO_3V3
5
IPP_5V ≤ 3 A, IPP_HV = 0, IPP_CABLE
≤ 315 mA
–40
–40
–40
–40
–40
–40
85
105
45
IPP_5V ≤ 1.5 A, IPP_HV = 0, I
PP_CABLE ≤ 315 mA
IPP_5V = 0, IPP_HV ≤ 7 A, IPP_CABLE
= 0
TA
Ambient operating temperature
°C
IPP_5V = 0, IPP_HV ≤ 6 A, IPP_CABLE
= 0
65
IPP_5V = 0, IPP_HV ≤ 5 A, IPP_CABLE
≤ 315 mA
85
IPP_5V = 0, IPP_HV ≤ 3.5 A, I
PP_CABLE ≤ 315 mA
105
TJ_PPHV
TJ
Operating junction temperature
Operating junction temperature
PP_HV switch
–40
–40
150
125
°C
°C
(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
(2) All VBUS and VBUS_IN pins be shorted together.
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7.3.2 TPS25750S - Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
3.0
4.9
4
MAX
3.6
5.5
22
UNIT
VIN_3V3
PP5V
VI
Input voltage range (1)
V
VBUS
VSYS
0
22
I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ,
ADCIN1, ADCIN2
0
3.6
VIO
I/O voltage range (1)
V
GPIOx
0
0
5.5
5.5
3
CC1, CC2
VBUS
A
IO
Output current (from PP5V)
CC1, CC2
315
mA
IO
IO
Output current (from LDO_3V3)
Output current (from VBUS LDO)
GPIOx
1
5
mA
sum of current from LDO_3V3 and
GPIOx
mA
IPP_5V ≤ 1.5 A, IPP_CABLE ≤ 315 mA
IPP_5V ≤ 3 A, IPP_CABLE ≤ 315 mA
–40
–40
–40
105
85
TA
TJ
Ambient operating temperature
Operating junction temperature
°C
°C
125
(1) All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board.
7.4 Recommended Capacitance
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
VOLTAGE RATING
MIN
5
NOM
10
MAX
UNIT
µF
CVIN_3V3
CLDO_3V3
CLDO_1V5
CVBUS
Capacitance on VIN_3V3
6.3 V
6.3 V
4 V
Capacitance on LDO_3V3
Capacitance on LDO_1V5
Capacitance on VBUS(4)
Capacitance on PP5V
5
10
25
12
10
µF
4.5
µF
25 V
10 V
1
4.7
47
µF
CPP5V
120(2)
µF
Capacitance on VSYS Sink from
VBUS
CVSYS (TPS25750S)
25 V
100
µF
Capacitance on PPHV Sink from
VBUS
CPPHV (TPS25750D)
CCCy
25 V
47
100
480
µF
pF
Capacitance on CCy pins(3)
6.3 V
200
400
(1) Capacitance values do not include any derating factors. For example, if 5.0 µF is required and the external capacitor value reduces by
50% at the required operating voltage, then the required external capacitor value would be 10 µF.
(2) This is a requirement from USB PD (cSrcBulkShared). Keep at least 10 µF tied directly to PP5V.
(3) This includes all external capacitance to the Type-C receptacle.
(4) The device can be configured to quickly disable the sinking power path upon certain events. When such a configuration is used, a
capacitance on the higher side of this range is recommended.
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7.5 Thermal Information
7.5.1 TPS25750D - Thermal Information
TPS25750D
QFN (RJK)
38 PINS
THERMAL METRIC(1)
UNIT
Junction-to-ambient thermal resistance
(sinking through PP_HV)
57.4
46.5
30.5
20.3
21.1
11.1
18.2
1.0
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
Junction-to-ambient thermal resistance
(sourcing through PP_5V)
Junction-to-case (top) thermal resistance
(sinking through PP_HV)
RθJC (top)
Junction-to-case (top) thermal resistance
(sourcing through PP_5V)
Junction-to-board thermal resistance
(sinking through PP_HV)
RθJB
Junction-to-board thermal resistance
(sourcing through PP_5V)
Junction-to-top characterization parameter
(sinking through PP_HV)
ψJT
Junction-to-top characterization parameter
(sourcing through PP_5V)
Junction-to-board characterization
parameter (sinking through PP_HV)
21.1
11.1
1.8
ψJB
Junction-to-board characterization
parameter (sourcing through PP_5V)
Junction-to-case (bottom GND pad)
thermal resistance
RθJC (bot_GND)
Junction-to-case (bottom DRAIN pad)
thermal resistance
RθJC (bot_DRAIN)
4.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5.2 TPS25750S - Thermal Information
TPS25750S
THERMAL METRIC(1)
QFN (RSM)
32 PINS
30.5
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
RθJC (top)
Junction-to-case (top) thermal resistance
24.5
Junction-to-board (bottom) thermal
resistance
RθJC
2
°C/W
RθJB
ψJT
Junction-to-board thermal resistance
9.8
0.2
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization
parameter
ψJB
9.7
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.6 Power Supply Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIN_3V3, VBUS
rising
falling
3.6
3.5
3.9
3.8
VVBUS_UVLO
VBUS UVLO threshold
hysteresis
0.1
2.66
2.54
0.12
rising, VVBUS = 0
falling, VVBUS = 0
hysteresis
2.56
2.44
2.76
2.64
Voltage required on VIN_3V3 for
power on
VVIN3V3_UVLO
V
LDO_3V3, LDO_1V5
VLDO_3V3
VVIN_3V3 = 0 V, 10 µA ≤ ILOAD
18 mA, VBUS ≥ 3.9 V
≤
Voltage on LDO_3V3
3.0
3.4
1.5
3.6
1.4
V
Ω
V
RLDO_3V3
Rdson of VIN_3V3 to LDO_3V3 ILDO_3V3 = 50 mA
up to maximum internal loading
condition
VLDO_1V5
Voltage on LDO_1V5
1.49
1.65
7.7 Power Consumption
Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V, no GPIO loading
PARAMETER
TEST CONDITIONS
MIN
TYP
3
MAX UNIT
IVIN_3V3,ActSrc
IVIN_3V3,ActSnk
IVIN_3V3,IdlSrc
IVIN_3V3,IdlSnk
Current into VIN_3V3
Active Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V
Active Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V
Idle Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V
Idle Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V
mA
Current into VIN_3V3
Current into VIN_3V3
Current into VIN_3V3
3
6
mA
mA
mA
1.0
1.0
Power drawn into PP5V CCm floating, VCCn = 0.4 V, VPP5V = 5 V, VVIN_3V3 = 3.3 V, V
and VIN_3V3 in Modern VBUS = 5.0 V, GATE_VBUS, GATE_VSYS disabled, and TJ
PMstbySnk
4.1
4.5
mW
mW
Standby Sink Mode
= 25°C
Power drawn into PP5V
and VIN_3V3 in Modern
Standby Source Mode
CCm floating, CCn tied to GND through 5.1 kΩ, VPP5V = 5
V, VVIN_3V3 = 3.3 V, IVBUS = 0, TJ = 25°C
PMstbySrc
Sleep source mode: VPA_VBUS = 0 V, VPB_VBUS = 0 V, V
VIN_3V3 = 3.3 V
IPP5V,Sleep
Current into PP5V
2
µA
µA
IVIN_3V3,Sleep
Current into VIN_3V3
Sleep DRP mode: VVBUS = 0 V, VVIN_3V3 = 3.3 V
56
7.8 PP_5V Power Switch Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
ILOAD = 3 A, TJ = 25°C
ILOAD = 3 A,TJ = 125°C
MIN
TYP
MAX
UNIT
RPP_5V
RPP_5V
Resistance from PP5V to VBUS
Resistance from PP5V to VBUS
36
36
38
53
mΩ
mΩ
VPP5V = 0 V, VVBUS = 5.5 V,
PP_5V disabled, TJ ≤ 85°C,
measure IPP5V
IPP5V_REV
VBUS to PP5V leakage current
PP5V to VBUS leakage current
5
µA
µA
VPP5V = 5.5 V, VVBUS = 0 V,
PP_5V disabled, TJ ≤ 85°C,
measure IVBUS
IPP5V_FWD
15
ILIM5V
ILIM5V
ILIM5V
ILIM5V
ILIM5V
Current limit setting
Current limit setting
Current limit setting
Current limit setting
Current limit setting
Configure to setting 0
Configure to setting 1
1.15
1.61
2.3
1.36
1.90
2.70
3.58
3.78
A
A
A
A
A
Configure to setting 3
Configure to setting 4
3.04
3.22
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Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PP5V to VBUS current sense
accuracy
IVBUS
3.64 A ≥ IVBUS ≥ 1 A
3.05
3.5
3.75
A/V
RCP clears and PP_5V starts turning
on when VVBUS – VPP5V < V
PP_5V_RCP. Measure VVBUS – VPP5V
VPP_5V_RCP
10
20
mV
µs
VBUS to GND through 10
mΩ, CVBUS = 0
tiOS_PP_5V
Response time to VBUS short circuit
1.15
4.5
Enable PP_5V, IRpDef being
drawn from PP5V,
configure VOVP4RCP to
setting 2, ramp VVBUS from
tPP_5V_ovp
Response time to VVBUS > VOVP4RCP 4V to 20 V at 100 V/ms, C
µs
µs
PP5V = 2.5 µF, measure
time from OVP detection
until reverse current < 100
mA
Response time to VPP5V < V
RL = 100 Ω, no external
PP5V_UVLO, PP_VBUS is deemed off
capacitance on VBUS
tPP_5V_uvlo
4
when VVBUS < 0.8 V
VPP5V = 5.5 V, IRpDef being
drawn from PP5V, enable
PP_5V, configure VOVP4RCP
to setting 2, ramp VVBUS
Response time to VPP5V < VVBUS + V from 4 V to 21.5 V at 10
tPP_5V_rcp
0.7
µs
V/µs, measure VPP5V. C
PP_5V_RCP
PP5V = 104 µF, CVBUS=10
µF, measure time from
RCP detection until reverse
current < 100 mA
tILIM
tON
Current clamping deglitch time
5.1
3.3
ms
ms
From enable signal to VBUS at 90% RL = 100 Ω, VPP5V = 5 V, C
2.3
0.30
1.2
4.3
0.6
of final value
From disable signal to VBUS at 10% RL = 100 Ω, VPP5V = 5 V, C
of final value L = 0
L = 0
tOFF
tRISE
tFALL
0.45
1.7
ms
ms
ms
VBUS from 10% to 90% of final value RL = 100 Ω, VPP5V = 5 V, C
L = 0
2.2
VBUS from 90% to 10% of initial
value
RL = 100 Ω, VPP5V = 5 V, C
L = 0
0.06
0.1
0.14
7.9 PPHV Power Switch Characteristics - TPS25750D
Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TJ_PPHV = 25°C, IPPHV = 6.5
A
16
19
mΩ
Resistance from VBUS_IN to PPHV TJ_PPHV = 125°C, IPPHV
=
RPPHV
24
27
6
29
32
10
12
14
16
power switch resistance
6.5A
TJ_PPHV = 150°C, IPPHV
6.5 A
=
mΩ
mV
mV
mV
mV
Setting 0, 4 V ≤ VVBUS ≤ 22
V, VVIN_3V3 ≤ 3.63 V
2
4
6
8
setting 1, 4 V ≤ VVBUS ≤ 22
V, VVIN_3V3 ≤ 3.63 V
8
Comparator mode RCP threshold, V
PPHV - VVBUS
VRCP
Setting 2, 4 V ≤ VVBUS ≤ 22
V, VVIN_3V3 ≤ 3.63 V
10
12
Setting 3, 4 V ≤ VVBUS ≤ 22
V, VVIN_3V3 ≤ 3.63 V
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Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4 V ≤ VVBUS ≤ 22 V, ILOAD
100 mA, 500 pF < C
GATE_VSYS < 16 nF,
measure slope from 10% to
90% of final VSYS value
=
Soft start slew rate for GATE_VSYS,
setting 0
0.35
0.41
0.47
4 V ≤ VVBUS ≤ 22 V, ILOAD
100 mA, 500 pF < C
GATE_VSYS < 16 nF,
measure slope from 10% to
90% of final VSYS value
=
Soft start slew rate for GATE_VSYS,
setting 1
0.67
1.33
2.8
0.81
1.7
0.95
2.0
SS
V/ms
4 V ≤ VVBUS ≤ 22 V, ILOAD
100 mA, 500 pF < C
GATE_VSYS < 16 nF,
measure slope from 10% to
90% of final VSYS value
=
Soft start slew rate for GATE_VSYS,
setting 2
4 V ≤ VVBUS ≤ 22 V, ILOAD
100 mA, 500 pF < C
GATE_VSYS < 16 nF,
measure slope from 10% to
90% of final VSYS value
=
Soft start slew rate for GATE_VSYS,
setting 3
3.3
3.80
1000
VVBUS = 20 V, VPPHV = 20 V
(initially), CPPHV< 1 nF, I
PPHV = 0.1 A, switch is off
Time allowed to disable the internal
PPHV switch in normal shutdown
mode
tPPHV_OFF
400
µs
µs
when VVBUS_IN – VPPHV
1V
>
OVP: VOVP4RCP = setting
57, VVBUS = 20 V initially,
then raised to 23 V in 50
Time allowed to disable the internal
PPHV switch in fast shutdown mode ns, VPPHV = V
tPPHV_OVP
2
4
(VOVP4RCP exceeded), this includes
the response time of the comparator nF, IPPHV = 0.1 A, switch is
off when VVBUS_IN – V
VBUS_IN (initially), CPPHV< 1
PPHV > 0.1 V
RCP: VRCP= setting 0, V
VBUS = 5 V, VVSYS = 5 V
Time allowed to disable the internal
PPHV switch in fast shutdown mode with dV/dt = 0.1 V/µs, C
initially, then raised to 6 V
tPPHV_RCP
1
2
µs
(VRCP exceeded), this includes the
response time of the comparator
VBUS=10 µF, measure time
from VVSYS > VBUS + VRCP
to the time of peak voltage
on VBUS
VPPHV = 20 V (initially), V
VBUS=20 V then raised to
23 V in 50 ns, rOVP = 1, C
PPHV < 1 nF, IPPHV = 0.1 A,
switch is off when VVBUS_IN
– VPPHV > 0.5 V
Time allowed to disable the internal
PPHV switch in fast shutdown mode
(OVP)
tPPHV_FSD
0.25
20
μs
μs
VVBUS_IN = 5 V, CPPHV = 0, I
PPHV = 0, measure time
from register write to
enable PPHV until V
VBUS_IN - VPPHV < 0.1 V,
soft start setting 3
Time to enable the internal PPHV
switch
tPPHV_ON
1500
1800
2100
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7.10 PP_EXT Power Switch Characteristics - TPS25750S
Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0 ≤ VGATE_VSYS - VVSYS ≤ 6
V, VVSYS ≤ 22 V, VVBUS > 4
V, measure IGATE_VSYS
8.5
11.5
µA
IGATE_ON
Gate driver sourcing current
0 ≤ VGATE_VBUS - VVBUS ≤ 6
V, 4 V ≤ VVBUS ≤ 22 V,
measure IGATE_VBUS
8.5
6
11.5
12
µA
V
0 ≤ VVSYS ≤ 22 V, I
GATE_VSYS < 4 µA, measure
VGATE_VSYS – VVSYS, VVBUS
> 4 V
VGATE_ON
Sourcing voltage (ON)
4 V ≤ VVBUS ≤ 22 V, I
GATE_VBUS < 4 µA, measure
VGATE_VBUS – VVBUS
6
12
V
Setting 0, 4 V ≤ VVBUS ≤ 22
V, VVIN_3V3 ≤ 3.63 V
2
4
6
8
6
8
10
12
14
16
mV
mV
mV
mV
Setting 1, 4 V ≤ VVBUS ≤ 22
V, VVIN_3V3 ≤ 3.63 V
Comparator mode RCP threshold, V
VSYS - VVBUS
VRCP
Setting 2, 4 V ≤ VVBUS ≤ 22
V, VVIN_3V3 ≤ 3.63 V
10
12
Setting 3, 4 V ≤ VVBUS ≤ 22
V, VVIN_3V3 ≤ 3.63 V
Normal turnoff: VVSYS = 5
V, VGATE_VSYS = 6 V,
measure IGATE_VSYS
13
13
µA
µA
IGATE_OFF
Sinking strength
Normal turnoff: VVBUS = V
VSYS = 5 V, VGATE_VBUS = 6
V, measure IGATE_VBUS
Fast turnoff: VVSYS = 5 V, V
GATE_VSYS = 6 V, assert
PPHV1_FAST_DISABLE,
measure RGATE_VSYS
85
85
Ω
Ω
RGATE_FSD
Sinking strength
Fast turnoff: VVBUS = VVSYS
= 5 V, VGATE_VBUS = 6 V,
assert
PPHV1_FAST_DISABLE,
measure RGATE_VBUS
VVIN_3V3 = 0 V, VVBUS = 3.0
V, VGATE_VSYS = 0.1 V,
measure resistance from
GATE_VSYS to GND
RGATE_OFF_UVLO
Sinking strength in UVLO (safety)
1.5
MΩ
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Operating under these conditions unless otherwise noted: , 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4 V ≤ VVBUS ≤ 22 V, ILOAD
100 mA, 500 pF < C
GATE_VSYS < 16 nF,
measure slope from 10% to
90% of final VSYS value
=
Soft start slew rate for GATE_VSYS,
setting 0
0.35
0.41
0.47
4 V ≤ VVBUS ≤ 22 V, ILOAD
100 mA, 500 pF < C
GATE_VSYS < 16 nF,
measure slope from 10% to
90% of final VSYS value
=
Soft start slew rate for GATE_VSYS,
setting 1
0.67
1.33
2.8
0.81
1.7
0.91
1.80
3.80
4000
SS
V/ms
4 V ≤ VVBUS ≤ 22 V, ILOAD
100 mA, 500 pF < C
GATE_VSYS < 16 nF,
measure slope from 10% to
90% of final VSYS value
=
Soft start slew rate for GATE_VSYS,
setting 2
4 V ≤ VVBUS ≤ 22 V, ILOAD
100 mA, 500 pF < C
GATE_VSYS < 16 nF,
measure slope from 10% to
90% of final VSYS value
=
Soft start slew rate for GATE_VSYS,
setting 3
3.3
VVBUS = 20 V, QG of
Time allowed to disable the external external FET = 40 nC or C
tGATE_VBUS_OFF
FET via GATE_VBUS in normal
GATE_VBUS < 3 nF, gate is off
when VGATE_VBUS – VVBUS
< 1 V
450
µs
µs
shutdown mode.(1)
OVP: VOVP4RCP = setting
Time allowed to disable the external 57, VVBUS = 20 V initially,
FET via GATE_VBUS in fast
shutdown mode (VOVP4RCP
exceeded), this includes the
response time of the comparator(1)
then raised to 23 V in 50
ns, QG of external FET = 40
nC or CGATE_VBUS < 3 nF,
gate is off when V
tGATE_VBUS_OVP
3
5
GATE_VBUS – VVBUS < 1 V
RCP: VRCP = setting 0, V
Time allowed to disable the external VBUS = 5 V, VVSYS = 5 V
FET via GATE_VBUS in fast
shutdown mode (VRCP exceeded),
initially, then raised to 5.5 V
in 50 ns, QG of external
tGATE_VBUS_RCP
1
2
µs
µs
this includes the response time of the FET = 40 nC or CGATE_VBUS
comparator(1)
< 3 nF, gate is off when V
GATE_VBUS – VVBUS < 1 V
VVSYS= 20 V, QG of
Time allowed to disable the external external FET = 40 nC or C
tGATE_VSYS_OFF
FET via GATE_VSYS in normal
GATE_VBUS < 3 nF, gate is off
when VGATE_VSYS – VVSYS
< 1 V
450
4000
shutdown mode(1)
VVBUS = 20 V initially, then
raised to 23 V in 50 ns, QG
of external FET = 40 nC or
CGATE_VBUS < 3 nF, gate is
off when VGATE_VSYS – V
VSYS < 1 V, rOVP = 1
Time allowed to disable the external
FET via GATE_VSYS in fast
shutdown mode (OVP)(1)
tGATE_VSYS_FSD
0.25
0.25
20
2
μs
Measure time from when V
GS = 0 V until VGS >3 V,
tGATE_VBUS_ON
Time to enable GATE_VBUS (1)
ms
where VGS = VGATE_VBUS
VVBUS
–
(1) These values depend upon the characteristics of the external N-ch MOSFET. The typical values were measured when
Px_GATE_VSYS and Px_GATE_VBUS were used to drive two CSD17571Q2 in common drain back-to-back configuration.
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7.11 Power Path Supervisory
Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
5.0
TYP
MAX
24
UNIT
VBUS overvoltage protection for RCP OVP detected when VVBUS
>
VOVP4RCP
V
programmable range
Hysteresis
VOVP4RCP
VOVP4RCPH
1.75
2
1
2.25
%
setting 0
setting 1
setting 2
setting 3
V/V
V/V
V/V
V/V
Ratio of OVP4RCP input used for
OVP4VSYS comparator. rOVP × V
0.95
0.90
0.875
rOVP
= VOVP4RCP
OVP4VSYS
VBUS overvoltage protection range for OVP detected when rOVP
×
VOVP4VSYS
5
1.75
1.8
1.9
2
27.5
2.25
2.4
V
VSYS protection
Hysteresis
VVBUS > VOVP4RCP
VBUS falling, % of V
OVP4VSYS, rOVP setting 0
2
2.1
2.2
2.3
VBUS falling, % of V
OVP4VSYS, rOVP setting 1
VOVP4VSYS
%
VBUS falling, % of V
2.5
OVP4VSYS, rOVP setting 2
VBUS falling, % of V
OVP4VSYS, rOVP setting 3
2.6
rising
3.9
3.8
4.1
4.0
0.1
4.3
4.2
VPP5V_UVLO
Voltage required on PP5V
VBUS discharge current
falling
V
hysteresis
VVBUS = 22 V, measure I
IDSCH
4
15
mA
VBUS
7.12 CC Cable Detection Parameters
Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Type-C Source (Rp pullup)
Unattached CCy open circuit
voltage while Rp enabled, no load
VOC_3.3
VOC_5
VLDO_3V3 > 2.302 V, RCC = 47 kΩ
VPP5V > 3.802 V, RCC = 47 kΩ
1.85
2.95
V
V
Attached CCy open circuit voltage
while Rp enabled, no load
VCCy = 5.5 V, VCCx = 0 V, V
LDO_3V3_UVLO < VLDO_3V3 < 3.6 V, V
PP5V = 3.8 V, measure current into
CCy
10
10
Unattached reverse current on
CCy
IRev
µA
VCCy = 5.5 V, VCCx = 0 V, V
LDO_3V3_UVLO < VLDO_3V3 < 3.6 V, V
PP5V = 0, TJ ≤ 85°C, measure
current into CCy
IRpDef
IRp1.5
Current source - USB Default
Current source - 1.5 A
0 < VCCy < 1.0 V, measure ICCy
64
80
96
µA
µA
4.75 V < VPP5V < 5.5 V, 0 < VCCy
1.5 V, measure ICCy
<
<
166
180
194
4.75 V < VPP5V < 5.5 V, 0 < VCCy
2.45 V, measure ICCy
IRp3.0
Current source - 3.0 A
304
330
356
µA
V
Type-C Sink (Rd pulldown)
Open/Default detection threshold
when Rd applied to CCy
VSNK1
rising
falling
0.2
0.24
0.20
Open/Default detection threshold
when Rd applied to CCy
0.16
V
V
VSNK1
Hysteresis
0.04
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Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
0.62
0.63
TYP
MAX
0.68
0.69
UNIT
VSNK2
VSNK2
Default/1.5-A detection threshold
Default/1.5-A detection threshold
Hysteresis
falling
rising
V
V
V
0.66
0.01
1.5-A/3.0-A detection threshold
when Rd applied to CCy
VSNK3
falling
rising
1.17
1.22
1.25
1.3
V
1.5-A/3.0-A detection threshold
when Rd applied to CCy
V
V
VSNK3
Hysteresis
0.05
0.25 V ≤ VCCy ≤ 2.1 V, measure
resistance on CCy, after trimming
RSNK
Rd pulldown resistance
4.6
4.0
5.6
kΩ
kΩ
using trim_cd_rd, VLDO_3V3_UVLO
VLDO_3V3 < 3.6 V,
<
0V ≤ VCCy ≤ 5.5 V, measure
resistance on CCy, after trimming
using trim_cd_rd
RVCONN_DIS
VCONN discharge resistance
Dead battery Rd clamp
6.12
VVIN_3V3 = 0 V, 64 µA < ICCy < 96
µA
0.25
0.65
1.20
500
500
1.32
1.32
2.18
VVIN_3V3 = 0 V, 166 µA < ICCy
194 µA
<
VCLAMP
V
VVIN_3V3 = 0 V, 304 µA < ICCy
356 µA
<
VVBUS = 0, VVIN_3V3 = 3.3 V, VCCy
= 5 V, measure resistance on CCy
kΩ
kΩ
Resistance from CCy to GND
when configured as open
ROpen
VVBUS = 5 V, VVIN_3V3 = 0, VCCy
=
5 V, measure resistance on CCy
7.13 CC VCONN Parameters
Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
VPP5V = 5 V, IL = 250 mA,
measure resistance from PP5V
to CCy
RPP_CABLE
Rdson of the VCONN path
1.2
Ω
Setting 0, VPP5V = 5 V, RL=10
mΩ, measure ICCy
ILIMVC
ILIMVC
Short circuit current limit
Short circuit current limit
350
540
410
600
470
660
mA
mA
Setting 1, VPP5V = 5 V, RL=10
mΩ, measure ICCy
VCONN disabled, TJ ≤ 85°C, V
CCy = 5.5 V, VPP5V = 0 V, VVBUS
= 5 V, LDO forced to draw from
VBUS, measure ICCy
Reverse leakage current
through VCONN FET
ICC2PP5V
10
µA
Overvoltage protection
threshold for PP_CABLE
VVC_OVP
VPP5V rising
5.6
60
5.9
6.2
340
470
V
VPP5V ≥ 4.9 V, VCCy = VPP5V, V
CCx rising
200
mV
Reverse current protection
threshold for PP_CABLE,
sourcing VCONN through CCx
VVC_RCP
VPP5V ≥ 4.9 V, VCCy ≤ 4 V, VCCx
rising
210
340
1.3
mV
ms
tVCILIM
Current clamp deglitch time
Time to disable PP_CABLE
tPP_CABLE_FSD
after VPP5V > VVC_OVP or VCCx - CL = 0
VPP5V > VVC_RCP
0.5
µs
µs
From disable signal to CCy at
10% of final value
IL = 250 mA, VPP5V = 5 V, CL =
0
tPP_CABLE_off
100
200
300
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Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
VPP5V = 5 V, for short circuit RL
= 10 mΩ
tiOS_PP_CABLE
Response time to short circuit
2
µs
7.14 CC PHY Parameters
Operating under these conditions unless otherwise noted: and ( 3.0 V ≤ VVIN_3V3 ≤ 3.6 V or VVBUS ≥ 3.9 V )
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmitter
VTXHI
Transmit high voltage on CCy
Transmit low voltage on CCy
Standard External load
Standard External load
1.05
–75
1.125
1.2
75
V
VTXLO
mV
Transmit output impedance while
driving the CC line using CCy
ZDRIVER
measured at 750 kHz
33
54
75
Ω
Rise time. 10 % to 90 % amplitude
points on CCy, minimum is under
an unloaded condition. Maximum
set by TX mask
tRise
CCCy = 520 pF
300
ns
Fall time. 90 % to 10 % amplitude
points on CCy, minimum is under
an unloaded condition. Maximum
set by TX mask
tFall
CCCy = 520 pF
300
5.5
ns
V
0 ≤ VVIN_3V3 ≤ 3.6 V, 0 ≤ VPP5V
≤
OVP detection threshold for USB 5.5 V, VVBUS ≥ 4 V. Initially VCC1
PD PHY 5.5 V and VCC2 ≤ 5.5 V, then VCCx
≤
VPHY_OVP
8.5
rises
Receiver
Does not include pullup or
ZBMCRX
Receiver input impedance on CCy pulldown resistance from cable
detect. Transmitter is Hi-Z
1
MΩ
Capacitance looking into the CC
Receiver capacitance on CCy(1)
CCC
120
551
866
270
578
pF
pin when in receiver mode
Rising threshold on CCy for
Sink mode (rising)
VRX_SNK_R
VRX_SRC_R
VRX_SNK_F
VRX_SRC_F
499
784
230
523
525
825
250
550
mV
mV
mV
mV
receiver comparator
Rising threshold on CCy for
Source mode (rising)
receiver comparator
Falling threshold on CCy for
Sink mode (falling)
receiver comparator
Falling threshold on CCy for
Source mode (falling)
receiver comparator
(1) CCC includes only the internal capacitance on a CCy pin when the pin is configured to be receiving BMC data. External capacitance is
needed to meet the required minimum capacitance per the USB-PD Specifications (cReceiver). Therefore, TI recommends adding C
CCy externally.
7.15 Thermal Shutdown Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Temperature rising
Hysteresis
MIN
TYP
160
15
MAX
UNIT
°C
145
175
TSD_MAIN
Temperature shutdown threshold
°C
Temperature controlled shutdown Temperature rising
threshold. The power paths for
135
150
165
°C
each port sourcing from PP5V and
TSD_PP5V
PP_CABLE power paths have
local sensors that disables them
when this temperature is exceeded
Hysteresis
10
°C
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7.16 ADC Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.6-V max scaling, voltage
divider of 3
14
mV
LSB
Least significant bit
25.2-V max scaling, voltage
divider of 21
98
mV
mA
4.07-A max scaling
16.5
0.05 V ≤ VADCINx ≤ 3.6 V, V
ADCINx ≤ VLDO_3V3
–2.7
2.7
0.05 V ≤ VGPIOx ≤ 3.6 V, VGPIOx
≤ VLDO_3V3
GAIN_ERR
Gain error
%
2.7 V ≤ VLDO_3V3 ≤ 3.6 V
0.6 V ≤ VVBUS ≤ 22 V
1 A ≤ IVBUS ≤ 3 A
–2.4
–2.1
–2.1
2.4
2.1
2.1
0.05 V ≤ VADCINx ≤ 3.6 V, V
ADCINx ≤ VLDO_3V3
–4.1
4.1
0.05 V ≤ VGPIOx ≤ 3.6 V, VGPIOx
≤ VLDO_3V3
mV
mA
VOS_ERR
Offset error(1)
2.7 V ≤ VLDO_3V3 ≤ 3.6 V
0.6 V ≤ VVBUS ≤ 22 V
1 A ≤ IVBUS ≤ 3 A
–4.5
–4.1
–4.5
4.5
4.1
4.5
(1) The offset error is specified after the voltage divider.
7.17 Input/Output (I/O) Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB_P, USB_N
GPIO_VIH
GPIOx high-Level input voltage VLDO_3V3 = 3.3 V
GPIOx low-level input voltage VLDO_3V3 = 3.3 V
GPIOx input hysteresis voltage VLDO_3V3 = 3.3 V
1.3
V
V
GPIO_VIL
0.54
GPIO_HYS
0.09
–1
V
GPIO_ILKG
GPIO_RPU
GPIOx leakage current
GPIOx internal pullup
GPIOx internal pulldown
GPIOx input deglitch
VGPIOx = 3.45 V
Pullup enabled
Pulldown enabled
1
150
150
50
µA
kΩ
kΩ
ns
50
100
100
20
GPIO_RPD
50
GPIO_DG
GPIO0-7 (Outputs)
GPIO_VOH
GPIOx output high voltage
GPIOx output low voltage
VLDO_3V3 = 3.3 V, IGPIOx= -2 mA
VLDO_3V3 = 3.3 V, IGPIOx = 2 mA
2.9
–1
V
V
GPIO_VOL
0.4
1
ADCIN1, ADCIN2
ADCIN_ILKG
ADCINx leakage current
VADCINx ≤ VLDO_3V3
µA
ms
Time from LDO_3V3 going high
until ADCINx is read for
configuration
tBOOT
10
7.18 BC1.2 Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
DATA CONTACT DETECT
IDP_SRC DCD source current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLDO_3V3 = 3.3 V
7
10
13
µA
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Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
14.25
14.25
TYP
20
MAX
24.8
24.8
UNIT
kΩ
RDM_DWN
RDP_DWN
DCD pulldown resistance
DCD pulldown resistance
VUSB_N = 3.6 V
VUSB_P = 3.6 V
20
kΩ
VUSB_P ≥ VLGC_HI, VLDO_3V3 = 3.3 V, R
USB_P = 300 kΩ
VLGC_HI
VLGC_LO
Threshold for no connection
Threshold for connection
2
0
3.6
0.8
V
V
VUSB_N ≤ VLGC_LO, VLDO_3V3 = 3.3 V, R
USB_P = 24.8 kΩ
Advertisement and Detection
VDX_SRC
VDX_ILIM
IDX_SNK
IDX_SNK
Source voltage
VDX_SRC current limit
Sink Current
CGPIO4 ≤ 600 pF
0.55
250
25
0.6
0.65
400
125
125
V
µA
µA
µA
VUSB_P ≥ 250 mV
VUSB_N ≥ 250 mV
75
75
Sink Current
25
0.5 V ≤ VUSB_P ≤ 0.7 V, 25 µA ≤ IUSB_N
≤ 175 µA
RDCP_DAT
Dedicated Charging Port Resistance
200
Ω
7.19 I2C Requirements and Characteristics
Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2Cs_IRQ
OD_VOL_IRQ
OD_LKG_IRQ
I2Cm_IRQ
Low level output voltage
Leakage Current
IOL = 2 mA
0.4
1
V
Output is Hi-Z, VI2Cx_IRQ = 3.45 V
–1
µA
IRQ_VIH
High-Level input voltage
VLDO_3V3 = 3.3 V
1.3
V
V
IRQ_VIH_THRESH
IRQ_VIL
High-Level input voltage threshold VLDO_3V3 = 3.3 V
0.72
1.3
0.54
1.08
low-level input voltage
low-level input voltage threshold
input hysteresis voltage
input deglitch
VLDO_3V3 = 3.3 V
VLDO_3V3 = 3.3 V
VLDO_3V3 = 3.3 V
V
IRQ_VIL_THRESH
IRQ_HYS
0.54
0.09
V
V
IRQ_DEG
20
ns
µA
IRQ_ILKG
I2C3m_IRQ leakage current
VI2C3m_IRQ = 3.45 V
–1
1
SDA and SCL Common Characteristics (Master, Slave)
VIL
Input low signal
VLDO_3V3 = 3.3 V
0.54
V
V
VIH
Input high signal
VLDO_3V3 = 3.3 V
1.3
VHYS
VOL
ILEAK
IOL
Input hysteresis
VLDO_3V3 = 3.3 V
0.165
V
Output low voltage
Input leakage current
Max output low current
Max output low current
IOL = 3 mA
0.36
3
V
Voltage on pin = VLDO_3V3
VOL = 0.4 V
–3
15
20
12
12
µA
mA
mA
ns
ns
ns
pF
IOL
VOL = 0.6 V
VDD = 1.8 V, 10 pF ≤ Cb ≤ 400 pF
VDD = 3.3 V, 10 pF ≤ Cb ≤ 400 pF
80
150
50
Fall time from 0.7 × VDD to 0.3 × V
tf
DD
tSP
CI
I2C pulse width surpressed
Pin capacitance (internal)
10
Capacitive load for each bus line
(external)
Cb
400
pF
SDA and SCL Standard Mode Characteristics (Slave)
fSCLS
Clock frequency for slave
Valid data time
VDD = 1.8 V or 3.3 V
100
kHz
µs
Transmitting Data, VDD = 1.8 V or
3.3 V, SCL low to SDA output valid
tVD;DAT
3.45
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Operating under these conditions unless otherwise noted: 3.0 V ≤ VVIN_3V3 ≤ 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmitting Data, VDD = 1.8 V or
3.3 V, ACK signal from SCL low to
SDA (out) low
tVD;ACK
Valid data time of ACK condition
3.45
µs
SDA and SCL Fast Mode Characteristics (Slave)
fSCLS
Clock frequency for slave
VDD = 1.8 V or 3.3 V
100
400
0.9
kHz
µs
Transmitting data, VDD = 1.8 V,
SCL
tVD;DAT
Valid data time
low to SDA output valid
Transmitting data, VDD = 1.8 V or
3.3 V, ACK
signal from SCL low to SDA (out)
low
tVD;ACK
Valid data time of ACK condition
0.9
µs
SDA and SCL Fast Mode Plus Characteristics (Slave)
Clock frequency for Fast Mode
fSCLS
VDD = 1.8 V or 3.3 V
400
800
kHz
µs
Plus(1)
Transmitting data, VDD = 1.8 V or
3.3 V, SCL
tVD;DAT
Valid data time
0.55
low to SDA output valid
Transmitting data, VDD = 1.8 V or
3.3 V, ACK
signal from SCL low to SDA (out)
low
tVD;ACK
Valid data time of ACK condition
0.55
410
µs
SDA and SCL Fast Mode Characteristics (Master)
fSCLM
Clock frequency for master
VDD = 3.3 V
VDD = 3.3 V
390
kHz
µs
Start or repeated start condition
hold time
tHD;STA
0.6
tLOW
tHIGH
Clock low time
Clock high time
VDD = 3.3 V
VDD = 3.3 V
1.3
0.6
µs
µs
Start or repeated start condition
setup time
tSU;STA
VDD = 3.3 V
0.6
µs
tSU;DAT
tSU;STO
Serial data setup time
Transmitting data, VDD = 3.3 V
VDD = 3.3 V
100
0.6
ns
µs
Stop condition setup time
Bus free time between stop and
start
tBUF
VDD = 3.3 V
1.3
µs
µs
Transmitting data, VDD = 3.3 V,
SCL low to SDA output valid
tVD;DAT
Valid data time
0.9
0.9
Transmitting data, VDD = 3.3 V,
ACK signal from SCL low to SDA
(out) low
tVD;ACK
Valid data time of ACK condition
µs
(1) Master must control fSCLS to ensure tLOW > tVD; ACK.
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7.20 Typical Characteristics
50
48
46
44
42
40
38
36
34
32
1.05
1
0.95
0.9
0.85
0.8
0.75
0.7
0.65
0.6
-20
0
20
40
60
TJ (oC)
80
100
120
140
-20
0
20
40
60
TJ (oC)
80
100
120
140
TypG
TypG
Figure 7-2. PP_CABLE Rdson vs. Temperature
Figure 7-1. PP_5V Rdson vs. Temperature.
7.5
5.8
VPx_VBUS = 4V
VPx_VBUS = 22V
5.78
5.76
5.74
5.72
5.7
7
6.5
6
5.5
5
-50
0
50
TJ (oC)
100
150
-60
-30
0
30
60
90
120
150
TJ (oC)
TypG
TypG
Figure 7-4. VOVP4RCP (Setting 2) vs. Temperature
Figure 7-3. VRCP vs. Temperature
100
28
26
24
22
20
18
16
14
Single Pulse Duration
70
50
100 ms
10 ms
1 ms
100 ms
10 ms
30
20
10
7
5
3
2
1
0.7
0.5
0.3
0.2
0.1
0.1
0.2 0.3
0.5 0.7
1
2
3
4
5
6 7 8 10
20 30 40 50
-20
0
20
40
60
80
100 120 140 160
Source-to-Source Voltage (V)
SOAf
TJ (oC)
TypG
Figure 7-6. Safe-Operating-Area (SOA) of PPHV for TPS25750D
Figure 7-5. RPPHV vs. Temperature for TPS25750D
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7.20 Typical Characteristics (continued)
10.2
10.15
10.1
10.05
10
9.4
9.2
IGATE_VBUS
IGATE_VSYS
9
GATE_VSYS: VSYS= 0 V
GATE_VSYS: VSYS= 22 V
8.8
GATE_VBUS
8.6
8.4
8.2
8
9.95
9.9
9.85
7.8
-40
-20
0
20
40
60
TJ (oC)
80
100
120
140
-20
0
20
40
60
80
100 120 140
TJ (oC)
TypG
TypG
Figure 7-8. VGATE_VSYS_ON vs. Temperature for TPS25750S
Figure 7-7. VGATE_VBUS_ON vs. Temperature for TPS25750S
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8 Parameter Measurement Information
t
f
t
r
t
SU;DAT
70 %
30 %
70 %
30 %
SDA
cont.
cont.
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
t
r
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
SCL
t
HD;STA
t
LOW
th
9
clock
1 / f
S
SCL
st
1
clock cycle
t
BUF
SDA
SCL
t
VD;ACK
t
t
t
t
SU;STO
SU;STA
HD;STA
SP
70 %
30 %
Sr
P
S
th
9
clock
002aac938
Figure 8-1. I2C Slave Interface Timing
ILIM5V, ILIMVC
tiOS_PP_5V, tiOS_PP_CABLE
Figure 8-2. Short-circuit Response Time for Internal Power Paths PP_5Vx and PP_CABLEx
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9 Detailed Description
9.1 Overview
The TPS25750 is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug and
orientation detection for USB Type-C and PD receptacles. The TPS25750 communicates with the cable and
another USB Type-C and PD device at the opposite end of the cable. It also enables integrated port power
switch for sourcing, and controls a high current port power switch for sinking.
The TPS25750 is divided into several main sections:
•
•
•
•
•
USB-PD controller
Cable plug and orientation detection circuitry
Port power switches
Power management circuitry
Digital core
The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD
data is output through either the CC1 pin or the CC2 pin, depending on the orientation of the reversible USB
Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features, and
more detailed circuitry, see USB-PD Physical Layer.
The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug
insertion the cable orientation. For a high-level block diagram of cable plug and orientation detection, a
description of its features, and more detailed circuitry, see Cable Plug and Orientation Detection.
The port power switches provide power to the VBUS pin and CC1 or CC2 pins based on the detected plug
orientation. For a high-level block diagram of the port power switches, a description of its features, and more
detailed circuitry, see Power Paths.
The power management circuitry receives and provides power to the TPS25750 internal circuitry and LDO_3V3
output. See Power Management for more information.
The digital core provides the engine for receiving, processing, and sending all USB-PD packets as well as
handling control of all other TPS25750 functionality. A portion of the digital core contains ROM memory, which
contains all the necessary firmware required to execute Type-C and PD applications. In addition, a section of the
ROM, called boot code, is capable of initializing the TPS25750, loading of the device configuration information,
and loading any code patches into volatile memory in the digital core. For a high-level block diagram of the
digital core, a description of its features, and more detailed circuitry, see Digital Core.
The TPS25750 has one I2C master to write to and read from external slave devices such as a battery charger or
an optional external EEPROM memory (see I2C Interface).
The TPS25750 also integrates a thermal shutdown mechanism and runs off of accurate clocks provided by the
integrated oscillator.
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9.2 Functional Block Diagram
PPHV
PP5V
VBUS_IN
VBUS
LDO_3V3
LDO_1V5
Power Supervisor
VIN_3V3
GND
ADCIN1
ADCIN2
3
I2Cm_SDA/SCL/IRQ
Core & Other Digital
3
I2Cs_SDA/SCL/IRQ
CC1
CC2
Cable Detect, Cable Power, & USB
PD PHY
9
GPIO0-7,11
Figure 9-1. TPS25750D
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PA_VBUS
PP5V
3A
LDO_3V3
LDO_1V5
VSYS
VIN_3V3
GND
Power Supervisor
ADCIN1
ADCIN2
3
3
I2Cm_SDA/SCL/IRQ
I2Cs_SDA/SCL/IRQ
Core & Other Digital
PA_CC1
Cable Detect, Cable Power, & USB
PD PHY
9
PA_CC2
GPIO0-7,11
Figure 9-2. TPS25750S
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9.3 Feature Description
9.3.1 USB-PD Physical Layer
Figure 9-3 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and
orientation detection block.
Fast
current
limit
IVCON
PP5V
CC1 Gate Control and Current
Limit
LDO_3V3
IRp
RSNK
CC1
Digital
Core
USB-PD PHY
(Rx/Tx)
CC2
LDO_3V3
IRp
RSNK
CC1 Gate Control and Current
Limit
Fast
current
limit
Figure 9-3. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry
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USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output
on the same pin (CC1 or CC2) that is DC biased due to the Rp (or Rd) cable attach mechanism.
9.3.1.1 USB-PD Encoding and Signaling
Figure 9-4 illustrates the high-level block diagram of the baseband USB-PD transmitter. Figure 9-5 illustrates the
high-level block diagram of the baseband USB-PD receiver.
4b5b
Encoder
BMC
Encoder
Data
to PD_TX
CRC
Figure 9-4. USB-PD Baseband Transmitter Block Diagram
Data
BMC
Decoder
SOP
Detect
4b5b
Decoder
from PD_RX
CRC
Figure 9-5. USB-PD Baseband Receiver Block Diagram
9.3.1.2 USB-PD Bi-Phase Marked Coding
The USB-PD physical layer implemented in the TPS25750 is compliant to the USB-PD Specifications. The
encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark
Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in
the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity
(limited to 1/2 bit over an arbitrary packet, so a very low DC level). Figure 9-6 illustrates Biphase Mark Coding.
0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
0
1
1
Data in
BMC
Figure 9-6. Biphase Mark Coding Example
The USB PD baseband signal is driven onto the CC1 or CC2 pin with a tri-state driver. The tri-state driver is slew
rate to limit coupling to D+/D– and to other signal lines in the Type-C fully featured cables. When sending the
USB-PD preamble, the transmitter starts by transmitting a low level. The receiver at the other end tolerates the
loss of the first edge. The transmitter terminates the final bit by an edge to ensure the receiver clocks the final bit
of EOP.
9.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks
The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded “1” contains a signal edge
at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning, the masks
are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The boundaries of the
Rx outer mask are specified to accommodate a change in signal amplitude due to the ground offset through the
cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly, the boundaries of
the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time masks are
superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge rate that
has minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits on the rise
and fall times. Refer to the USB-PD Specifications for more details.
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9.3.1.4 USB-PD BMC Transmitter
The TPS25750 transmits and receives USB-PD data over one of the CCy pins for a given CC pin pair (one pair
per USB Type-C port). The CCy pins are also used to determine the cable orientation and maintain the cable/
device attach detection. Thus, a DC bias exists on the CCy pins. The transmitter driver overdrives the CCy DC
bias while transmitting, but returns to a Hi-Z state, allowing the DC voltage to return to the CCy pin when it is not
transmitting. While either CC1 or CC2 can be used for transmitting and receiving, during a given connection only,
the one that mates with the CC pin of the plug is used, so there is no dynamic switching between CC1 and CC2.
Figure 9-7 shows the USB-PD BMC TX and RX driver block diagram.
LDO_3V3
PD_TX
Level Shifter
Driver
CC1
CC2
PD_RX
Level Shifter
Digitally
Adjustable
VREF (VRXHI, VRXLO
)
USB-PD Modem
Figure 9-7. USB-PD BMC TX/Rx Block Diagram
Figure 9-8 shows the transmission of the BMC data on top of the DC bias. Note that the DC bias can be
anywhere between the minimum and maximum threshold for detecting a Sink attach. This means that the DC
bias can be above or below the VOH of the transmitter driver.
VOH
DC Bias
DC Bias
VOL
VOH
DC Bias
DC Bias
VOL
Figure 9-8. TX Driver Transmission with DC Bias
The transmitter drives a digital signal onto the CCy lines. The signal peak, VTXHI, is set to meet the TX masks
defined in the USB-PD Specifications. Note that the TX mask is measured at the far-end of the cable.
When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by the
driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts the
noise ingression in the cable.
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Figure 9-9 shows the simplified circuit determining Z DRIVER. It is specified such that noise at the receiver is
bounded.
RDRIVER
ZDRIVER
Driver
CDRIVER
Figure 9-9. ZDRIVER Circuit
9.3.1.5 USB-PD BMC Receiver
The receiver block of the TPS25750 receives a signal that follows the allowed Rx masks defined in the USB PD
specification. The receive thresholds and hysteresis come from this mask.
Figure 9-10 shows an example of a multi-drop USB-PD connection (only the CC wire). This connection has the
typical Sink (device) to Source (host) connection, but also includes cable USB-PD Tx/Rx blocks. Only one
system can be transmitting at a time. All other systems are Hi-Z (Z BMCRX). The USB-PD Specification also
specifies the capacitance that can exist on the wire as well as a typical DC bias setting circuit for attach
detection.
Source
System
Sink
System
Pullup for
Attach
Detection
Connector
Connector
Cable
CC wire
Tx
Tx
CRECEIVER
CRECEIVER
Rx
Rx
CCablePlug_CC
CCablePlug_CC
RD for
Attach
Detection
Rx
Rx
Tx
Tx
SOP‘ PD
communication only
(eMarker #1)
SOP‘‘ PD
communication only
(eMarker #2)
Figure 9-10. Example USB-PD Multi-Drop Configuration
9.3.1.6 Squelch Receiver
The TPS25750 has a squelch receiver to monitor for the bus idle condition as defined by the USB PD
specification. The CC line is deemed active (that is not idle) when a minimum of NCOUNT transitions occur at
the receiver within a time window of TTRANWIN. After waiting TTRANWIN without detecting NCOUNT
transitions, the bus is declared idle. The squelch receiver output reflects the state of the CC pin regardless of the
source of the tranmission.
9.3.2 Power Management
The TPS25750 power management block receives power and generates voltages to provide power to the
TPS25750 internal circuitry. These generated power rails are LDO_3V3 and LDO_1V5. LDO_3V3 can also be
used as a low power output for external EEPROM memory. The power supply path is shown in Figure 9-11.
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RLDO_3V3
VIN_3V3
VBUS
VREF
LDO
LDO_3V3
VREF
LDO_1V5
LDO
Figure 9-11. Power Supplies
The TPS25750 is powered from either VIN_3V3 or VBUS. The normal power supply input is VIN_3V3. When
powering from VIN_3V3, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3-V circuitry and I/Os. A
second LDO steps the voltage down from LDO_3V3 to LDO_1V5 to power the 1.5-V core digital circuitry. When
VIN_3V3 power is unavailable and power is available on VBUS, it is referred to as the dead-battery start-up
condition. In a dead-battery start-up condition, the TPS25750 opens the VIN_3V3 switch until the host clears the
dead-battery flag through I2C. Therefore, the TPS25750 is powered from the VBUS input with the higher voltage
during the dead-battery start-up condition and until the dead-battery flag is cleared. When powering from a
VBUS input, the voltage on VBUS is stepped down through an LDO to LDO_3V3.
9.3.2.1 Power-On And Supervisory Functions
A power-on reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a
good supply is present.
9.3.2.2 VBUS LDO
The TPS25750 contains an internal high-voltage LDO which is capable of converting VBUS to 3.3 V for
powering internal device circuitry. The VBUS LDO is only used when VIN_3V3 is low (the dead-battery
condition). The VBUS LDO is powered from VBUS.
9.3.3 Power Paths
The TPS25750 has internal sourcing power paths: PP_5V and PP_CABLE. TPS25750D has a integrated
bidirectional high voltage load switch for sinking power path: PPHV. TPS25750S has a high volatge gate driver
for sink path control: PP_EXT. Each power path is described in detail in this section.
9.3.3.1 Internal Sourcing Power Paths
Figure 9-12 shows the TPS25750 internal sourcing power paths available in both TPS25750D and TPS25750S.
The TPS25750 features two internal 5-V sourcing power paths. The path from PP5V to VBUS is called PP_5V.
The path from PP5V to CCx is called PP_CABLE. Each path contains two back-to-back common drain N-FETs,
with current clamping protection, overvoltage protection, UVLO protection, and temperature sensing circuitry.
PP_5V can conduct up to 3 A continuously, while PP_CABLE can conduct up to 315 mA continuously. When
disabled, the blocking FET protects the PP5V rail from high-voltage that can appear on VBUS.
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3A
Fast current clamp, ILIM5V
VBUS
Temp
Sensor
PP_5V Gate Control and Sense
PP_5V
PP_CABLE
CC1 Gate Control
TSD_PP5V
Fast current limit, IVCON
CC1
CC2 Gate Control
Temp
Sensor
PP5V
CC2
Figure 9-12. Port Power Switches
9.3.3.1.1 PP_5V Current Clamping
The current through the internal PP_5V path are current limited to ILIM5V. The ILIM5V value is configured by
application firmware. When the current through the switch exceeds ILIM5V, the current limiting circuit activates
within tiOS_PP_5V and the path behaves as a constant current source. If the duration of the overcurrent event
exceeds tILIM, the PP_5V switch is disabled.
9.3.3.1.2 PP_5V Local Overtemperature Shut Down (OTSD)
When PP_5V clamps the current, the temperature of the switch will begin to increase. When the local
temperature sensors of PP_5V or PP_CABLE detect that TJ > TSD_PP5V, the PP_5V switch is disabled and the
affected port enters the USB Type-C ErrorRecovery state.
9.3.3.1.3 PP_5V OVP
The overvoltage protection level is automatically configured based on the expected maximum V BUS voltage,
which depends upon the USB PD contract. When the voltage on the VBUS pin of a port exceeds the configured
value (VOVP4RCP) while PP_5V is enabled, then PP_5V is disabled within tPP_5V_ovp and the port enters into the
Type-C ErrorRecovery state.
9.3.3.1.4 PP_5V UVLO
If the PP5V pin voltage falls below its undervoltage lock out threshold (VPP5V_UVLO) while PP_5V is enabled, then
PP_5V is disabled within tPP_5V_uvlo and the port that had PP_5V enabled enters into the Type-C ErrorRecovery
state.
9.3.3.1.5 PP_5Vx Reverse Current Protection
If VVBUS - VPP5V > VPP_5V_RCP, then the PP_5V path is automatically disabled within t PP_5V_rcp. If the RCP
condition clears, then the PP_5V path is automatically enabled within tON
.
9.3.3.1.6 PP_CABLE Current Clamp
When enabled and providing VCONN power, the TPS25750 PP_CABLE power switch clamps the current to I
VCON. When the current through the PP_CABLE switch exceeds IVCON, the current clamping circuit activates
within tiOS_PP_CABLE and the switch behaves as a constant current source.
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9.3.3.1.7 PP_CABLE Local Overtemperature Shut Down (OTSD)
When PP_CABLE clamps the current, the temperature of the switch will begin to increase. When the local
temperature sensors of PP_5V or PP_CABLE detect that TJ>TSD_PP5V, the PP_CABLE switch is disabled and
latched off within tPP_CABLE_off. The port then enters the USB Type-C ErrorRecovery state.
9.3.3.1.8 PP_CABLE UVLO
If the PP5V pin voltage falls below its undervoltage lock out threshold (VPP5V_UVLO), then the PP_CABLE switch
is automatically disabled within tPP_CABLE_off
.
9.3.3.2 TPS25750D Internal Sink Path
The TPS25750D has internal controls for internal FETs (GATE_VSYS and GATE_VBUS as shown in Figure
9-13) that require that VBUS_IN be above VVBUS_UVLO before being able to enable the sink path. Figure 9-13
shows a diagram of the sink path. When a sink path is enabled, the circuitry includes a slew rate control loop to
ensure that external switches do not turn on too quickly (SS). The TPS25750D senses the PPHV and VBUS
voltages to control the gate voltages to enable or disable the FETs.
The sink-path control includes overvoltage protection (OVP) and reverse current protection (RCP).
PP_HV
PPHV
VBUS
Gate Control and Sense
Copyright © 2018, Texas Instruments Incorporated
Figure 9-13. Internal Sink Path
9.3.3.2.1 Overvoltage Protection (OVP)
The application firmware enables the OVP and configures it based on the expected VBUS voltage. If the voltage
on VBUS surpasses the configured threshold VOVP4VSYS = VOVP4RCP/rOVP, then GATE_VSYS is
automatically disabled within tPPHV_FSD to protect the system. If the voltage on VBUS surpasses the
configured threshold VOVP4RCP, then GATE_VBUS is automatically disabled within tPPHV_OVP. When
VVBUS falls below VOVP4RCP - VOVP4RCPH, GATE_VBUS is automatically re-enabled within tPPHV_ON
since the OVP condition has cleared. This allows two sinking power paths to be enabled simultaneously and
GATE_VBUS will be disabled when necessary to ensure that VVBUS remains below VOVP4RCP.
While the TPS25750D is in BOOT mode in a dead-battery scenario (that is VIN_3V3 is low), it handles an OVP
condition slightly differently. As long as the OVP condition is present, GATE_VBUS and GATE_VSYS are
disabled. Once the OVP condition clears, both GATE_VBUS and GATE_VSYS are re-enabled. Since this is a
dead-battery condition, the TPS25750D will be drawing approximately IVIN_3V3, ActSnk from VBUS during this
time to help discharge it.
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Power Path Supervisor
VOVP4RCP
VOVP4VSYS = VOVP4RCP / rOVP
Figure 9-14. Diagram for OVP Comparators
9.3.3.2.2 Reverse-Current Protection (RCP)
The VSYS gate control circuit monitors the PPHV and VBUS voltages and detects reverse current when the
VVSYS surpasses VVBUS by more than VRCP. When the reverse current condition is detected, GATE_VBUS is
disabled within tPPHV_RCP. When the reverse current condition is cleared, GATE_VBUS is re-enabled within
tPPHV_ON. This limits the amount of reverse current that can flow from PPHV to VBUS through the external N-
ch MOSFETs. In reverse current protection mode, the power switch controlled by GATE_VBUS is allowed to
behave resistively until the current reaches VRCP/ RPPHV and then blocks reverse current from PPHV to
VBUS.
I
1/RPPHV
-VRCP
V=VVBUS œ VPPHV
VRCP/RPPHV
Copyright © 2018, Texas Instruments Incorporated
Figure 9-15. Switch I-V Curve for RCP on Sink-path Switches.
9.3.3.2.3 VBUS UVLO
The TPS25750D monitors VBUS voltage and detects when it falls below VVBUS_UVLO. When the UVLO
condition is detected, GATE_VBUS is disabled within tPPHV_RCP. When the UVLO condition is cleared,
GATE_VBUS is reenabled within tPPHV_ON.
9.3.3.2.4 Discharging VBUS to Safe Voltage
The TPS25750D has an integrated active pulldown (IDSCH) on VBUS for discharging from high voltage to
VSAFE0V (0.8 V). This discharge is applied when it is in an Unattached Type-C state.
9.3.3.3 TPS25750S - External Sink Path Control PP_EXT
The TPS25750S has two N-ch gate drivers designed to control a sinking path from VBUS to VSYS. The charge
pump for these gate drivers requires VBUS to be above VVBUS_UVLO. When a sink path is enabled, the
circuitry includes a slew rate control loop to ensure that external switches do not turn on too quickly (SS). The
TPS25750S senses the VSYS and VBUS voltages to control the gate voltages to enable or disable the external
FETs.
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The sink-path control includes overvoltage protection (OVP), and reverse current protection (RCP). Adding
resistance in series with a GATE pin of the TPS25750S and the gate pin of the N-ch MOSFET will slow down the
turnoff time when OVP or RCP occurs. Any such resistance must be minimized, and not allowed to exceed 3 Ω.
PP_EXT
PP_EXT Gate Control and
Sense
Copyright © 2018, Texas Instruments Incorporated
Figure 9-16. PP_EXT External Sink Path Control
Figure 9-17 shows the GATE_VSYS gate driver in more detail.
switch enabled when
gate driver is disabled and
VVIN_3V3 < VVIN_3V3_UVLO
VGATE_ON
RGATE_FSD
Regular enable/
disable
Fast
disable
IGATE_OFF
IGATE_ON
Charge
Pump
VBUS
RGATE_OFF_UVLO
Figure 9-17. Details of the VSYS Gate Driver
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9.3.3.3.1 Overvoltage Protection (OVP)
The application firmware enables the OVP and configures it based on the expected VBUS voltage. If the voltage
on VBUS surpasses the configured threshold VOVP4VSYS = VOVP4RCP/rOVP, then GATE_VSYS is
automatically disabled within tPPHV_FSD to protect the system. If the voltage on VBUS surpasses the
configured threshold VOVP4RCP, then GATE_VBUS is automatically disabled within tPPHV_OVP. When
VVBUS falls below VOVP4RCP - VOVP4RCPH, GATE_VBUS is automatically re-enabled within tPPHV_ON
since the OVP condition has cleared. This allows two sinking power paths to be enabled simultaneously and
GATE_VBUS will be disabled when necessary to ensure that VVBUS remains below VOVP4RCP.
While the TPS25750D is in BOOT mode in a dead-battery scenario (that is VIN_3V3 is low), it handles an OVP
condition slightly differently. As long as the OVP condition is present, GATE_VBUS and GATE_VSYS are
disabled. Once the OVP condition clears, both GATE_VBUS and GATE_VSYS are re-enabled. Since this is a
dead-battery condition, the TPS25750D will be drawing approximately IVIN_3V3, ActSnk from VBUS during this
time to help discharge it.
Power Path Supervisor
VOVP4RCP
VOVP4VSYS = VOVP4RCP / rOVP
Figure 9-18. Diagram for OVP Comparators
9.3.3.3.1.1 Reverse-Current Protection (RCP)
The VSYS gate control circuit monitors the PPHV and VBUS voltages and detects reverse current when the
VVSYS surpasses VVBUS by more than VRCP. When the reverse current condition is detected, GATE_VBUS is
disabled within tPPHV_RCP. When the reverse current condition is cleared, GATE_VBUS is re-enabled within
tPPHV_ON. This limits the amount of reverse current that can flow from PPHV to VBUS through the external N-
ch MOSFETs. In reverse current protection mode, the power switch controlled by GATE_VBUS is allowed to
behave resistively until the current reaches VRCP/ RPPHV and then blocks reverse current from PPHV to
VBUS.
I
1/RPPHV
-VRCP
V=VVBUS œ VPPHV
VRCP/RPPHV
Copyright © 2018, Texas Instruments Incorporated
Figure 9-19. Switch I-V Curve for RCP on Sink-path Switches.
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9.3.3.3.1.2 VBUS UVLO
The TPS25750D monitors VBUS voltage and detects when it falls below VVBUS_UVLO. When the UVLO
condition is detected, GATE_VBUS is disabled within tPPHV_RCP. When the UVLO condition is cleared,
GATE_VBUS is reenabled within tPPHV_ON.
9.3.3.3.1.3 Discharging VBUS to Safe Voltage
The TPS25750D has an integrated active pulldown (IDSCH) on VBUS for discharging from high voltage to
VSAFE0V (0.8 V). This discharge is applied when it is in an Unattached Type-C state.
9.3.4 Cable Plug and Orientation Detection
Figure 9-20 shows the plug and orientation detection block at each CCy pin (CC1, CC2). Each pin has identical
detection circuitry.
IRpDef
IRp1.5
IRp3.0
VREF1
VREF2
VREF3
CCy
RSNK
Figure 9-20. Plug and Orientation Detection Block
9.3.4.1 Configured as a Source
When configured as a source, the TPS25750 detects when a cable or a Sink is attached using the CC1 and CC2
pins. When in a disconnected state, the TPS25750 monitors the voltages on these pins to determine what, if
anything, is connected. See USB Type-C Specification for more information.
Table 9-1 shows the Cable Detect States for a Source.
Table 9-1. Cable Detect States for a Source
CC1
CC2
CONNECTION STATE
RESULTING ACTION
Continue monitoring both CCy pins for attach. Power is not applied to VBUS or
VCONN.
Open
Open Nothing attached
Open Sink attached
Rd
Monitor CC1 for detach. Power is applied to VBUS but not to VCONN (CC2).
Monitor CC2 for detach. Power is applied to VBUS but not to VCONN (CC1).
Open
Rd
Sink attached
Powered Cable-No UFP
attached
Monitor CC2 for a Sink attach and CC1 for cable detach. Power is not applied to
VBUS or VCONN (CC1).
Ra
Open
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Table 9-1. Cable Detect States for a Source (continued)
CC1
CC2
CONNECTION STATE
RESULTING ACTION
Powered Cable-No UFP
attached
Monitor CC1 for a Sink attach and CC2 for cable detach. Power is not applied to
VBUS or VCONN (CC1).
Open
Ra
Provide power on VBUS and VCONN CC1) then monitor CC2 for a Sink detach.
CC1 is not monitored for a detach.
Ra
Rd
Rd
Ra
Rd
Ra
Rd
Ra
Powered Cable-UFP Attached
Powered Cable-UFP attached
Provide power on VBUS and VCONN (CC2) then monitor CC1 for a Sink detach.
CC2 is not monitored for a detach.
Debug Accessory Mode
attached
Sense either CCy pin for detach.
Sense either CCy pin for detach.
Audio Adapter Accessory
Mode attached
When a TPS25750 port is configured as a Source, a current IRpDef is driven out each CCy pin and each pin is
monitored for different states. When a Sink is attached to the pin, a pulldown resistance of Rd to GND exists.
The current IRpDef is then forced across the resistance Rd, generating a voltage at the CCy pin. The TPS25750
applies IRpDef until it closes the switch from PP5V to VBUS, at which time application firmware can change to I
Rp1.5A or IRp3.0A
.
When the CCy pin is connected to an active cable VCONN input, the pulldown resistance is different (Ra). In this
case, the voltage on the CCy pin will lower the PD controller recognizes it as an active cable.
The voltage on CCy is monitored to detect a disconnection depending upon which Rp current source is active.
When a connection has been recognized and the voltage on CCy subsequently rises above the disconnect
threshold for tCC, the system registers a disconnection.
9.3.4.2 Configured as a Sink
When a TPS25750 port is configured as a Sink, the TPS25750 presents a pulldown resistance RSNK on each
CCy pin and waits for a Source to attach and pull up the voltage on the pin. The Sink detects an attachment by
the presence of VBUS and determines the advertised current from the Source based on the voltage on the CCy
pin.
9.3.4.3 Configured as a DRP
When a TPS25750 port is configured as a DRP, the TPS25750 alternates the CCy pins of the port between the
pulldown resistance, RSNK, and pullup current source, IRp.
9.3.4.4 Dead Battery Advertisement
The TPS25750 supports booting from no-battery or dead-battery conditions by receiving power from VBUS.
Type-C USB ports require a sink to present Rd on the CC pin before a USB Type-C source provides a voltage on
VBUS. TPS25750 hardware is configured to present this Rd during a dead-battery or no-battery condition.
Additional circuitry provides a mechanism to turn off this Rd once the device no longer requires power from
VBUS.
9.3.5 Overvoltage Protection (CC1, CC2)
The TPS25750 detects when the voltage on the CC1 or CC2 pin is too high or there is reverse current into the
PP5V pin and takes action to protect the system. The protective action is to disable PP_CABLE within t
PP_CABLE_FSD and disable the USB PD transmitter.
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max(VCC1, VCC2) - VPP5V
VVC_RCP
PP5V
Control Logic
Disable PP_CABLE
and USB PD PHY
Tx
VVC_OVP
CC1
CC2
VPHY_OVP
VPHY_OVP
Figure 9-21. Overvoltage and Reverse Current Protection for CC1 and CC2
9.3.6 ADC
The TPS25750 ADC is shown in Figure 9-22. The ADC is an 8-bit successive approximation ADC. The input to
the ADC is an analog input mux that supports multiple inputs from various voltages and currents in the device.
The output from the ADC is available to be read and used by application firmware.
Voltage
VBUS
Divider 2
Voltage
Divider 1
LDO_3V3
GPIO0
8 bits
Input
Mux
GPIO2
ADCIN1
ADCIN2
GPIO4
ADC
Buffers &
Voltage
Divider 1
GPIO5
I_VBUS
I-to-V
Copyright © 2018, Texas Instruments Incorporated
Figure 9-22. SAR ADC
9.3.7 BC 1.2 (USB_P, USB_N)
The TPS25750 supports BC 1.2 as a Portable Device or Downstream Port using the hardware shown in Figure
9-23.
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Figure 9-23. BC1.2 Hardware Components (External for DRP)
9.3.8 Digital Interfaces
The TPS25750 contains several different digital interfaces which can be used for communicating with other
devices. The available interfaces include one I2C Master, one I2C Slave and additional GPIOs.
9.3.8.1 General GPIO
GPIOn pins can be mapped to USB Type-C, USB PD, and application-specific events to control other ICs,
interrupt a host processor, or receive input from another IC. This buffer is configurable to be a push-pull output, a
weak push-pull, or open drain output. When configured as an input, the signal can be a de-glitched digital input .
The push-pull output is a simple CMOS output with independent pull-down control allowing open-drain
connections. The weak push-pull is also a CMOS output, but with GPIO_RPU resistance in series with the drain.
The supply voltage to the output buffer is LDO_3V3 and LDO_1V5 to the input buffer. When interfacing with non
3.3-V I/O devices the output buffer may be configured as an open drain output and an external pull-up resistor
attached to the GPIO pin. The pull-up and pull-down output drivers are independently controlled from the input
and are enabled or disabled via application code in the digital core.
Table 9-2. GPIO Functionality Table
Pin Name
GPIO0
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Special Functionality
General-purpose input or output
GPIO1
General-purpose input or output
GPIO2
General-purpose input or output
GPIO3
General-purpose input or output
GPIO4
D+, or used as a general-purpose input or output
D-, or used as a general-purpose input or output
General-purpose input or output
GPIO5
GPIO6
GPIO7
General-purpose input or output
I2Cs_IRQ(GPIO10)
GPIO11
IRQ for optional I2Cs, or used as a general-purpose output
General-purpose output
O
I2Cm_IRQ(GPIO12)
I
IRQ for I2Cm, or used as a general-purpose input
9.3.8.2 I2C Interface
The TPS25750 features two I2C interfaces that uses an I2C I/O driver like the one shown in Figure 9-24. This I/O
consists of an open-drain output and an input comparator with de-glitching.
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50ns
Deglitch
I2C_DI
I2C_SDA/SCL
I2C_DO
Figure 9-24. I2C Buffer
9.3.9 Digital Core
Figure 9-25 shows a simplified block diagram of the digital core.
GPIO0-9
I2Cs_SDA
I2C to
System Control
I2C
I2Cs_SCL
(slave)
I2C_IRQ
Digital Core
CBL_DET
Bias CTL
and USB-PD
USB PD Phy
I2Cm_SDA
I2C to
Battery Charger
I2Cm_SCL
I2Cm_IRQ
I2C
(master)
OSC
ADC Read
Temp
Sense
Thermal
Shutdown
ADC
Figure 9-25. Digital Core Block Diagram
9.3.10 I2C Interface
The TPS25750 has one I2C slave interface ports: I2Cs. I2C port I2Cs is comprised of the I2Cs_SDA, I2Cs_SCL,
and I2Cs_IRQ pins. This interface provide general status information about the TPS25750, as well as the ability
to control the TPS25750 behavior, supporting communications to/from a connected device and/or cable
supporting BMC USB-PD, and providing information about connections detected at the USB-C receptacle.
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When the TPS25750 is in 'APP ' mode it is recommended to use Standard Mode or Fast Mode (that is a clock
speed no higher than 400 kHz). However, in the 'BOOT' mode when a patch bundle is loaded Fast Mode Plus
may be used (see fSCLS).
The TPS25750 has one I2C master interface port. I2C is comprised of the I2C_SDA and I2C_SCL pins. This
interface can be used to read from or write to external slave devices.
During boot, the TPS25750 attempts to read patch and Application Configuration data from an external
EEPROM with a 7-bit slave address of 0x50. The EEPROM should be at least 32 kilo-bytes.
Table 9-3. I2C Summary
I2C BUS
TYPE
TYPICAL USAGE
I2Cs
Slave
Optionally can be connected to an external MCU. Also used to load the patch and application
configuration.
I2Cm
Master
Connect to a I2C EEPROM, Battery Charger. Use the LDO_3V3 pin as the pullup voltage. Multi-master
configuration is not supported.
9.3.10.1 I2C Interface Description
The TPS25750 supports Standard and Fast mode I2C interfaces. The bidirectional I2C bus consists of the serial
clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pullup resistor. Data
transfer can be initiated only when the bus is not busy.
A master sending a Start condition, a high-to-low transition on the SDA input and output, while the SCL input is
high initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit
(MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/
output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred during
each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period as
changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a
Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must
generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to
ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this
event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 9-26 shows the start and stop conditions of the transfer. Figure 9-27 shows the SDA and SCL signals for
transferring a bit. Figure 9-28 shows a data transfer sequence with the ACK or NACK at the last clock pulse.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 9-26. I2C Definition of Start and Stop Conditions
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SDA
SCL
Data Line
Change
Figure 9-27. I2C Bit Transfer
Data Output
by Transmitter
Nack
Data Output
by Receiver
SCL From
Master
Ack
1
2
8
9
S
Clock Pulse for
Acknowledgement
Start
Condition
Figure 9-28. I2C Acknowledgment
9.3.10.1.1 I2C Clock Stretching
The TPS25750 features clock stretching for the I2C protocol. The TPS25750 slave I2C port may hold the clock
line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The
master communicating with the slave must not finish the transmission of the current bit and must wait until the
clock line actually goes high. When the slave is clock stretching, the clock line remains low.
The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for
standard 100-kbps I2C) before pulling the clock low again.
Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit.
9.3.10.1.2 I2C Address Setting
The host should only use I2Cs_SCL/SDA for loading a patch bundle. Once the boot process is complete, the
port has a unique slave address on the I2Cm_SCL/SDA bus as selected by the ADCINx pins.
Table 9-4. I2C Default Slave Address for I2Cs_SCL/SDA.
I2C address index (decoded
from ADCIN1 and ADCIN2)(1)
Available During
BOOT
Slave Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
#1
#2
#3
#4
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Yes
Yes
Yes
Yes
(1) See Pin Strapping to Configure Default Behavior details about ADCIN1 and ADCIN2 decoding.
9.3.10.1.3 Unique Address Interface
The Unique Address Interface allows for complex interaction between an I2C master and a single TPS25750.
The I2C Slave sub-address is used to receive or respond to Host Interface protocol commands. Figure 9-29 and
Figure 9-30 show the write and read protocol for the I2C slave interface, and a key is included in Figure 9-31 to
explain the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated
here in part.
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1
7
1
1
8
1
8
1
8
1
S
Unique Address
Wr
A
Register Number
A
Byte Count = N
A
Data Byte 1
A
8
1
8
1
Data Byte 2
A
Data Byte N
A
P
Figure 9-29. I2C Unique Address Write Register Protocol
1
S
7
1
1
8
1
1
7
1
1
8
1
Unique Address
Wr
A
Register Number
A
Sr
Unique Address
Rd
A
Byte Count = N
A
8
1
8
1
8
1
Data Byte 1
A
Data Byte 2
A
Data Byte N
A
1
P
Figure 9-30. I2C Unique Address Read Register Protocol
1
7
1
1
A
x
8
1
A
x
1
S
Slave Address
Wr
Data Byte
P
S
Start Condition
SR
Rd
Wr
x
Repeated Start Condition
Read (bit value of 1)
Write (bit value of 0)
Field is required to have the value x
Acknowledge (this bit position may be 0 for an ACK or
1 for a NACK)
A
P
Stop Condition
Master-to-Slave
Slave-to-Master
Continuation of protocol
Figure 9-31. I2C Read/Write Protocol Key
9.4 Device Functional Modes
9.4.1 Pin Strapping to Configure Default Behavior
During the boot procedure, the device will read the ADCINx pins and set the configurations based on the table
below. It then attempts to load a configuration from an external EEPROM on the I2Cm bus. If no EEPROM is
detected, then the device will wait for an external host to load a configuration.
When an external EEPROM is used, each device is connected to a unique EEPROM, it cannot be shared for
multiple devices. The external EEPROM shall be at 7-bit slave address 0x50.
Table 9-5. Device Configuration using ADCIN1 and ADCIN2
ADCIN1 decoded
value(2)
ADCIN2 decoded
value(2)
I2C address Index(1)
Dead Battery Configuration
7
5
2
1
5
5
0
7
#1
#2
#3
#4
AlwaysEnableSink: The device always enables the sink path
regardless of the amount of current the attached source is
offering. USB PD is disabled until configuration is loaded.
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Table 9-5. Device Configuration using ADCIN1 and ADCIN2 (continued)
ADCIN1 decoded
value(2)
ADCIN2 decoded
value(2)
I2C address Index(1)
Dead Battery Configuration
7
3
4
3
3
3
0
7
#1
#2
#3
#4
NegotiateHighVoltage: The device always enables the sink path
during the initial implicit contract regardless of the amount of
current the attached source is offering. The PD controller will
enter the 'APP ' mode, enable USB PD PHY and negotiate a
contract for the highest power contract that is offered up to 20 V.
This cannot be used when a patch is loaded from EEPROM.
This option is not recommended for systems that can boot from
5 V.
7
0
6
5
0
0
0
7
#1
#2
#3
#4
SafeMode: The device does not enable the sink path. USB PD is
disabled until configuration is loaded. Note that the configuration
could put the device into a source-only mode. This is
recommended when the application loads the patch from
EEPROM.
(1) See I2C Address Setting to see the exact meaning of I2C Address Index.
(2) See Pin Strapping to Configure Default Behavior for how to configure a given ADCINx decoded value.
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9.4.2 Power States
The TPS25750 can operate in one of three different power states: Active, Idle, or Sleep. The Modern Standby
mode is a special case of the Idle mode. The functionality available in each state is summarized in Table 9-6.
The device will automatically transition between the three power states based on the circuits that are active and
required. See Figure 9-32. In the Sleep state, the TPS25750 will detect a Type-C connection. Transitioning
between the Active mode to Idle mode requires a period of time (T) without any of the following activity:
•
•
•
•
•
•
Incoming USB PD message
Change in CC status
GPIO input event
I2C transactions
Voltage alert
Fault alert
Sleep State
No CC connection
New
activity
CC detached & No activity for T
New activity
Idle State
CC connected
Active State
CC attached &
No new activity for T
Figure 9-32. Flow Diagram for Power States
Table 9-6. Power Consumption States
MODERN
ACTIVE
SOURCE
MODE(1)
MODERN
STANDBY
ACTIVE SINK IDLE SOURCE
IDLE SINK
MODE
STANDBY
SOURCE
MODE(3)
SLEEP
MODE(5)
MODE
MODE(2)
SINK MODE(4)
PP_5V
enabled
disabled
disabled
enabled
enabled
disabled
disabled
enabled
enabled
disabled
disabled
disabled
disabled
disabled
PP_HV
(TPS25750D)
PP_EXT
disabled
enabled
disabled
enabled
disabled
disabled
disabled
(TPS25750S)
PP_CABLE
enabled
Rd
enabled
Rp 3.0A
enabled
Rd
enabled
Rp 3.0A
disabled
open
disabled
open
disabled
open
external CC1
termination
external CC2
termination
open
open
open
open
open
open
open
(1) This mode is used for: IVIN_3V3,ActSrc
(2) This mode is used for: IVIN_3V3,Sleep
(3) This mode is used for: PMstbySrc
(4) This mode is used for: PMstbySnk
.
(5) This mode is used for: IVIN_3V3,ActSnk
9.4.3 Schottky for Current Surge Protection
To prevent the possibility of large ground currents into the TPS25750 during sudden disconnects due to
inductive effects in a cable, it is recommended that a Schottky diode be placed from VBUS to ground.
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PPHV
VBUS_IN
PP5V
VBUS
GND
Copyright © 2018, Texas Instruments Incorporated
Figure 9-33. TPS25750D Schottky for Current Surge Protection
PP5V
VBUS
GND
Figure 9-34. TPS25750S Schottky for Current Surge Protection
9.4.4 Thermal Shutdown
The TPS25750 features a central thermal shutdown as well as independent thermal sensors for each internal
power path. The central thermal shutdown monitors the overall temperature of the die and disables all functions
except for supervisory circuitry when die temperature goes above a rising temperature of T SD_MAIN. The
temperature shutdown has a hysteresis of TSDH_MAIN and when the temperature falls back below this value, the
device resumes normal operation.
The power path thermal shutdown monitors the temperature of each internal PP5V-to-VBUS power path and
disables both power paths and the VCONN power path when either exceeds TSD_PP5V. Once the temperature
falls by at least TSDH_PP5V, the path can be configured to resume operation or remain disabled until re-enabled
by firmware.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The TPS25750 is a stand-alone Type-C PD controller for power-only USB-PD applications. Initial device
configuration is configured from an external EEPROM through a firmware configuration bundle loaded on to the
device during boot.The bundle is loaded over I 2C from an external EEPROM. The TPS25750 firmware
configuration can be customized for each specific application. The firmware configuration can be generated
through the Application Customization Tool.
The TPS25750 works very well in single port power applications supporting the following PD architectures.
•
•
Designs for both Power Provider (Source) and Power Consumer (Sink)
Designs for Power Consumer (Sink)
An external EEPROM is required to download a pre-configured firmware on the TPS25750 device through the I
2C interface.
The TPS25750 firmware can be configured using the Application Customization Tool for the application-specific
PD charging architecture requirements and data roles. The Tool also provides additional optional firmware
configuration that integrates control for select Battery Charger Products (BQ). The TPS25750 I 2C Master
interfaces with the Battery Chargers with pre-configured GPIO settings and I2C master events. The Application
Customization Tool available with the TPS25750 provides details of the supported Battery Charger Products
(BQ).
10.2 Typical Application
10.2.1 USB-PD Power Application Design Considerations
10.2.1.1 Supported Power Configurations
The Application Customization Tool available with TPS25750 lets the user select one of the following Power
Application configurations and generates a pre-configured firmware.
Figure 10-1 shows the Power Source and Sink configuration when the TPS25750 is connected to a 5-V DC.
Figure 10-1. Power Source and Sink Configuration with 5-V DC
Figure 10-2 shows the Power Source and Sink configuration when the Battery Charger (BQ) is connected to the
high voltage power path.
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Figure 10-2. Power Source and Sink configuration with the Battery Charger (BQ)
Figure 10-3 shows the configuration where the a 5-V DC is connected to the source path and a Battery Charger
(BQ) is connected to the sink path.
Figure 10-3. Power Source and Sink configuration with 5V DC and Battery Charger (BQ)
In a Sink Only Configuration, the TPS25750 can be used as shown in Figure 10-4.
Figure 10-4. Power Consumer (Sink) Only Configuration
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Figure 10-5. Power Source Only Configuration
In a Source Only Configuration, the TPS25750 can be used with a 5V source as shown in Figure 10-5
10.2.2 Application Block Diagram
Figure 10-6 shows the system block diagram for TPS25750D connected to a supported Battery Charger (BQ).
Figure 10-6. Power Only Battery Charger Application Block Diagram
10.2.3 Type-C VBUS Design Considerations
USB Type-C and PD allows for voltages up to 20 V with currents up to 5 A. This introduces power levels that can
damage components touching or hanging off of VBUS. Under normal conditions, all high power PD contracts
must start at 5 V and then transition to a higher voltage. However, there are some devices that are not compliant
to the USB Type-C and Power Delivery standards and can have 20 V on VBUS. This can cause a 20-V hot plug
that can ring above 30 V. Adequate design considerations are recommended below for these non-compliant
devices.
10.2.3.1 Design Requirements
Table 10-1 shows VBUS conditions that can be introduced to a USB Type-C and PD Sink. The system should be
able to handle these conditions to ensure that the system is protected from non-compliant, damaged USB PD
sources, or both. A USB Sink should be able to protect from the following conditions being applied to its VBUS.
Detailed Design Procedure explains how to protect from these conditions.
Table 10-1. VBUS Conditions
CONDITION
VOLTAGE APPLIED
4 V - 21.5 V
Abnormal VBUS Hot Plug
VBUS Transient Spikes
4 V - 43 V
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10.2.3.2 Detailed Design Procedure
10.2.3.2.1 Type-C Connector VBUS Capacitors
C_VBUS
C_VBUS
VBUS A4
VBUS B9
10 nF
35V
10 nF
35V
Type-C
Connector
GND
GND
C_VBUS
C_VBUS
VBUS A9
VBUS B4
10 nF
35V
10 nF
35V
GND
GND
Figure 10-7. Type-C Connector VBUS Capacitors
The first level of protection starts at the Type-C connector and the VBUS pin capacitors. These capacitors help
filter out high frequency noise but can also help absorb short voltage transients. Each VBUS pin should have a
10-nF capacitor rated at or above 25 V and placed as close to the pin as possible. The GND pin on the
capacitors should have a very short path to GND on the connector. The derating factor of ceramic capacitors
should be taken into account as they can lose more than 50% of their effective capacitance when biased. Adding
the VBUS capacitors can help reduce voltage spikes by 2 V to 3 V.
10.2.3.2.2 TPS25750 VBUS Schottky and TVS Diodes
Schottky diodes are used on VBUS to help absorb large GND currents when a Type-C cable is removed while
drawing high current. The inductance in the cable will continue to draw current on VBUS until the energy stored
is dissipated. Higher currents can cause the body diodes on IC devices connected to VBUS to conduct. When
the current is high enough, it can damage the body diodes of IC devices. Ideally, a VBUS Schottky diode should
have a lower forward voltage so it can turn on before any other body diodes on other IC devices. Schottky
diodes on VBUS also help during hard shorts to GND which can occur with a faulty Type-C cable or damaged
Type-C PD device. VBUS can ring below GND which can damage devices hanging off of VBUS. The Schottky
diode will start to conduct once VBUS goes below the forward voltage. When the TPS25750 is the only device
connected to VBUS, place the Schottky Diode close to the VBUS pin of the TPS25750. Figure 10-9 and Figure
10-10 show a short condition with and without a Schottky diode on VBUS. Without the Schottky diode, VBUS
rings 2-V below GND and oscillates after settling to 0 V. With the Schottky diode, VBUS drops 750 mV below
GND (Schottky diode Vf) and the oscillations are minimized.
TVS Diodes help suppress and clamp transient voltages. Most TVS diodes can fully clamp around 10 ns and can
keep the VBUS at their clamping voltage for a period of time. Looking at the clamping voltage of TVS diodes
after they settle during a transient will help decide which TVS diode to use. The peak power rating of a TVS
diode must be able to handle the worst case conditions in the system. A TVS diode can also act as a “pseudo
schottky diode” as they will also start to conduct when VBUS goes below GND.
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10.2.3.2.3 VBUS Snubber Circuit
VBUS
4.7 …F
3.48Ω
1 …F
GND
Figure 10-8. VBUS Snubber
Another method of clamping the USB Type-C VBUS is to use a VBUS RC Snubber. An RC Snubber is a great
solution because in general, it is much smaller than a TVS diode, and typically more cost effective as well. An
RC Snubber works by modifying the characteristic of the total RLC response in the USB Type-C cable hot-plug
from being under-damped to critically-damped or over-damped. So rather than clamping the overvoltage directly,
it changes the hot-plug response from under-damped to critically-damped, so the voltage on VBUS does not ring
at all; so the voltage is limited, but without requiring a clamping element like a TVS diode.
However, the USB Type-C and Power Delivery specifications limit the range of capacitance that can be used on
VBUS for the RC snubber. VBUS capacitance must have a minimum 1 µF and a maximum of 10 µF. The RC
snubber values chosen support up to 4-m USB Type-C cable (maximum length allowed in the USB Type-C
specification) being hot plugged, is to use 4.7-μF capacitor in series with a 3.48-Ω resistor. In parallel with the
RC Snubber a 1-μF capacitor is used, which always ensures the minimum USB Type-C VBUS capacitance
specification is met. This circuit is shown in Figure 10-8.
10.2.4 Application Curves
Figure 10-9. VBUS Short to Ground (Zoomed In)
Figure 10-10. VBUS Short to Ground (Zoomed Out)
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11 Power Supply Recommendations
11.1 3.3-V Power
11.1.1 VIN_3V3 Input Switch
The VIN_3V3 input is the main supply of the TPS25750 device. The VIN_3V3 switch (see Power Management)
is a uni-directional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3 to
VIN_3V3. This switch is on when the 3.3-V supply is available and the dead-battery flag is cleared. The
recommended capacitance CVIN_3V3 (see Recommended Capacitance) should be connected from the VIN_3V3
pin to the GND pin).
11.2 1.5-V Power
The internal circuitry is powered from 1.5 V. The 1.5-V LDO steps the voltage down from LDO_3V3 to 1.5 V. The
1.5-V LDO provides power to all internal low-voltage digital circuits which includes the digital core, and memory.
The 1.5-V LDO also provides power to all internal low-voltage analog circuits. Connect the recommended
capacitance CLDO_1V5 (see Recommended Capacitance) from the LDO_1V5 pin to the GND pin.
11.3 Recommended Supply Load Capacitance
Recommended Capacitance lists the recommended board capacitances for the various supplies. The typical
capacitance is the nominally rated capacitance that must be placed on the board as close to the pin as possible.
The maximum capacitance must not be exceeded on pins for which it is specified. The minimum capacitance is
minimum capacitance allowing for tolerances and voltage derating ensuring proper operation.
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12 Layout
12.1 TPS25750D - Layout
12.1.1 Layout Guidelines
Proper routing and placement will maintain signal integrity for high speed signals and improve the heat
dissipation from the power paths. The combination of power and high speed data signals are easily routed if the
following guidelines are followed. It is a best practice to consult with board manufacturing to verify manufacturing
capabilities.
12.1.1.1 Top Placement and Bottom Component Placement and Layout
When the TPS25750 is placed on top and its components on bottom, the solution size will be at its smallest.
12.1.2 Layout Example
Follow the differential impedances for Super / High Speed signals defined by their specifications (USB2.0). All
I/O will be fanned out to provide an example for routing out all pins, not all designs will utilize all of the I/O on the
TPS25750.
Figure 12-1. Example Schematic
12.1.3 Component Placement
Top and bottom placement is used for this example to minimize solution size. The TPS25750D is placed on the
top side of the board and the majority of its components are placed on the bottom side. When placing the
components on the bottom side, it is recommended that they are placed directly under the TPS25750D. When
placing the VBUS, PPHV, and PP5V capacitors, it is easiest to place them with the GND terminal of the
capacitors to face outward from the TPS25750D or to the side since the drain connection pads on the bottom
layer should not be connected to anything and left floating. All other components that are for pins on the GND
pad side of the TPS25750D should be placed where the GND terminal is underneath the GND pad.
The CC capacitors should be placed on the same side as the TPS25750D close to the respective CC1 and CC2
pins. Do NOT via to another layer in between the CC pins to the CC capacitor, placing a via after the CC
capacitor is recommended.
Figure 12-2 through Figure 12-5 show the placement in 2-D and 3-D.
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Figure 12-3. Bottom View Layout
Figure 12-2. Top View Layout
Figure 12-5. Bottom View 3-D
Figure 12-4. Top View 3-D
12.1.4 Routing PP_5V, VBUS, VIN_3V3, LDO_3V3, LDO_1V5
On the top side, create pours for PP5V, VBUS, VBUS_IN, and PPHV. Connect PP5V and VBUS from the top
layer to the bottom layer using at least 6 8-mil hole and 16-mil diameter vias. See Figure 12-6 for the
recommended via sizing. For VBUS_IN and PPHV, connect from the top to bottom layer using 15 8-mil hole and
16-mil diameter vias. The via placement and copper pours are highlighted in Figure 12-7.
Figure 12-6. Recommended Minimum Via Sizing
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Figure 12-7. PP5V, VBUS, VBUS_IN, and PPHV Copper Pours and Via Placement
Next, VIN_3V3, LDO_3V3, and LDO_1V5 will be routed to their respective decoupling capacitors. Additionally, a
copper pour on the bottom side is added to connect PP5V and PPHV to their decoupling capacitors located on
the bottom of the PCB. This is highlighted in Figure 12-8.
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Figure 12-8. VIN_3V3, LDO_3V3, and LDO_1V5 Routing
12.1.5 Routing CC and GPIO
Routing the CC lines with a 10-mil trace will ensure the needed current for supporting powered Type-C cables
through VCONN. For more information on VCONN refer to the Type-C specification. For capacitor GND pin use
a 16-mil trace if possible.
Most of the GPIO signals can be fanned out on the top or bottom layer using either a 8-mil or 10-mil trace. The
following images highlights how the CC lines and GPIOs are routed out.
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Figure 12-9. Top Layer GPIO Routing
Table 12-1. Routing Widths
ROUTE
CC1, CC2
WIDTH (MIL MINIMUM)
8
8
VIN_3V3, LDO_3V3, LDO_1V8
Component GND
GPIO
10
8
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12.2 TPS25750S - Layout
12.2.1 Layout Guidelines
Proper routing and placement will maintain signal integrity for high speed signals and improve the heat
dissipation from the power paths. The combination of power and high speed data signals are easily routed if the
following guidelines are followed. It is a best practice to consult with board manufacturing to verify manufacturing
capabilities.
12.2.1.1 Top Placement and Bottom Component Placement and Layout
When the TPS25750 is placed on top and its components on bottom, the solution size will be at its smallest.
12.2.2 Layout Example
Follow the differential impedances for Super / High Speed signals defined by their specifications (USB2.0). All
I/O will be fanned out to provide an example for routing out all pins, not all designs will utilize all of the I/O on the
TPS25750S.
Figure 12-10. Example Schematic
12.2.3 Component Placement
Top and bottom placement is used for this example to minimize solution size. The TPS25750S is placed on the
top side of the board and the majority of its components are placed on the bottom side. When placing the
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components on the bottom side, it is recommended that they are placed directly under the TPS25750S. When
placing the PP5V capacitors it is easiest to place them with the GND terminal of the capacitors to face inward the
TPS25750S or to the side. All other components that are for pins on the GND pad side of the TPS25750S
should be placed where the GND terminal is underneath the GND pad.
The CC capacitors should be placed on the same side as the TPS25750S close to the respective CC1 and CC2
pins. Do NOT via to another layer in between the CC pins to the CC capacitor, placing a via after the CC
capacitor is recommended.
Figure 12-11 through Figure 12-14 show the placement in 2-D and 3-D.
Figure 12-12. Bottom View Layout
Figure 12-11. Top View Layout
Figure 12-13. Top View 3-D
Figure 12-14. Bottom View 3-D
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12.2.4 Routing PP5V, VBUS, PPHV, VIN_3V3, LDO_3V3, LDO_1V5
On the top side, create pours for PP5V, VBUS, and PPHV. Connect PP5V from the top layer to the bottom layer
using at least 8, 8-mil hole and 16-mil diameter vias. Connect PPHV from the top layer to the bottom layer using
at least 12, 8-mil hole and 16-mil diameter vias. See Figure 12-15 for the recommended via sizing. The via
placement and copper pours are highlighted in Figure 12-16.
Figure 12-15. Recommended Minimum Via Sizing
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Figure 12-16. PP5V and VBUS1/2 Copper Pours and Via Placement
Next, VIN_3V3, LDO_3V3, and LDO_1V5 will be routed to their respective decoupling capacitors. Additionally, a
copper pour on the bottom side is added to connect PP5V to the decoupling capacitors located on the bottom of
the PCB. This is highlighted in Figure 12-17.
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Figure 12-17. VIN_3V3, LDO_3V3, and LDO_1V5 Routing
Figure 12-18 and Figure 12-19 show how to properly connect VSYS and the SYS_Gate control signals for the
external N-FETs. The control signals can be routed on an internal layer using a 12-mil trace, and the trace going
to VSYS should be as short as possible to minimize impedance, so placing a via directly on the high-voltage
power path is ideal.
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Figure 12-19. Bottom Polygon Pours
Figure 12-18. Top Polygon Pours
12.2.5 Routing CC and GPIO
Routing the CC lines with a 10-mil trace will ensure the needed current for supporting powered Type-C cables
through VCONN. For more information on VCONN refer to the Type-C specification. For capacitor GND pin use
a 16-mil trace if possible.
Most of the GPIO signals can be fanned out on the top or bottom layer using either a 8-mil trace or a 10-mil
trace.The following images highlight how the CC lines and GPIOs are routed out.
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Figure 12-20. Top Layer GPIO Routing
Table 12-2. Routing Widths
ROUTE
WIDTH (MIL MINIMUM)
PA_CC1, PA_CC2, PB_CC1, PB_CC2
VIN_3V3, LDO_3V3, LDO_1V8
Component GND
8
6
10
4
GPIO
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
•
•
USB-PD Specifications
USB Power Delivery Specification
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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12-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS25750DRJKT
TPS25750DRJKR
ACTIVE
WQFN
WQFN
RJK
RJK
38
38
250
TBD
Call TI
Call TI
-40 to 125
-40 to 125
PREVIEW
3000
Green (RoHS
& no Sb/Br)
NIPDAUAG
NIPDAU
Level-2-260C-1 YEAR
25750D
25750
TPS25750SRSMR
PREVIEW
VQFN
RSM
32
3000
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
RJK 38
6 x 4, 0.4 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224943/A
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PACKAGE OUTLINE
RJK0038B
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
8
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 4.8
4X (0.275)
1.53 0.1
18
(0.2)
TYP
2.72 0.1
7
EXPOSED
THERMAL PAD
29X 0.4
6
20
2X
2.65 0.1
4X 0.45
SYMM
2
40
39
0.2
(1.153)
25
1
PIN 1 ID
(OPTIONAL)
26
38
0.5
0.3
34X
0.25
0.15
(0.965)
(1.56)
PKG
38X
0.1
C A B
0.05
4224923/A 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RJK0038B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.6) TYP
4X (0.275)
(2.72)
PKG
(1.53)
METAL UNDER
(R0.05)
TYP
38
SOLDER MASK
TYP
26
2X
(0.253)
32X (0.6)
1
25
2X
(1.153)
2X
4X
(1.075)
32X (0.2)
SYMM
(2.65)
(0.1)
(3.8)
39
40
29X (0.4)
6
4X
(0.2)
20
4X (0.25)
(
0.2) TYP
VIA
SOLDER MASK
OPENING
TYP
7
19
2X
(1.11)
(0.965)
(2.075)
(2.9)
(1.56)
(2.9)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
PADS 20-25
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224923/A 04/2019
NOTES: (continued)
4. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RJK0038B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.6) TYP
4X (0.275)
4X (1.2)
PKG
2X (1.35)
26
(R0.05) TYP
38
2X
(0.253)
38X (0.6)
1
40
39
25
6X
(1.17)
2X
(1.153)
38X (0.2)
SYMM
2X
(0.1)
(3.8)
6X
(0.69)
4X (0.2)
34X (0.4)
6
20
4X
(0.25)
EXPOSED
METAL
TYP
METAL UNDER
SLODER MASK
TYP
19
7
2X (0.265)
2X (1.665)
2X (1.56)
(2.9)
(2.9)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PADS 39 & 40
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4224923/A 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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