TPS254900AIRVCRQ1 [TI]

带 VBATT 短路保护功能的汽车类 USB 主机充电器 | RVC | 20 | -40 to 85;


型号：	TPS254900AIRVCRQ1
厂家：	TEXAS INSTRUMENTS
描述：	带 VBATT 短路保护功能的汽车类 USB 主机充电器 \| RVC \| 20 \| -40 to 85
文件：	总42页 (文件大小：2120K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Support &

Community

Reference

Design

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

带有 V_BATT短路保护功能的 TPS254900A-Q1 汽车 USB 主机充电器

1 特性

当发生电池短路条件时，内部 MOSFET 迅速关断。迅

速关断功能对于保护上行直流/直流转换器、处理器或

集线器数据线路来说非常重要。

•

符合汽车应用应用

•

具有符合 AEC-Q100 标准的下列特性：

–

器件温度 1 级：-40℃ 至 +125℃ 的环境运行温

度范围

TPS254900A-Q1 具有低至 3.5V 的 UVLO 电压，因此

电源开关在启动/停止期间不会关断。

器件人体放电模式 (HBM) 静电放电 (ESD) 分类

等级 H2

TPS254900A-Q1 45mΩ 电源开关具有两个可选可调节

电流限值，可通过在相邻端口承载高负载时切换至较低

电流限值来支持端口电源管理。对于具有多个端口且上

行电源容量有限的系统而言，这一功能非常重要。

器件组件充电模式 (CDM) ESD 分类等级 C5

•

4.5V 至 6.5V 的输入工作电压范围

3.5V（典型值）UVLO 支持启动/停止

集成 45mΩ（典型值）高侧 MOSFET

3.2A 最大连续输出电流

TPS254900A-Q1 具有一个能够控制上行电源的电流感

测输出，即使在充电电流过大时也能在 USB 端口保持

5V 的电压。该功能对于 USB 电缆较长的系统而言至

关重要，因为在对便携式设备进行快速充电的过程中会

产生大幅压降。

连接器上的电缆补偿精度 V_BUS±5%

支持 USB BC 1.2 充电下行端口 (CDP) 和标准下行

端口 (SDP) 模式

•

OUT、DP_IN 和 DM_IN 引脚上具备电池短路保护

凭借电流监视器，系统能够通过监视 IMON 电压来实

时监视负载电流。电流监视器非常有用，可用于端口电

源动态管理。

DP_IN 和 DM_IN 上的保护等级符合 IEC 61000-4-

2 标准

–

±8kV 接触放电和 ±15kV 空气放电

•

20 引脚 4mm x 3mm 四方扁平无引线 (QFN) 封装

TPS254900A-Q1 器件还为 DP_IN 和 DM_IN 引脚提

供符合 IEC 61000-4-2 标准的 4 级 ESD 保护功能。

2 应用范围

器件信息⁽¹⁾

•

汽车 USB 充电端口（主机和集线器）

汽车类 USB 保护

器件型号

封装

WQFN (20)

封装尺寸（标称值）

TPS254900A-Q1

4.00mm × 3.00mm

3 说明

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

TPS254900A-Q1 器件是一款具有电池短路保护功能的

USB 充电端口控制器和电源开关。该特性为 OUT、

DM_IN 和 DP_IN 引脚提供保护。这三个引脚最高可承

受 18V 电压。

原理图

TPS254900A-Q1

10 µF

5 V

V_BUS

D–

OUT

DM_OUT

DP_OUT

To Host

Controller

DM_IN

DP_IN

BIAS

D+

FAULT

GND

FAULT

STATUS

CTL1

STATUS

2.2 µF

Mode

Select I/O

CTL2

OVP_SEL

Logic I/O

ILIM_LO

ILIM_HI

GND

Upstream DC-DC

ADC

IMON

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSCU5

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

8.4 Device Functional Modes........................................ 23

Application and Implementation ........................ 26

9.1 Application Information............................................ 26

9.2 Typical Application ................................................. 26

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 8

6.7 Typical Characteristics.............................................. 9

Parameter Measurement Information ................ 15

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Functional Block Diagram ....................................... 17

8.3 Feature Description................................................. 17

10 Power Supply Recommendations ..................... 30

11 Layout................................................................... 30

11.1 Layout Guidelines ................................................. 30

11.2 Layout Example .................................................... 32

12 器件和文档支持 ..................................................... 33

12.1 器件支持................................................................ 33

12.2 文档支持................................................................ 33

12.3 接收文档更新通知 ................................................. 33

12.4 社区资源................................................................ 33

12.5 商标....................................................................... 33

12.6 静电放电警告......................................................... 33

12.7 Glossary................................................................ 33

13 机械、封装和可订购信息....................................... 33

4 修订历史记录

Changes from Original (November 2017) to Revision A

Page

•

已更改将“预告信息”更改成了“生产数据” ................................................................................................................................ 1

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

5 Pin Configuration and Functions

RVC Package

20-Pin WQFN

Top View

IMON

OUT

Thermal

Pad

DM_IN

DP_IN

BIAS

GND

DM_OUT

DP_OUT

Not to scale

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Used for IEC protection. Typically, connect a 2.2-µF capacitor and a transient-voltage suppressor

BIAS

PWR

(TVS) to ground and 5.1 kΩ to OUT.

Linear cable compensation current. Connect to divider resistor of front-end dc-dc converter.

Logic-level control input for controlling the charging mode and the signal switches; see the Device

Truth Table (TT).

CTL1

Logic-level control input for controlling the charging mode and the signal switches; see the Device

Truth Table (TT).

CTL2

DM_IN

I/O

D– data line to downstream connector

D– data line to upstream USB host controller

D+ data line to downstream connector

D+ data line to upstream USB host controller

DM_OUT

DP_IN

DP_OUT

Logic-level control input for turning the power and signal switches on or off. When EN is low, the

device is disabled, and the signal and power switches are OFF.

Active-low, open-drain output, asserted during overtemperature, overcurrent, and overvoltage

conditions.

FAULT

GND

—

Ground connection; should be connected externally to the thermal pad.

External resistor used to set the high current-limit threshold.

ILIM_HI

ILIM_LO

External resistor used to set the low current-limit threshold and the load-detection current threshold.

This pin sources a scaled-down ratio of current through the internal FET. A resistor from this pin to

GND converts current to proportional voltage; used as an analog current monitor.

IMON

Input supply voltage; connect a 0.1-µF or greater ceramic capacitor from IN to GND as close to the

IC as possible.

2,3

PWR

OUT

15,16

Power-switch output

(1) I = Input, O = Output, I/O = Input and output, PWR = Power

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Logic-level control input for choosing the OUT overvoltage threshold. When OVP_SEL is low,

V_{(OV_OUT_LOW)}is active. When OVP_SEL is high, V_{(OV_OUT_HIGH)}is active.

OVP_SEL

STATUS

—

Active-low open-drain output, asserted in load-detect conditions

Thermal pad on the bottom of the package

Thermal pad

—

6 Specifications

6.1 Absolute Maximum Ratings

Voltages are with respect to GND unless otherwise noted⁽¹⁾

MIN

MAX

UNIT

CS, CTL1, CTL2, EN, FAULT, ILIM_HI, ILIM_LO, IN,

–0.3

IMON, OVP_SEL, STATUS

DM_OUT, DP_OUT

BIAS, DM_IN, DP_IN, OUT

DM_IN to DM_OUT or DP_IN to DP_OUT

OUT

Voltage range

–0.3

–100

5.7

100

Continuous current

Internally limited

Continuous output source current, I_SRC

Continuous output sink current, I_SNK

ILIM_HI, ILIM_LO, IMON

FAULT, STATUS

Internally limited

Operating junction temperature, T_J

Storage temperature,T_stg

–40

–65

Internally limited

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000⁽²⁾

±750⁽³⁾

±8000

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

Electrostatic

discharge

V_(ESD)

IEC 61000-4-2 contact discharge

IEC 61000-4-2 air discharge

DP_IN and DM_IN pins⁽⁴⁾

±15000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) The passing level per AEC-Q100 Classification H2.

(3) The passing level per AEC-Q100 Classification C5

(4) Surges per IEC 61000-4-2, level 4, 1999 applied from DP_IN and DM_IN to output ground of the TPS254900Q1EVM-817 (SLUUBI0)

evaluation module.

6.3 Recommended Operating Conditions

Voltages are with respect to GND unless otherwise noted.

MIN

4.5

NOM

MAX

6.5

UNIT

V_(IN)

Supply voltage

Input voltage

CTL1, CTL2, EN, OVP_SEL

DM_IN, DM_OUT, DP_IN, DP_OUT

OUT (–40°C ≤ T_A≤ 85°C)

DM_IN to DM_OUT or DP_IN to DP_OUT

FAULT, STATUS

6.5

3.6

3.2

I_(OUT)

Output continuous current

–30

kΩ

°C

Continuous output sink current

R_{(ILIM_xx)}Current-limit-set resistors

T_JOperating junction temperature

13.7

–40

1000

125

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

6.4 Thermal Information

TPS254900A-Q1

THERMAL METRIC⁽¹⁾

RVC (WQFN)

20 PINS

37.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

39.9

11.9

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

11.8

R_θJC(bot)

3.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Unless otherwise noted, –40°C ≤ T_J≤ 125°C and 4.5 V ≤ V_(IN)≤ 6.5 V, V_(EN)= V_(CTL1)= V_(CTL2)= V_(IN), R_(FAULT)= R_(STATUS)

10 kΩ, R_(IMON)= 2.55 kΩ, R_{(ILIM_HI)}= 19.1 kΩ, R_{(ILIM_LO)}= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C.

All voltages are with respect to GND.

PARAMETER

OUT – POWER SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

T_J= 25°C

r_DS(on)

On-resistance⁽¹⁾

–40°C ≤ T_J≤ 85°C

–40°C ≤T_J≤ 125°C

69 mΩ

V_OUT= 6.5 V, V_IN= V_EN= 0 V, –40°C ≤ T_J≤ 85°C,

measure I_(IN)

I_lkg

Reverse leakage current

0.01

µA

OUT – DISCHARGE

Discharge resistance

(mode change)

R_(DCHG)

400

500

630

CTL1, CTL2, EN, OVP_SEL INPUTS

Input pin rising logic

threshold voltage

0.8

0.7

1.35

Input pin falling logic

threshold voltage

Hysteresis⁽²⁾

1.15

200

1.65

µA

Input current

Pin voltage = 0 V or 6.5 V

–1

CURRENT LIMIT

R_{(ILIM_LO)}= 210 kΩ

R_{(ILIM_LO)}= 80.6 kΩ

R_{(ILIM_LO)}= 21.5 kΩ

R_{(ILIM_LO)}= 19.1 kΩ

R_{(ILIM_HI)}= 18.2 kΩ

R_{(ILIM_HI)}= 14.3 kΩ

R_{(ILIM_HI)}shorted to GND

190

555

240

620

290

680

2145

2420

2545

3240

5000

2300

2590

2720

3455

6500

2460

2760

2895

3670

8000

OUT short-circuit current

limit

I_OS

SUPPLY CURRENT

V_(EN)= 0 V, V_(OUT)= 0 V, –40°C ≤ T_J≤ 85°C, no

5.1-kΩ resistor (open) between BIAS and OUT

I_{(IN_OFF)}

Disabled IN supply current

0.1

µA

SDP mode (CTL1, CTL2 = 0, 1)

CDP mode (CTL1, CTL2 = 1, 1)

Client mode (CTL1, CTL2 = 0, 0)

170

200

120

250

280

210

I_{(IN_ON)}

Enabled IN supply current

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account

separately.

(2) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's

product warranty.

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

Electrical Characteristics (continued)

Unless otherwise noted, –40°C ≤ T_J≤ 125°C and 4.5 V ≤ V_(IN)≤ 6.5 V, V_(EN)= V_(CTL1)= V_(CTL2)= V_(IN), R_(FAULT)= R_(STATUS)

10 kΩ, R_(IMON)= 2.55 kΩ, R_{(ILIM_HI)}= 19.1 kΩ, R_{(ILIM_LO)}= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C.

All voltages are with respect to GND.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

UNDERVOLTAGE LOCKOUT, IN

IN rising

IN falling

3.9

3.3

4.1

3.5

4.3

V_(UVLO)

UVLO threshold voltage

3.7

FAULT

Output low voltage

Off-state leakage

I_(FAULT)= 1 mA

V_(FAULT)= 6.5 V

100

µA

STATUS

Output low voltage

Off-state leakage

I_(STATUS)= 1 mA

V_(STATUS)= 6.5 V

100

µA

THERMAL SHUTDOWN

Thermal shutdown

T_(OTSD2)

155

135

°C

threshold

Thermal shutdown

threshold in current-limit

T_(OTSD1)

°C

Hysteresis⁽³⁾

LOAD DETECT (V_CTL1= V_CTL2= V_IN

)

I_OUTload detection

threshold

Hysteresis⁽³⁾

I_(LD)

R_{(ILIM_LO)}= 80.6 kΩ, rising load current

585

3.3

650

715

DM_IN AND DP_IN OVERVOLTAGE PROTECTION

V_{(OV_Data)}

Protection trip threshold

Hysteresis⁽³⁾

DP_IN and DM_IN rising

3.9

100

200

370

390

4.15

DP_IN = DM_IN = 18 V, IN = 5 V or 0 V

DP_IN = DM_IN = 5 V, IN = 5 V

DP_IN = DM_IN = 5 V, IN = 0

Discharge resistor after

OVP(2)

R_{(DCHG_Data)}

kΩ

OUT OVERVOLTAGE PROTECTION

V_{(OV_OUT_LOW)}

Protection trip threshold

Hysteresis⁽³⁾

OUT rising

5.65

6.6

6.35

7.3

V_{(OV_OUT_HIGH)}

Protection trip threshold

Hysteresis⁽³⁾

6.95

130

OUT = 18 V, IN = 5 V

OUT = 18 V, IN = 0

R_{(DCHG_OUT)}

Discharge resistor

kΩ

120

CABLE COMPENSATION

Load = 3.2 A, 2.5 V ≤ V_(CS)≤ 6.5 V

Load = 3 A, 2.5 V ≤ V_(CS)≤ 6.5 V

Load = 2.4 A, 2.5 V ≤ V_(CS)≤ 6.5 V

Load = 2.1 A, 2.5 V ≤ V_(CS)≤ 6.5 V

Load = 1 A, 2.5 V ≤ V_(CS)≤ 6.5 V

250

234

187

163

262

246

197

172

275

258

207

181

I_(CS)

Sink current

µA

(3) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's

product warranty.

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

Electrical Characteristics (continued)

Unless otherwise noted, –40°C ≤ T_J≤ 125°C and 4.5 V ≤ V_(IN)≤ 6.5 V, V_(EN)= V_(CTL1)= V_(CTL2)= V_(IN), R_(FAULT)= R_(STATUS)

10 kΩ, R_(IMON)= 2.55 kΩ, R_{(ILIM_HI)}= 19.1 kΩ, R_{(ILIM_LO)}= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C.

All voltages are with respect to GND.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CURRENT MONITOR OUTPUT (IMON)

Load = 3.2 A, 0 ≤ V_(IMON)≤ 2.5 V

Load = 3 A, 0 ≤ V_(IMON)≤ 2.5 V

Load = 2.4 A, 0 ≤ V_(IMON)≤ 2.5 V

Load = 2.1 A, 0 ≤ V_(IMON)≤ 2.5 V

Load = 1 A, 0 ≤ V_(IMON)≤ 2.5 V

Load = 0.5 A, 0 ≤ V_(IMON)≤ 2.5 V

306

287

230

201

333

312

250

218

104

359

337

270

µA

I_(IMON)

Source current

235

114

HIGH-BANDWIDTH ANALOG SWITCH

V_{(DP_OUT)}= V_{(DM_OUT)}= 0 V, I_{(DP_IN)}= I_{(DM_IN)}

30 mA

3.2

3.8

6.5

DP and DM switch on-

resistance

R_{(HS_ON)}

V_{(DP_OUT)}= V_{(DM_OUT)}= 2.4 V, I_{(DP_IN)}= I_{(DM_IN)}

–15 mA

7.6

V_{(DP_OUT)}= V_{(DM_OUT)}= 0 V, I_{(DP_IN)}= I_{(DM_IN)}

30 mA

0.05

8.8

0.15

Switch resistance mismatch

between DP and DM

channels

|ΔR_{(HS_ON)}

V_{(DP_OUT)}= V_{(DM_OUT)}= 2.4 V, I_{(DP_IN)}= I_{(DM_IN)}

–15 mA

0.15

DP and DM switch off-state V_EN= 0 V, V_{(DP_IN)}= V_{(DM_IN)}= 0.3 V, Vac = 0.03

capacitance⁽⁴⁾

V_PP, f = 1 MHz

C_{(IO_OFF)}

C_{(IO_ON)}

DP and DM switch on-state V_{(DP_IN)}= V_{(DM_IN)}= 0.3 V, Vac = 0.03 V_PP, f = 1

10.9

capacitance⁽⁴⁾

MHz

Off-state isolation(3)

V_(EN)= 0 V, f = 250 MHz

On-state cross-channel

isolation⁽⁴⁾

f = 250 MHz

V_EN= 0 V, V_{(DP_IN)}= V _{(DM_IN)}= 3.6 V, V_{(DP_OUT)}

= V_{(DM_OUT)}= 0 V, measure I_{(DP_OUT)}and

I_{(DM_OUT)}

I_lkg(OFF)

Off-state leakage current

Bandwidth (–3 dB)⁽⁴⁾

0.1

1.5

µA

R_(L)= 50 Ω

940

MHz

CHARGING DOWNSTREAM PORT DETECT

V_{(DM_SRC)}

DM_IN CDP output voltage V_{(DP_IN)}= 0.6 V, –250 µA < I_{(DM_IN)}< 0 µA

0.5

0.6

0.7

0.4

DP_IN rising lower window

threshold for V_{(DM_SRC)}

activation

V_{(DAT_REF)}

0.36

Hysteresis⁽⁴⁾

DP_IN rising upper window

threshold for VDM_SRC

de-activation

Hysteresis⁽⁴⁾

V_{(LGC_SRC)}

0.8

0.88

100

V_{(LGC_SRC_HYS)}

I_{(DP_SINK)}

100

µA

DP_IN sink current

V_{(DP_IN)}= 0.6 V

(4) This parameter is provided for reference only and does not constitute part of TI's published device specifications for purposes of TI's

product warranty.

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

6.6 Switching Characteristics

Unless otherwise noted –40°C ≤ T_J≤ 125°C and 4.5 V ≤ V_(IN)≤ 6.5 V, V_(EN)= V_(IN), V_(CTL1)= V_(CTL2)= V_(IN). R_(FAULT)= R_(STATUS)

= 10 kΩ, R_(IMON)= 2.55 KΩ, R_{(ILIM_HI)}= 19.1 kΩ, R_{(ILIM_LO)}= 80.6 kΩ. Positive currents are into pins. Typical values are at

25°C. All voltages are with respect to GND.

PARAMETER

TEST CONDITIONS

MIN

1.05

0.27

TYP

1.75

0.47

7.5

MAX UNIT

t_r

OUT voltage rise time

OUT voltage fall time

OUT voltage turnon time

OUT voltage turnoff time

3.1

0.82

V_(IN)= 5 V, C_(L)= 1 µF, R_(L)= 100 Ω

t_f

t_on

t_off

V_(IN)= 5 V, C_(L)= 1 µF, R_(L)= 100 Ω

2.7

Discharge hold time (mode

change)

t_{(DCHG_S)}

t_(IOS)

t_{(OC_OUT_FAULT)}

t_pd

Time V_(OUT)< 0.7 V

1.1

5.5

2.9

OUT short-circuit response

time⁽¹⁾

V_(IN)= 5 V, R_(SHORT)= 50 mΩ

µs

Bidirectional deglitch applicable to current-limit

condition only (no deglitch assertion for OTSD)

OUT FAULT deglitch time

Analog switch propagation

8.5

0.14

11.5

V_(IN)= 5 V

(1)

delay

Analog switch skew

between opposite

t_(SK)

V_(IN)= 5 V

0.02

transitions of the same port

(1)

(t_PHL– t_PLH

)

t_{(LD_SET)}

Load-detect set time

Load-detect reset time

V_(IN)= 5 V

120

1.8

210

280

4.2

t_{(LD_RESET)}

DP_IN and DM_IN

overvoltage protection

response time

t_{(OV_Data)}

µs

OUT overvoltage protection

response time

t_{(OV_OUT)}

0.3

µs

DP_IN and DM_IN FAULT-

asserted degltich time

t_{(OV_D_FAULT)}

OUT FAULT-asserted

degltich time

(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

6.7 Typical Characteristics

T_A= 25°C, V_(IN)= 5 V, V_(EN)= 5 V, V_(CTL1)= V_(CTL2)= 5 V, FAULT and STATUS connect to V_(IN)via a 10-kΩ pullup resistor

(unless stated otherwise)

40.8

40.6

40.4

40.2

39.8

39.6

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D001

D002

V_(IN)= 5 V

V_(OUT)= 5 V

Measure I_(OUT)

图 1. Power Switch On-Resistance vs Temperature

图 2. Reverse Leakage Current vs Temperature

570

560

550

540

530

520

510

500

490

480

100

V_IN= 4.5 V

V_IN= 5.0 V

V_IN= 6.5 V

V_IN= 5 V

V_IN= 0 V

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D003

D004

图 3. OUT Discharge Resistance (Mode Change) vs

图 4. OUT Discharge Resistance (OVP) vs Temperature

Temperature

3600

3400

3200

3000

2800

2600

2400

2200

2000

700

600

500

400

300

200

100

RILIM_HI = 21.5 K

RILIM_HI = 19.1 K

RILIM_HI = 18.2 K

RILIM_HI = 14.3 K

R_{ILIM_LO}= 210 kW

R_{ILIM_LO}= 80.6 kW

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D005

D006

V_(IN)= 5 V

图 5. OUT Short-Circuit Current Limit vs Temperature I

图 6. OUT Short-Circuit Current Limit vs Temperature II

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

Typical Characteristics (接下页)

T_A= 25°C, V_(IN)= 5 V, V_(EN)= 5 V, V_(CTL1)= V_(CTL2)= 5 V, FAULT and STATUS connect to V_(IN)via a 10-kΩ pullup resistor

(unless stated otherwise)

240

220

200

180

160

V_IN= 4.5 V

V_IN= 5 V

V_IN= 6.5 V

V_IN= 4.5 V

V_IN= 5 V

V_IN= 6.5 V

-2

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D007

D008

CTL1 = 1

CTL2 = 1

CTL1 = 1

CTL2 = 1

图 7. Disabled IN Supply Current vs Temperature

图 8. Enabled IN Supply Current – CDP (11) vs Temperature

660

650

640

630

620

610

600

4.2

4.1

3.9

3.8

3.7

3.6

LLD - I_OUTRising Load Detect Threshold

IOS - I_OUTShort Circuit Current Limit

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D011

D012

V_(IN)= 5 V

R_{(ILIM_LO)}= 80.6 kΩ

V_(IN)= 5 V

图 9. I_(OUT)Rising Load-Detect Threshold and OUT Short-

图 10. DP_IN Overvoltage Protection Threshold vs

Circuit Limit vs Temperature

Temperature

300

250

200

150

100

7.3

7.2

7.1

6.9

6.8

6.7

6.6

I_OUT= 1 A

I_OUT= 2.1 A

I_OUT= 2.4 A

I_OUT= 3 A

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125 140

Junction Temperature (èC)

D014

D016

V_(IN)= 5 V

V_(CS)= 25 V

图 11. OUT Overvoltage Protection Threshold vs

图 12. I_(CS)vs Temperature

Temperature

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

Typical Characteristics (接下页)

T_A= 25°C, V_(IN)= 5 V, V_(EN)= 5 V, V_(CTL1)= V_(CTL2)= 5 V, FAULT and STATUS connect to V_(IN)via a 10-kΩ pullup resistor

(unless stated otherwise)

300

250

200

150

100

340

320

300

280

260

240

220

200

IOUT = 2.1 A

IOT = 2.4 A

IOUT = 3 A

I_OUT= 1 A

I_OUT= 2.1 A

I_OUT= 2.4 A

I_OUT= 3 A

2.5

3.5

4.5

5.5

6.5

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

D017

D018

V_IN= 6.5 V

V_IN= 5 V

V_(IMON)= 25 V

图 13. I_(CS)vs V_(CS)Voltage

图 14. I_(IMON)vs Temperature

320

300

280

260

240

220

200

IOUT = 2.1 A

IOUT = 2.4 A

IOUT = 3 A

180

0.5

1.5

2.5

V_CSVoltage (V)

D020

V_IN= 4.5 V

图 15. I_(IMON)vs V_(CS)Voltage

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

Typical Characteristics (接下页)

T_A= 25°C, V_(IN)= 5 V, V_(EN)= 5 V, V_(CTL1)= V_(CTL2)= 5 V, FAULT and STATUS connect to V_(IN)via a 10-kΩ pullup resistor

(unless stated otherwise)

Measured on EVM with 10-cm cable

图 16. Bypassing the TPS254900A-Q1 Data Switch

图 17. Through the TPS254900A-Q1 Data Switch

V_EN

5 V/div

V_OUT

2 V/div

I_OUT

0.5 A/div

R_(LOAD)= 5 Ω

C_(LOAD)= 10 µF

t = 1 ms/div

R_(LOAD)= 5 Ω

C_(LOAD)= 10 µF

t = 2 ms/div

图 19. Turnoff Response

图 18. Turnon Response

R_{(ILIM_HI)}= 19.1 kΩ

t = 4 ms/div

R_{(ILIM_LO)}= 80.6 kΩ

t = 4 ms/div

图 21. Enable Into Short (CDP) – Thermal Cycling

图 20. Enable Into Short (SDP)

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

Typical Characteristics (接下页)

T_A= 25°C, V_(IN)= 5 V, V_(EN)= 5 V, V_(CTL1)= V_(CTL2)= 5 V, FAULT and STATUS connect to V_(IN)via a 10-kΩ pullup resistor

(unless stated otherwise)

R_{(ILIM_HI)}= 19.1 kΩ

t = 4 ms/div

R_{(ILIM_LO)}= 80.6 kΩ

t = 2 ms/div

图 23. Short Circuit to No Load (CDP)

图 22. Short Circuit to No Load (SDP)

R_{(ILIM_LO)}= 80.6 kΩ

t = 100 ms/div

R_{(ILIM_HI)}= 19.1 kΩ

R(short) = 50 mΩ

图 24. Hot Short

t = 2 ms/div

图 25. Load-Detection Set Time

R_{(ILIM_LO)}= 80.6 kΩ

t = 1 s/div

t = 4 ms/div

图 26. Load-Detection Reset Time

图 27. OUT Short to Battery

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

Typical Characteristics (接下页)

T_A= 25°C, V_(IN)= 5 V, V_(EN)= 5 V, V_(CTL1)= V_(CTL2)= 5 V, FAULT and STATUS connect to V_(IN)via a 10-kΩ pullup resistor

(unless stated otherwise)

t = 100 ms/div

图 28. OUT Short-to-Battery Recovery

t = 4 ms/div

图 29. DP_IN Short to Battery

R_(BIAS)= 5.1 kΩ

t = 100 ms/div

R_(BIAS)= 5.1 kΩ

t = 4 ms/div

图 30. DP_IN Short-to-Battery Recovery

图 31. DP_IN Short to V_BUS

R_(BIAS)= 5.1 kΩ

t = 200 ms/div

图 33. Data Transmission Characteristics vs Frequency

图 32. DP_IN Short-to-V_BUSand Recovery

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

Typical Characteristics (接下页)

T_A= 25°C, V_(IN)= 5 V, V_(EN)= 5 V, V_(CTL1)= V_(CTL2)= 5 V, FAULT and STATUS connect to V_(IN)via a 10-kΩ pullup resistor

(unless stated otherwise)

图 34. Off-State Data-Switch Isolation vs Frequency

图 35. On-State Cross-Channel Isolation vs Frequency

7 Parameter Measurement Information

10 cm AWG18

0.5 m AWG28

Manually Hot-short

0.5 m AWG22

18 V

5 V

OUT

DM_IN

DP_IN

GND

27 mF

35 V

GND

PWR817A

图 36. Short-to-Battery System Test Setup

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

8 Detailed Description

8.1 Overview

The TPS254900A-Q1 device is a USB charging controller and power switch which integrates D+ and D– short-to-

battery protection, cable compensation, current monitor (IMON), and IEC ESD protection suitable for automotive

USB charging and USB port protection applications.

The integrated power distribution switch uses N-channel MOSFETs suitable for applications where short circuits

or heavy capacitive loads will be encountered. The device allows the user to adjust the current-limit thresholds

using external resistors. The device enters constant-current mode when the load exceeds the current-limit

threshold.

The TPS254900A-Q1 device provides V_BUS, D+, and D– short-to-battery protection. This protects the upstream

voltage regulator, automotive processor, and hub when these pins are exposed to fault conditions.

The device also integrates CDP mode, defined in the BC1.2 specification, to enable up to 1.5-A fast charging of

most portable devices during data communication.

The TPS254900A-Q1 device integrates a cable compensation (CS) feature to compensate for long-cable voltage

drop. This keeps the remote USB port output voltage constant to enhance the user experience under high-

current charging conditions.

The TPS254900A-Q1 device provides a current-monitor function (IMON) by connecting a resistor from the IMON

pin to GND to provide a positive voltage linearly with load current. This can be used for system power or dynamic

power management.

Additionally, the device provides ESD protection up to ±8 kV (contact discharge) and ±15 kV (air discharge) per

IEC 61000-4-2 on DP_IN and DM_IN.

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

8.2 Functional Block Diagram

Current

Sense

OUT

OVP1

(Short to BAT)

Disable + UVLO +

Discharge + OVP

ILIM_HI

ILIM_LO

Current

Limit

OVP_SEL

GND

Charge

Pump

8-ms

Deglitch

Driver

UVLO

FAULT

Thermal

Sense

´82 µA/A

OTSD

IEC ESD

Protection

BIAS

OVP2/3 (Short to BAT)

´104 µA/A

IMON

DM_OUT

DP_OUT

DM_IN

DP_IN

CDP

Detection

CTL1

CTL2

STATUS

Logic

Control

Discharge

8.3 Feature Description

8.3.1 FAULT Response

The device features an active-low, open-drain fault output. FAULT goes low when there is a fault condition. Fault

detection includes overtemperature, overcurrent, or overvoltage on V_BUS, DP_IN and DM_IN. Connect a 10-kΩ

pullup resistor from FAULT to IN.

表 1 summarizes the conditions that generate a fault and actions taken by the device.

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

Feature Description (接下页)

表 1. Fault Conditions

EVENT

CONDITION

ACTION

Overvoltage on the data lines

V_{(DP_IN)}or V_{(DM_IN)}> 3.9 V

V_(OUT)> 6 V or 6.95 V

I_(OUT)> I_(OS)

The device immediately shuts off the USB data switches and

the internal power switch. The fault indicator asserts with a

16-ms deglitch, and deasserts without deglitch.

Overvoltage on V_(OUT)

Overcurrent on V_(OUT)

The device immediately shuts off the internal power switch

and the USB data switches. The fault indicator asserts with a

16-ms deglitch and deasserts without deglitch.

The device regulates switch current at I_(OS)until thermal

cycling occurs. The fault indicator asserts and deasserts with

an 8-ms deglitch (the device does not assert FAULT on

overcurrent in SDP1 mode).

Overtemperature

T_J> OTSD2 in non-current-limited or T_JThe device immediately shuts off the internal power switch

> OTSD1 in current-limited mode.

and the USB data switches. The fault indicator asserts

immediately when the junction temperature exceeds OTSD2

or OTSD1 while in a current-limiting condition. The device

has a thermal hysteresis of 20°C.

8.3.2 Cable Compensation

When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to

the load. In the vehicle from the voltage regulator 5-V output to the V_{PD_IN}(input voltage of portable device), the

total resistance of power switch r_DS(on)and cable resistance causes an IR drop at the PD input. So the charging

current of most portable devices is less than their expected maximum charging current.

V_(OUT)With Compensation

5.x

V_BUSWith Compensation

V_(DROP)

V_BUSWithout Compensation

I_(OUT)(A)

0.5

1.5

2.5

图 37. Voltage Drop

The TPS254900A-Q1 device detects the load current and applies a proportional sink current that can be used to

adjust the output voltage of the upstream regulator to compensate for the IR drop in the charging path. The gain

G_(CS)of the sink current proportional to load current is 82 µA/A.

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

r_DS(on)

V_(OUT)

To Regulator OUT

C_(COMP)

To Load

OUT

R_(WIRE)

R_(LOAD)

R_(FA)

C_(BUS)

R_(FB)

To Regulator

Resistor Divider

R_(G)

图 38. Cable Compensation Equivalent Circuit

8.3.2.1 Design Procedure

To start the procedure, the total resistance, including the power switch r_DS(on)and wire resistance R_(WIRE), must

be known.

1. Choose R_(G)following the voltage-regulator feedback resistor-divider design guideline.

2. Calculate R_(FA)according to 公式 1.

R_FA= (r_DS(on)+ R_(WIRE)) / G_(CS)

(1)

3. Calculate R_(FB)according to 公式 2.

(OUT)

R_(FB)

- R_(G)- R_(FA)

/ R_(G)

(FB)

(2)

4. C_(COMP)in parallel with R_(FA)is required to stablilize V_(OUT)when C_(BUS)is large. Start with C_(COMP)≥ 3 × G_(CS)

× C_(OUT), then adjust C_(COMP)to optimize the load transient of the voltage regulator output. V_(OUT)stability

should always be verified in the end application circuit.

8.3.3 D+ and D– Protection

D+ and D– protection consists of ESD and OVP (overvoltage protection). The DP_IN and DM_IN pins provide

ESD protection up to ±15 kV (air discharge) and ±8 kV (contact discharge) per IEC 61000-4-2 (see the ESD

Ratings section for test conditions).

The ESD stress seen at DP_IN and DM_IN is impacted by many external factors, like the parasitic resistance

and inductance between ESD test points and the DP_IN and DM_IN pins. For air discharge, the temperature and

humidity of the environment can cause some difference, so the IEC performance should always be verified in the

end-application circuit.

The IEC ESD performance of the TPS254900A-Q1 device depends on the capacitance connected from BIAS to

GND. A 2.2-µF capacitor placed close to the BIAS pin is recommended. Connect the BIAS pin to OUT using a

5.1-kΩ resistor as a discharge path for the ESD stress.

OVP protection is provided for short-to-V_BUSor short-to-battery conditions in the vehicle harness, preventing

damage to the upstream USB transceiver or hub. When the voltage on DP_IN or DM_IN exceeds 3.9 V (typical),

the TPS254900A-Q1 device quickly responds to block the high-voltage reverse connection to DP_OUT and

DM_OUT. Overcurrent short-to-GND protection for D+ and D– is provided by the upstream USB transceiver.

8.3.4 V_BUSOVP Protection

The TPS254900A-Q1 OUT pin can withstand up to 18 V. The internal MOSFET turns off quickly when a short-to-

battery condition occurs.

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

The TPS254900A-Q1 device has two OVP thresholds; one is 6 V (typical) and the other is 6.95 V (typical). Set

the OVP threshold using the external OVP_SEL pin.

8.3.5 Output and D+ or D– Discharge

To allow a charging port to renegotiate current with a portable device, the TPS254900A-Q1 device uses the OUT

discharge function. During mode change, the TPS254900A-Q1 device turns off the power switch while

discharging OUT with a 500-Ω resistance, then turning back on the power switches to reassert the OUT voltage.

When an OVP condition occurs on DP_IN or DM_IN, the TPS254900A-Q1 device enables an internal 200-kΩ

discharge resistance from DP_IN to ground and from DM_IN to ground. The analog switches are also turned off.

The TPS254900A-Q1 device automatically disables the discharge paths and turns on the analog switches once

the OVP condition is removed.

When an OVP condition occurs on OUT, the TPS254900A-Q1 device turns on an internal discharge path (see 表

2 for the discharge resistance). The TPS254900A-Q1 device automatically turns off the discharge path and turns

on the power switch once the OVP condition is removed.

表 2. OUT Discharge Resistance

OUT DISCHARGE

VIN⁽¹⁾

EN⁽¹⁾

OVP⁽¹⁾

RESISTANCE⁽²⁾

—

80 kΩ

—

80 kΩ

500 Ω

500 Ω or 55 kΩ

—

55 kΩ

(1) 0 = inactive, 1 = active

(2) — = no discharge resistance

8.3.6 Port Power Management (PPM)

PPM is the intelligent and dynamic allocation of power. PPM is for systems that have multiple charging ports but

cannot power them all simultaneously.

8.3.6.1 Benefits of PPM

The benefits of PPM include the following:

•

Delivers better user experience

Prevents overloading of system power supply

Allows for dynamic power limits based on system state

Allows every port potentially to be a high-power charging port

Allows for smaller power-supply capacity because loading is controlled

8.3.6.2 PPM Details

All ports are allowed to broadcast high-current charging. The current limit is based on ILIM_HI. The system

monitors the STATUS pin to see when high-current loads are present. Once the allowed number of ports asserts

STATUS, the remaining ports are toggled to a non-charging port. The current limit of the non-charging port is

based on the ILIM_LO setting. The non-charging ports are automatically toggled back to charging ports when a

charging port deasserts STATUS.

STATUS asserts in a charging port when the load current is above ILIM_LO + 30 mA for 210 ms (typical).

STATUS deasserts in a charging port when the load current is below ILIM_LO – 20 mA for 3 seconds (typical).

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

8.3.6.3 Implementing PPM in a System With Two Charging Ports (CDP and SDP1)

图 39 shows the implementation of the two charging ports with data communication, each with a TPS254900A-

Q1 device and configured in CDP mode. In this example, the 5-V power supply for the two charging ports is

rated at less than 3.5 A. Both TPS254900A-Q1 devices have R_(ILIM)chosen to correspond to the low (1-A) and

high (2.4-A) current-limit setting for the port. In this implementation, the system can support only one of the two

ports at 2.4-A charging current, whereas the other port is set to the SDP1 mode and I_OScorresponds to 1 A.

USB Charging

Port 1

TPS254900A-Q1 Port 1

5 V

OUT

EN1

DM_IN

FAULT1

DP_IN

FAULT

STATUS

CTL1

ILIM_LO

ILIM_HI

GND

100 kW

CTL2

USB Charging

Port 1

TPS254900A-Q1 Port 1

OUT

EN2

DM_IN

FAULT2

DP_IN

FAULT

STATUS

CTL1

ILIM_LO

ILIM_HI

GND

100 kW

CTL2

图 39. PPM Between CDP and SDP1

8.3.7 Overcurrent Protection

When an overcurrent condition is detected, the device maintains a constant output current and reduces the

output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output is

shorted before the device is enabled or before the application of V_(IN). The TPS254900A-Q1 device senses the

short and immediately switches into a constant-current output. In the second condition, a short or an overload

occurs while the device is enabled. At the instant the overload occurs, high currents flow for 1 to 2 μs (typical)

before the current-limit circuit reacts. The device operates in constant-current mode after the current-limit circuit

has responded. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting.

The device remains off until the junction temperature cools approximately 20°C and then restarts. The device

continues to cycle on and off until the overcurrent condition is removed.

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

8.3.8 Undervoltage Lockout

The undervoltage-lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO

turnon threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from

large current surges.

8.3.9 Thermal Sensing

Two independent thermal-sensing circuits protect the TPS254900A-Q1 device if the temperature exceeds

recommended operating conditions. These circuits monitor the operating temperature of the power-distribution

switch and disable operation. The power dissipation in the package is proportional to the voltage drop across the

power switch, so the junction temperature rises during an overcurrent condition. The first thermal sensor turns off

the power switch when the die temperature exceeds 135ºC and the device is in current limit. The second thermal

sensor turns off the power switch when the die temperature exceeds 155ºC regardless of whether the power

switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns on after the device

has cooled by approximately 20°C. The switch continues to cycle off and then on until the fault is removed. The

open-drain false-reporting output, FAULT, is asserted (low) during an overtemperature shutdown condition.

8.3.10 Current-Limit Setting

The TPS254900A-Q1 has two independent current-limit settings that are each adjusted externally with a resistor.

The ILIM_HI setting is adjusted with R_{(ILIM_HI)}connected between ILIM_HI and GND. The ILIM_LO setting is

adjusted with R_{(ILIM_LO)}connected between ILIM_LO and GND. Consult the device truth table (表 3) to see when

each current limit is used. Both settings have the same relation between the current limit and the adjusting

resistor.

The following equation calculates the value of resistor for adjusting the typical current limit:

48687 V

0.9945

I_OS(nom)(mA) =

R_{(ILIM_ xx)}

(3)

Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance

limits, both the tolerance of the TPS254900A-Q1 current limit and the tolerance of the external adjusting resistor

must be taken into account. The following equations approximate the TPS254900A-Q1 minimum and maximum

current limits to within a few milliamperes and are appropriate for design purposes. The equations do not

constitute part of TI’s published device specifications for purposes of TI’s product warranty. These equations

assume an ideal—no variation—external adjusting resistor. To take resistor tolerance into account, first

determine the minimum and maximum resistor values based on its tolerance specifications and use these values

in the equations. Because of the inverse relation between the current limit and the adjusting resistor, use the

maximum resistor value in the I_OS(min)equation and the minimum resistor value in the I_OS(max)equation.

46464 V

0.9974

I_OS(min)(mA) =

- 32

R_{(ILIM_ xx)}

(4)

(5)

51820 V

0.9987

I_OS(max)(mA) =

+ 38

R_{(ILIM_ xx)}

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

4000

3500

3000

2500

2000

1500

1000

500

600

500

400

300

200

100

I_OS, Min

_OS, Max

I_OS, Typ

I_OS, Min

_OS, Max

I_OS, Typ

Adjusting Resistor (kW)

100

100 200 300 400 500 600 700 800 900 1000

Adjusting Resistor (kW)

D022

D023

图 40. Current-Limit Setting vs Adjusting Resistor I

图 41. Current-Limit Setting vs Adjusting Resistor II

The routing of the traces to the R_{(ILIM_xx)}resistors should have a sufficiently low resistance so as not to affect the

current-limit accuracy. The ground connection for the R_{(ILIM_xx)}resistors is also very important. The resistors must

reference back to the TPS254900A-Q1 GND pin. Follow normal board layout practices to ensure that current

flow from other parts of the board does not impact the ground potential between the resistors and the

TPS254900A-Q1 GND pin.

8.4 Device Functional Modes

8.4.1 Device Truth Table (TT)

The device truth table (表 3) lists all valid combinations for both control pins (CTL1 and CTL2), and the

corresponding charging mode. The TPS254900A-Q1 device monitors the CTL inputs and transitions to the

charging mode to which it is commanded.

表 3. Truth Table

STATUS

FOR LOAD

DETECT

IMON FOR

CURRENT

MONITOR

CURRENT LIMIT

SELECTED

CS FOR CABLE

COMPENSATION

FAULT

REPORT

CTL1

CTL2

MODE

NOTES

N/A

Client

OFF

Power switch

is disabled,

only analog

switch is on.

mode⁽¹⁾

ILIM_LO

SDP

OFF

Standard

SDP

SDP1⁽²⁾

ON⁽³⁾

No OUT

discharge

between CDP

and SDP1 for

PPM

ILIM_HI

CDP⁽²⁾

(1) No 5.1-kΩ resistor from BIAS to OUT (open between the pins), or OUT still has 5-V voltage from an external downstream port; client

mode is still active.

(2) No OUT discharge when changing from 10 to 11 or from 11 to 10.

(3) A fault only trips OTSD, OUT, DP_IN, DM_IN, and OVP.

8.4.2 USB BC1.2 Specification Overview

The BC1.2 specification includes three different port types:

•

Standard downstream port (SDP)

Charging downstream port (CDP)

Dedicated charging port (DCP)

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

BC1.2 defines a charging port as a downstream-facing USB port that provides power for charging portable

equipment. Under this definition, CDP and DCP are defined as charging ports.

表 4 lists the difference between these port types.

表 4. Operating Modes Table

MAXIMUM ALLOWABLE CURRENT

DRAWN BY PORTABLE EQUIPMENT (A)

PORT TYPE

SUPPORTS USB 2.0 COMMUNICATION

SDP (USB 2.0)

SDP (USB 3.0)

CDP

YES

0.5

0.9

1.5

DCP

8.4.3 Standard Downstream Port (SDP) Mode — USB 2.0 and USB 3.0

An SDP is a traditional USB port that follows the USB 2.0 or USB 3.0 protocol. An SDP supplies a minimum of

500 mA per port for USB 2.0 and 900 mA per port for USB 3.0. USB 2.0 and USB 3.0 communication is

supported, and the host controller must be active to allow charging.

8.4.4 Charging Downstream Port (CDP) Mode

A CDP is a USB port that follows the USB BC1.2 specification and supplies a minimum of 1.5 A per port. A CDP

provides power and meets the USB 2.0 requirements for device enumeration. USB 2.0 communication is

supported, and the host controller must be active to allow charging. The difference between CDP and SDP is the

host-charge handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2

client device and allows for additional current draw by the client device.

The CDP handshaking process occurs in two steps. During the first step, the portable equipment outputs a

nominal 0.6-V output on the D+ line and reads the voltage input on the D– line. The portable device detects the

connection to an SDP if the voltage is less than the nominal data-detect voltage of 0.3 V. The portable device

detects the connection to a CDP if the D– voltage is greater than the nominal data-detect voltage of 0.3 V and

optionally less than 0.8 V.

The second step is necessary for portable equipment to determine whether the equipment is connected to a CDP

or a DCP. The portable device outputs a nominal 0.6-V output on the D– line and reads the voltage input on the

D+ line. The portable device concludes the equipment is connected to a CDP if the data line being read remains

less than the nominal data detects voltage of 0.3 V. The portable device concludes it is connected to a DCP if

the data line being read is greater than the nominal data-detect voltage of 0.3 V.

The TPS254900A-Q1 device integrates CDP detection protocol, used at a downstream port as the CDP

controller to support CDP portable-device fast charge up to 1.5 A.

8.4.5 Client Mode

The TPS254900A-Q1 device integrates client mode as shown in 图 42. The internal power switch is OFF to block

current flow from OUT to IN, and the signal switches are ON. This mode can be used for software upgrades from

the USB port.

OUT

DP_IN

DM_IN

OFF

DP_OUT

DM_OUT

图 42. Client-Mode Equivalent Circuit

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

Passing the IEC 61000-4-2 test for DP_IN and DM_IN requires connecting a discharge resistor to OUT during

USB 2.0 high-speed enumeration. In client mode, because the power switch is OFF, OUT must be 5 V so that

the device can work normally (usually powered by an external downstream USB port). If the OUT voltage is low,

the communication may not work properly.

8.4.6 High-Bandwidth Data-Line Switch

The D+ and D– data lines pass through the device to enable monitoring and handshaking while supporting the

charging operation. A wide-bandwidth signal switch allows data to pass through the device without corrupting

signal integrity. The data-line switches are turned on in any of the CDP, SDP or client operating modes. The EN

input must be at logic high for the data-line switches to be enabled.

注

•

While in CDP mode, the data switches are ON, even during CDP handshaking.

The data switches are only for the USB-2.0 differential pair. In the case of a USB-3.0

host, the super-speed differential pairs must be routed directly to the USB connector

without passing through the TPS254900A-Q1 device.

•

Data switches are OFF during OUT (V_BUS) discharge.

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS254900A-Q1 device is a USB charging-port controller and power switch with cable compensation and

short-to-battery protection for V_BUS, D+, and D–. The device is typically used for automotive USB port protection

and as a USB charging controller. The following design procedure can be used to select components for the

TPS254900A-Q1 device. This section presents a simplified discussion of how to choose external components for

V_BUS, D+, and D– short-to-battery protection. For cable-compensation design information, see the data sheet

(SLUSCE3) for the TPS2549-Q1 device, which has features and design considerations very similar to those of

the TPS254900A-Q1 device.

9.2 Typical Application

For an automotive USB charging port, the V_BUS, D+, and D– pins are exposed and require a protection device.

The protection required includes V_BUSovercurrent, D+ and D– ESD protection, and short-to-battery protection.

This charging-port device protects the upstream dc-dc converter (bus line) and automotive SOC or hub chips (D+

and D– data lines). An application schematic of this circuit with short-to-battery protection is shown in 图 43.

10 µF

TPS254900A-Q1

1210

35 V

X7R

5 V

V_BUS

D–

OUT

DM_IN

DP_IN

DM_OUT

DP_OUT

To Host

Controller

D+

GND

FAULT

BIAS

FAULT

2.2 µF

STATUS

0805

50 V

X7R

STATUS

CTL1

Mode

Select I/O

ILIM_LO

ILIM_HI

CTL2

OVP_SEL

Logic I/O

Upstream DC-DC

Converter

GND

ADC

IMON

图 43. Typical Application Schematic: USB Port Charging With Cable Compensation

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

Typical Application (接下页)

9.2.1 Design Requirements

For this design example, use the following as the input parameters.

DESIGN PARAMETER

EXAMPLE VALUE

Battery voltage, V_(BAT)

Short-circuit cable

18 V

0.5 m

9.2.2 Detailed Design Procedure

To begin the design process, the designer must know the following:

•

The battery voltage

The short-circuit cable length

The maximum continuous output current for the charging port. The minimum current-limit setting of

TPS254900A-Q1 device must be higher than this current.

•

The maximum output current of the upstream dc-dc converter. The maximum current-limit setting of

TPS254900A-Q1 device must be lower than this current.

For cable compensation, the total resistance including power switch r_DS(on), cable resistance, and connector

contact resistance must be specified.

9.2.2.1 Input Capacitance

Consider the following application situations when choosing the input capacitors.

For all applications, TI recommends a 0.1-µF or greater ceramic bypass capacitor between IN and GND, placed

as close as possible to the device for local noise decoupling.

During output short or hot plug-in of a capacitive load, high current flows through the TPS254900A-Q1 device

back to the upstream dc-dc converter until the TPS254900A-Q1 device responds (after t_(IOS)). During this

response time, the TPS254900A-Q1 input capacitance and the dc-dc converter output capacitance source

current to keep V_INabove the UVLO of the TPS254900A-Q1 device and any shared circuits. Size the input

capacitance for the expected transient conditions and keep the path between the TPS254900A-Q1 device and

the dc-dc converter short to help minimize voltage drops.

Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input

voltage in conjunction with input power-bus inductance and input capacitance when the IN pin is in the high-

impedance state (before turnon). Theoretically, the peak voltage is 2 times the applied voltage. The second

cause is due to the abrupt reduction of output short-circuit current when the TPS254900A-Q1 device turns off

and energy stored in the input inductance drives the input voltage high. Applications with large input inductance

(for example, a connection between the evaluation board and the bench power supply through long cables) may

require large input capacitance to prevent the voltage overshoot from exceeding the absolute-maximum voltage

of the device.

During the short-to-battery (EN = HIGH) condition, the input voltage follows the output voltage until OVP

protection is triggered (t_{(OV_OUT)}). After the TPS254900A-Q1 device responds and turns off the power switch, the

stored energy in the input inductance can cause ringing.

Based on the three situations described, 10-µF and 0.1-µF low-ESR ceramic capacitors, placed close to the

input, are recommended.

9.2.2.2 Output Capacitance

Consider the following application situations when choosing the output capacitors.

After an output short occurs, the TPS254900A-Q1 device abruptly reduces the OUT current, and the energy

stored in the output power-bus inductance causes voltage undershoot and potentially reverse voltage as it

discharges.

Applications with large output inductance (such as from a cable) benefit from the use of a high-value output

capacitor to control the voltage undershoot.

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

For USB port applications, because the V_BUSpin is exposed to IEC61000-4-2 level-4 ESD, use a low-ESR

capacitance to protect OUT.

The TPS254900A-Q1 device is capable of handling up to 18-V battery voltage. When V_BUSis shorted to the

battery, the LCR tank circuit formed can induce ringing. The peak voltage seen on the OUT pin depends on the

short-circuit cable length. The parasitic inductance and resistance varies with length, causing the damping factor

and peak voltage to differ. Longer cables with larger resistance reduce the peak current and peak voltage.

Consider high-voltage derating for the ceramic capacitor, because the peak voltage can be higher than twice the

battery voltage.

Based on the three situations described, a 10-µF, 35-V, X7R, 1210 low-ESR ceramic capacitor placed close to

OUT is recommended. If the battery voltage is 16 V and a 16-V transient voltage suppressor (TVS) is used, then

the capacitor voltage can be reduced to 25 V. Considering temperature variation, placing an additional 35-V

aluminum electrolytic capacitor can lower the peak voltage and make the system more robust.

9.2.2.3 BIAS Capacitance

The capacitance on the BIAS pin helps the IEC ESD performance on the DM_IN and DP_IN pins.

When a short to battery on DP_IN, DM_IN and/or OUT occurs, high voltage can be seen on the BIAS pin. Place

a 2.2-µF, 50-V, X7R, 0805, low-ESR ceramic capacitor close to the BIAS pin. The whole current path from BIAS

to GND should be as short as possible. Additionally, use a 5.1-kΩ discharge resistor from BIAS to OUT.

9.2.2.4 Output and BIAS TVS

The TPS254900A-Q1 device can withstand high transient voltages due to LCR tank ringing, but in order to make

OUT, DP_IN, and DM_IN robust, place one TVS close to the OUT pin, and another TVS close to the BIAS pin.

When choosing the TVS, the reverse standoff voltage V_Rdepends on the battery voltage (16 V or 18 V).

Considering the peak pulse power capability, a 400-W device is recommended such as an SMAJ16 for a 16-V

battery or an SMAJ18 for an 18-V battery.

9.2.3 Application Curves

V_BAT= 14 V

t = 10 µs/div

V_BAT= 18 V

t = 10 µs/div

图 44. Disabled, 25-V, 1206, X7R C_OUTCapacitor Without

图 45. Disabled, 35-V, 1210, X7R C_OUTCapacitor Without

SMAJ18

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

t = 10 µs/div

图 46. Disabled, 25-V, 1206, X7R C_OUTCapacitor With

图 47. Disabled, 35-V, 1210, X7R C_OUTCapacitor With

SMAJ18, OUT Shorted to Battery

t = 10 µs/div

图 48. DC-DC Input Is Floating, OUT Shorted to Battery

图 49. Enabled With OVP_SEL = High, OUT Shorted to

Battery

t = 10 µs/div

R_BIAS= 5.1 kΩ

t = 2 µs/div

图 50. Enabled With OVP_SEL = Low, OUT Shorted to

图 51. Disabled, DP_IN Shorted to Battery

Battery

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

R_BIAS= 5.1 kΩ

t = 2 µs/div

R_(BIAS)= 5.1 kΩ

t = 2 µs/div

R_{(DP_OUT)}= 15 kΩ

图 52. DC-DC Input Is Floating, DP_IN Shorted to Battery

图 53. Enabled, DP_IN Shorted to Battery

10 Power Supply Recommendations

The TPS254900A-Q1 device is designed for a supply voltage range of 4.5 V ≤ V_IN≤ 6.5 V, with its power switch

used for protecting the upstream power supply when a fault such as overcurrent or short to ground occurs on the

USB port. Therefore, the power supply should be rated higher than the current-limit setting to avoid voltage drops

during overcurrent or short-circuit conditions.

11 Layout

11.1 Layout Guidelines

Layout best practices for the TPS254900A-Q1 device are listed as follows.

•

Considerations for input and output power traces

–

Make the power traces as short as possible.

Make the power traces as wide as possible.

•

Considerations for input-capacitor traces

–

For all applications, 10-µF and 0.1-µF low-ESR ceramic capacitors are recommended, placed close to the

IN pin.

The resistors attached to the ILIM_HI and ILIM_LO pins of the device have several requirements.

–

It is recommended to use 1% low-temperature-coefficient resistors.

The trace routing between these two pins and GND should be as short as possible to reduce parasitic

effects on current limit. These traces should not have any coupling to switching signals on the board.

•

Locate all TPS254900A-Q1 pullup resistors for open-drain outputs close to their connection pin. Pullup

resistors should be 100 kΩ.

–

If a particular open-drain output is not used or needed in the system, tie it to GND.

ESD considerations

–

The TPS254900A-Q1 device has built-in ESD protection for DP_IN and DM_IN. Keep trace lengths

minimal from the USB connector to the DP_IN and DM_IN pins on the TPS254900A-Q1 device, and use

minimal vias along the traces.

The capacitor on BIAS helps to improve the IEC ESD performance. A 2.2-µF capacitor should be placed

close to BIAS, and the current path from BIAS to GND across this capacitor should be as short as

possible. Do not use vias along the connection traces.

–

A 10-µF output capacitor should be placed close to the OUT pin and TVS.

See the ESD Protection Layout Guide (SLVA680) for additional information.

•

TVS Considerations

–

For OUT, a TVS like SMAJ18 should be placed near the OUT pin.

For BIAS, a TVS like SMAJ18 should be placed close to the BIAS pin, but behind the 2.2-µF capacitor.

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

Layout Guidelines (接下页)

–

The whole path from OUT to GND or BIAS to GND across the TVS should be as short as possible.

•

DP_IN, DM_IN, DP_OUT, and DM_OUT routing considerations

–

Route these traces as microstrips with nominal differential impedance of 90 Ω.

Minimize the use of vias on the high-speed data lines.

Keep the reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance

discontinuities.

–

For more USB 2.0 high-speed D+ and D– differential routing information, see the High Speed USB

Platform Design Guideline from Intel.

•

Thermal Considerations

–

When properly mounted, the thermal-pad package provides significantly greater cooling ability than an

ordinary package. To operate at rated power, the thermal pad must be soldered to the board GND plane

directly under the device. The thermal pad is at GND potential and can be connected using multiple vias

to inner-layer GND. Other planes, such as the bottom side of the circuit board, can be used to increase

heat sinking in higher-current applications. See the PowerPad™ Thermally Enhanced Package application

report (SLMA002) and PowerPAD™ Made Easy application brief (SLMA004) for more information on

using this thermal pad package.

TPS254900A-Q1

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

www.ti.com.cn

11.2 Layout Example

Top Layer Signal Trace

Top Layer Signal Ground Plane

Bottom Layer Signal Trace

Via to Bottom layer Signal Ground Plane

Via to Bottom layer Signal

IMON

OUT

Thermal

Pad

DM_IN

DP_IN

BIAS

DM_OUT

DP_OUT

GND

图 54. TPS254900A-Q1 Layout Diagram

TPS254900A-Q1

www.ti.com.cn

ZHCSHG3A –NOVEMBER 2017–REVISED JANUARY 2018

12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.2 文档支持

12.2.1 相关文档

如需相关文档，请参阅：

•

《高速 USB 平台设计指南》，Intel

《TPS254900AQ1EVM-003 评估模块用户指南》(SLVUB94)

《TPS254900Q1EVM-817 评估模块用户指南》(SLUUBI0)

《具有电缆补偿功能的 TPS2549-Q1 汽车类 USB 充电端口控制器和电源开关数据表》(SLUSCE3)

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是适用于指定器件的最新数据。数据如有变更，恕不另行通知和

修订此文档。要获取数据表的浏览器版本，请查看左侧的导航面板。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS254900AIRVCRQ1

TPS254900AIRVCTQ1

ACTIVE

WQFN

RVC

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

25490AQ

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS254900AIRVCRQ1

TPS254900AIRVCTQ1

WQFN

RVC

3000

250

330.0

180.0

12.4

3.3

4.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS254900AIRVCRQ1

TPS254900AIRVCTQ1

WQFN

RVC

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RVC0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

0.45

0.35

4.1

3.9

0.25

0.15

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

2X 1.5

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

16X 0.5

SYMM

2.5

2.6 0.1

SEE TERMINAL

DETAIL

0.25

20X

0.15

PIN 1 ID

(OPTIONAL)

0.1

C A B

1.6 0.1

0.05

0.45

0.35

20X

4219150/B 03/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RVC0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.6)

SYMM

(R0.05)

TYP

20X (0.6)

20X (0.2)

(1)

TYP

(3.8)

(2.6)

SYMM

16X (0.5)

(

0.2) TYP

VIA

(1 TYP)

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219150/B 03/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RVC0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

2X (1.47)

20X (0.6)

20X (0.2)

(R0.05) TYP

SYMM

(1.15)

(3.8)

(0.675)

TYP

16X (0.5)

METAL

TYP

SYMM

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD X

81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219150/B 03/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS254900AIRVCRQ1 [TI]

相关型号：

TPS254900AIRVCTQ1

TPS254900IRVCRQ1

TPS254900IRVCTQ1

TPS2549IRTERQ1

TPS2549IRTETQ1

TPS2549RTER

TPS2549RTET

TPS2550

TPS2550DBV

TPS2550DBVR

TPS2550DBVRG4

TPS2550DBVT