TPS23882B1RTQR_技术文档

TPS23882B

ZHCSNB6A –APRIL 2021 –REVISED FEBRUARY 2022

TPS23882B 带自主模式、SRAM 和200mΩ RSENSE 的3 类、2 线对8 通道PSE

控制器

外部 FET 架构使设计能够平衡尺寸、效率、散热和解

决方案成本要求。

1 特性

• 适用于PoE 2 3 类2 线对以太网供电应用的IEEE

端口重映射以及与 TPS2388 、TPS23880 和

802.3bt PSE 解决方案

TPS23881 的引脚对引脚兼容性可轻松实现上一代

• 与TI 的FirmPSE 系统固件兼容

PSE 设计的迁移，并支持可互换2 层PCB 设计以适应

不同系统PoE 电源配置。

• SRAM 可编程存储器

• 可编程功率限制精度±4%

• 200 mΩ电流感测电阻

器件信息⁽¹⁾

• 用户可选择15W 或30W 自主模式，无需MCU

封装尺寸（标称值）

器件型号

TPS23882B

封装

VQFN (56)

8.00mm x 8.00mm

• 可选的2 线对端口功率分配

– 4W、7W、15.4W 或30W

• 各端口专用的14 位积分电流ADC

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

+3.3

V

+54

V

+54 V

– 用于直流断开的抗噪MPS

– 2% 电流感测精度

2P Port #1

2P Port #5

0.1 uF

100

0.1 uF

RJ45

&

XFrmr

Alt

A

Alt

A

RJ45 & XFrmr

V

VDD

VPWR

100

V

DRAIN1

DRAIN5

GAT5

SEN5

• 1 位或3 位快速端口关断输入

• Auto-class 发现和功率测量

• 可靠的4 点检测

GAT1

SEN1

2P Port #2

2P Port #6

0.200

0.1 uF

100

0.1uF

100V

RJ45

&

XFrmr

Alt

A

V

Alt

A

RJ45 & XFrmr

TPS23882

KSENSEA

KSENSEC

0.200

SEN2

SEN6

GAT6

2P Port #3

2P Port #7

GAT2

DRAIN2

DRAIN6

• 浪涌和操作折返保护

• 425mA 和1.25A 可选电流限值

• 端口重映射

RJ45

&

XFrmr

Alt

A

Alt

A

RJ45 & XFrmr

GND

2P Port #4

2P Port #8

RJ45

&

XFrmr

RJ45 & XFrmr

I2C Bus

• 8 位或16 位I²C 通信

• 灵活的处理器控制运行模式

– 自动、半自动和手动/诊断

• 各端口电压监控和遥测

• -40 °C 至+125 °C 工作温度

简化版原理图

2 应用

• 录像机（NVR、DVR 等）

• 小型企业交换机

• 园区交换机和分支交换机

3 说明

TPS23882B 是一款8 通道电源设备(PSE) 控制器，旨

在按照 IEEE 802.3bt 标准向以太网电缆提供电力。

PSE 控制器可以检测具有有效签名、完全相互识别和

接通电源的供电设备(PD)。

TPS23882B 在 TPS2388 的基础上进行了改进，减小

了电流感测电阻，提供了 SRAM 可编程性、可编程功

率限制、电容测量以及与 TI FirmPSE 系统固件的兼容

性（请参阅器件比较表）。

可编程 SRAM 支持通过 I²C 实现现场固件可升级性，

从而确保 IEEE 合规性以及与支持新 PoE 器件的互操

作性。各端口专用 ADC 可提供持续的端口电流监控和

执行并行分级测量的功能，以实现更快的端口开启速

度。1.25A 端口电流限制和可调节功率限制可支持

60W 以上的非标准应用。 200mΩ 电流感测电阻器和

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSG51

TPS23882B

ZHCSNB6A –APRIL 2021 –REVISED FEBRUARY 2022

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Table of Contents

9.5 I²C Programming...................................................... 30

9.6 Register Maps...........................................................33

10 Application and Implementation..............................107

10.1 Application Information......................................... 107

10.2 Typical Application................................................ 109

11 Power Supply Recommendations............................114

11.1 VDD.......................................................................114

11.2 VPWR....................................................................114

12 Layout.........................................................................115

12.1 Layout Guidelines................................................. 115

12.2 Layout Example.................................................... 116

13 Device and Documentation Support........................117

13.1 Documentation Support........................................ 117

13.2 接收文档更新通知................................................. 117

13.3 支持资源................................................................117

13.4 Trademarks........................................................... 117

13.5 Electrostatic Discharge Caution............................117

13.6 术语表................................................................... 117

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

6.1 Detailed Pin Description..............................................5

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings........................................ 7

7.2 ESD Ratings............................................................... 7

7.3 Recommended Operating Conditions.........................7

7.4 Thermal Information....................................................7

7.5 Electrical Characteristics.............................................8

7.6 Typical Characteristics..............................................14

8 Parameter Measurement Information..........................19

8.1 Timing Diagrams.......................................................19

9 Detailed Description......................................................21

9.1 Overview...................................................................21

9.2 Functional Block Diagram.........................................26

9.3 Feature Description...................................................27

9.4 Device Functional Modes..........................................29

Information.................................................................. 117

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (April 2021) to Revision A (February 2022)

Page

• 将提到I²C 的旧术语实例通篇更改为控制器和目标.............................................................................................1

• Corrected the ESD Ratings charged device model row to show testing was per JS-002.................................. 7

• Updated the Functional Block Diagram ........................................................................................................... 26

• Changed the reset state value for register 0x43...............................................................................................33

• Updated 图12-2 .............................................................................................................................................115

2

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5 Device Comparison Table

表5-1 summarizes the primary differences between the available 2-pair PSE devices.

KEY FEATURES

TPS23880

TPS23881

TPS23882B

Compatible with TI's FirmPSE system

firmware

N/A

Yes

Pin-to-pin compatible

Yes

8

Yes

8

Yes

8

Number of PSE channels

PoE 2

802.3bt Type 3 or 4

(2 or 4 pair)

PoE 2

802.3bt Type 3 or 4

(2 or 4 pair)

PoE 2

802.3bt Type 3 (2 pair)

Supported IEEE 802.3 PSE Types

R_SENSE

0.255 Ω

0.5 W to 54 W

0.5 W to 108 W

±3.0 %

0.200 Ω

2 W to 65 W

4 W to 127 W

±2.5 %

0.200 Ω

2 W to 65 W

N/A

2-pair P_CUTprogrammable ranges

4-pair P_CUTprogrammable ranges

90+ W 4-pair P_CUTaccuracy

N/A

Channel capacitance measurement

range

N/A

1 µF to 12 µF

ULA packaging

No

Yes (TPS23881A)

16 kB

N/A

I²C programmable SRAM memory

16 kB

表5-1. 2-Pair PSE Key Feature Comparisons

KEY FEATURES

TPS23861

TPS2388

TPS23881

TPS23882B

Compatible with TI's FirmPSE

system firmware

N/A

Yes

Pin-to-pin compatible

N/A

4

Yes

8

Yes

8

Yes

8

Number of PSE channels

PoE 2

802.3bt Type 3 or 4

(2 or 4 pair)

Supported IEEE 802.3 PSE

Types

PoE 1

802.3 at Type 1 or 2

PoE 1

802.3 at Type 1 or 2

PoE 2

802.3bt Type 3 (2 pair)

R_SENSE

0.255 Ω

0.200 Ω

N/A

2-pair P_CUTprogrammable

ranges

I_CUTadjustable up to 920 I_CUTadjustable up to 920

2 W to 65 W

mA

T_MPS

15 ms

3 ms

Port current limit (1x / 2x)

425 mA / 1060 mA

425 mA / 1250 mA

Channel capacitance

measurement range

N/A

1 µF to 12 µF

Yes

1 µF to 12 µF

Yes

PD auto-class discovery and

power measurement

I²C programmable SRAM

memory

16 kB

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6 Pin Configuration and Functions

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1

2

GAT1

GAT8

SEN1

DRAIN1

KSENSA

DRAIN2

SEN2

SEN8

3

DRAIN8

KSENSD

DRAIN7

SEN7

4

5

6

7

GAT2

GAT7

Thermal Pad

8

GAT3

GAT6

9

SEN3

SEN6

10

DRAIN3

DRAIN6

KSENSC

KSENSB 11

12

13

14

DRAIN4

SEN4

DRAIN5

SEN5

GAT4

GAT5

图6-1. RTQ Package with Exposed Thermal Pad 56-Pin VQFN Top View

表6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

48–51

21

A1-4

I

I²C A1-A4 address lines. These pins are internally pulled up to VDD.

Analog ground. Connect to GND plane and exposed thermal pad.

Digital ground. Connect to GND plane and exposed thermal pad.

AGND

DGND

—

46

3, 5, 10, 12, 31,

33, 38, 40

DRAIN1-8

GAT1-8

I

Channel 1-8 output voltage monitor

Channel 1-8 gate drive output

1, 7, 8, 14, 29, 35,

36, 42

O

INT

45

O

I

Interrupt output. This pin asserts low when a bit in the interrupt register is asserted. This output is open-drain.

Kelvin point connection for SEN1-4

KSENSA/B

KSENSC/D

4, 11

32, 39

I

Kelvin point connection for SEN5-8

4

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表6-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

No connect pins. These pins are internally biased at 1/3 and 2/3 of VPWR in order to control the voltage

gradient from VPWR. Leave open.

15, 16, 18, 19

O

NC

22, 27, 28

No connect pin. Leave open.

—

OSS

56

44

53

54

I

Channel 1-8 fast shutdown. This pin is internally pulled down to DGND.

Reset input. When asserted low, the TPS23882B is reset. This pin is internally pulled up to VDD.

Serial clock input for I²C bus.

RESET

SCL

SDAI

Serial data input for I²C bus. This pin can be connected to SDAO for non-isolated systems.

Serial data output for I²C bus. This pin can be connected to SDAI for non-isolated systems. This output is open-

drain.

SDAO

AUTO

SEN1-8

55

52

O

I/O Autonomous mode enable and selection pin

Channel 1-8 current sense input

I/O Used internally for test purposes only. Leave open.

2, 6, 9, 13, 30, 34,

37, 41

I

20, 23, 24, 25, 26,

47

TEST0-5

Thermal pad

VDD

The DGND and AGND terminals must be connected to the exposed thermal pad for proper operation.

Digital supply. Bypass with 0.1 µF to DGND pin.

—

43

17

—

VPWR

Analog 54-V positive supply. Bypass with 0.1 µF to AGND pin.

6.1 Detailed Pin Description

The following descriptions refer to the pinout and the functional block diagram.

DRAIN1-DRAIN8: Channels 1-8 output voltage monitor and detect sense. Used to measure the port output

voltage, for port voltage monitoring, port power good detection and foldback action. Detection probe currents

also flow into this pin.

The TPS23882B uses an innovative 4-point technique to provide reliable PD detection and avoids powering an

invalid load. The discovery is performed by sinking two different current levels via the DRAINn pin, while the PD

voltage is measured from VPWR to DRAINn. If prior to starting a new detection cycle the port voltage is > 2.5 V,

an internal 100-kΩresistor is connected in parallel with the port and a 400-ms detect backoff period is applied to

allow the port capacitor to be discharged before the detection cycle starts.

There is an internal resistor between each DRAINn pin and VPWR in any operating mode except during

detection or while the port is ON. If the port n is not used, DRAINn can be left floating or tied to GND.

GAT1-GAT8: Channels 1-8 gate drive outputs are used for external N-channel MOSFET gate control. At port

turn-on, the gate drive outputs are driven positive by a low current source to turn the MOSFET on. GATn is

pulled low whenever any of the input supplies are low or if an overcurrent timeout has occurred. GATn is also

pulled low if the port is turned off by use of manual shutdown inputs. Leave floating if unused.

For improved design robustness, the current foldback functions limit the power dissipation of the MOSFET

during low resistance load or short-circuit events and during the inrush period at port turn on. There is also fast

overload protection comparator for major faults like a direct short that forces the MOSFET to turn off in less than

a microsecond.

The circuit leakage paths between the GATn pin and any nearby DRAINn pin, GND or Kelvin point connection

must be minimized (< 250 nA), to ensure correct MOSFET control.

INT: This interrupt output pin asserts low when a bit in the interrupt register is asserted. This output is open-

drain.

KSENSA, KSENSB, KSENSC, KSENSD: Kelvin point connection used to perform a differential voltage

measurement across the associated current sense resistors.

Each KSENS is shared between two neighbor SEN pins as following: KSENSA with SEN1 and SEN2, KSENSB

with SEN3 and SEN4, KSENSC with SEN5 and SEN6, KSENSD with SEN7 and SEN8. To optimize the

measurement accuracy, ensure proper PCB layout practices are followed.

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OSS: Fast shutdown, active high. This pin is internally pulled down to DGND, with an internal 1-µs to 5-µs

deglitch filter.

The turn-off procedure is similar to a port reset using reset command (1Ah register). The 3-bit OSS function

allows for a series of pulses on the OSS pin to turn off individual or multiple ports with up to eight levels of

priority.

RESET: Reset input, active low. When asserted, the TPS23882B resets, turning off all ports and forcing the

registers to their power-up state. This pin is internally pulled up to VDD, with internal 1-µs to 5-µs deglitch filter.

The designer can use an external RC network to delay the turn-on. There is also an internal power-on-reset

which is independent of the RESET input.

SCL: Serial clock input for I²C bus.

SDAI: Serial data input for I²C bus. This pin can be connected to SDAO for non-isolated systems.

SDAO: Open-drain I²C bus output data line. Requires an external resistive pullup. The TPS23882B uses

separate SDAO and SDAI lines to allow optoisolated I²C interface. SDAO can be connected to SDAI for non-

isolated systems.

AUTO: Autonomous mode selection pin: Floating this pin disables autonomous operation. Tying this pin to GND

through a resistor (R_AUTO) enables autonomous operation at selectable port power allocation levels. A 10-nF

capacitor is required between the AUTO pin and GND if R_AUTOis connected.

A4-A1: I²C bus address inputs. These pins are internally pulled up to VDD. See 节9.6.2.13 for more details.

SEN1-8: Channel current sense input relative to KSENSn (see KSENSn description). A differential measurement

is performed using KSENSA-D Kelvin point connection. Monitors the external MOSFET current by use of a

0.200-Ω current sense resistor connected to GND. Used by current foldback engine and also during

classification. Can be used to perform load current monitoring via ADC conversion.

When the TPS23882B performs the classification measurements, the current flows through the external

MOSFETs. This flow avoids heat concentration in the device and makes it possible for the TPS23882B to

perform classification measurements on multiple ports at the same time. For the current limit with foldback

function, there is an internal 2-µS analog filter on the SEN1-8 pins to provide glitch filtering. For measurements

through an ADC, an anti-aliasing filter is present on the SEN1-8 pins. This includes the port-powered current

monitoring, port policing, and DC disconnect.

If the port is not used, tie SENn to GND.

VDD: 3.3-V logic power supply input.

VPWR: High voltage power supply input. Nominally 54 V.

AGND and DGND: Ground references for internal analog and digital circuitry respectively. Not connected

together internally. Both pins require a low resistance path to the system GND plane. If a robust GND plane is

used to extract heat from the device's thermal pad, these pins can be connected together through the thermal

pad connection on the pcb.

6

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

70

4

UNIT

V

VPWR

–0.3

VDD

V

OSS, RESET, A1-A4

SDAI, SDAO, SCL, INT

4

V

4

V

Voltage

SEN1-8, KSENSA, KSENSB, KSENSC, KSENSD

3

V

GATE1-8

13

70

0.3

20

260

150

V

DRAIN1-8

AGND-GDND

INT, SDA

V

Sink Current

mA

°C

Lead Temperature 1/6mm from case for 10 seconds

T_stgStorage temperature

–65

(1) Stresses beyond those listed underAbsolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/JEDEC

JS-002, all pins⁽²⁾

± 500

(1) JEDEC documentJEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC documentJEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3

NOM

3.3

MAX

3.6

57

UNIT

V

V_VDD

V_VPWR

44

54

V

Voltage slew rate on VPWR

I²C clock frequency

1

V/µs

kHz

°C

f_SCL

T_J

400

125

Junction temperature

–40

7.4 Thermal Information

TPS23882B

THERMAL METRIC⁽¹⁾

RTQ Package (VQFN)

UNIT

56 PINS

25.3

9.7

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

3.7

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Ψ_JT

3.7

Ψ_JB

R_θJC(bot)

0.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.5 Electrical Characteristics

Conditions are –40 < T_J< 125 °C unless otherwise noted.V_VDD= 3.3 V,V_VPWR= 54 V, V_DGND= V_AGND,DGND, KSENSA,

KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn =0. Positive currents are into

pins. R_S= 0.200 Ω, to KSENSA (SEN1 orSEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD

(SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted. Operating

registers loaded with default values unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY VPWR

I_VPWR

VPWR Current consumption

VVPWR = 54 V

10

12.5

17.5

18.5

28

mA

V

V_{UVLOPW_F}

V_{UVLOPW_R}

V_{PUV_F}

VPWR UVLO falling threshold

VPWR UVLO rising threshold

VPWR Undervoltage falling threshold

Check internal oscillator stops operating

14.5

15.5

25

V

VPUV threshold

26.5

V

INPUT SUPPLY VDD

I_VDD

VDD Current consumption

6

2.25

2.6

12

2.4

mA

V

V_{UVDD_F}

V_{UVDD_R}

V_{UVDD_HYS}

V_{UVW_F}

VDD UVLO falling threshold

VDD UVLO rising threshold

Hysteresis VDD UVLO

For channel deassertion

VDD falling

2.1

2.45

2.75

V

0.35

2.8

V

VDD UVLO warning threshold

2.6

3

V

A/D CONVERTERS

T_{CONV_I}

Conversion time

All ranges, each channel

0.64

0.82

0.8

1.03

102

0.96

1.2

122

20

ms

T_{CONV_V}

T_{INT_CUR}

T_{INT_DET}

T_{INT_channelV}

T_{INT_inV}

Conversiontime

All ranges, each channel

Integration time, Current

Integration time, Detection

Integration time, Channel Voltage

Integration time, Input Voltage

Each channel, channel ON current

82

13.1

16.6

4.12

15565

57

channel powered

3.25

4.9

3.25

15175

55.57

11713

42.89

15175

55.57

11713

42.89

–2.5

8431

754.5

1084

97

15955 Counts

58.43

12316 Counts

45.10

15955 Counts

58.43

12316 Counts

VVPWR = 57 V

V

Input voltage conversion scale factor and

accuracy

12015

44

VVPWR = 44 V

V

15565

57

VVPWR - VDRAINn = 57 V

VVPWR - VDRAINn = 44 V

V

Powered Channel voltage conversion scale

factor and accuracy

12015

44

45.10

2.5

V

Voltage reading accuracy

%

δV/V_Channel

8604

770

8776 Counts

785.4 mA

1152 Counts

Channel current = 770 mA

Channel Current = 100 mA

Powered Channel current conversion scale

factor and accuracy

1118

100

103

3

mA

Channel Current = 100 mA

Channel Current = 770 mA

–3

Current reading accuracy

%

δI/I_Channel

2

–2

15 kΩ≤R_Channel≤33 kΩ, C_Channel≤0.25

µF

Resistance reading accuracy

Sense Pin bias current

7

0

%

δR/R_Channel

–7

I_bias

Channel ON or during class

µA

–2.5

8

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7.5 Electrical Characteristics (continued)

Conditions are –40 < T_J< 125 °C unless otherwise noted.V_VDD= 3.3 V,V_VPWR= 54 V, V_DGND= V_AGND,DGND, KSENSA,

KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn =0. Positive currents are into

pins. R_S= 0.200 Ω, to KSENSA (SEN1 orSEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD

(SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted. Operating

registers loaded with default values unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GATE 1-8

V_GOH

Gate drive voltage

10

60

12.5

190

V

V_GATEn, I_GATE= –1 µA

Gate sinking current with Power-on Reset,

OSS detected or channel turnoff command

I_GO-

V_GATEn= 5 V

100

mA

V_GATEn= 5 V,

V_SENn≥V_short(or V_short2Xif 2X mode)

I_{GO short-}

I_GO+

Gate sinking current with channel short-circuit

Gate sourcing current

60

39

1

100

50

190

63

5

mA

µA

µs

V_GATEn= 0 V, default selection

From OSS to VGATEn < 1 V,

VSENn = 0 V, MbitPrty = 0

t_{D_off_OSS}

Gate turnoff time from 1-bit OSS input

From Start bit falling edge to VGATEn < 1 V,

VSENn = 0 V, MbitPrty = 1

t_{OSS_OFF}

t_{P_off_CMD}

t_{P_off_RST}

Gate turnoff time from 3-bit OSS input

72

104

300

5

µs

Gate turnoff time from channel turnoff

command

From Channel off command (POFFn = 1) to

V_GATEn< 1 V, V_SENn= 0 V

From /RESET low to V_GATEn< 1 V, V_SENn= 0

V

Gate turnoff time with /RESET

1

DRAIN 1-8

V_PGT

Power-Good threshold

Shorted FET threshold

Measured at V_DRAINn

1

4

2.13

6

3

8

V

V_SHT

Any operating mode except during detection

or while the Channel is ON, including in

device RESET state

R_DRAIN

Resistance from DRAINn to VPWR

80

100

190

kΩ

AUTOCLASS

t_{Class_ACS}

Start of Autoclass Detection

Measured from the start of Class

Measured from the end of Inrush

90

100

1.6

ms

s

1.4

t_{AUTO_PSE1}

Start of Autoclass Power Measurement

Measured from setting the MACx bit while

channel is already powered

10

1.9

0.3

ms

s

t_AUTO

Duration of Autoclass Power Measurement

1.7

1.8

Autoclass Power Measurement Sliding

Window

t_{AUTO_window}

0.15

s

VPWR = 52 V, VDRAINn = 0 V,

Channel current = 770 mA

76

9

80

10

84 Counts

11

Autoclass Channel Power conversion scale

factor and accuracy

P_AC

VPWR = 50 V, VDRAINn = 0 V,

Channel current = 100 mA

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7.5 Electrical Characteristics (continued)

Conditions are –40 < T_J< 125 °C unless otherwise noted.V_VDD= 3.3 V,V_VPWR= 54 V, V_DGND= V_AGND,DGND, KSENSA,

KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn =0. Positive currents are into

pins. R_S= 0.200 Ω, to KSENSA (SEN1 orSEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD

(SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted. Operating

registers loaded with default values unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DETECTION

First and 3rd detection points

VVPWR –VDRAINn = 0 V

145

235

160

270

190

300

I_DISC

Detection current

µA

2nd and 4th detection points VVPWR –

VDRAINn = 0 V

VVPWR - VDRAINn = 0 V

98

23.5

0.86

33

110

26

118

29

µA

V

ΔI_DISC

V_{det_open}

R_{REJ_LOW}

R_{REJ_HI}

R_ACCEPT

R_SHORT

R_OPEN

2nd –1st detection currents

Open circuit detection voltage

Rejected resistance low range

Rejected resistance high range

Accepted resistance range

Shorted Channel threshold

Open Channel Threshold

Detection Duration

Measured as VVPWR –VDRAINn

15

kΩ

Ω

100

26.5

360

19

25

400

275

300

20

kΩ

ms

t_DET

Time to complete a detection

VVPWR –VDRAINn > 2.5 V

VVPWR –VDRAINn < 2.5 V

350

400

425

500

100

Detect backoff pause between discovery

attempts

t_{DET_BOFF}

From command or PD attachment to Channel

detection complete

t_{DET_DLY}

Detection delay

590

ms

uF

Capacitance Measurement

Cport = 10uF

8.5

10

11.5

CLASSIFICATION

V_CLASS

VVPWR –VDRAINn, VSENn ≥0 mV

Classification Voltage

15.5

18.5

75

20.5

V

I_channel≥180 µA

I_{CLASS_Lim}

Classification Current Limit

65

5

90

8

mA

ms

VVPWR –VDRAINn = 0 V

Class 0-1

Class 1-2

13

21

31

45

95

6.5

16

25

35

51

105

12

I_{CLASS_TH}

Classification Threshold Current

Class 2-3

Class 3-4

Class 4-Class overcurrent

From detection complete

From Mark complete

t_LCE

Classification Duration (1st Finger)

t_CLE2/3

MARK

Classification Duration (2nd & 3th Finger)

4 mA ≥I_Channel≥180 µA

VVPWR –VDRAINn

V_MARK

Mark Voltage

7

10

V

I_{MARK_Lim}

t_ME

Mark Sinking Current Limit

Mark Duration

60

6

75

90

12

mA

ms

VVPWR –VDRAINn = 0 V

10

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7.5 Electrical Characteristics (continued)

Conditions are –40 < T_J< 125 °C unless otherwise noted.V_VDD= 3.3 V,V_VPWR= 54 V, V_DGND= V_AGND,DGND, KSENSA,

KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn =0. Positive currents are into

pins. R_S= 0.200 Ω, to KSENSA (SEN1 orSEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD

(SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted. Operating

registers loaded with default values unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC DISCONNECT

V_IMIN

t_MPDO

t_MPS

DC disconnect threshold

0.8

320

75

1.3

1.8

400

100

200

800

3

mV

ms

TMPDO = 00

TMPDO = 01

TMPDO = 10

TMPDO = 11

PD Maintain Power signature dropout time

limit

150

600

PD Maintain Power Signature time for validity

2.5

PORT POWER POLICING

PCUT tolerance

< 15 W

0

6

4

12

8

%

δP_CUT/P_CUT

PCUT tolerance

≥15 W

TOVLD = 00

TOVLD = 01

TOVLD = 10

TOVLD = 11

50

70

25

35

t_OVLD

PCUT time limit

ms

100

200

140

280

PORT CURRENT INRUSH

19

33

80

19

36

53

80

50

25

100

30

44

41

55

90

41

58

75

90

70

35

140

VVPWR –VDRAINn = 1 V

VVPWR –VDRAINn = 10 V

VVPWR –VDRAINn = 15 V

VVPWR –VDRAINn = 30 V

VVPWR –VDRAINn = 55 V

VVPWR –VDRAINn = 1 V

VVPWR –VDRAINn = 10 V

VVPWR –VDRAINn = 15 V

VVPWR –VDRAINn = 30 V

VVPWR –VDRAINn = 55 V

TSTART = 00

IInrush limit, ALTIRNn = 0

V_Inrush

mV

30

47

64

IInrush limit, ALTIRNn = 1

t_START

Maximum current limit duration in start-up

TSTART = 01

ms

TSTART = 10

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7.5 Electrical Characteristics (continued)

Conditions are –40 < T_J< 125 °C unless otherwise noted.V_VDD= 3.3 V,V_VPWR= 54 V, V_DGND= V_AGND,DGND, KSENSA,

KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn =0. Positive currents are into

pins. R_S= 0.200 Ω, to KSENSA (SEN1 orSEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD

(SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted. Operating

registers loaded with default values unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PORT CURRENT FOLDBACK

VDRAINn = 1 V

80

51

23

80

45

23

245

164

51

23

245

139

45

23

55

15

10

6

90

65

37

90

57

37

262

196

64

37

262

155

57

37

65

17

12

7

VDRAINn = 15 V

VDRAINn = 30 V

VDRAINn = 50 V

VDRAINn = 1 V

VDRAINn = 25 V

VDRAINn = 40 V

VDRAINn = 50 V

VDRAINn = 1 V

VDRAINn = 10 V

VDRAINn = 30 V

VDRAINn = 50 V

VDRAINn = 1 V

VDRAINn = 20 V

VDRAINn = 40 V

VDRAINn = 50 V

2xFBn = 0

ILIM 1X limit, 2xFB = 0 and ALTFBn = 0

ILIM 1X limit, 2xFB = 0 and ALTFBn = 1

ILIM 2X limit, 2xFB = 1 and ALTFBn = 0

58

30

V_LIM

mV

51

30

250

180

58

30

V_LIM2X

mV

250

147

51

ILIM 2X limit, 2xFB = 1 and ALTFBn = 1

ILIM time limit

30

60

TLIM = 00

60

t_LIM

TLIM = 01

16

ms

2xFBn = 1

TLIM = 10

11

TLIM = 11

6.5

SHORT CIRCUIT DETECTION

I_SHORTthreshold in 1X mode and during

inrush

V_short

205

280

245

320

0.9

mV

µs

V_short2X

I_SHORTthreshold in 2X mode

2xFBn = 0, VDRAINn = 1 V

From VSENn pulsed to 0.425 V.

t_{D_off_SEN}

Gate turnoff time from SENn input

2xFBn = 1, VDRAINn = 1 V

From VSENn pulsed to 0.62 V.

0.9

CURRENT FAULT RECOVERY (BACKOFF) TIMING

Error delay timing. Delay before next attempt

t_ed

to power a channel following power removal

due to error condition

P_CUT, I_LIMor I_Inrushfault semiauto mode

0.8

5.5

1

1.2

6.7

s

Duty cycle of I_channelwith current fault

%

δI_fault

THERMAL SHUTDOWN

Shutdown temperature

Temperature rising

135

146

7

°C

Hysteresis

12

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7.5 Electrical Characteristics (continued)

Conditions are –40 < T_J< 125 °C unless otherwise noted.V_VDD= 3.3 V,V_VPWR= 54 V, V_DGND= V_AGND,DGND, KSENSA,

KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn =0. Positive currents are into

pins. R_S= 0.200 Ω, to KSENSA (SEN1 orSEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD

(SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted. Operating

registers loaded with default values unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL I/O (SCL, SDAI, A1-A4, /RESET, OSS unless otherwise stated)

V_IH

Digital input High

2.1

V

V_IL

Digital input Low

0.9

V_{IT_HYS}

Input voltage hysteresis

Digital output Low

0.17

V

SDAO at 9mA

0.4

80

V

V_OL

Digital output Low

/INT at 3mA

V

R_pullup

Pullup resistor to VDD

Pulldown resistor to DGND

/RESET, A1-A4, TEST0

OSS, TEST1, TEST2

30

50

kΩ

R_pulldown

80

Time to internally register an Interrupt fault,

from Channel turn off

t_{FLT_INT}

Fault to /INT assertion

50

500

µs

T_RESETmin

T_{bit_OSS}

/RESET input minimum pulse width

3-bit OSS bit period

5

µs

MbitPrty = 1

24

48

25

50

26

Idle time between consecutive shutdown code

transmission in 3-bit mode

t_{OSS_IDL}

µs

t_{r_OSS}

t_{f_OSS}

Input rise time of OSS in 3-bit mode

Input fall time of OSS in 3-bit mode

1

300

ns

0.8 V →2.3 V, MbitPrty = 1

2.3 V →0.8 V, MbitPrty = 1

I2C TIMING REQUIREMENTS

t_PORDevice power-on reset delay

f_SCL

t_LOW

t_HIGH

20

ms

kHz

µs

SCL clock frequency

10

0.5

400

LOW period of the clock

HIGH period of the clock

0.26

µs

SDAO, 2.3 V →0.8 V, Cb = 10 pF, 10 kΩ

pull-up to 3.3 V

10

50

ns

t_fo

SDAO output fall time

SDAO, 2.3 V →0.8 V, Cb = 400 pF, 1.3 kΩ

pull-up to 3.3 V

C_I2C

SCL capacitance

10

6

pF

ns

C_{I2C_SDA}

t_SU,DATW

t_HD,DATW

t_HD,DATR

t_fSDA

SDAI, SDAO capacitance

Data setup tme (Write operation)

Data hold time (Write operation)

Data hold time (Read operation)

Input fall times of SDAI

50

0

150

20

400

120

2.3 V →0.8 V

0.8 V →2.3 V

2.3 V →0.8 V

t_rSDA

Input rise times of SDAI

Input rise time of SCL

t_r

t_f

Input fall time of SCL

Bus free time between a STOP and START

condition

t_BUF

0.5

µs

t_HD,STA

t_SU,STA

t_SU,STO

t_DG

Hold time After (Repeated) START condition

Repeated START condition setup time

STOP condition setup time

0.26

50

µs

Suppressed spike pulse width, SDAI and SCL

I2C Watchdog trip delay

ns

t_{WDT_I2C}

1.1

2.2

3.3

sec

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7.6 Typical Characteristics

Conditions are –40 < T_J< 125 °C unless otherwise noted.V_VDD= 3.3 V, V_VPWR= 54 V, V_DGND= V_AGND, DGND, KSENSA,

KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn = 0. Positive currents are into

pins. R_S= 0.200 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to

KSENSD (SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted.

Operating registers loaded with default values unless otherwise noted.

9.8

9.6

9.4

9.2

9

19

18.5

18

VUVLO_Falling

VUVLO_Rising

17.5

17

8.8

8.6

8.4

8.2

8

16.5

16

7.8

7.6

7.4

7.2

7

15.5

15

14.5

14

6.8

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

D002

图7-1. VPWR Current Consumption vs Temperature

图7-2. VPWR UVLO Thresholds vs Temperature

30

6

VPUV_Falling

VPUV_Rising

29.4

5.75

28.8

28.2

27.6

27

5.5

5.25

5

4.75

4.5

4.25

4

26.4

25.8

25.2

24.6

24

3.75

3.5

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D003

D004

图7-3. VPUV Thresholds vs Temperature

图7-4. VDD Current Consumption vs Temperature

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2

0.2

VDUV_Falling

VDUV_Rising

Classification

Port On

Port Off

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

-1.1

-1.2

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D005

D006

图7-5. VDUV Thresholds vs Temperature

图7-6. SENSE Pin Bias Current vs Temperature

14

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7.6 Typical Characteristics (continued)

Conditions are –40 < T_J< 125 °C unless otherwise noted.V_VDD= 3.3 V, V_VPWR= 54 V, V_DGND= V_AGND, DGND, KSENSA,

KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn = 0. Positive currents are into

pins. R_S= 0.200 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to

KSENSD (SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted.

Operating registers loaded with default values unless otherwise noted.

320

34

Idiscovery_low

Idiscovery_high

300

30

280

26

260

22

18

14

10

6

240

220

200

180

160

140

120

15 kW

19 kW

26.5 kW

33 kW

2

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D008

D007

图7-8. Discovery Resistance Measurement vs Temperature

图7-7. Discovery Currents vs Temperature

26

25.8

25.6

25.4

25.2

25

19.5

-40 èC

25 èC

19.4

19.3

19.2

19.1

19

125 èC

18.9

18.8

18.7

18.6

18.5

18.4

18.3

18.2

18.1

18

24.8

24.6

24.4

24.2

24

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D009

0

5

10 15 20 25 30 35 40 45 50 55

I_CLASS(mA)

图7-9. Discovery Open Circuit Voltage vs Temperature

D010

图7-10. Classification Voltage vs I_CLASSand Temperature

9.5

78

-40 èC

Class I_LIM

Mark I_LIM

9.4

77.2

25 èC

125 èC

9.3

76.4

75.6

74.8

74

9.2

9.1

9

8.9

8.8

8.7

8.6

8.5

73.2

72.4

71.6

70.8

70

0

0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6

I_MARK(mA)

4

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D011

D012

图7-11. Mark Voltage vs I_MARKand Temperature

图7-12. Classification and Mark Current Limit vs Temperature

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7.6 Typical Characteristics (continued)

Conditions are –40 < T_J< 125 °C unless otherwise noted.V_VDD= 3.3 V, V_VPWR= 54 V, V_DGND= V_AGND, DGND, KSENSA,

KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn = 0. Positive currents are into

pins. R_S= 0.200 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to

KSENSD (SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted.

Operating registers loaded with default values unless otherwise noted.

2.4

2.34

2.28

2.22

2.16

2.1

11.6

11.58

11.56

11.54

11.52

11.5

11.48

11.46

11.44

11.42

11.4

2.04

1.98

1.92

1.86

1.8

11.38

11.36

11.34

11.32

11.3

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D013

D014

图7-13. Power Good Threshold vs Temperature

57.5

图7-14. Gate Voltage (Port On) vs Temperature

57.5

57.4

57.3

57.2

57.1

57

57.4

57.3

57.2

57.1

57

56.9

56.8

56.7

56.6

56.5

56.9

56.8

56.7

56.6

56.5

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (è C)

Temperature (èC)

D015

D016

图7-15. Port Voltage ADC Measurement vs Temperature

图7-16. VPWR Voltage ADC Measurement vs Temperature

101

100.9

100.8

100.7

100.6

100.5

100.4

100.3

100.2

100.1

100

780

779

778

777

776

775

774

773

772

771

770

769

768

767

766

765

99.9

99.8

99.7

99.6

99.5

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D017

D018

图7-17. Port Current ADC Measurement (100mA) vs

图7-18. Port Current ADC Measurement (770mA) vs

Temperature

16

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7.6 Typical Characteristics (continued)

Conditions are –40 < T_J< 125 °C unless otherwise noted.V_VDD= 3.3 V, V_VPWR= 54 V, V_DGND= V_AGND, DGND, KSENSA,

KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn = 0. Positive currents are into

pins. R_S= 0.200 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to

KSENSD (SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted.

Operating registers loaded with default values unless otherwise noted.

1.01

1.009

1.008

1.007

1.006

1.005

1.004

1.003

1.002

1.001

1

32

31.8

31.6

31.4

31.2

31

30.8

30.6

30.4

30.2

30

0.999

0.998

0.997

0.996

0.995

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D019

D020

图7-19. Port Current ADC Measurement (1 A) vs Temperature

图7-20. PCut Threshold (30W) vs Temperature

426

425.2

424.4

423.6

422.8

422

2xFBn = 0

2xFBn = 1

425.2

424.4

423.6

422.8

422

421.2

420.4

419.6

418.8

418

421.2

420.4

419.6

418.8

418

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D023

D024

图7-21. Inrush Current Limit vs Temperature

图7-22. 1x Mode (2xFBn = 0) Current Limit vs Temperature

1.25

1.249

1.248

1.247

1.246

1.245

1.244

1.243

1.242

1.241

1.24

1.75

2xFBn = 0

2xFBn = 1

1.7

1.65

1.6

1.55

1.5

1.45

1.4

1.35

1.3

1.25

1.2

1.15

1.1

1.05

1

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D025

D026

图7-23. 2x Mode (2xFBn = 1) Current Limit vs Temperature

图7-24. I_SHORTThreshold vs Temperature

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7.6 Typical Characteristics (continued)

Conditions are –40 < T_J< 125 °C unless otherwise noted.V_VDD= 3.3 V, V_VPWR= 54 V, V_DGND= V_AGND, DGND, KSENSA,

KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn = 0. Positive currents are into

pins. R_S= 0.200 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to

KSENSD (SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted.

Operating registers loaded with default values unless otherwise noted.

112

111

110

109

108

107

106

105

104

103

102

101

100

0.55

0.5

ALTIRn = 0

ALTIRn = 1

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

-40

-20

0

20

40

60

80

100 120 140

0

6

12

18

24 30

V_PORT(V)

36

42

48

54

Temperature (èC)

D027

D028

图7-25. R_OFF(VPWR to DRAIN) vs Temperature

0.55

图7-26. Inrush Current Foldback vs Port Voltage

1.3

1.2

1.1

1

2xFBn =0, ALTFBn = 0

2xFBn =0, ALTFBn = 1

2xFBn =1, ALTFBn = 0

2xFBn =1, ALTFBn = 1

0.5

0.45

0.4

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.35

0.3

0.25

0.2

0.15

0.1

0

6

12

18

24 30

V_DRAIN(V)

36

42

48

54

0

6

12

18

24 30

V_DRAIN(V)

36

42

48

54

D029

D030

图7-27. 1x Mode (2xFBn = 0) Current Foldback vs Drain Voltage 图7-28. 2x Mode (2xFBn = 1) Current Foldback vs Drain Voltage

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8 Parameter Measurement Information

8.1 Timing Diagrams

t_rSDA

SDAI/

SDAO

t_fSDA

t_fo

t_BUF

t_SU,DAT

t_f

t_r

t_LOW

SCL

t_HIGH

t_SU,STO

t_HD,DAT

t_SU,STA

t_HD,STA

Stop Condition

Start Condition

Repeated

Start Condition

图8-1. I²C Timings

SPACE

V_LIM

V_CUT

SEN

0 V

GATE

t_OVLD

图8-2. Overcurrent Fault Timing

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Port turn-on

Class

V_CLASS

Four-point

detection

V_MARK

Mark

V_PORT

0 V

t_CLE-1

t_pon

图8-3. 2-Pair Detection, 1-Event Classification and Turn On

t_DET

SPACE

Port turn-on

Class

V_CLASS

Four-point

detection

V_MARK

Mark

V_PORT

0 V

t_CLE-1

t_ME

t_DET

t_CLE

t_pon

图8-4. 2-Pair Detection, 3-Event Classification and Turn-On

SPACE

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9 Detailed Description

9.1 Overview

The TPS23882B is an eight-channel PSE for Power over Ethernet applications. Each of the eight channels

provides detection, classification, protection, and shutdown in compliance with the IEEE 802.3bt standard.

Basic PoE features include the following:

• Performs high-reliability 4-point load detection

• Performs multi-finger classification including the 100-ms long first class finger for autoclass discovery and to

identify as a 802.3bt complainant PSE

• Enables power with protective foldback current limiting and an adjustable P_CUTthreshold

• Shuts down during faults such as overcurrent or outputs shorts

• Performs a maintain power signature function to ensure power is removed if the load is disconnected

• Undervoltage lockout occurs if VPWR falls below V_{PUV_F}(typical 26.5 V)

Enhanced features include the following:

• Programmable SRAM memory

• Dedicated 14-bit integrating current ADCs per port

• Port re-mapping capability

• 8- and 16-bit access mode selectable

• 1- and 3-bit port shutdown priority

9.1.1 Operating Modes

9.1.1.1 Auto

The port performs detection and classification (if valid detection occurs) continuously. Registers are updated

each time a detection or classification occurs. The port power is automatically turned on based on the Power

Allocation settings in register 0x29 if a valid classification is measured.

9.1.1.2 Autonomous

Unlike auto mode, which still requires a host to initialize the TPS23882B operation through a series of I²C

commands, there is no host or I²C communication required when the device is in configured in autonomous

mode.

During power up, the resistance on the AUTO pin (R_AUTO) is measured, and the device is pre-configured

according to 表 9-15. The port automatically performs detection and classification (if valid detection occurs)

continuously on all ports. Port power is automatically turned on based on power allocation settings in register

0x29 if a valid classification is measured.

For applications that still require port telemetry, the I²C functionality is still supported in autonomous mode.

备注

A 10-nF capacitor is required in parallel with R_AUTOto ensure stability in the autonomous mode

selection.

The auto pin resistance (R_AUTO) is measured following a device reset (assertion of the RESET pin or

RESAL bit in register 0x1A). The device only measures (R_AUTO) and pre-configures the internal

registers during power up (V_VPWRand V_VDDrising above their respective UVLO thresholds).

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备注

The device SRAM must be programmed to support applications that desire to remove a device from

autonomous mode after having initially powered up in autonomous mode.

A device running from the internal ROM (SRAM unprogrammed) in autonomous mode turns off and

automatically resume discovery and power on any valid loads following the assertion of the RESET

pin, I2C register 0x1A RESAL or RESPn bits, or a mode off command. Whereas a device running in

autonomous mode with the SRAM programmed turns off and remains inactive until the host re-

enables the ports through the I²C bus.

9.1.1.3 Semiauto

The port performs detection and classification (if valid detection occurs) continuously. Registers are updated

each time a detection or classification occurs. The port power is not automatically turned on. A Power Enable

command is required to turn on the port.

9.1.1.4 Manual and Diagnostic

The use of this mode is intended for system diagnostic purposes only in the event that ports cannot be powered

in accordance with the IEEE 802.3bt standard from semiauto or auto modes.

The port performs the functions as configured in the registers. There is no automatic state change. Singular

detection and classification measurements are performed when commanded. Ports are turned on immediately

after a Power Enable command without any detection or classification measurements. Even though multiple

classification events can be provided, the port voltage resets immediately after the last finger, resetting the PD.

9.1.1.5 Power Off

The port is powered off and does not perform a detection, classification, or power-on. In this mode, status and

enable bits for the associated port are reset.

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9.1.2 PoE Compliance Terminology

With the release of the IEEE 802.3bt standard, compliant PoE equipment has expanded to include four different

Types of devices that support power over 2 pair or 4 pair, in either single or dual signature configurations, with

classifications ranging from 0 to 8. Different manufactures have used varying terminology over time to describe

their equipment capabilities, and it can become difficult to identify how to correctly categorize and brand a

particular piece of equipment. For this reason and in conjunction with the Ethernet Alliance (EA), the industry

leading providers of PoE equipment and devices have agreed to transition to using the "PoE 1" and "PoE 2"

banding per 表9-1 below.

SPACE

表9-1. Summary Table of PoE Compliance Terminology

Brand,

Acronym

IEEE

Standard

Clause

Clause Title

Types

Classes

EA Certified Logo

802.3af

802.3at

1

2

0 - 3

0 - 4

Power over Ethernet over 2

pairs

PoE 1

PoE 2

33

Gen 1 Class 1-4

1 - 6, or 1-4

DS⁽¹⁾

3

4

802.3bt

145

Power over Ethernet

Gen 2 Class 1-8

7 - 8, or 5

DS⁽¹⁾

(1) "DS" is used to designate "Dual Signature" PDs.

备注

By design PoE 2 PSEs are fully interoperable with any existing PoE 1 equipment, and although not all

functionality may be enabled, PoE 2 PDs connected to PoE 1 PSEs are required to limit their power

consumption to the PSE presented power capabilities. See Power Allocation and Power Demotion.

9.1.3 PoE 2 Type-3 2-Pair PoE

Upon release of the new IEEE 802.3bt standard, the IEEE introduced two new "Types" of PoE equipment. The

addition of Type-3 and Type-4 equipment are most commonly associated with the addition of 4-Pair PoE and

their available power increases of to up to 90 W sourced from a PSE port. However, the new PoE 2 Type-3

designation also applies to new 2-Pair PoE equipment as well. Most notably, the new 802.3bt standard supports

a reduced T_MPStime (6 ms versus 60 ms) and a new feature called Autoclass, and by definition any device that

supports these new features is designated as Type-3 equipment even if power is only provided over 2 pairs (one

alternative pairset) in an Ethernet cable. Because the TPS23882B supports these new features including its use

of the 100-ms long first class finger to identify itself as an IEEE 802.3bt PSE, it is officially classified as a Type-3

PSE even through power delivery is limited to 2 pair.

Please note that as the 802.3at standard created "Type-2" equipment that was fully interoperable with the

previous PoE 1 Type-1 (802.3af) equipment, any new 802.3bt Type-3 equipment including the TPS23882B is

fully operable with any existing PoE 1 Type-1 (.af) and Type-2 (.at) equipment.

SPACE

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9.1.4 Requested Class Versus Assigned Class

The requested class is the classification the PSE measures during mutual identification prior to turn-on, whereas

the assigned class is the classification level the channel was powered on with based on the power allocation

setting in register 0x29h. In most cases where the power allocation equals or exceeds the requested class, the

requested and assigned classes is the same. However, in the case of power demotion, these values differ.

For example: If a 4-pair Class 8 PD is connected to a 30-W (Class 4) configured PSE port, the requested class

reports "Class 8", while the assigned class reports "Class 4".

The requested classification results are available in registers 0x0C-0F.

The assigned classification results are available in registers 0x4C-4F.

备注

There is no Assigned Class assigned for ports and channels powered out of manual and diagnostic

mode.

9.1.5 Power Allocation and Power Demotion

The Power Allocation settings in register 0x29 sets the maximum power level a port powers on. Settings for each

class level from 2-pair 4 W (Class 1) up to 2-pair 30 W (Class 4) have been provided to maximize system design

flexibility.

备注

The Power Allocation settings in register 0x29 do not set the power limit for a given port. The port and

channel power limiting is configured with the 2P (registers 0x1E- x 21) policing registers

During a turn-on attempt, if a PD presents a classification level greater than the power allocation setting for a

port, the TPS23882B limits the number of classification fingers presented to the PD prior to turn on based on the

power allocation settings in register 0x29. This behavior is called Power Demotion as it is the number of fingers

presented to the PD that sets the maximum level of power the PD is allowed to draw before the PSE is allowed

to disable it.

备注

The IEEE 802.3 standard requires PDs that are power demoted by a PSE to limit their total power

draw below the Type/class level set by the number of fingers presented by the PSE during mutual

identification.

In a 2-pair system, Power demotion is limited to either 30 W (3-fingers) or 15.4 W (1-finger) as there is

no other physical means of indicating to a PD over the physical layer that less than 15.4 W is

available.

If register 0x29 is configured for either 4 W (class 1) or 7 W (Class 2), and a class 3 or higher device is

connected, the port is not powered and a Start Fault is reported along with an "Insufficient Power"

indication provided in register 0x24.

表9-2. 2-Pair Power Demotion Table

Assigned Class Value (Based on the PD Connected at the Port)

Power Allocation

Register 0x29

Class 1 PD

Class 2 PD

Class 3 PD

Class 4 PD

Class 5+ PDs

Start Fault

Insufficient Power

Start Fault

Insufficient Power

Start Fault

Insufficient Power

Start Fault

Insufficient Power

2-Pair 4 W

Class 1

Start Fault

Insufficient Power

Start Fault

Insufficient Power

Start Fault

Insufficient Power

2-Pair 7 W

Class 1

Class 2

2-Pair 15.5 W

Class 3

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表9-2. 2-Pair Power Demotion Table (continued)

Assigned Class Value (Based on the PD Connected at the Port)

Power Allocation

Register 0x29

Class 1 PD

Class 2 PD

Class 3 PD

Class 4 PD

Class 5+ PDs

2-Pair 30 W

Class 1

Class 2

Class 3

Class 4

9.1.6 Programmable SRAM

The TPS23882B device has been designed to include programmable SRAM that accommodates future firmware

updates to support interoperability and compliance issues that can arise as new equipment is introduced in

conjunction with the release of the IEEE 802.3bt standard.

备注

The latest version of firmware and SRAM release notes can be accessed from the TI mySecure

Software web page.

The SRAM release notes and ROM advisory document includes more detailed information regarding

any know issues and changes that were associated with each firmware release.

Upon power up, it is recommended that the TPS23882B device's SRAM be programmed with the latest version

of SRAM code via the I²C to ensure proper operation and IEEE complaint performance. All I²C traffic other than

those commands required to program the SRAM should be deferred until after the SRAM programming

sequences are completed.

For systems that include multiple TPS23882B devices, the 0x7F "global" broadcast I2C address can be used to

programmed all of the devices at the same time.

For more detailed instructions on the SRAM programing procedures, please refer to SRAM CONTROL Register

and the How to Load TPS2388x SRAM and Parity Code Over I²C application brief on TI.com.

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9.3 Feature Description

9.3.1 Port Remapping

The TPS23882B provides port remapping capability, from the logical ports to the physical channels and pins.

The remapping is between any channel of a 4-port group (1 to 4, 5 to 8).

The following example is applicable to 0x26 register = 00111001, 00111001b.

• Logical port 1 (5) ↔ Physical channel 2 (6)

• Logical port 2 (6) ↔ Physical channel 3 (7)

• Logical port 3 (7) ↔ Physical channel 4 (8)

• Logical port 4 (8) ↔ Physical channel 1 (5)

备注

The device ignores any remapping command unless all four ports are in off mode.

If the TPS23882B receives an incorrect configuration, it ignores the incorrect configuration and retains the

previous configuration. The ACK is sent as usual at the end of communication. For example, if the same

remapping code is received for more than one port, then a read back of the Re-Mapping register (0x26) is the

last valid configuration.

Note that if an IC reset command (1Ah register) is received, the port remapping configuration is kept unchanged.

However, if there is a Power-on Reset or if the RESET pin is activated, the Re-Mapping register is reinitialized to

a default value.

9.3.2 Port Power Priority

The TPS23882B supports 1- and 3-bit shutdown priority, which are selected with the MbitPrty bit of General

Mask register (0x17).

The 1-bit shutdown priority works with the Port Power Priority (0x15) register. An OSSn bit with a value of 1

indicates that the corresponding port is treated as low priority, while a value of 0 corresponds to a high priority.

As soon as the OSS input goes high, the low-priority ports are turned off.

The 3-bit shutdown priority works with the Multi Bit Power Priority (0x27/28) register, which holds the priority

settings. A port with “000” code in this register has highest priority. Port priority reduces as the 3-bit value

increases, with up to 8 priority levels. See 图9-1.

The multi bit port priority implementation is defined as the following:

• OSS code ≤Priority setting (0x27/28 register): Port is disabled

• OSS code > Priority setting (0x27/28 register): Port remains active

Shutdown Code

START bits

3.3 V

0 V

SC 1

SC 2

SC 0

OSS

IDLE

t_{f_OSS}

t_{OSS_IDL}

t_{r_OSS}

t_{bit_OSS}

one-bit

duration

t_{OSS_OFF}

GATE

图9-1. Multi Bit Priority Port Shutdown if Lower-Priority Port

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备注

Prior to setting the MbitPrty bit from 0 to 1, make sure the OSS input is in the idle (low) state for a

minimum of 200 µs, to avoid any port misbehavior related to loss of synchronization with the OSS bit

stream.

备注

The OSS input has an internal 1-µs to 5-µs deglitch filter. From the idle state, a pulse with a longer

duration is interpreted as a valid start bit. Ensure that the OSS signal is noise free.

9.3.3 Analog-to-Digital Converters (ADC)

The TPS23882B features 10 multi-slope integrating converters. Each of the first eight converters is dedicated to

current measurement for one channel and operate independently to perform measurements during classification

and when the channel is powered on. When the channel is powered, the converter is used for current (100-ms

averaged) monitoring, power policing, and DC disconnect. Each of the last two converters are shared within a

group of four channels for discovery (16.6-ms averaged), port powered voltage monitoring, power-good status,

and FET short detection. These converters are also used for general-purpose measurements including input

voltage (1 ms) and die temperature.

The ADC type used in the TPS23882B differs from other similar types of converters in that the ADCs

continuously convert while the input signal is sampled by the integrator, providing inherent filtering over the

conversion period. The typical conversion time of the current converters is 800 µs, while the conversion time is 1

ms for the other converters. Powered-device detection is performed by averaging 16 consecutive samples which

provides significant rejection of noise at 50-Hz or 60-Hz line frequency. While a port is powered, digital averaging

provides a channel current measurement integrated over a 100-ms time period. Note that an anti-aliasing filter is

present for powered current monitoring.

备注

During powered mode, current conversions are performed continuously. Also, in powered mode, the

t_STARTtimer must expire before any current or voltage ADC conversion can begin.

9.3.4 I²C Watchdog

An I²C Watchdog timer is available on the TPS23882B device. The timer monitors the I²C, SCL line for clock

edges. When enabled, a timeout of the watchdog resets the I²C interface along with any active ports. This

feature provides protection in the event of a hung software situation or I²C bus hang-up by target devices. In the

latter case, if a target is attempting to send a data bit of 0 when the controller stops sending clocks, then the

target may drive the data line low indefinitely. Because the data line is driven low, the controller cannot send a

STOP to clean up the bus. Activating the I²C watchdog feature of the TPS23882B clears this deadlocked

condition. If the timer of two seconds expires, the ports latch off and the WD status bit is set. Note that WD

Status is set even if the watchdog is not enabled. The WD status bit can only be cleared by a device reset or

writing a 0 to the WDS status bit location. The 4-bit watchdog disable field shuts down this feature when a code

of 1011b is loaded. This field is preset to 1011b whenever the TPS23882B is initially powered. See I²C

WATCHDOG Register for more details.

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9.3.5 Current Foldback Protection

The TPS23882B features two types of foldback mechanisms for complete MOSFET protection.

During inrush, at channel turn-on, the foldback is based on the channel voltage as shown in 图9-2. Note that the

inrush current profile remains the same, regardless of the state of the 2xFBn bits in register 0x40.

After the channel is powered and the Power Good is valid, a dual-slope operational foldback is used, providing

protection against partial and total short-circuit at port output, while still being able to maintain the PD powered

during normal transients at the PSE input voltage. Note that setting the 2xFBn bit selects the 2× curve and

clearing it selects the 1× curve. See 图9-3.

In addition to the default foldback curves, the TPS23882B has individually enabled alternative foldback curves

for both inrush and powered operation. These curves have been designed to accommodate certain loads that do

not fully comply with the IEEE standard and requires additional power to be turned on or remain powered. See

图9-2 and 图9-3.

备注

If using the Alternative Foldback curves (ALTIRn or ALTFBn = 1), designers must account for the

additional power dissipation that can occur in the FETs under these conditions.

0.55

0.5

1.3

1.2

1.1

1

ALTIRn = 0

ALTIRn = 1

2xFBn =0, ALTFBn = 0

2xFBn =0, ALTFBn = 1

2xFBn =1, ALTFBn = 0

2xFBn =1, ALTFBn = 1

0.45

0.4

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

3

6

9

12

15

18

21

24

27 30

V_PORT(V)

33

36

39

42

45

48

51

54

57

D100

0

3

6

9

12

15

18

21

24

27 30

V_DRAIN(V)

33

36

39

42

45

48

51

54

57

D200

图9-2. Foldback During Inrush (at Port Turn-On): 图9-3. Foldback When the Port is Already On: I_LIM

I_LIMvs V_port

vs V_drain

9.4 Device Functional Modes

9.4.1 Detection

To eliminate the possibility of false detection, the TPS23882B uses a TI proprietary 4-point detection method to

determine the signature resistance of the PD device. A false detection of a valid 25-kΩsignature can occur with

2-point detection type PSEs in noisy environments or if the load is highly capacitive.

Detection 1 and Detection 2 are merged into a single detection function which is repeated. Detection 1 applies I1

(160 μA) to a channel, waits approximately 60 ms, then measures the channel voltage (V1) with the integrating

ADC. Detection 2 then applies I2 (270 μA) to the channel, waits another approximately 60 ms, then measures

the channel voltage again (V2). The process is then repeated a second time to capture a third (V3) and fourth

(V4) channel voltage measurements. Multiple comparisons and calculations are performed on all four

measurement point combinations to eliminate the effects of a nonlinear or hysteretic PD signature. The resulting

channel signature is then sorted into the appropriate category.

备注

The detection resistance measurement result is also available in the Channel Detect Resistance

registers (0x44 - 0x47).

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9.4.2 Classification

Hardware classification (class) is performed by supplying a voltage and sampling the resulting current. To

eliminate the high power of a classification event from occurring in the power controller chip, the TPS23882B

uses the external power FET for classification.

During classification, the voltage on the gate node of the external MOSFET is part of a linear control loop. The

control loop applies the appropriate MOSFET drive to maintain a differential voltage between VPWR and DRAIN

of 18.5 V. During classification the voltage across the sense resistor in the source of the MOSFET is measured

and converted to a class level within the TPS23882B. If a load short occurs during classification, the MOSFET

gate voltage reduces to a linearly controlled, short-circuit value for the duration of the class event.

Classification results are read through the I²C Detection Event and Channel-n Discovery Registers. The

TPS23882B also supports 1, and 3 finger classification for PDs ranging from Class 0 through Class 4, using the

Power Enable and Port Power Allocation registers. Additionally, by providing a 3^rdclass finger during discovery

in semiauto mode, the TPS23882B is capable of identifying if a 4-pair Class 5-8 PD is connected to the port.

9.4.3 DC Disconnect

Disconnect is the automated process of turning off power to the port. When the port is unloaded or at least falls

below minimum load, it is required to turn off power to the port and restart detection. In DC disconnect, the

voltage across the sense resistors is measured. When enabled, the DC disconnect function monitors the sense

resistor voltage of a powered port to verify the port is drawing at least the minimum current to remain active. The

T_DIStimer counts up whenever the port current is below the disconnect threshold (6.5-mA typical). If a timeout

occurs, the port is shut down and the corresponding disconnect bit in the Fault Event Register is set. In the case

of a PD implementing MPS (maintain Power Signature) current pulsing, the T_DIScounter is reset each time the

current goes continuously higher than the disconnect threshold for at least 3 ms.

The T_DISduration is set by the T_MPDOBits of the Timing Configuration register (0x16).

9.5 I²C Programming

9.5.1 I²C Serial Interface

The TPS23882B features a 3-wire I²C interface, using SDAI, SDAO, and SCL. Each transmission includes a

START condition sent by the controller, followed by the device address (7-bit) with R/W bit, a register address

byte, then one or two data bytes and a STOP condition. The recipient sends an acknowledge bit following each

byte transmitted. SDAI/SDAO is stable while SCL is high except during a START or STOP condition.

图 9-4 and 图 9-5 show read and write operations through I²C interface, using configuration A or B (see 表 9-24

for more details). The parametric read operation is applicable to ADC conversion results. The TPS23882B

features quick access to the latest addressed register through I²C bus. When a STOP bit is received, the register

pointer is not automatically reset.

It is also possible to perform a write operation to many TPS23882B devices at the same time. The target

address during this broadcast access is 0x7F, as shown in PIN STATUS Register. Depending on which

configuration (A or B) is selected, a global write proceeds as following:

• Config A: Both 4-port devices (1 to 4 and 5 to 8) are addressed at same time.

• Config B: The whole device is addressed.

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R/ W

Bit

Address

Pins

Address

Pins

R/ W

Bit

Non-Parametric Read

Cycle

SDAI

C0

R/W

C1

0

1

A4 A3 A2 A1 A0 R/W

C5 C4 C3 C2

0

1

A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

C6

C7

Command Code

Target Address

R/ W=0

Target Address

R/ W=1

Data from

Target to Host

SDAO

D7 D6 D5 D4 D3 D2 D1 D0

R/ W

Bit

Address

Pins

R/ W

Bit

Address

Pins

Parametric Read

Cycle

C0

C1

D7 D6 D5 D4 D3 D2 D1 D0

0

1

A4 A3 A2 A1 A0 R/W

C5 C4 C3 C2

0

1

A4 A3 A2 A1 A0 R/W

C6

C7

SDAI

Command Code

Target Address

R/ W=0

Target Address

R/ W=1

LSByte Data from

Target to Host

MSByte Data from

Target to Host

D7 D6 D5 D4 D3 D2 D1 D0

SDAO

Address

Pins

R/ W

Bit

Write Cycle

C0

C1

0

1

A4 A3 A2 A1 A0 R/W

C4

C2

D7 D6 D5 D4 D3 D2 D1 D0

C5

C3

C6

C7

SDAI

Target Address

R/ W=0

Data from

Command Code

Host to Target

SDAO

Quick Read Cycle

(latest addressed register)

R/ W

Bit

Address

Pins

SDAI

0

1

A4 A3 A2 A1 A0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

Target Address

R/ W=1

Data from

Target to Host

SDAO

D7 D6 D5 D4 D3 D2 D1 D0

图9-4. I²C interface Read and Write Protocol –Configuration A

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Non-Parametric

Read Cycle

R/ W

Bit

Address

Pins

Address

Pins

R/ W

Bit

SDAI

C0

C1

D7 D6 D5 D4 D3 D2 D1 D0

0

1

A4 A3 A2 A1

0

R/W

C5 C4 C3 C2

0

1

A4 A3 A2 A1

0

D7 D6 D5 D4 D3 D2 D1 D0

C6

R/W

C7

Command Code

Target Address

R/ W=0

Target Address

R/ W=1

Port 4-1 Data from

Target to Host

Port 8-5 Data from

Target to Host

SDAO

D7 D6 D5 D4 D3 D2 D1 D0

Address

Pins

Address

Pins

R/ W

Bit

R/ W

Bit

Parametric Read

Cycle

C0

C1

D7 D6 D5 D4 D3 D2 D1 D0

0

1

A4 A3 A2 A1

0

R/W

C5 C4 C3 C2

0

1

A4 A3 A2 A1 0 R/W

C6

C7

SDAI

...

Command Code

Target Address

R/ W=0

Slave Address

R/ W=1

Port 4-1

LSByte Data from

Port 4-1

MSByte Data from

Target to Host

D7 D6 D5 D4 D3 D2 D1 D0

SDAO

D7 D6 D5 D4 D3 D2 D1 D0

SDAI

...

Port 8-5

LSByte Data from

Port 8-5

MSByte Data from

Target to Host

D7 D6 D5 D4 D3 D2 D1 D0

SDAO

R/ W

Bit

Address

Pins

Write Cycle

C0

C1

D7 D6 D5 D4 D3 D2 D1 D0

0

1

A4 A3 A2 A1

0

R/W

C4

C2

D7 D6 D5 D4 D3 D2 D1 D0

C5

C3

C6

C7

SDAI

Target Address

R/ W=0

Port 4-1 Data from

Host to Target

Port 8-5 Data from

Host to Target

Command Code

SDAO

图9-5. I²C interface Read and Write Protocol –Configuration B

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9.6 Register Maps

9.6.1 Complete Register Set

表9-3. Main Registers

Cmd

Code

Register or

Command Name

I²C

R/W

Data

Byte

RST State

Bits Description

INTERRUPTS

00h

01h

INTERRUPT

RO

1

1000,0000b

SUPF

STRTF

IFAULT

IFMSK

CLASC

CLMSK

DETC

DISF

PGC

PEC

(1)

INTERRUPT MASK R/W

1000,0000b

SUMSK

STMSK

DEMSK

DIMSK

PGMSK

PEMSK

EVENT

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

RO

POWER EVENT

CoR

1

Power Good status change

Power Enable status change

0000,0000b

PGC4

PGC3

PGC2

PGC1

CLSC1

DISF1

PEC4

DETC4

PCUT4

PEC3

PEC2

PEC1

DETC1

PCUT1

RO

Classification

Detection

DETECTION

EVENT

CoR

CLSC4

CLSC3

CLSC2

DETC3

DETC2

RO

FAULT EVENT

CoR

Disconnect occurred

PCUT fault occurred

PCUT3 PCUT2

START fault occurred

DISF4

DISF3

DISF2

RO

START/ILIM EVENT

CoR

ILIM fault occurred

ILIM4

TSD

ILIM3

ILIM2

ILIM1

VPUV

STRT4

Rsvrd

STRT3

STRT2

STRT1

RO

SUPPLY/FAULT

0111,0000b

VDUV

VDWRN

Rsvrd

OSSE

RAMFLT

(2)

EVENT

CoR

STATUS

CHANNEL 1

RO

0Ch

0Dh

0Eh

0Fh

1

0000,0000b

Requested CLASS Channel 1

Requested CLASS Channel 2

Requested CLASS Channel 3

Requested CLASS Channel 4

DETECT Channel 1

DETECT Channel 2

DETECT Channel 3

DETECT Channel 4

DISCOVERY

CHANNEL 2

RO

DISCOVERY

CHANNEL 3

RO

DISCOVERY

CHANNEL 4

RO

DISCOVERY

10h

11h

POWER STATUS

PIN STATUS

RO

1

0000,0000b

0,A[4:0],0,0

PG4

PG3

PG2

PG1

PE4

PE3

PE2

PE1

Rsvd

SLA4

SLA3

SLA2

SLA1

SLA0

Rsvd

CONFIGURATION

Channel 4 Mode

12h

13h

OPERATING MODE R/W

1

0000,0000b

0000 ,1111b

Channel 3 Mode

Channel 2 Mode

Channel 1 Mode

DISCONNECT

R/W

Rsvd

CLE4

OSS4

Rsvd

CLE3

OSS3

Rsvd

CLE2

OSS2

Rsvd

CLE1

OSS1

DCDE4

DETE4

DCUT4

DCDE3

DETE3

DCUT3

DCDE2

DCDE1

DETE1

DCUT1

ENABLE

DETECT/CLASS

R/W

14h

15h

1

0000,0000b

DETE2

DCUT2

ENABLE

PWRPR/PCUT

R/W

DISABLE

16h

17h

TIMING CONFIG

GENERAL MASK

R/W

1

0000,0000b

1000,0000b

TLIM

TSTART

TOVLD

TMPDO

Rsvd

INTEN

Rsvd

nbitACC

MbitPrty

CLCHE

DECHE

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表9-3. Main Registers (continued)

Cmd

Register or

I²C

R/W

Data

Byte

RST State

Bits Description

Code

Command Name

PUSH BUTTONS

DETECT/CLASS

Restart

18h

WO

1

0000,0000b

RCL4

RCL3

RCL2

RCL1

RDET4

RDET3

RDET2

RDET1

19h

1Ah

POWER ENABLE

RESET

WO

1

0000,0000b

POFF4

POFF3

CLINP

POFF2

Rsvd

POFF1

RESAL

PWON4

RESP4

PWON3

RESP3

PWON2

RESP2

PWON1

RESP1

CLRAIN

GENERAL/SPECIALIZED

MFR ID

1Bh

1Ch

1Dh

ID

RO

R/O

R/W

1

0101,0101b

0000,0000b

IC Version

Rsvrd

AUTOCLASS

RESERVED

AC4

AC3

AC2

AC1

Rsvrd

Rsrvd

2P POLICE 1

CONFIG

1Eh

1Fh

20h

21h

22h

R/W

1

1111,1111b

2-Pair POLICE Channel 1

2-Pair POLICE Channel 2

2-Pair POLICE Channel 3

2-Pair POLICE Channel 4

2P POLICE 2

CONFIG

2P POLICE 3

CONFIG

2P POLICE

4CONFIG

CAP

0000,0000b

Rsvd

CDET4

Rsvd

CDET3

Rsvd

CDET2

Rsvd

CDET1

Rsvd

MEASUREMENT⁽³⁾

23h

24h

25h

Reserved

R/W

RO

1

Power-on FAULT

0000,0000b

1110,0100b

PF Channel 4

PF Channel 3

PF Channel 2

PF Channel 1

CoR

Physical re-map

Logical Port 4

Physical re-map

Logical Port 3

Physical re-map

Logical Port 2

Physical re-map

Logical Port 1

26h

RE-MAPPING

R/W

1

27h

28h

Multi-Bit Priority 21

Multi-Bit Priority 43

R/W

1

0000,0000b

Rsvd

Channel 2

Rsvd

Channel 1

Channel 4

MC34

Channel 3

MC12

Port Power

Allocation

29h

R/W

1

0000,0000b

1111,1111b

Rsvd

2A -

2Bh

Reserved

Rsrvd

2Ch

2Dh

2Eh

2Fh

TEMPERATURE

Reserved

RO

R/W

RO

1

0000,0000b

Temperature (bits 7 to 0)

Rsvd Rsvd

Input Voltage: LSByte

Input Voltage: MSByte (bits 13 to 8)

Rsvd

INPUT VOLTAGE

2

RO

EXTENDED REGISTER SET –PARAMETRIC MEASUREMENT

30h

31h

32h

33h

RO

0000,0000b

Channel 1 Current: LSByte

Channel 1

CURRENT

2

Rsvd

Channel 1 Current: MSByte (bits 13 to 8)

Channel 1 Voltage: LSByte

Channel 1

VOLTAGE

Channel 1 Voltage: MSByte (bits 13 to 8)

(1) SUPF bit reset state shown is at Power up only

(2) VDUV, VPUV and VDWRN bits reset state shown is at Power up only

(3) Capacitance Measurement is only supported if SRAM code is programmed

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表9-4. Main Registers

Cmd

Register or

I²C

R/W

Data

Byte

RST State

Bits Description

Code Command Name

34h

RO

0000,0000b

Channel 2 Current: LSByte

Channel 2

CURRENT

2

35h

Rsvd

Channel 2 Current: MSByte (bits 13 to 8)

Channel 2 Voltage: LSByte

36h

Channel 2

VOLTAGE

37h

Channel 2 Voltage: MSByte (bits 13 to 8)

Channel 3 current: LSByte

38h

Channel 3

CURRENT

39h

Channel 3 Current: MSByte (bits 13 to 8)

Channel 3 Voltage: LSByte

3Ah

Channel 3

VOLTAGE

3Bh

Channel 3 Voltage: MSByte (bits 13 to 8)

Channel 4 current: LSByte

3Ch

Channel 4

CURRENT

3Dh

Channel 4 Current: MSByte (bits 13 to 8)

Channel 4 Voltage: LSByte

3Eh

Channel 4

VOLTAGE

3Fh

Channel 4 Voltage: MSByte (bits 13 to 8)

CONFIGURATION/OTHERS

CHANNEL

40h

R/W

RO

1

0000,0000b

2xFB4

Rsvd

2xFB3

2xFB2

2xFB1

MPOL4

MPOL3

MPOL2

MPOL1

WDS

FOLDBACK

FIRMWARE

41h

RRRR,RRRRb

Firmware Revision

REVISION

42h

43h

I2C WATCHDOG

DEVICE ID

R/W

RO

1

0001,0110b

0011,0100b

Rsvd

Watchdog Disable

Silicon Revision number

Device ID number

SIGNATURE MEASUREMENTS

Ch1 DETECT

RESISTANCE

44h

45h

46h

47h

RO

1

0000,0000b

Channel 1 Resistance

Channel 2 Resistance

Channel 3 Resistance

Channel 4 Resistance

Ch2 DETECT

RESISTANCE

Ch3 DETECT

RESISTANCE

Ch4 DETECT

RESISTANCE

Ch1 CAP

48h

49h

4Ah

4Bh

MEASUREMENT

RO

1

0000,0000b

Channel 1 Capacitance

Channel 2 Capacitance

Channel 3 Capacitance

Channel 4 Capacitance

(3)

Ch2 CAP

MEASUREMENT

(3)

Ch3 CAP

MEASUREMENT

(3)

Ch4 CAP

MEASUREMENT

(3)

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表9-4. Main Registers (continued)

Cmd

Register or

I²C

R/W

Data

Byte

RST State

Bits Description

Code Command Name

ASSIGNED CHANNEL STATUS

ASSIGNED

4Ch

4Dh

4Eh

4Fh

CLASS CHANNEL

1

RO

1

0000,0000b

Assigned CLASS Channel 1

Previous CLASS Channel 1

ASSIGNED

CLASS CHANNEL

2

Assigned CLASS Channel 2

Assigned CLASS Channel 3

Assigned CLASS Channel 4

Previous CLASS Channel 2

Previous CLASS Channel 3

Previous CLASS Channel 4

ASSIGNED

CLASS CHANNEL

3

ASSIGNED

CLASS CHANNEL

4

AUTOCLASS CONFIGURATION/MEASUREMENTS

AUTOCLASS

CONTROL

50h

51h

R/W

RO

1

0000,0000b

MAC4

Rsrvd

MAC3

MAC2

MAC1

AAC4

AAC3

AAC2

AAC1

CHANNEL 1

AUTOCLASS

PWR

Channel 1 AutoClass Power

Channel 2 AutoClass Power

Channel 3 AutoClass Power

Channel 4 AutoClass Power

CHANNEL 2

AUTOCLASS

PWR

52h

53h

54h

RO

1

0000,0000b

Rsrvd

CHANNEL 3

AUTOCLASS

PWR

CHANNEL 4

AUTOCLASS

PWR

MISCELLANEOUS

ALTERNATIVE

FOLDBACK

ALTFB

2

55h

R/W

1

0000,0000b

ALTFB4

Rsrvd

ALTFB3

Rsrvd

ALTFB1

Rsrvd

ALTIR4

Rsrvd

ALTIR3

Rsrvd

ALTIR2

Rsrvd

ALTIR1

Rsrvd

56h -

5Fh

RESERVED

Rsrvd

SRAM

0000,0000b PROG_SEL CPU_RST Rsrvd PAR_EN RAM_EN PAR_SEL

60h

61h

62h

63h

SRAM CONTROL R/W

1

-

RZ/W

CLR_PTR

SRAM DATA

R/W

-

SRAM DATA - Read and Write (continuous)

Programming Start Address (LSB)

Programming Start Address (MSB)

1

0000,0000b

START ADDRESS

64h -

6Fh

RESERVED

R/W

1

0000,0000b

Rsrvd

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9.6.2 Detailed Register Descriptions

9.6.2.1 INTERRUPT Register

COMMAND = 00h with 1 Data Byte, Read only

Active high, each bit corresponds to a particular event that occurred. Each bit can be individually reset by doing

a read at the corresponding event register address, or by setting bit 7 of Reset register.

Any active bit of Interrupt register activates the INT output if its corresponding Mask bit in INTERRUPT Mask

register (01h) is set, as well as the INTEN bit in the General Mask register.

图9-6. INTERRUPT Register Format

7

6

5

4

3

2

1

0

SUPF

R-1

STRTF

R-0

IFAULT

R-0

CLASC

R-0

DETC

R-0

DISF

R-0

PGC

R-0

PEC

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-5. INTERRUPT Register Field Descriptions

Bit

Field

Type

Reset Description

7

SUPF

R

1

0

Indicates that a Supply Event Fault or SRAM memory fault occurred

SUPF = TSD || VDUV || VDWRN || VPUV || RAMFLT

1 = At least one Supply Event Fault or SRAM memory fault occurred

0 = No such event occurred

6

5

4

3

2

1

STRTF

IFAULT

CLASC

DETC

DISF

R

Indicates that a t_STARTFault occurred on at least one channel.

STRTF = STRT1 || STRT2 || STRT3 || STRT4

1 = t_STARTFault occurred for at least one channel

0 = No t_STARTFault occurred

Indicates that a t_OVLDor t_LIMFault occurred on at least one channel.

IFAULT = PCUT1 || PCUT2 || PCUT3 || PCUT4 || ILIM1 || ILIM2 || ILIM3 || ILIM4

1 = t_OVLDand/or t_LIMFault occurred for at least one channel

0 = No t_OVLDnor t_LIMFault occurred

Indicates that at least one classification cycle occurred on at least one channel

CLASC = CLSC1 || CLSC2 || CLSC3 || CLSC4

1 = At least one classification cycle occurred for at least one channel

0 = No classification cycle occurred

Indicates that at least one detection cycle occurred on at least one channel

DETC = DETC1 || DETC2 || DETC3 || DETC4

1 = At least one detection cycle occurred for at least one channel

0 = No detection cycle occurred

Indicates that a disconnect event occurred on at least one channel.

DISF = DISF1 || DISF2 || DISF3 || DISF4

1 = Disconnect event occurred for at least one channel

0 = No disconnect event occurred

PGC

Indicates that a power good status change occurred on at least one channel.

PGC = PGC1 || PGC2 || PGC3 || PGC4

1 = Power good status change occurred on at least one channel

0 = No power good status change occurred

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表9-5. INTERRUPT Register Field Descriptions (continued)

Bit

Field

Type

Reset Description

0

PEC

R

0

Indicates that a power enable status change occurred on at least one channel

PEC = PEC1 || PEC2 || PEC3 || PEC4

1 = Power enable status change occurred on at least one channel

0 = No power enable status change occurred

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9.6.2.2 INTERRUPT MASK Register

COMMAND = 01h with 1 Data Byte, Read/Write

Each bit corresponds to a particular event or fault as defined in the Interrupt register.

Writing a 0 into a bit will mask the corresponding event/fault from activating the INT output.

Note that the bits of the Interrupt register always change state according to events or faults, regardless of the

state of the state of the Interrupt Mask register.

Note that the INTEN bit of the General Mask register must also be set in order to allow an event to activate the

INT output.

图9-7. INTERRUPT MASK Register Format

7

6

5

4

3

2

1

0

SUMSK

R/W-1

STMSK

R/W-0

IFMSK

R/W-0

CLMSK

R/W-0

DEMSK

R/W-0

DIMSK

R/W-0

PGMSK

R/W-0

PEMSK

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-6. INTERRUPT MASK Register Field Descriptions

Bit

Field

Type Reset Description

7

SUMSK

R/W

1

0

Supply Event Fault mask bit.

1 = Supply Event Fault will activate the INT output.

0 = Supply Event Fault will have no impact on INT output.

6

5

4

3

2

1

0

STMSK

IFMSK

t_STARTFault mask bit.

1 = t_STARTFault will activate the INT output.

0 = t_STARTFault will have no impact on INT output.

t_OVLDor t_LIMFault mask bit.

1 = t_OVLDand/or t_LIMFault occurrence will activate the INT output

0 = t_OVLDand/or t_LIMFault occurrence will have no impact on INT output

CLMSK

DEMSK

DIMSK

PGMSK

PEMSK

Classification cycle mask bit.

1 = Classification cycle occurrence will activate the INT output.

0 = Classification cycle occurrence will have no impact on INT output.

Detection cycle mask bit.

1 = Detection cycle occurrence will activate the INT output.

0 = Detection cycle occurrence will have no impact on INT output.

Disconnect event mask bit.

1 = Disconnect event occurrence will activate th INT output.

0 = Disconnect event occurrence will have no impact on INT output.

Power good status change mask bit.

1 = Power good status change will activate the INT output.

0 = Power good status change will have no impact on INT output.

Power enable status change mask bit.

1 = Power enable status change will activate the INT output.

0 = Power enable status change will have no impact on INT output.

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SPACE

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9.6.2.3 POWER EVENT Register

COMMAND = 02h with 1 Data Byte, Read only

COMMAND = 03h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual channel.

A read at each location (02h or 03h) returns the same register data with the exception that the Clear on Read

command clears all bits of the register.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

图9-8. POWER EVENT Register Format

7

6

5

4

3

2

1

0

PGC4

R-0

PGC3

R-0

PGC2

R-0

PGC1

R-0

PEC4

R-0

PEC3

R-0

PEC2

R-0

PEC1

R-0

CR-0

LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset

表9-7. POWER EVENT Register Field Descriptions

Bit

Field

Type Reset Description

R or

CR

0

Indicates that a power good status change occurred.

1 = Power good status change occurred

7–4

PGC4–PGC1

0 = No power good status change occurred

R or

CR

0

Indicates that a power enable status change occurred.

1 = Power enable status change occurred

3–0

PEC4–PEC1

0 = No power enable status change occurred

SPACE

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9.6.2.4 DETECTION EVENT Register

COMMAND = 04h with 1 Data Byte, Read only

COMMAND = 05h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual channel.

A read at each location (04h or 05h) returns the same register data with the exception that the Clear on Read

command clears all bits of the register. These bits are cleared when channel-n is turned off.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

图9-9. DETECTION EVENT Register Format

7

6

5

4

3

2

1

0

CLSC4

R-0

CLSC3

R-0

CLSC2

R-0

CLSC1

R-0

DETC4

R-0

DETC3

R-0

DETC2

R-0

DETC1

R-0

CR-0

LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset

表9-8. DETECTION EVENT Register Field Descriptions

Bit

Field

Type Reset Description

R or

CR

0

Indicates that at least one classification cycle occurred if the CLCHE bit in General Mask

register is low. Conversely, it indicates when a change of class occurred if the CLCHE bit is

set.

7–4

CLSC4–CLSC1

1 = At least one classification cycle occurred (if CLCHE = 0) or a change of class occurred

(CLCHE = 1)

0 = No classification cycle occurred (if CLCHE = 0) or no change of class occurred (CLCHE

= 1)

R or

CR

0

Indicates that at least one detection cycle occurred if the DECHE bit in General Mask

register is low. Conversely, it indicates when a change in detection occurred if the DECHE

bit is set.

3–0

DETC4–DETC1

1 = At least one detection cycle occurred (if DECHE = 0) or a change in detection occurred

(DECHE = 1)

0 = No detection cycle occurred (if DECHE = 0) or no change in detection occurred (DECHE

= 1)

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9.6.2.5 FAULT EVENT Register

COMMAND = 06h with 1 Data Byte, Read only

COMMAND = 07h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual channel.

A read at each location (06h or 07h) returns the same register data with the exception that the Clear on Read

command clears all bits of the register. These bits are cleared when channel-n is turned off.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

图9-10. FAULT EVENT Register Format

7

6

5

4

3

2

1

0

DISF4

R-0

DISF3

R-0

DISF2

R-0

DISF1

R-0

PCUT4

R-0

PCUT3

R-0

PCUT2

R-0

PCUT1

R-0

CR-0

LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset

表9-9. FAULT EVENT Register Field Descriptions

Bit

Field

Type Reset Description

R or

CR

0

Indicates that a disconnect event occurred.

1 = Disconnect event occurred

7–4

DISF4–DISF1

0 = No disconnect event occurred

R or

CR

0

Indicates that a t_OVLDFault occurred.

1 = t_OVLDFault occurred

3–0

PCUT4–PCUT1

0 = No t_OVLDFault occurred

SPACE

Clearing a PCUT event has no impact on the TLIM or TOVLD counters.

SPACE

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9.6.2.6 START/ILIM EVENT Register

COMMAND = 08h with 1 Data Byte, Read only

COMMAND = 09h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual channel.

A read at each location (08h or 09h) returns the same register data with the exception that the Clear on Read

command clears all bits of the register. These bits are cleared when channel-n is turned off.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

图9-11. START/ILIM EVENT Register Format

7

6

5

4

3

2

1

0

ILIM4

R-0

ILIM3

R-0

ILIM2

R-0

ILIM1

R-0

STRT4

R-0

STRT3

R-0

STRT2

R-0

STRT1

R-0

CR-0

LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset

表9-10. START/ILIM EVENT Register Field Descriptions

Bit

Field

Type Reset Description

R or

CR

0

Indicates that a t_LIMfault occurred, which means the channel has limited its output current to

7–4

ILIM4–ILIM1

I_LIMor the folded back I_LIMfor more than t_LIM

.

1 = t_LIMfault occurred

0 = No t_LIMfault occurred

R or

CR

0

Indicates that a t_STARTfault occurred during turn on.

1 = t_STARTfault or class/detect error occurred

0 = No t_STARTfault or class/detect error occurred

3–0

STRT4–STRT1

SPACE

备注

When a Start Fault is reported and the PECn bit in Power Event register is set, then there is an Inrush

fault.

When a Start Fault is reported and the PECn bit is not set, then the Power-On Fault register (0x24h)

will indicate the cause of the fault.

In auto mode, STRTn faults will not be reported and register 0x24h will not be updated due to invalid

discovery results.

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9.6.2.7 SUPPLY and FAULT EVENT Register

COMMAND = 0Ah with 1 Data Byte, Read only

COMMAND = 0Bh with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

A read at each location (0Ah or 0Bh) returns the same register data with the exception that the Clear on Read

command clears all bits of the register.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

图9-12. SUPPLY and FAULT EVENT Register Format

7

TSD

R

6

VDUV

R

5

VDWRN

R

4

VPUV

R

3

Rsvrd

R

2

Rsvrd

R

1

OSSE

R

0

RAMFLT

R

CR

LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset

表9-11. SUPPLY and FAULT EVENT Register Field Descriptions

Bit

POR/R

Field

Type

ST

Description

7

TSD

R or CR 0 / P Indicates that a thermal shutdown occurred. When there is thermal shutdown, all channels are turned off

and are put in OFF mode. The internal circuitry continues to operate however, including the ADCs. Note

that at as soon as the internal temperature has decreased below the low threshold, the channels can be

turned back ON regardless of the status of the TSD bit.

1 = Thermal shutdown occurred

0 = No thermal shutdown occurred

6

5

4

VDUV

R or CR 1 / P Indicates that a VDD UVLO occurred.

1 = VDD UVLO occurred

0 = No VDD UVLO occurred

VDWRN

VPUV

R or CR 1 / P Indicates that the VDD has fallen under the UVLO warning threshold.

1 = VDD UV Warning occurred

0 = No VDD UV warning occurred

R or CR 1 / P Indicates that a VPWR undervoltage occurred.

1 = VPWR undervoltage occurred

0 = No VPWR undervoltage occurred

3-2

1

Rsvrd

OSSE

R or CR 0 / 0 Reserved

R or CR 0 / 0 Indicates that an OSS Event occurred

1 = one or more channels with a group of 4 were disabled due to the assertion of the OSS pin or

provided 3-bit OSS code

0 = No OSS events occurred

0

RAMFLT

R or CR 0 / 0 Indicates that a SRAM fault has occurred

1 = SRAM fault occurred

0 = No SRAM fault occurred

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SPACE

备注

The RST condition of "P" indicates that the previous state of these bits will be preserved following a

device reset using the RESET pin. Thus, pulling the RESET input low will not clear the TSD, VDUV,

VDWRN, or VPUV bits.

备注

While the VPUV bit is set, any PWONn commands will be ignored until V_VPWR> 30 V.

During VPUV undervoltage condition, the Detection Event register (CLSCn, DETCn) is not cleared,

unless VPWR also falls below the VPWR UVLO falling threshold (approximately18 V).

A clear on Read will not effectively clear VDUV bit as long as the VPWR undervoltage condition is

maintained.

备注

In 1-bit mode (MbitPrty = 0 in reg 0x17), the OSSE bit will be set anytime a channel within a group of 4

has OSS enabled and the OSS pin is asserted.

In 3-bit mode (MbitPrty = 1 in reg 0x17), the OSSE bit will be set anytime a 3-bit priority code is sent

that is equal to or greater than the MBPn settings in registers 0x27 and 0x28 channel for a group of 4

channels.

SPACE

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9.6.2.7.1 Detected SRAM Faults and "Safe Mode"

The TPS23882B is configured with internal SRAM memory fault monitoring, and in the event that an error is

detected with the SRAM memory, the device will enter “safe mode”. While in “Safe mode”the FW Revision

value in register 0x41 will be set to 0xFFh.

Any channels that are currently powered will remain powered, but the majority of the operation will be disabled

until the SRAM can be reloaded. The device UVLO and Thermal Shutdown features in addition to the disconnect

and current foldback functions for the powered channels will be preserved in “safe mode”.

Any channels that were not powered prior to the SRAM fault detection will be set to OFF mode (see register

0x12h description for additional changes that will occur as a result of the change to OFF mode). Port Remapping

(0x26h) and any other channel configuration settings (ie Power Allocation 0x29h) will be preserved.

Upon detection of a SRAM fault the “RAM_EN” bit in 0x60 will be cleared and the RAMFLT bit will be set in

register 0x0A. The internal firmware will continue to run in “safe mode” until this bit is set again by the host

after the SRAM is reloaded or a POR (Power on Reset) event occurs. In order to ensure a smooth transition into

and out of “safe mode”, any I2C commands other than those to reprogram the SRAM need to be deferred

until after the SRAM is reloaded and determined to be “valid” (see register 0x60 SRAM programing

descriptions).

备注

Once set, the RAMFLT bit will remain set even after the device is removed from safe mode. it is

recommend that this bit be cleared prior to setting the RAM_EN bit in register 0x60 following the

SRAM reload.

备注

The PAR_EN bit in reg 0x60 must be set and the corresponding SRAM_Parity code (available for

download from the TI mySecure Software webpage) must be loaded into the device in order for the

SRAM fault monitoring to be active.

Please refer to the How to Load TPS2388x SRAM Code document for more information on the

recommended SRAM programming procedure.

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9.6.2.8 CHANNEL 1 DISCOVERY Register

COMMAND = 0Ch with 1 Data Byte, Read Only

图9-13. CHANNEL 1 DISCOVERY Register Format

7

6

5

4

3

2

1

0

REQUESTED CLASS Ch1

R-0 R-0

DETECT Ch1

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.9 CHANNEL 2 DISCOVERY Register

COMMAND = 0Dh with 1 Data Byte, Read Only

图9-14. CHANNEL 2 DISCOVERY Register Format

7

6

5

4

3

2

1

0

REQUESTED CLASS Ch2

R-0 R-0

DETECT Ch2

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.10 CHANNEL 3 DISCOVERY Register

COMMAND = 0Eh with 1 Data Byte, Read Only

图9-15. CHANNEL 3 DISCOVERY Register Format

7

6

5

4

3

2

1

0

REQUESTED CLASS Ch3

R-0 R-0

DETECT Ch3

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.11 CHANNEL 4 DISCOVERY Register

COMMAND = 0Fh with 1 Data Byte, Read Only

图9-16. CHANNEL 4 DISCOVERY Register Format

7

6

5

4

3

2

1

0

REQUESTED CLASS Ch4

R-0 R-0

DETECT Ch4

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Bit Descriptions: These bits represent the most recent "requested" classification and detection results for

channel n. These bits are cleared when channel n is turned off.

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Bit Field

表9-12. CHANNEL n DISCOVERY Register Field Descriptions

Type Reset

Description

RCLASS

Ch-n

R 0

Most recent classification result on channel n.

The selection is as following:

7–4

RCLASS Ch-n

Requested Class

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Unknown

Class 1

Class 2

Class 3

Class 4

Reserved –read as Class 0

Class 0

Class Overcurrent

Class 5 - 4-Pair Single Signature

Class 6 - 4-Pair Single Signature

Class 7 - 4-Pair Single Signature

Class 8 - 4-Pair Single Signature

Class 4+ - Type-1 Limited

Class 5 - 4-Pair Dual Signature

Reserved

Class Mismatch

DETECT

Ch-n

R

0

Most recent detection result on channel n.

The selection is as following:

3–0

DETECT Ch-n

Detection Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Unknown

Short-circuit

Reserved

Too Low

Valid

Too High

Open Circuit

Reserved

MOSFET fault

“Requested”vs. “Assigned”Classification: The “requested”class is the classification the PSE measures

during Mutual Identification prior to turn on, whereas the “assigned” class is the classification level the

channel was powered on with based on the Power Allocation setting in register 0x29h. The “assigned”

classification values are available in registers 0x4C-4F

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备注

Due to the need to power on after 1 class finger, the "Class 4+ - Type 1 Limited" Requested Class is

reported anytime a Class 4 or higher PD is powered with register 0x29 configured for 15.5W.

Upon being powered, devices that present a class 0 signature during discovery will be given an

assigned class of "Class 3"

Even though the TPS23882B is a 2-pair PSE controller, due to the use of 3-finger classification, it is

still capable of identifying if a Class 5+ 4-pair PDs is connected.

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9.6.2.12 POWER STATUS Register

COMMAND = 10h with 1 Data Byte, Read only

Each bit represents the actual power status of a channel.

Each bit xx1-4 represents an individual channel.

These bits are cleared when channel-n is turned off, including if the turn off is caused by a fault condition.

图9-17. POWER STATUS Register Format

7

6

5

4

3

2

1

0

PG4

R-0

PG3

R-0

PG2

R-0

PG1

R-0

PE4

R-0

PE3

R-0

PE2

R-0

PE1

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-13. POWER STATUS Register Field Descriptions

Bit

Field

Type Reset Description

R

0

Each bit, when at 1, indicates that the channel is on and that the voltage at DRAINn pin has

gone below the power good threshold during turn on.

7–4

PG4–PG1

These bits are latched high once the turn on is complete and can only be cleared when the

channel is turned off or at RESET/POR.

1 = Power is good

0 = Power is not good

R

0

Each bit indicates the ON/OFF state of the corresponding channel.

3–0

PE4–PE1

1 = Channel is on

0 = Channel is off

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9.6.2.13 PIN STATUS Register

COMMAND = 11h with 1 Data Byte, Read Only

图9-18. PIN STATUS Register Format

7

0

6

5

4

3

2

1

0

SLA4

A4 pin

SLA3

A3 pin

SLA2

A2 pin

SLA1

A1 pin

SLA0

0/1⁽¹⁾

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) If Configuration A, it can be 0 or 1. If configuration B, it is 0.

表9-14. PIN STATUS Register Field Descriptions

Bit

Field

Type Reset Description

6-3

SLA4-SLA1

R

See I²C device address, as defined while using pins A4-A1.

above

2

SLA0

-

R

SLA0 bit is internally defined to 0 or 1

0 = Channel 1-4

1 = Channels 5-8

7, 1-0

R

Reserved

BINARY DEVICE ADDRESS

ADDRESS PINS

DESCRIPTION

6

1

0

5

1

4

1

0

1

3

1

0

1

0

1

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A4

A3

A2

A1

Broadcast access

Target 0

1

X

0/1

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

GND

HIGH

Target 15

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9.6.2.13.1 AUTONOMOUS MODE

In autonomous mode, the TPS23882B is capable of operating without any I²C communication or host control. As

in auto mode, when the device is operating in autonomous mode, the ports will be continuously cycling through

discovery, and the ports will automatically power whenever a valid (defection and classification) PD is connected.

Connecting a resistor between the AUTO pin and GND based on the table below 表9-15will enable autonomous

mode and configure all the ports to the same Power Allocation settings. In the event a PD is connected with a

higher requested class than the autonomous mode configuration, the port will power demote the PD to the

selected autonomous mode configuration power level.

表9-15. AUTO Pin Programming

AUTO Pin

Autonomous Mode Configuration

Resulting Register Configurations

0x12h

0x14h

0x29h

Open/Floating

124 kΩ

Disabled

2-pair 15W

2-pair 30W

0000, 0000b

1111, 1111b

0000, 0000b

1111, 1111b

0000, 0000b

0011 0011b

62 kΩ

SPACE

备注

A 10 nF capacitor is required in parallel with R_AUTOto ensure stability in the Autonomous mode

selection.

The I2C interface is still fully operational in Autonomous mode, and the all of the port telemetry and

configurability is still supported

The AUTO pin resistance (R_AUTO) will not be measured following a device reset (assertion of the

RESET pin or RESAL bit in register 0x1A). The device wil only measured (R_AUTO) and pre-configure

the internal registers during power up (V_VPWRand V_VDDrising above their respective UVLO

thresholds).

备注

The device SRAM will need to be programmed in order to support applications that desire to remove a

device from Autonomous mode after having initially powered up in Autonomous mode.

A device running from the internal ROM (SRAM unprogrammed) in Autonomous mode will turn off and

automatically resume discovery and power on any valid loads following the assertion of the RESET

pin, I2C register 0x1A RESAL or RESPn bits, or a mode off command. Whereas a device running in

Autonomous mode with the SRAM programmed will turn off and remain inactive until the host re-

enables the port(s) through the I²C bus.

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9.6.2.14 OPERATING MODE Register

COMMAND = 12h with 1 Data Byte, Read/Write

图9-19. OPERATING MODE Register Format

7

6

5

4

3

2

1

0

C4M1

R/W-0

C4M0

R/W-0

C3M1

R/W-0

C3M0

R/W-0

C2M1

R/W-0

C2M0

R/W-0

C1M1

R/W-0

C1M0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-16. OPERATING MODE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

R/W

0

Each pair of bits configures the operating mode per channel.

The selection is as following:

CnM1–

CnM0

M1

0

M0

0

Operating Mode

OFF

0

1

Diagnostic/Manual

Semiauto

1

0

1

Auto

SPACE

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OFF MODE:

In OFF mode, the Channel is OFF and neither detection nor classification is performed independent of the

DETE, CLSE or PWON bits.

The table below depicts what bits will be cleared when a channel is changed to OFF mode from any other

operating mode:

表9-17. Transition to OFF Mode

Register

0x04

Bits to be reset

CLSCn and DETCn

DISFn and PCUTn

0x06

0x08

STRTn and ILIMn

0x0C-0F

0x10

Requested Class and Detection

PGn and PEn

0x14

CLEn and DETEn

0x1C

ACn

0x1E-21

0x24

2P Policing set to 0xFFh

PFn

0x30-3F

0x40

Channel Voltage and Current Measurements

2xFBn

0x44 - 47

0x4C-4F

0x51-54

Detection Resistance Measurements

Assigned Class and Previous Class

Autoclass Measurement

SPACE

备注

it may take upwards of 5 ms before all of the registers are cleared following a change to OFF mode.

Only the bits associated with the channel/port ("n") being set into OFF mode will be cleared. Those bits

associated with channels/ports remaining in operation will not be changed.

In the event either the PGn or PEn bits were changed from a 1 to a zero, the corresponding PGCn and PECn

bits will be set in the POWER EVENT register 0x02h.

Also, a change of mode from semiauto to manual/diagnostic mode or OFF mode will cancel any ongoing

cooldown time period.

SPACE

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DIAGNOSTIC/MANUAL MODE:

In Manual/Diagnostic mode, there is no automatic state change. The channel remains idle until DETE, CLSE

(0x14h or 0x18h), or PWON command is provided. Upon the setting of the DETE and/or CLSE bits, the channel

will perform a singular detection and/or classification cycle on the corresponding channel.

SPACE

备注

Setting a PWONn bit in register 0x19 results in the immediate turn on of that channel.

There is no Assigned Class assigned for ports/channels powered out of Manual/Diagnostic mode. Any

settings such as the port power policing and 1x/2x foldback selection that are typically configure based

on the assigned class result need to manually configured by the user.

备注

Setting a PWONn bit in register 0x19 results in the immediate turn on of that channel.

SEMIAUTO MODE:

In semiauto mode, as long as the Channel is unpowered, detection and classifications may be performed

continuously depending if the corresponding class and detect enable bits are set (register 0x14h).

表9-18. Channel Behavior in Semiauto Mode

CLEn

DETn

Channel Operation

0

1

0

1

0

1

Idle

Cycling Detection Measurements only

Idle

Cycling Detection and Classification Measurements

SPACE

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AUTO MODE:

In auto mode, channels will automatically power on any valid detection and classification signature based on the

Port Power Allocation settings in 0x29. The channels will remain idle until DETE and CLSE (0x14 or 0x18) are

set, or a PWON command is given.

Prior to setting DETE and CLE or sending a PWON command in AUTO mode, the following registers need to be

configured according to the system requirements and configuration:

Register

0x26

Bits

Port Re-mapping

0x29

Port Power Allocation

0x50

Auto AC Enable

0x55

Alternative Inrush and Powered Foldback Enable

备注

Changes to these registers after the DETE and CLE bits are set in auto mode may result in undesired

or non IEEE complaint operation.

The following registers may be configured or changed after turn on if changes to the default operation are

desired as these values are internally set during power on based on the port configuration and resulting

assigned PD class:

Register

0x1E-21

0x40

Bits

2-Pair Policing

2x Foldback Enable

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9.6.2.15 DISCONNECT ENABLE Register

COMMAND = 13h with 1 Data Byte, Read/Write

Bit Descriptions: Defines the disconnect detection mechanism for each channel.

图9-20. DISCONNECT ENABLE Register Format

7

6

5

4

3

2

1

0

DCDE4

R/W-1

DCDE3

R/W-1

DCDE2

R/W-1

DCDE1

R/W-1

–

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-19. DISCONNECT ENABLE Register Field Descriptions

Bit

Field

Type Reset Description

R/W

0

1

7–4

3–0

—

DC disconnect enable

DCDE4–

DCDE1

1 = DC Disconnect Enabled

0 = DC Disconnect Disabled

Look at the TIMING CONFIGURATION register for more details on how to define the TDIS

time period.

DC disconnect consists in measuring the Channel DC current at SENn, starting a timer (T_DIS) if this current is

below a threshold and turning the Channel off if a time-out occurs. Also, the corresponding disconnect bit

(DISFn) in the FAULT EVENT register is set accordingly. The T_DIScounter is reset each time the current rises

above the disconnect threshold for at least 3 msec. The counter does not decrement below zero.

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9.6.2.16 DETECT/CLASS ENABLE Register

COMMAND = 14h with 1 Data Byte, Read/Write

During t_OVLD, t_LIMor t_STARTcool down cycle, any Detect/Class Enable command for that channel will be delayed

until end of cool-down period. Note that at the end of cool down cycle, one or more detection/class cycles are

automatically restarted as described previously, if the class and/or detect enable bits are set.

图9-21. DETECT/CLASS ENABLE Register Format

7

6

5

4

3

2

1

0

CLE4

R/W-0

CLE3

R/W-0

CLE2

R/W-0

CLE1

R/W-0

DETE4

R/W-0

DETE3

R/W-0

DETE2

R/W-0

DETE1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-20. DETECT/CLASS ENABLE Register Field Descriptions

Bit

Field

Type Reset Description

CLE4-CLE1

DETE4-DETE1

R/W

0

Classification enable bits.

Detection enable bits.

7–4

3–0

Bit Descriptions:

Detection and classification enable for each channel.

When in Manual mode, setting a bit means that only one cycle (detection or classification) is performed for the

corresponding channel. The bit is automatically cleared by the time the cycle has been completed.

Note that similar result can be obtained by writing to the Detect/Class Restart register 0x18.

It is also cleared if a turn off (Power Enable register) command is issued.

When in semiauto mode, as long as the port is kept off, detection and classification are performed continuously,

as long as the class and detect enable bits are kept set, but the class will be done only if the detection was valid.

A Detect/Class Restart PB command can also be used to set the CLEn and DETEn bits, if in semiauto mode.

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9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name

COMMAND = 15h with 1 Data Byte, R/W

图9-22. Power Priority / 2P-PCUT Disable Register Format

7

6

5

4

3

2

1

0

OSS4

R/W-0

OSS3

R/W-0

OSS2

R/W-0

OSS1

R/W-0

DCUT4

R/W-0

DCUT3

R/W-0

DCUT2

R/W-0

DCUT1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-21. Power Priority / 2P-PCUT Disable Register Field Descriptions

Bit

Field

Type

Reset Description

OSS4-OSS1

R/W

0

Power priority bits:

When the MBitPrty bit in 0x17 =0:

7–4

1 = When the OSS signal is asserted, the corresponding channel is powered off.

0 = OSS signal has no impact on the channel.

DCUT4-DCUT1 R/W

0

2-Pair PCUT disable for each channel. Used to prevent removal of the associated

channel’s power due to a 2-Pair PCUT fault, regardless of the programming status of the

Timing Configuration register. Note that there is still monitoring of ILIM faults.

3–0

1: Channel’s PCUT is disabled. This means that an PCUT fault alone will not turn off this

channel.

0: Channel’s PCUT is enabled. This enables channel turn off if there is PCUT fault.

SPACE

备注

If the MbitPrty bit = 1 (0x17h): The OSSn bits must be cleared to ensure proper operation. Refer to

registers 0x27/28h for more information on the Multi-bit priority shutdown feature.

备注

If DCUT = 1 for a channel, the channel will not be automatically turned off during a PCUT fault

condition. However, the PCUT fault flag will still be operational, with a fault timeout equal to t_OVLD

.

Any change in the state of DCUTn bits will result in the resetting of the T_OVLDtimer for that channel.

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The OSSn bits are used to determine which channels are shut down in response to an external assertion of the

OSS fast shutdown signal.

The turn off procedure due to OSS is similar to a channel reset or change to OFF mode, with the exception that

OSS does not cancel any ongoing fault cool down timers. the table below includes the bits that will be cleared

when a channel is disabled due to OSS:

表9-22. Channel Turn Off with OSS

Register

0x04

Bits to be reset

CLSCn and DETCn

DISFn and PCUTn

0x06

0x08

STRTn and ILIMn

0x0C-0F

0x10

Requested Class and Detection

PGn and PEn

0x14

CLEn and DETEn

0x1C

ACn

0x1E-21

0x24

2P Policing set to 0xFFh

PFn

0x30-3F

0x40

Channel Voltage and Current Measurements

2xFBn

0x44 - 47

0x4C-4F

0x51-54

Detection Resistance Measurements

Assigned Class and Previous Class

Autoclass Measurement

SPACE

备注

it may take upwards of 5 ms before all of the registers are cleared following an OSS event.

Only the bits associated with the channel/port ("n") with OSS enabled will be cleared. Those bits associated with

channels/ports remaining in operation will not be changed.

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9.6.2.18 TIMING CONFIGURATION Register

COMMAND = 16h with 1 Data Byte, Read/Write

Bit Descriptions: These bits define the timing configuration for all four channels.

图9-23. TIMING CONFIGURATION Register Format

7

6

5

4

3

2

1

0

TLIM

TSTART

TOVLD

TMPDO

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-23. TIMING CONFIGURATION Register Field Descriptions

Bit

Field

Type Reset

Description

TLIM

R/W 0

ILIM fault timing, which is the output current limit time duration before channel turn off.

7 –6

When a 2xFBn bit in register 0x40 = 0, the t_LIMused for the associated channel is always the

nominal value (about 60 ms).

This timer is active and increments to the settings defined below after expiration of the TSTART

time window and when the channel is limiting its output current to I_LIM. If the ILIM counter is allowed

to reach the programmed time-out duration specified below, the channel will be powered off. The 1-

second cool down timer is then started, and the channel can not be turned-on until the counter has

reached completion.

In other circumstances (ILIM time-out has not been reached), while the channel current is below

I_LIM, the same counter decrements at a rate 1/16th of the increment rate. The counter does not

decrement below zero. The ILIM counter is also cleared in the event of a turn off due to a Power

Enable or Reset command, a DC disconnect event or the OSS input.

Note that in the event the TLIM setting is changed while this timer is already active for a channel,

this timer is automatically reset then restarted with the new programmed time-out duration.

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically

restarted if the detect enable bit is set. Also note that the cool down time count is immediately

canceled with a reset command, or if the OFF or Manual mode is selected.

If 2xFBn bit is asserted in register 0x40, then t_LIMfor associated channel is programmable with the

following selection:

TLIM

Minimum t_LIM(ms)

0

1

0

1

0

1

58

15

10

6

5-4 TSTART

(or

R/W

0

START fault timing, which is the maximum allowed overcurrent time during inrush. If at the end of

TSTART period the current is still limited to I_Inrush, the channel is powered off.

This is followed by a 1-second cool down period, during which the channel can not be turned-on

TINRUSH)

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically

restarted if the class and detect enable bits are set.

Note that in the event the TSTART setting is changed while this timer is already active for a

channel, this new setting is ignored and will be applied only next time the channel is turned ON.

The selection is as following:

TSTART

Nominal t_START(ms)

0

1

0

1

0

1

60

30

120

Reserved

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表9-23. TIMING CONFIGURATION Register Field Descriptions (continued)

Bit

Field

Type Reset

Description

TOVLD

R/W 0

PCUT fault timing, which is the overcurrent time duration before turn off. This timer is active and

increments to the settings defined below after expiration of the TSTART time window and when the

current meets or exceeds P_CUT, or when it is limited by the current foldback. If the PCUT counter is

allowed to reach the programmed time-out duration specified below, the channel will be powered

off. The 1-second cool down timer is then started, and the channel can not be turned-on until the

counter has reached completion.

3–2

In other circumstances (PCUT time-out has not been reached), while the current is below P_CUT, the

same counter decrements at a rate 1/16th of the increment rate. The counter does not decrement

below zero. The PCUT counter is also cleared in the event of a turn off due to a Power Enable or

Reset command, a DC disconnect event or the OSS input

Note that in the event the TOVLD setting is changed while this timer is already active for a channel,

this timer is automatically reset then restarted with the new programmed time-out duration.

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically

restarted if the detect enable bit is set. Also note that the cool down time count is immediately

canceled with a reset command, or if the OFF or Manual mode is selected.

Note that if a DCUTn bit is high in the Power Priority/PCUT Disable register, the PCUT fault timing

for the associated channel is still active. However, even though the channel will not be turned off

when the tOVLD time expires, the PCUT fault bits will still be set.

The selection is as following:

TOVLD

Nominal t_OVLD(ms)

0

1

0

1

0

1

60

30

120

240

TMPDO

R/W

0

Disconnect delay, which is the time to turn off a channel once there is a disconnect condition, and if

the dc disconnect detect method has been enabled.

1–0

The TDIS counter is reset each time the current goes continuously higher than the disconnect

threshold for nominally 15 ms.

The counter does not decrement below zero.

The selection is as following:

TMPDO

Nominal t_MPDO(ms)

0

1

0

1

0

1

360

90

180

SPACE

备注

The PGn and PEn bits (Power Status register) are cleared when there is a TLIM, TOVLD, TMPDO, or

TSTART fault condition.

备注

The settings for t_LIMset the minimum timeout based on the IEEE compliance requirements.

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9.6.2.19 GENERAL MASK Register

COMMAND = 17h with 1 Data Byte, Read/Write

图9-24. GENERAL MASK Register Format

7

6

5

4

3

2

1

0

INTEN

R/W-1

nbitACC

R/W-0

MbitPrty

R/W-0

CLCHE

R/W-0

DECHE

R/W-0

–

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-24. GENERAL MASK Register Field Descriptions

Bit

Field

Type Reset Description

7

INTEN

R/W

1

INT pin mask bit. Writing a 0 will mask any bit of Interrupt register from activating the INT

output, whatever the state of the Interrupt Mask register. Note that activating INTEN has no

impact on the event registers.

1 = Any unmasked bit of Interrupt register can activate the INT output

0 = INT output cannot be activated

6

5

R/W

0

–

nbitACC

I²C Register Access Configuration bit.

1 = Configuration B. This means 16-bit access with a single device address (A0 = 0).

0 = Configuration A. This means 8-bit access, while the 8-channel device is treated as 2

separate 4-channel devices with 2 consecutive target addresses.

See register 0x11 for more information on the I2C address programming

4

MbitPrty

R/W

0

Multi Bit Priority bit. Used to select between 1-bit shutdown priority and 3-bit shutdown

priority.

1 = 3-bit shutdown priority. Register 0x27 and 0x28 need to be followed for priority and OSS

action.

0 = 1-bit shutdown priority. Register 0x15 needs to be followed for priority and OSS action

3

2

CLCHE

DECHE

R/W

0

Class change Enable bit. When set, the CLSCn bits in Detection Event register only

indicates when the result of the most current classification operation differs from the result

of the previous one.

1 = CLSCn bit is set only when a change of class occurred for the associated channel.

0 = CLSCn bit is set each time a classification cycle occurred for the associated channel.

Detect Change Enable bit. When set, the DETCn bits in Detection Event register only

indicates when the result of the most current detection operation differs from the result of

the previous one.

1 = DETCn bit is set only when a change in detection occurred for the associated channel.

0 = DETCn bit is set each time a detection cycle occurred for the associated channel.

1

0

R/W

0

–

SPACE

备注

If the MbitPrty bit needs to be changed from 0 to 1, make sure the OSS input pin is in the idle (low)

state for a minimum of 200 µsec prior to setting the MbitPrty bit, to avoid any misbehavior related to

loss of synchronization with the OSS bit stream.

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备注

Only the nbitACC bit for channels 1-4 needs to be set to enable 16-bit I²C operation.

表9-25. nbitACC = 1: Register Operations in 8-Bit (Config A) and 16-bit (Config B) I²C Mode

Cmd

Code

Register or Command

Bits Description

Configuration A (8-bit)

Configuration B (16-bit)

Name

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

INTERRUPT

INT bits P1-4, P5-8

Separate mask and interrupt result per group of 4 channels.

The Supply event bit is repeated twice.

INTERRUPT MASK

POWER EVENT

MSK bits P1-4, P5-8

PGC_PEC P4-1, P8-5

DETECTION EVENT

FAULT EVENT

CLS_DET P4-1, P8-5

DIS_PCUT P4-1, P8-5

ILIM_STR P4-1, P8-5

Separate event byte per group of 4 channels.

START/ILIM EVENT

Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same results for TSD,

TSD, VDUV, VDUW, VPUV ,

RAMFLT OSSE4-1, OSSE8-5 group of 4 channels.

Clearing at least one VPUV/VDUV also clears the other one.

VDUV, VPUV and RAMFLT. The PCUTxx and OSSEx bits will. have separate status per

SUPPLY/FAULT EVENT

0Bh

CHANNEL 1

DISCOVERY

0Ch

0Dh

0Eh

CLS&DET1_CLS&DET5

CLS&DET2_CLS&DET6

CLS&DET3_CLS&DET7

CHANNEL 2

DISCOVERY

Separate Status byte per channel

CHANNEL 3

DISCOVERY

CHANNEL 4

DISCOVERY

0Fh

10h

CLS&DET4_CLS&DET8

PG_PE P4-1, P8-5

POWER STATUS

Separate status byte per group of 4 channels

Both 8-bit registers (channel 1 to 4 and

channel 5 to 8) will show the same result,

except that A0 = 0 (channel 1 to 4) or 1

(channel 5 to 8).

Both 8-bit registers (channel 1 to 4 and

channel 5 to 8) will show the same result,

including A0 = 0.

11h

PIN STATUS

A4-A1,A0

12h

13h

OPERATING MODE

MODE P4-1, P8-5

Separate Mode byte per group of 4 channels.

DISCONNECT ENABLE DCDE P4-1, P8-5

Separate DC disconnect enable byte per group of 4 channels.

Separate Detect/Class Enable byte per group of 4 channels.

DETECT/CLASS

CLE_DETE P4-1, P8-5

ENABLE

14h

15h

PWRPR/2P-PCUT

OSS_DCUT P4-1, P8-5

DISABLE

Separate OSS/DCUT byte per group of 4 channels.

Separate Timing byte per group of 4 channels.

TLIM_TSTRT_TOVLD_TMPD

O P4-1,

P8-5

16h

17h

TIMING CONFIG

Separate byte per group of 4 channels.

n-bit access: Setting this in at least one of the virtual quad register space is enough to

enter Config B mode. To go back to config A, clear both.

MbitPrty: Setting this in at least one of the virtual quad register space is enough to enter 3-

bit shutdown priority. To go back to 1-bit shutdown, clear both MbitPrty bits.

P4-1, P8-5 including n-bit

access

GENERAL MASK

18h

19h

DETECT/CLASS Restart RCL_RDET P4-1, P8-5

Separate DET/CL RST byte per group of 4 channels

Separate POF/PWON byte per group of 4 channels

POWER ENABLE

POF_PWON P4-1, P8-5

P4-1, P8-5

Separate byte per group of 4 channels, Clear Separate byte per group of 4 channels.

Int pin and Clear All int.

1Ah RESET

Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result unless

1Bh ID

modified through I²C.

1Ch AUTOCLASS

AC4-1, AC8-5

Separate byte per group of 4 channels.

1Eh 2P POLICE 1/5 CONFIG POL1, POL5

1Fh 2P POLICE 2/6 CONFIG POL2, POL6

Separate Policing byte per channel.

20h

21h

2P POLICE 3/7 CONFIG POL3, POL7

2P POLICE 4/8 CONFIG POL4, POL8

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表9-25. nbitACC = 1: Register Operations in 8-Bit (Config A) and 16-bit (Config B) I²C Mode (continued)

Cmd

Code

Register or Command

Name

Bits Description

Configuration A (8-bit)

Configuration B (16-bit)

22h

24h

25h

CAP MEASUREMENT

CDET4-1, CDET8-5

Separate capacitance measurement enable bytes per group of 4 channels.

Separate Power-on FAULT byte per group of 4 channels

Power-on FAULT

PF P4-1, P8-5

Separate Remapping byte per group of 4 channels.

26h

PORT REMAPPING

Logical P4-1, P8-5

Reinitialized only if POR or RESET pin. Kept unchanged if 0x1A IC reset or CPU watchdog

reset.

27h

28h

Multi-Bit Priority 21 / 65

Multi-Bit Priority 43 / 87

MBP2-1, MBP6-5

MBP4-3, MBP8-7

Separate MBP byte per group of 2 channels

PORT POWER

ALLOCATION

29h

MC34-12, MC78-56

TEMP P1-4, P5-8

Separate MCnn byte per group of 4 channels

2Ch TEMPERATURE

Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result.

2Eh

INPUT VOLTAGE

2Fh

VPWR P1-4, P5-8

Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result.

Separate 2-byte per group of 4 channels.

30h

Separate 2-byte per group of 4 channels

2-byte Read at 0x30 gives I1

4-byte Read at 0x30 gives I1, I5.

CHANNEL 1 CURRENT I1, I5

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

N/A

2-byte Read at 0x31 gives I5.

2-byte Read at 0x32 gives V1

4-byte Read at 0x32 gives V1, V5.

Separate 2-byte per group of 4 channels

CHANNEL 1 VOLTAGE

V1, V5

N/A

2-byte Read at 0x33 gives V5.

2-byte Read at 0x34 gives I2

4-byte Read at 0x34 gives I2, I6.

Separate 2-byte per group of 4 channels

CHANNEL 2 CURRENT I2, I6

N/A

2-byte Read at 0x35 gives I6.

2-byte Read at 0x36 gives V2

4-byte Read at 0x36 gives V2, V6.

Separate 2-byte per group of 4 channels

CHANNEL 2 VOLTAGE

V2, V6

N/A

2-byte Read at 0x37 gives V6.

2-byte Read at 0x38 gives I3

4-byte Read at 0x38 gives I3, I7.

Separate 2-byte per group of 4 channels

CHANNEL 3 CURRENT I3, I7

N/A

2-byte Read at 0x39 gives I7.

2-byte Read at 0x3A gives V3

4-byte Read at 0x3A gives V3, V7.

Separate 2-byte per group of 4 channels

CHANNEL 3 VOLTAGE

V3, V7

N/A

2-byte Read at 0x3B gives V7.

2-byte Read at 0x3C gives I4

4-byte Read at 0x3C gives I4, I8.

Separate 2-byte per group of 4 channels

CHANNEL 4 CURRENT I4, I8

N/A

2-byte Read at 0x3D gives I8.

2-byte Read at 0x3E gives V4

4-byte Read at 0x3E gives V4, V8.

Separate 2-byte per group of 4 channels

N/A

CHANNEL 4 VOLTAGE

V4, V8

2-byte Read at 0x3F gives V8.

OPERATIONAL

FOLDBACK

2xFB4-1, 2xFB8-5

FRV P1-4, P5-8

Separate 2xFBn config byte per group of 4 channels.

FIRMWARE REVISION

I2C WATCHDOG

DEVICE ID

Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result.

IWD3-0: if at least one of the two 4-port settings is different than 1011b, the watchdog is

enabled for all 8 channels.

42h

P1-4, P5-8

WDS: Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same WDS

result. Each WDS bit needs to be cleared individually through I²C.

43h

44h

DID_SR P1-4, P5-8

RDET1, RDET5

Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result .

CHANNEL 1

RESISTANCE

CHANNEL 2

RESISTANCE

45h

46h

47h

RDET2, RDET6

RDET3, RDET7

RDET4, RDET8

Separate byte per channel.

Detection resistance always updated, detection good or bad.

CHANNEL 3

RESISTANCE

CHANNEL 4

RESISTANCE

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表9-25. nbitACC = 1: Register Operations in 8-Bit (Config A) and 16-bit (Config B) I²C Mode (continued)

Cmd

Code

Register or Command

Name

Bits Description

Configuration A (8-bit)

Configuration B (16-bit)

CHANNEL 1 ASSIGNED

CLASS

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

ACLS&PCLS1_ACLS&PCLS5

ACLS&PCLS2_ACLS&PCLS6

ACLS&PCLS3_ACLS&PCLS7

ACLS&PCLS4_ACLS&PCLS8

CHANNEL 2 ASSIGNED

CLASS

Separate Status byte per channel

CHANNEL 3 ASSIGNED

CLASS

CHANNEL 4 ASSIGNED

CLASS

MAC4-1, AAC4-1, MAC8-5,

AAC8-5

AUTOCLASS CONTROL

Separate Auto Class control bytes per 4 channels

AUTOCLASS POWER

1/5

PAC1, PAC5

PAC2, PAC6

PAC3, PAC7

PAC4, PAC8

AUTOCLASS POWER

2/6

Separate Auto Class Power Measurement byte per channel

Separate Alternative Foldback byte per group of 4 channels

AUTOCLASS POWER

3/7

AUTOCLASS POWER

4/8

ALTERNATIVE

FOLDBACK

ALTFB4-1, ALTIR4-1,

ALTFN8-5, ALTIR8-5

These bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have

no functionality for the upper virtual quad (A0=1, Ch 5-8) device

60h

61h

62h

SRAM CONTROL

SRAM DATA

SRAM CNTRL BITS

Streaming data input is independent of I²C configuration

These bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have

no functionality for the upper virtual quad (A0=1, Ch 5-8) device

START ADDRESS (LSB)

These bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have

no functionality for the upper virtual quad (A0=1, Ch 5-8) device

63h

START ADDRESS (MSB)

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9.6.2.20 DETECT/CLASS RESTART Register

COMMAND = 18h with 1 Data Byte, Write Only

Push button register.

Each bit corresponds to a particular cycle (detect or class restart) per channel. Each cycle can be individually

triggered by writing a 1 at that bit location, while writing a 0 does not change anything for that event.

In Diagnostic/Manual mode, a single cycle (detect or class restart) will be triggered when these bits are set while

in semiauto mode, it sets the corresponding bit in the Detect/Class Enable register 0x14.

A Read operation will return 00h.

During t_OVLD, t_LIMor t_STARTcool down cycle, any Detect/Class Restart command for that channel will be

accepted but the corresponding action will be delayed until end of cool-down period.

图9-25. DETECT/CLASS RESTART Register Format

7

6

5

4

3

2

1

0

RCL4

W-0

RCL3

W-0

RCL2

W-0

RCL1

W-0

RDET4

W-0

RDET3

W-0

RDET2

W-0

RDET1

W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表9-26. DETECT/CLASS RESTART Register Field Descriptions

Bit

Field

Type Reset Description

W

0

Restart classification bit

Restart detection bits

7–4

3–0

RCL4–RCL1

RDET4–RDET1

SPACE

These bits may be used in place of completing a "Read-Modify-Write" sequence in register 0x14 to enable

detection and classification on a per channel basis.

9.6.2.21 POWER ENABLE Register

COMMAND = 19h with 1 Data Byte, Write Only

Push button register.

Used to initiate a channel(s) turn on or turn off in any mode except OFF mode.

图9-26. POWER ENABLE Register Format

7

6

5

4

3

2

1

0

POFF4

W-0

POFF3

W-0

POFF2

W-0

POFF1

W-0

PWON4

W-0

PWON3

W-0

PWON2

W-0

PWON1

W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表9-27. POWER ENABLE Register Field Descriptions

Bit

Field

Type Reset Description

W

0

Channel power off bits

Channel power on bits

7–4

3–0

POFF4–POFF1

PWON4–PWON1

SPACE

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备注

Writing a “1” at POFFn and PWONn on same Channel during the same write operation turns the

Channel off.

备注

The t_OVLD, t_LIM, t_STARTand disconnect events have priority over the PWON command. During t_OVLD

,

t_LIMor t_START, cool down cycle, any channel turn on using Power Enable command will be ignored and

the Channel will be kept off.

PWONn in Diagnostic/Manual Mode:

If the PSE controller is configured in Diagnostic mode, writing a “1” at that PWONn bit location will

immediately turn on the associated Channel.

SPACE

PWONn in Semiauto Mode:

While in semiauto mode, writing a “1” at a PWONn bit will attempt to turn on the associated Channel. If the

detection or class results are invalid, the Channel is not turned on, and there will be no additional attempts to

turn on the Channel until this push button is reasserted and the channel will resume its configured semiauto

mode operation.

备注

In semiauto mode, the Power Allocation (0x29h) value needs to be set prior to issuing a PWON

command. Any changes to the Power Allocation value after a PWON command is given may be

ignored.

表9-28. Channel Response to PWONn Command in Semiauto Mode

CLEn

DETEn

Channel Operation

Result of PWONn Command

Singular Turn On attempted with Full DET

and CLS cycle

0

Idle

Singular Turn On attempted with Full DET

and CLS cycle

0

1

0

1

Cycling Detection Measurements only

Idle

Singular Turn On attempted with Full DET

and CLS cycle

Cycling Detection and Classification

Measurements

Singular Turn On attempted after next (or

current) DET and CLS cycle

In semiauto mode with DETE and CLE set, as long as the PWONx command is received prior to the start of

classification, the Channel will be powered immediately after classification is complete provided the classification

result is valid and the power allocations settings (see register 0x29h) are sufficient to enable power on.

SPACE

PWONn in Auto Mode:

In auto mode with DETE or CLE set to 0, a PWONx command will initiate a singular detection and classification

cycle and the port/channel will be powered immediately after classification is complete provided the classification

result is valid and the power allocations settings (see register 0x29h) are sufficient to enable power on.

In auto mode with DETE and CLE = 1, there is no need for a PWON command. The port/channel will

automatically attempt to turn on after each detection and classification cycle.

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备注

In auto mode, the Power Allocation (0x29h) value needs to be set prior to issuing a PWON command.

Any changes to the Power Allocation value after a PWON command is given may be ignored.

表9-29. Channel Response to PWONn Command in Auto Mode

CLEn

DETEn

Channel Operation

Result of PWONn Command

Singular Turn On attempted with Full DET

and CLS cycle

0

Idle

Singular Turn On attempted with Full DET

and CLS cycle

0

1

0

1

Cycling Detection Measurements only

Idle

Singular Turn On attempted with Full DET

and CLS cycle

Cycling Detection and Classification

Measurements

NA - Channel will power automatically after a

valid detection and classification

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PWOFFn in any Mode:

The channel is immediately disabled and the following registers are cleared:

表9-30. Channel Turn Off with PWOFFn Command

Register

0x04

Bits to be Reset

CLSCn and DETCn

DISFn and PCUTn

0x06

0x08

STRTn and ILIMn

0x0C-0F

0x10

Requested Class and Detection

PGn and PEn

0x14

CLEn and DETEn

0x1C

ACn

0x1E-21

0x24

2P Policing set to 0xFFh

PFn

0x30-3F

0x40

Channel Voltage and Current Measurements

2xFBn

0x44 - 47

0x4C-4F

0x51-54

Detection Resistance Measurements

Assigned Class and Previous Class

Autoclass Measurement

备注

It may take upwards of 5ms after PWOFFn command for all register values to be updated.

Only the bits associated with the channel/port ("n") with PWOFFn set will be cleared. Those bits associated with

channels/ports remaining in operation will not be changed.

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9.6.2.22 RESET Register

COMMAND = 1Ah with 1 Data Byte, Write Only

Push button register.

Writing a 1 at a bit location triggers an event while a 0 has no impact. Self-clearing bits.

图9-27. RESET Register Format

7

6

5

4

3

2

1

0

CLRAIN

W-0

CLINP

W-0

RESAL

W-0

RESP4

W-0

RESP3

W-0

RESP2

W-0

RESP1

W-0

–

W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表9-31. RESET Register Field Descriptions

Bit

Field

Type Reset Description

7

CLRAIN

W

0

Clear all interrupts bit. Writing a 1 to CLRAIN clears all event registers and all bits in the

Interrupt register. It also releases the INT pin

6

CLINP

W

When set, it releases the INT pin without any impact on the Event registers nor on the

Interrupt register.

5

4

W

0

–

RESAL

Reset all bits when RESAL is set. Results in a state similar to a power-up reset. Note that

the VDUV and VPUV bits (Supply Event register) follow the state of VDD and VPWR supply

rails.

W

0

Reset channel bits. Used to force an immediate channel(s) turn off in any mode, by writing a

1 at the corresponding RESPn bit location(s).

3–0

RESP4–RESP1

Setting the RESAL bit will result in all of the I2C register being restored to the RST condition with the exception

of those in the following table:

Register

0x00

Bits

RESAL Result

All

0x0A/B

TSD, VPUV, VDWRN, and VPUV

0x26

All

Pre RESAL value will remain

0x2C and 0x2E

0x41

备注

Setting the RESAL bit for only one group of four channels (1-4 or 5-8) will result in only those four

channels being reset.

备注

After using the CLINP command, the INT pin will not be reasserted for any interrupts until all existing

interrupts have been cleared.

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Setting the RESPn bit will immediate turn off the associated channel and clear the registers according to the

following table:

表9-32. Channel Turn Off with RESPn Command

Register

0x04

Bits to be Reset

CLSCn and DETCn

DISFn and PCUTn

0x06

0x08

STRTn and ILIMn

0x0C-0F

0x10

Requested Class and Detection

PGn and PEn

0x14

CLEn and DETEn

0x1C

ACn

0x1E-21

0x24

2P Policing set to 0xFFh

PFn

0x30-3F

0x40

Channel Voltage and Current Measurements

2xFBn

0x44 - 47

0x4C-4F

0x51-54

Detection Resistance Measurements

Assigned Class and Previous Class

Autoclass Measurement

SPACE

备注

Only the bits associated with the channel/port ("n") with RESPn set will be cleared. Those bits

associated with channels/ports remaining in operation will not be changed.

it may take upwards of 5 ms before all of the registers are cleared following a RESPn command.

The RESPn command will cancel any ongoing cool down cycles .

Users need to wait at least 3ms before trying to reenable discovery or power on ports following a

RESPn command.

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9.6.2.23 ID Register

COMMAND = 1Bh with 1 Data Byte, Read/Write

图9-28. ID Register Format

7

6

5

4

3

2

1

0

MFR ID

R/W-0

ICV

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-33. ID Register Field Descriptions

Bit

Field

Type Reset Description

MFR ID

R/W 01010 Manufacture Identification number (0101,0)

b

7–3

ICV

R/W

101b IC version number (011)

2–0

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9.6.2.24 Connection Check and Auto Class Status Register

COMMAND = 1Ch with 1 Data Byte, Read Only

图9-29. Connection Check and Auto Class Register Format

7

6

5

4

3

2

1

0

AC4

R-0

AC3

R-0

AC2

R-0

AC1

R-0

Rsvrd

R-0

Rsvrd

R-0

Rsvrd

R-0

Rsvrd

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-34. Connection Check and Auto Class Field Descriptions

Bit

Field

Type Reset Description

ACn

R

0000b Auto Class Detection Status

1 = PD supports Auto Class

7–4

0 = PD does not support Auto Class

3-0

Rsvrd

R

00b Reserved

Auto Class:

The auto class detection measurement is completed at the end of the long classification finger, and if a PD is

determined to support auto class, an auto class power measurement will be automatically completed after turn

on in accordance with the IEEE auto class timing requirements.

备注

An Auto Class power measurement will be completed shortly after power on for all channels that are

found to support auto class during classification.

These measurement results are available in registers (0x51h – 0x54h), and the auto class power

measurements are provide per individual channel.

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9.6.2.25 2-Pair Police Ch-1 Configuration Register

COMMAND = 1Eh with 1 Data Byte, Read/Write

图9-30. 2-Pair Police Ch-1 Register Format

7

6

5

4

3

2

1

0

POL1_7

R/W-1

POL1_6

R/W-1

POL1_5

R/W-1

POL1_5

R/W-1

POL1_3

R/W-1

POL1_2

R/W-1

POL1_1

R/W-1

POL1_0

R/W1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.26 2-Pair Police Ch-2 Configuration Register

COMMAND = 1Fh with 1 Data Byte, Read/Write

图9-31. 2-Pair Police Ch-2 Register Format

7

6

5

4

3

2

1

0

POL2_7

R/W-1

POL2_6

R/W-1

POL2_5

R/W-1

POL2_4

R/W-1

POL2_3

R/W-1

POL2_2

R/W-1

POL2_1

R/W-1

POL2_0

R/W1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.27 2-Pair Police Ch-3 Configuration Register

COMMAND = 20h with 1 Data Byte, Read/Write

图9-32. 2-Pair Police Ch-3 Register Format

7

6

5

4

3

2

1

0

POL3_7

R/W-1

POL3_6

R/W-1

POL3_5

R/W-1

POL3_5

R/W-1

POL3_3

R/W-1

POL3_2

R/W-1

POL3_1

R/W-1

POL3_0

R/W1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.28 2-Pair Police Ch-4 Configuration Register

COMMAND = 21h with 1 Data Byte, Read/Write

图9-33. 2-Pair Police Ch-4 Register Format

7

6

5

4

3

2

1

0

POL4_7

R/W-1

POL4_6

R/W-1

POL4_5

R/W-1

POL4_4

R/W-1

POL4_3

R/W-1

POL4_2

R/W-1

POL4_1

R/W-1

POL4_0

R/W1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-35. 2-Pair Policing Register Fields Descriptions

Bit

Field

Type Reset Description

POLn_7-

POLn_0

R/W

1

1-byte defining 2-Pair P_CUTminimum threshold.

The equation defining the P_CUTis:

7–0

P_CUT= (N × PC_STEP

)

Where, when assuming 0.200-ΩRsense resistor is used:

PC_STEP= 0.5 W

SPACE

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备注

These bits set the minimum threshold for the design. Internally, the typical PCUT threshold is set

slightly above this value to ensure that the device does not trip a Pcut fault at or below the set value in

this register due to part to part or temperature variation.

The contents of this register is reset to 0xFFh anytime the port is turned off or disabled either due to

fault condition or user command

备注

Programmed values of less than 2W are not supported. If a value of less than 2W is programmed into

these registers, the device will use 2W as the 2-pair Policing value.

SPACE

Power Policing:

The TPS23882B implements a true Power Policing limit, where the device will adjust the policing limit based on

both voltage and current variation in order to ensure a reliable power limit.

In semiauto and auto modes, these bits are automatically set during power on based on the assigned class (see

tables below). If an alternative value is desired, it needs to be set after the PEn bit is set in 0x10h, or it may also

be configured prior to port turn on in combination with the use of the MPOLn bits in register 0x40 (see 节

9.6.2.45).

表9-36. 2-Pair Policing Settings based on the Assigned Class

Assigned Class

POLn7-0 Settings

Minimum Power

Class 1

0000 1000

4W

7W

Class 2

0000 1110

Class 3

0001 1111

15.5W

30W

Class 4

0011 1100

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9.6.2.29 Capacitance (Legacy PD) Detection

COMMAND = 22h with 1 Data Byte, Write Only

Used to do enable capacitance measurement from Maunal mode

图9-34. Capacitance Detection Register Format

7

-

6

5

4

3

2

1

-

0

CDET4

R/W-0

-

CDET3

R/W-0

-

CDET2

R/W-0

CDET1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表9-37. Capacitance Detection Register Field Descriptions

Bit

Field

Type Reset Description

7, 5, 3, Reserved

1

R/W

0

6, 4, 2, CDETn

0

Enables Capacitance defection for channel "n"

0 = Capacitance defection disabled

1 = Capacitance detection enabled

To complete a capacitance measurement on a channel, the channel must first be placed into diagnostic mode.

Set the bits in register 0x22h to enable capacitance detection on the channel(s) desired. Then set the DETE bits

in register 0x14h to begin the detection and process.

备注

The TPS23882B SRAM needs to be programmed in order for the capacitance measurement to

operate properly.

The capacitance measurement is only supported in Manual/Diagnostic mode.

No capacitance measurement will be made if the result of the resistance detection is returned as

"valid".

Upon completion of the capacitance measurement the DETCn bit will bet in register 0x04h, and the resistance

and capacitance values will be updated in registers 0x44h - 0x4Bh.

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9.6.2.30 Power-on Fault Register

COMMAND = 24h with 1 Data Byte, Read Only

COMMAND = 25h with 1 Data Byte, Clear on Read

图9-35. Power-on Fault Register Format

7

6

5

4

3

2

1

0

PF4

PF3

PF2

PF1

R-0

CR-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; CR = Clear on Read; -n = value after reset

表9-38. Power-on Fault Register Field Descriptions

Bit Field

Type

Reset

Description

R or CR

0

Represents the fault status of the classification and detection for channel n, following a failed turn

on attempt with the PWONn command. These bits are cleared when channel n is turned off.

7– PF4–PF1

0

PFn: the selection is as follows:

Fault Code

Power-on Fault Description

No fault

0

1

0

1

0

1

Invalid detection

Classification Error

Insufficient Power

SPACE

备注

When a Start Fault occurs and the PECn bit is not set, then this register will indicate the cause of the

fault.

An insufficient power fault is reported anytime the reg 0x29 configuration will not allow a channel to be

powered. See the section describing 节9.1.5.

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9.6.2.31 PORT RE-MAPPING Register

COMMAND = 26h with 1 Data Byte, Read/Write

图9-36. PORT RE-MAPPING Register Format

7

6

5

4

3

2

1

0

Physical Channel # of Logical

Channel 4

Physical Channel # of Logical

Channel 3

Physical Channel # of Logical

Channel 2

Physical Channel # of Logical

Channel 1

R/W-1

R/W-0

R/W-1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; CR = Clear on Read; -n = value after reset

表9-39. PORT RE-MAPPING Register Field Descriptions

Bit

POR /

RST

Field

Type

Description

Physical

Channel # of

Logical

R/W

1110 Used to re-map channels logically due to physical board constraints. Re-mapping is between any

0100b / channel within 4-channel group (1-4 or 5-8). All channels of a group of four must be in OFF mode

7–

0

P

prior to receiving the port re-mapping command, otherwise the command will be ignored. By

default there is no re-mapping.

Channel n

Each pair of bits corresponds to the logical port assigned.

The selection per port is as follows:

Physical

Channel

Re-Map Code

Package Pins

0

1

0

1

0

1

2

3

4

Drain1,Gat1,Sen1

Drain2,Gat2,Sen2

Drain3,Gat3,Sen3

Drain4,Gat4,Sen4

When there is no re-mapping the default value of this register is 1110,0100. The 2 MSbits with a

value 11 indicate that logical channel 4 is mapped onto physical channel #4, the next 2 bits, 10,

suggest logical channel 3 is mapped onto physical channel #3 and so on.

Note: Code duplication is not allowed –that is, the same code cannot be written into the

remapping bits of more than one port –if such a value is received, it will be ignored and the chip

will stay with existing configuration.

Note: Port remapping configuration is kept unchanged if 0x1A IC reset command is received.

SPACE

备注

The RST condition of "P" indicates that the previous state of these bits will be preserved following a

device reset using the RESET pin. Thus, pulling the RESET input low will not overwrite any user

changes to this register.

备注

After port remapping, TI recommends to do at least one detection-classification cycle before turn on.

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9.6.2.32 Channels 1 and 2 Multi Bit Priority Register

COMMAND = 27h with 1 Data Byte, Read/Write .

图9-37. Channels 1 and 2 MBP Register Format

7

6

5

4

3

2

1

0

MBP2_2

R/W-0

MBP2_1

R/W-0

MBP2_0

R/W-0

MBP1_2

R/W-0

MBP1_1

R/W-0

MBP1_0

R/W–0

–

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.33 Channels 3 and 4 Multi Bit Priority Register

COMMAND = 28h with 1 Data Byte, Read/Write

图9-38. Channels 3 and 4 MBP Register Format

7

6

5

4

3

2

1

0

MBP4_2

R/W-0

MBP4_1

R/W-0

MBP4_0

R/W-0

MBP3_2

R/W-0

MBP3_1

R/W-0

MBP3_0

R/W–0

–

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-40. Channels n MBP Register Field Descriptions

Bit Field

Type Reset Description

MBPn_2-0 R/W

0

MBPn_2-0: Multi Bit Priority bits, three bits per channel, if 3-bit shutdown priority has been selected

(MbitPrty in General Mask register is high). It is used to determine which channel(s) is (are) shut down

in response to a serial shutdown code received at the OSS shutdown input.

7–0

The turn off procedure (including register bits clearing) is similar to a channel reset using Reset

command (1Ah register), except that it does not cancel any ongoing fault cool down time count.

The priority is defined as followings:

OSS code ≤MBPn_2-0 : when the OSS code is received, the corresponding channel is powered off.

OSS code > MBPn_2-0 : OSS code has no impact on the channel

MBPn_2-0 0x27/28

Multi Bit Priority OSS Code for Channel Off

Register

0

1

0

1

0

1

0

1

0

1

0

1

Highest

OSS = ‘000’

2

OSS = ‘000’or ‘001’

OSS ≤‘010’

3

4

OSS ≤‘011’

4

OSS ≤‘100’

6

OSS = any code except ‘111’

OSS = any code

Lowest

The priority reduces as the 3-bit value increases. Thus, a channel with a "000" setting has the highest priority,

while one with a "111" setting has the lowest.

It is permissible to apply the same settings to multiple channels. Doing so will result in all channels with the same

setting will be disabled when the appropriate OSS code is presented.

The turn off procedure due to OSS is similar to a channel reset or change to OFF mode, with the exception that

OSS does not cancel any ongoing fault cool down timers. the table below includes the bits that will be cleared

when a channel is disabled due to OSS:

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表9-41. Channel Turn Off with MBP OSS

Register

0x04

Bits to be Reset

CLSCn and DETCn

DISFn and PCUTn

0x06

0x08

STRTn and ILIMn

0x0C-0F

0x10

Requested Class and Detection

PGn and PEn

0x14

CLEn and DETEn

0x1C

ACn

0x1E-21

0x24

2P Policing set to 0xFFh

PFn

0x30-3F

0x40

Channel Voltage and Current Measurements

2xFBn

0x44 - 47

0x4C-4F

0x51-54

Detection Resistance Measurements

Assigned Class and Previous Class

Autoclass Measurement

SPACE

备注

There is no memory of any preceding 3-bit OSS commands. Each 3-bit OSS command is processed

immediately (prior to the end of the last OSS MBP pulse) based on the MBPn settings for each

Channel. Any attempt to shutdown additional Channels thereafter will require additional 3-bit OSS

commands.

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9.6.2.34 Port Power Allocation Register

COMMAND = 29h with 1 Data Byte, Read/Write

图9-39. Power Allocation Register Format

7

6

5

4

3

2

1

0

Rsvrd

R/W-0

MC34_2

R/W-0

MC34_1

R/W-0

MC34_0

R/W-0

Rsvrd

R/W-0

MC12_2

R/W-0

MC12_1

R/W-0

MC12_0

R/W–0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-42. Power Allocation Register Field Descriptions

Bit Field

Type

R/W

Reset Description

7 , 3 Rsvrd

0

Reserved

6 - 4 , MCnn_2-0

2 - 0

MCnn_2-0: Port Power Allocation bits. These bits set the maximum power classification level that

a given channel is allowed to power on

In semiauto mode these bits need to be set prior to issuing a PWONn command, while in auto

mode these bits need to be set prior to setting the DETE and CLE bits in 0x14.

表9-43. Power Allocation Settings

MCnn_2

MCnn_1

MCnn_0

Power Allocation

2-Pair 15.4W

2-Pair 4 W

0

1

0

1

x

0

1

0

1

x

2-Pair 7 W

2-Pair 30W

Reserved

SPACE

备注

The Power Allocation (0x29h) value needs to be set prior to issuing a PWON command in semiauto or

auto modes, and prior to setting the DETE and CLE bits in auto mode. Any changes to the Power

Allocation value after a PWON command is given may be ignored.

备注

For 2-Pair wired ports, the MCnn_2-0 bits set the power allocation settings for both channels 1 and 2

and 3 and 4 concurrently.

It is possible to have channels 3 and 4 set to 15.4W while channels 1 and 2 are set to 30W, but it is

not possible to have different power allocation settings between channels 1 and 2 or 3 and 4

备注

Setting register 0x29 to the 4 W Power Allocation configuration will only allow Class 1 PDs to be

powered. Attempts to power any other class PDs will result in an insufficient power fault

Setting register 0x29 to the 7 W Power Allocation configuration will only allow Class 1 & 2 PDs to be

powered. Attempts to power a class 3 or 4+ PDs will result in an insufficient power fault

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9.6.2.35 TEMPERATURE Register

COMMAND = 2Ch with 1 Data Byte, Read Only

图9-40. TEMPERATURE Register Format

7

6

5

4

3

2

1

0

TEMP7

R-0

TEMP6

R-0

TEMP5

R-0

TEMP4

R-0

TEMP3

R-0

TEMP2

R-0

TEMP1

R-0

TEMP0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-44. TEMPERATURE Register Field Descriptions

Bit

Field

Type

Reset

Description

R

0

Bit Descriptions: Data conversion result. The I²C data transmission is a 1-byte transfer.

8-bit Data conversion result of temperature, from –20°C to 125°C. The update rate is

around once per second.

7–0 TEMP7–TEMP0

The equation defining the temperature measured is:

T = –20 + N × T_STEP

Where T_STEPis defined below as well as the full scale value:

Mode

Full Scale Value

T_STEP

Any

146.2°C

0.652°C

84

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9.6.2.36 INPUT VOLTAGE Register

COMMAND = 2Eh with 2 Data Byte (LSByte first, MSByte second), Read only

图9-41. INPUT VOLTAGE Register Format

7

6

5

4

3

2

1

0

LSB:

VPWR7

R-0

VPWR6

R-0

VPWR5

R-0

VPWR4

R-0

VPWR3

R-0

VPWR2

R-0

VPWR1

R-0

VPWR0

R-0

MSB:

VPWR13

R-0

VPWR12

R-0

VPWR11

R-0

VPWR10

R-0

VPWR9

R-0

VPWR8

R-0

–

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-45. INPUT VOLTAGE Register Field Descriptions

Bit

Field

Type Reset

Description

VPWR13- VPWR0

R

0

Bit Descriptions: Data conversion result. The I²C data transmission is a 2-byte transfer.

14-bit Data conversion result of input voltage.

13–0

The equation defining the voltage measured is:

V = N × V_STEP

Where V_STEPis defined below as well as the full scale value:

Mode

Full Scale Value V_STEP

60 V 3.662 mV

Any

Note that the measurement is made between VPWR and AGND.

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9.6.2.37 CHANNEL 1 CURRENT Register

COMMAND = 30h with 2 Data Byte, (LSByte First, MSByte second), Read Only

图9-42. CHANNEL 1 CURRENT Register Format

7

6

5

4

3

2

1

0

LSB:

MSB:

I1_7

R-0

I1_6

R-0

I1_5

R-0

I1_4

R-0

I1_3

R-0

I1_2

R-0

I1_1

R-0

I1_0

R-0

I1_13

R-0

I1_12

R-0

I1_11

R-0

I1_10

R-0

I1_9

R-0

I1_8

R-0

–

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.38 CHANNEL 2 CURRENT Register

COMMAND = 34h with 2 Data Byte, (LSByte First, MSByte second), Read Only

图9-43. CHANNEL 2 CURRENT Register Format

7

6

5

4

3

2

1

0

LSB:

MSB:

I2_7

R-0

I2_6

R-0

I2_5

R-0

I2_4

R-0

I2_3

R-0

I2_2

R-0

I2_1

R-0

I2_0

R-0

I2_13

R-0

I2_12

R-0

I2_11

R-0

I2_10

R-0

I2_9

R-0

I2_8

R-0

–

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.39 CHANNEL 3 CURRENT Register

COMMAND = 38h with 2 Data Byte, (LSByte First, MSByte second), Read Only

图9-44. CHANNEL 3 CURRENT Register Format

7

6

5

4

3

2

1

0

LSB:

MSB:

I3_7

R-0

I3_6

R-0

I3_5

R-0

I3_4

R-0

I3_3

R-0

I3_2

R-0

I3_1

R-0

I3_0

R-0

I3_13

R-0

I3_12

R-0

I3_11

R-0

I3_10

R-0

I3_9

R-0

I3_8

R-0

–

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.40 CHANNEL 4 CURRENT Register

COMMAND = 3Ch with 2 Data Byte, (LSByte First, MSByte second), Read Only

图9-45. CHANNEL 4 CURRENT Register Format

7

6

5

4

3

2

1

0

LSB:

I4_7

R-0

I4_6

R-0

I4_5

R-0

I4_4

R-0

I4_3

R-0

I4_2

R-0

I4_1

R-0

I4_0

R-0

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MSB:

图9-45. CHANNEL 4 CURRENT Register Format (continued)

I4_13

R-0

I4_12

R-0

I4_11

R-0

I4_10

R-0

I4_9

R-0

I4_8

R-0

–

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-46. CHANNEL n CURRENT Register Field Descriptions

Bit Field

Type

Reset

Description

13-0 In_13- In_0

R

0

Bit Descriptions: Data conversion result. The I²C data transmission is a 2-byte transfer.

Note that the conversion is done using a TI proprietary multi-slope integrating converter.

14-bit Data conversion result of current for channel n. The update rate is around once per 100 ms

in powered state.

The equation defining the current measured is:

I = N × I_STEP

Where I_STEPis defined below as well as the full scale value, according to the operating mode:

Mode

Full Scale Value

I_STEP

Powered and

Classification

1.46 A (with 0.2-Ω

Rsense)

89.5 µA

Note: in any of the following cases, the result through I²C interface is automatically 0000

channel is in OFF mode

channel is OFF while in semiauto mode and detect/class is not enabled

channel is OFF while in semiauto mode and detection result is incorrect

In diagnostic/manual mode, if detect/class has been enabled at least once, the register retains the

result of the last measurement

SPACE

备注

1.46A is the theoretical full scale range of the ADC based on 14bits * Istep. However, due to the 1.25A

channel current limit, the channel current will foldback and be disabled when the current exceeds the

ILIM-2X threshold (V_LIM2X).

SPACE

Class Current Reading

Following the completion of any classification measurement on a channel, the measured classification current is

reported in these registers until either a port current reading is completed following a port turn on or the port is

disabled.

备注

The scaling factor for the class current reading is decreased by a factor of 10x to 8.95uA/bit.

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9.6.2.41 CHANNEL 1 VOLTAGE Register

COMMAND = 32h with 2 Data Byte, (LSByte First, MSByte second), Read Only

图9-46. CHANNEL 1 VOLTAGE Register Format

7

6

5

4

3

2

1

0

LSB:

MSB:

V1_7

R-0

V1_6

R-0

V1_5

R-0

V1_4

R-0

V1_3

R-0

V1_2

R-0

V1_1

R-0

V1_0

R-0

V1_13

R-0

V1_12

R-0

V1_11

R-0

V1_10

R-0

V1_9

R-0

V1_8

R-0

–

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.42 CHANNEL 2 VOLTAGE Register

COMMAND = 36h with 2 Data Byte, (LSByte First, MSByte second), Read Only

图9-47. CHANNEL 2 VOLTAGE Register Format

7

6

5

4

3

2

1

0

LSB:

V2_7

R-0

V2_6

R-0

V2_5

R-0

V2_4

R-0

V2_3

R-0

V2_2

R-0

V2_1

R-0

V2_0

R-0

MSB:

V2_13

R-0

V2_12

R-0

V2_11

R-0

V2_10

R-0

V2_9

R-0

V2_8

R-0

–

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.43 CHANNEL 3 VOLTAGE Register

COMMAND = 3Ah with 2 Data Byte, (LSByte First, MSByte second), Read Only

图9-48. CHANNEL 3 VOLTAGE Register Format

7

6

5

4

3

2

1

0

LSB:

V3_7

R-0

V3_6

R-0

V3_5

R-0

V3_4

R-0

V3_3

R-0

V3_2

R-0

V3_1

R-0

V3_0

R-0

MSB:

V3_13

R-0

V3_12

R-0

V3_11

R-0

V3_10

R-0

V3_9

R-0

V3_8

R-0

–

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.44 CHANNEL 4 VOLTAGE Register

COMMAND = 3Eh with 2 Data Byte, (LSByte First, MSByte second), Read Only

图9-49. CHANNEL 4 VOLTAGE Register Format

7

6

5

4

3

2

1

0

LSB:

V4_7

R-0

V4_6

R-0

V4_5

R-0

V4_4

R-0

V4_3

R-0

V4_2

R-0

V4_1

R-0

V4_0

R-0

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MSB:

图9-49. CHANNEL 4 VOLTAGE Register Format (continued)

V4_13

R-0

V4_12

R-0

V4_11

R-0

V4_10

R-0

V4_9

R-0

V4_8

R-0

–

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-47. CHANNEL n VOLTAGE Register Field Descriptions

Bit

Field

Type

Reset

Description

13-0 Vn_13- Vn_0

R

0

Bit Descriptions: Data conversion result. The I²C data transmission is a 2-byte transfer.

The equation defining the voltage measured is:

V = N × V_STEP

Where V_STEPis defined below as well as the full scale value:

Mode

Full Scale Value

V_STEP

Powered

60 V

3.662 mV

Note that a powered voltage measurement is made between VPWR and DRAINn.

Note: if a channel is OFF, the result through I²C interface is automatically 0000.

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9.6.2.45 2x FOLDBACK SELECTION Register

COMMAND = 40h with1 Data Byte Read/Write

图9-50. 2x FOLDBACK SELECTION Register Format

7

6

5

4

3

2

1

0

2xFB4

R/W-0

2xFB3

R/W-0

2xFB2

R/W-0

2xFB1

R/W-0

MPOL4

R/W -0

MPOL3

R/W -0

MPOL2

R/W -0

MPOL1

R/W -0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-48. 2x FOLDBACK SELECTION Register Field Descriptions

Bit

Field

Type Reset

Description

2xFB4- 2xFB1

R/W 0

When set, this activates the 2x Foldback mode for a channel which increases its I_LIMand

I_SHORTlevels normal settings, as shown in 图9-3. Note that the fault timer starts when the I_LIM

threshold is exceeded.

7–4

Notes:

1)

At turn on, the inrush current profile is unaffected by these bits, as shown in 图9-2.

2) When a 2xFBn bit is deasserted, the t_LIMsetting used for the associated channel is always

the nominal value (approximately 60 ms). If 2xFBn bit is asserted, then t_LIMfor associated

channel is programmable as defined in the Timing Configuration register (0x16).

3) If the assigned class for a channel is class 4 or above, the 2xFB bit will be automatically

set during turn on.

3-0 MPOL4 -

MPOL1

R/W

0

Manual Policing and Foldback configuration bits

0 = The internal device firmware automatically adjusts the Policing (P_CUT) and 2xFBn settings

based on the assigned class during port turn on

1 = The Policing (P_CUT) and 2xFBn settings will not be changed during port turn on.

Note: Independent of these settings, the Policing (P_CUT) and 2xFBn settings are returned to

their default values upon port turn off.

Note: Setting either bit for a 4P configured port disables the automatic configuration on both

channels

The MPOLn bits are cleared upon port turn off.

备注

Refer to register 0x55h description for more information on additional Foldback and Inrush

configuration options

0.5

1.3

1.2

1.1

1

2xFBn =0, ALTFBn = 0

2xFBn =0, ALTFBn = 1

2xFBn =1, ALTFBn = 0

2xFBn =1, ALTFBn = 1

0.475

0.45

0.425

0.4

0.375

0.35

0.325

0.3

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.275

0.25

0.225

0.2

0.175

0.15

0.125

0.1

0.075

0.05

0.025

0

3

6

9

12

15

18

21

24

27 30

V_DRAIN(V)

33

36

39

42

45

48

51

54

57

D201

0

3

6

9

12

15

18

21

24

27 30

V_DRAIN(V)

33

36

39

42

45

48

51

54

57

D202

图9-51. 1x Mode (2xFBn = 0) Foldback Curves,

图9-52. 2x Mode (2xFBn = 1) Foldback Curves,

I_PORTvs V_DRAIN

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9.6.2.46 FIRMWARE REVISION Register

COMMAND = 41h with 1 Data Byte, Read Only

图9-53. FIRMWARE REVISION Register Format

7

6

5

4

3

2

1

0

FRV

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-49. FIRMWARE REVISION Register Field Descriptions

Bit

Field

Type Reset Description

FRV

R

Firmware Revision number

7–0

After a RESET or POR fault this value will default to 0000, 0000b, but upon a “valid” SRAM load, this value

will reflect the corresponding SRAM version of firmware (0x01h –0xFEh).

备注

If the value of this register = 0xFFh, the device is running in “safe mode”, and the SRAM needs to

be reprogrammed to resume normal operation.

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9.6.2.47 I2C WATCHDOG Register

COMMAND = 42h with 1 Data Byte, Read/Write

The I²C watchdog timer monitors the I²C clock line in order to prevent hung software situations that could leave

ports in a hazardous state. The timer can be reset by either edge on SCL input. If the watchdog timer expires, all

channels will be turned off and WDS bit will be set. The nominal watchdog time-out period is 2 seconds.

图9-54. I2C WATCHDOG Register Format

7

6

5

4

3

2

1

0

IWDD3

R/W-1

IWDD2

R/W-0

IWDD1

R/W-1

IWDD0

R/W-1

WDS

R/W-0

–

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-50. I2C WATCHDOG Register Field Descriptions

Bit

Field

Type Reset Description

I²C Watchdog disable. When equal to 1011b, the watchdog is masked. Otherwise, it is

umasked and the watchdog is operational.

R/W 1011b

4–1

IWDD3–IWDD0

0

WDS

R/W

0

I²C Watchdog timer status, valid even if the watchdog is masked. When set, it means that

the watchdog timer has expired without any activity on I²C clock line. Writing 0 at WDS

location clears it.

Note that when the watchdog timer expires and if the watchdog is unmasked, all channels

are also turned off.

When the channels are turned OFF due to I²C watchdog, the corresponding bits are also cleared:

表9-51. I2C WATCHDOG Reset

Register

0x04

Bits to be Reset

CLSCn and DETCn

DISFn and PCUTn

0x06

0x08

STRTn and ILIMn

0x0C-0F

0x10

Requested Class and Detection

PGn and PEn

0x14

CLEn and DETEn

0x1C

ACn

0x1E-21

0x24

2P Policing set to 0xFFh

PFn

0x30-3F

0x40

Channel Voltage and Current Measurements

2xFBn

0x44 - 47

0x4C-4F

0x51-54

Detection Resistance Measurements

Assigned Class and Previous Class

Autoclass Measurement

The corresponding PGCn and PECn bits of Power Event register will also be set if there is a change. The

corresponding PEn and PGn bits of Power Status Register are also updated accordingly.

备注

If the I²C watchdog timer has expired, the Temperature and Input voltage registers will stop being

updated until the WDS bit is cleared. The WDS bit must then be cleared to allow these registers to

work normally.

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9.6.2.48 DEVICE ID Register

COMMAND = 43h with 1 Data Byte, Read Only

图9-55. DEVICE ID Register Format

7

6

5

4

3

2

1

0

DID

SR

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-52. DEVICE ID Register Field Descriptions

Bit

Field

DID

SR

Type Reset Description

R

0011b Device ID number

7–5

4–0

0100b Silicon Revision number

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9.6.2.49 CHANNEL 1 DETECT RESISTANCE Register

COMMAND = 44h with 1 Data Byte, Read Only

图9-56. CHANNEL 1 DETECT RESISTANCE Register Format

7

6

5

4

3

2

1

0

R1_7

R-0

R1_6

R-0

R1_5

R-0

R1_4

R-0

R1_3

R-0

R1_2

R-0

R1_1

R-0

R1_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.50 CHANNEL 2 DETECT RESISTANCE Register

COMMAND = 45h with 1 Data Byte, Read Only

图9-57. CHANNEL 2 DETECT RESISTANCE Register Format

7

6

5

4

3

2

1

0

R2_7

R-0

R2_6

R-0

R2_5

R-0

R2_4

R-0

R2_3

R-0

R2_2

R-0

R2_1

R-0

R2_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.51 CHANNEL 3 DETECT RESISTANCE Register

COMMAND = 46h with 1 Data Byte, Read Only

图9-58. CHANNEL 3 DETECT RESISTANCE Register Format

7

6

5

4

3

2

1

0

R3_7

R-0

R3_6

R-0

R3_5

R-0

R3_4

R-0

R3_3

R-0

R3_2

R-0

R3_1

R-0

R3_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.52 CHANNEL 4 DETECT RESISTANCE Register

COMMAND = 47h with 1 Data Byte, Read Only

图9-59. CHANNEL 4 DETECT RESISTANCE Register Format

7

6

5

4

3

2

1

0

R4_7

R-0

R4_6

R-0

R4_5

R-0

R4_4

R-0

R4_3

R-0

R4_2

R-0

R4_1

R-0

R4_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-53. DETECT RESISTANCE Register Fields Descriptions

Bit

Field

Type

Reset

Description

7-0

Rn_7- Rn_0

R

0

8-bit data conversion result of detection resistance for channel n.

Most recent 2-point Detection Resistance measurement result. The I²C data transmission is a 1-byte transfer.

Note that the register content is not cleared at turn off.

The equation defining the resistance measured is:

R = N × R_STEP

Where R_STEPis defined below as well as the full scale value:

Useable Resistance Range

R_STEP

2 kΩto 50 kΩ

195.3125 Ω

94

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9.6.2.53 CHANNEL 1 DETECT CAPACITANCE Register

COMMAND = 48h with 1 Data Byte, Read Only

图9-60. CHANNEL 1 DETECT CAPACITANCE Register Format

7

6

5

4

3

2

1

0

C1_7

R-0

C1_6

R-0

C1_5

R-0

C1_4

R-0

C1_3

R-0

C1_2

R-0

C1_1

R-0

C1_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.54 CHANNEL 2 DETECT CAPACITANCE Register

COMMAND = 49h with 1 Data Byte, Read Only

图9-61. CHANNEL 2 DETECT CAPACITANCE Register Format

7

6

5

4

3

2

1

0

C2_7

R-0

C2_6

R-0

C2_5

R-0

C2_4

R-0

C2_3

R-0

C2_2

R-0

C2_1

R-0

C2_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.55 CHANNEL 3 DETECT CAPACITANCE Register

COMMAND = 4Ah with 1 Data Byte, Read Only

图9-62. CHANNEL 3 DETECT CAPACITANCE Register Format

7

6

5

4

3

2

1

0

C3_7

R-0

C3_6

R-0

C3_5

R-0

C3_4

R-0

C3_3

R-0

C3_2

R-0

C3_1

R-0

C3_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.56 CHANNEL 4 DETECT CAPACITANCE Register

COMMAND = 4Bh with 1 Data Byte, Read Only

图9-63. CHANNEL 4 DETECT CAPACITANCE Register Format

7

6

5

4

3

2

1

0

C4_7

R-0

C4_6

R-0

C4_5

R-0

C4_4

R-0

C4_3

R-0

R4_2C

R-0

C4_1

R-0

C4_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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表9-54. DETECT CAPACITANCE Register Fields Descriptions

Bit

Field

Type

Reset

Description

7-0

Cn_7- Cn_0

R

0

8-bit data conversion result of capacitance measurement for channel n.

Most recent capacitance measurement result. The I²C data transmission is a 1-byte transfer.

The equation defining the resistance measured is:

C = N × C_STEP

Where C_STEPis defined below as well as the full scale value:

Useable Resistance Range

C_STEP

1 µF to 12 µF

0.05 µF

Note that the register content is not cleared at turn off.

Note: The capacitance measurement is only supported in Manual/Diagnostic mode.

Note: No capacitance measurement will be made if the result of the resistance detection is

returned as "valid".

Note: The TPS23882B SRAM needs to be programmed in order for the capacitance

measurement to operate properly.

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9.6.2.57 CHANNEL 1 ASSIGNED CLASS Register

COMMAND = 4Ch with 1 Data Byte, Read Only

图9-64. CHANNEL 1 ASSIGNED CLASS Register Format

7

6

5

4

3

2

1

0

ACLASS Ch1

PCLASS Ch1

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.58 CHANNEL 2 ASSIGNED CLASS Register

COMMAND = 4Dh with 1 Data Byte, Read Only

图9-65. CHANNEL 2 ASSIGNED CLASS Register Format

7

6

5

4

3

2

1

0

ACLASS Ch2

PCLASS Ch2

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.59 CHANNEL 3 ASSIGNED CLASS Register

COMMAND = 4Eh with 1 Data Byte, Read Only

图9-66. CHANNEL 3 ASSIGNED CLASS Register Format

7

6

5

4

3

2

1

0

ACLASS Ch3

PCLASS Ch3

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.60 CHANNEL 4 ASSIGNED CLASS Register

COMMAND = 4Fh with 1 Data Byte, Read Only

图9-67. CHANNEL 4 ASSIGNED CLASS Register Format

7

6

5

4

3

2

1

0

ACLASS Ch4

PCLASS Ch4

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Bit Descriptions: These bits represent the "assigned" and previous classification results for channel n. These

bits are cleared when channel n is turned off.

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表9-55. CHANNEL n ASSIGNED CLASS Register Field Descriptions

Bit Field

Type Reset

Description

ACLASS

Ch-n

R

0

Assigned classification on channel n.

7–4

See 表9-56 below

PCLASS

Ch-n

R

Previous Class result on channel n.

3–0

See 表9-57 below

表9-56. Assigned Class Designations

ACLASS-Chn

Assigned Class

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Unknown

Class 1

0

1

0

1

0

Class 2

0

1

Class 3

0

1

0

Class 4

0

1

0

1

Reserved

0

1

0

1

X

表9-57. Previous Class Designations

PCLASS-Chn

Previous Class

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Unknown

0

1

Class 1

0

1

0

Class 2

0

1

Class 3

0

1

0

Class 4

0

1

0

1

Reserved

0

1

0

Class 0

0

1

Reserved

1

0

Class 5 - 4-Pair

Class 6 - 4-Pair

Class 7 - 4-Pair

Class 8 - 4-Pair

Reserved

1

0

1

0

1

0

1

0

1

X

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“Requested”vs. “Assigned”Classification:

The “requested” class is the classification the PSE measures during Mutual Identification prior to turn on,

whereas the “assigned”class is the classification level the Channel was powered on with based on the Power

Allocation setting in register 0x29h. The “requested”classification values are available in registers 0x0C-0F

备注

Upon being powered, devices that present a class 0 signature during discovery will be given an

assigned class of "Class 3"

备注

There is no Assigned Class assigned for ports/channels powered out of Manual/Diagnostic mode. Any

settings such as the port power policing and 1x/2x foldback selection that are typically configure based

on the assigned class result need to manually configured by the user.

Previous Classification

In certain circumstances the requested class result in 0x0C-0F can not properly reflect the actual classification of

the PD connected to the port/channel. This will happen when a port has a power allocation limit of 15.4W and

the PSE can only provide 1 classification finger during turn on. When this occurs and if the device is configured

to run in semiauto mode with det and cls enabled, the 3-finger classification measurement that preceded the turn

on detection and classification cycle will be stored here. This information can be useful in scenarios where a port

had to be demoted to stay under the system power limit at turn on but additional power budget comes available

later on.

备注

The Previous Classification results are only valid for channels being used in semiauto mode with

ongoing discovery (DETE and CLE = 1).

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9.6.2.61 AUTO CLASS CONTROL Register

COMMAND = 50h with 1 Data Byte, Read/Write

图9-68. AUTO CLASS CONTROL Register Format

7

6

5

4

3

2

1

0

MAC4

R/W-0

MAC3

R/W-0

MAC2

R/W-0

MAC1

R/W-0

AAC4

R/W-0

AAC3

R/W-0

AAC2

R/W-0

AAC1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-58. AUTO CLASS CONTROL Register Field Descriptions

Bit

Field

Type Reset Description

7 - 4

MACn

R/W

0

Manual Auto Class Measurement bits

1 = Manual Auto Class Measurement enabled

0 = Manual Auto Class measurement complete

The auto class measurement will begin within 10ms of this bit being set.

This bit will be cleared by the internal firmware within 1ms of the updated Autoclass

measurement result(s) in 0x51-54h.

3 -0

AACn

R/W

0

Auto Class Auto Adjustment Enable bits

1 = Autoclass auto adjust is enabled and the corresponding PCUT settings will be

automatically adjusted based on the measured autoclass power

0 = Autoclass auto adjust is disabled and it is up to the user to adjust the value of PCUT as

desired.

SPACE

备注

Any MACn bits set prior to turn on will be ignored and cleared during turn on.

Auto Class Pcut Adjustments:

If the ACx bit(s) are set in register 0x50h, the TPS23882B will automatically adjust its PCUT value based on the

auto class power measurement (P_ACin registers 0x51-54) and Any Automatic Auto Class facilitated (AACn = 1)

PCut adjustments will be made within 5 ms of the end of the auto class measurement period.

SPACE

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9.6.2.62 CHANNEL 1 AUTO CLASS POWER Register

COMMAND = 51h with 1 Data Byte, Read Only

图9-69. CHANNEL 1 AUTO CLASS POWER Register Format

7

-

6

5

4

3

2

1

0

PAC1_6

R-0

PAC1_5

R-0

PAC1_4

R-0

PAC1_3

R-0

PAC1_2

R-0

PAC1_1

R-0

PAC1_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.63 CHANNEL 2 AUTO CLASS POWER Register

COMMAND = 52h with 1 Data Byte, Read Only

图9-70. CHANNEL 2 AUTO CLASS POWER Register Format

7

-

6

5

4

3

2

1

0

PAC2_6

R-0

PAC2_5

R-0

PAC2_4

R-0

PAC2_3

R-0

PAC2_2

R-0

PAC2_1

R-0

PAC2_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.64 CHANNEL 3 AUTO CLASS POWER Register

COMMAND = 53h with 1 Data Byte, Read Only

图9-71. CHANNEL 3 AUTO CLASS POWER Register Format

7

-

6

5

4

3

2

1

0

PAC3_6

R-0

PAC3_5

R-0

PAC3_4

R-0

PAC3_3

R-0

PAC3_2

R-0

PAC3_1

R-0

PAC3_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.65 CHANNEL 4 AUTO CLASS POWER Register

COMMAND = 54h with 1 Data Byte, Read Only

图9-72. CHANNEL 4 AUTO CLASS POWER Register Format

7

-

6

5

4

3

2

1

0

PAC4_6

R-0

PAC4_5

R-0

PAC4_4

R-0

PAC4_3

R-0

PAC4_2

R-0

PAC4_1

R-0

PAC4_0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-59. AUTO CLASS POWER Register Fields Descriptions

Bit

Field

Type

Reset

Description

6-0

PACn_6-

PACn_0

R

0

8-bit data conversion result of the auto class power measurement for channel n.

Peak average power calculation result from channel voltage and current data conversion

measurements taken during the auto class power measurement window.

The equation defining the auto class power measured is:

P_AC= N × P_{AC_STEP}

Where, when assuming 0.200-ΩRsense resistor is used:

PC_STEP= 0.5 W

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9.6.2.66 ALTERNATIVE FOLDBACK Register

COMMAND = 55h with 1 Data Byte, Read/Write

图9-73. ALTERNATIVE FOLDBACK Register Format

7

6

5

4

3

2

1

0

ALTFB4

R/W-0

ALTFB3

R/W-0

ALTFB2

R/W-0

ALTFB1

R/W-0

ALTIR4

R/W-0

ALTIR3

R/W-0

ALTIR2

R/W-0

ALTIR1

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-60. ALTERNATIVE FOLDBACK Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

ALTFBn

R

0

Alternative Foldback Enable bits: Used to enable the operational alterative foldback curves while powered.

1 = Alternative Foldback is enabled

0 = Alternative Foldback is disabled

The ALTFBn bits should be set prior to issuing a PWONn command to ensure the desired foldback curve is

being used.

3-0

ALTIRn

R

0

Alternative Inrush Enable bits: Used to enable the alterative foldback curves during inrush on channel n

1 = Alternative Inrush is enabled

0 = Alternative Inrush is disabled

Note: The ALTIRn bits need to be set prior to sending a PWONn command to ensure the desired inrush

behavior is followed

SPACE

0.5

0.475

0.45

0.425

0.4

1.3

2xFBn =0, ALTFBn = 0

2xFBn =0, ALTFBn = 1

2xFBn =1, ALTFBn = 0

2xFBn =1, ALTFBn = 1

1.2

1.1

1

0.375

0.35

0.325

0.3

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.275

0.25

0.225

0.2

0.175

0.15

0.125

0.1

0.075

0.05

0.025

0

3

6

9

12

15

18

21

24

27 30

V_DRAIN(V)

33

36

39

42

45

48

51

54

57

D201

0

3

6

9

12

15

18

21

24

27 30

V_DRAIN(V)

33

36

39

42

45

48

51

54

57

D202

图9-74. 1x Mode (2xFBn = 0) Foldback Curves,

图9-75. 2x Mode (2xFBn = 1) Foldback Curves,

I_PORTvs V_DRAIN

0.55

ALTIRn = 0

ALTIRn = 1

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

3

6

9

12

15

18

21

24

27 30

V_PORT(V)

33

36

39

42

45

48

51

54

57

D100

图9-76. Inrush Foldback Curves, I_PORTvs V_PORT

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9.6.2.67 SRAM CONTROL Register

COMMAND = 60h with 1 Data Byte, Read/Write

图9-77. SRAM CONTROL Register Format

7

6

5

4

3

2

1

0

PROG_SEL

R/W-0

CPU_RST

R/W-0

-

PAR_EN

R/W-0

RAM_EN

R/W-0

PAR_SEL

R/W-0

R/WZ

R/W-0

CLR_PTR

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-61. SRAM CONTROL Register Field Descriptions

Bit

Field

Type Reset Description

7

PROG_SEL

R/W

0

I2C Programming select bit.

1 = SRAM I2C read/write is enabled

0 = SRAM I2C read/write is disabled.

6

CPU_RST

R/W

0

CPU Reset bit

1 = Internal CPU is held in RESET

0 = Internal CPU is active

This is strictly a CPU reset. Toggling this bit reset the cpu only and will not change any

contents of the I²C registers

5

4

Reserved

PAR_EN

R/W

0

Reserved

SRAM Parity Enable bit:

1 = SRAM Parity Check will be enabled

0 = SRAM Parity Check will be disabled

It is recommended that the Parity function be enable whenever SRAM is being used

3

RAM_EN

R/W

0

SRAM Enable bit

1 = SRAM will be enabled and the internal CPU will run from both SRAM and internal ROM

0 = Internal CPU will run from internal ROM only

This bit needs to be set to a 1 after SRAM programing to enable the utilization of the SRAM

code

2

1

PAR_SEL

R/WZ

R/W

0

SRAM Parity Select bit: Setting this bit to a 1 in conjunction with the RZ/W bit enables

access to the SRAM Parity bits.

1 = Parity bits read/write is enabled

0 = Parity bits read/write is disabled

SRAM Read/Write select bit:

0 = SRAM Write –SRAM data is written with a write to 0x61h

1 = SRAM Read –SRAM data is read with a read from 0x61h

SRAM data can be continuously read/written over I2C until a STOP bit is sent.

0

CLR_PTR

R/W

0

Clear Address Pointer bit:

1 = Resets the memory address pointer

0 = Releases pointer for use

In order to ensure proper programming, this bit should be toggled (0-1-0) to writing or

reading the SRAM or Parity memory.

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9.6.2.67.1 SRAM START ADDRESS (LSB) Register

COMMAND = 62h with 1 Byte, Read/Write

图9-78. SRAM START ADDRESS (LSB) Register Format

7

6

5

4

3

2

1

0

SA_7

R/W-0

SA_6

R/W-0

SA_5

R/W-0

SA_4

R/W-0

SA_3

R/W-0

SA_2

R/W-0

SA_1

R/W-0

SA_0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.67.2 SRAM START ADDRESS (MSB) Register

COMMAND = 63h with 1 Byte, Read/Write

图9-79. SRAM START ADDRESS (MSB) Register Format

7

6

5

4

3

2

1

0

SA_15

R/W-0

SA_14

R/W-0

SA_13

R/W-0

SA_12

R/W-0

SA_11

R/W-0

SA_10

R/W-0

SA_9

R/W-0

SA_8

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

9.6.2.67.3

表9-62. SRAM START ADDRESS Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0 SA_15- SA_0

R/W

0

SRAM and Parity Programing Start Address bits:

the value entered into these registers sets the start address location for the SRAM or Parity

programming

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SRAM Programming:

Upon power up, it is recommended that the TPS23882B device's SRAM be programmed with the latest version

of SRAM code via the I²C to ensure proper operation and IEEE complaint performance. All I²C traffic other than

those commands required to program the SRAM should be deferred until after the SRAM programming

sequences are completed.

备注

The latest version of firmware and SRAM release notes may be accessed from the TI mySecure

Software webpage.

The SRAM Release Notes and ROM Advisory document includes more detailed information regarding

any know issues and changes that were associated with each firmware release.

备注

The SRAM programming control must be completed at the lower I2C address (Channels 1-4, A0 = 0).

Configuring this registers for the upper I2C device address (Channels 5-8) will not program the SRAM

For systems that include multiple TPS23882B devices, the 0x7F "global" broadcast I2C address may

be used to programmed all of the devices at the same time.

备注

The SRAM programming needs to be delayed at least 50ms from the initial power on (VPWR and

VDD above UVLO) of the device to allow for the device to complete its internal hardware initialization

process

备注

For more detailed instructions on the SRAM programing procedures please refer the How to Load

TPS2388x SRAM Code document on TI.com.

SPACE

0x60h setup for SRAM Programming: Prior to programming/writing the SRAM, the following bits sequence

needs to be completed in register 0x60h:

7

6

5

-

4

PAR_EN

0

3

RAM_EN

0

2

PAR_SEL

0

1

0

PROG_SEL

0 →1

CPU_RST

0 →1

R/WZ

1 →0

CLR_PTR

0 →1 →0

0

The same sequence is required to read the SRAM with the exception that the R/WZ bit needs to be set to “1”.

If the device is in “Safe Mode”, the same sequence as above may be used to reprogram the SRAM.

An I²C write to 0x61h following this sequence actively programs the SRAM program memory starting from the

address set in registers 0x62h and 63h.

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0x60h setup for SRAM Parity Programming: Following the programming of the SRAM program memory, the

following bits sequence needs to be completed in register 0x60h in order to configure the device to program the

Parity memory:

7

6

5

-

4

PAR_EN

0

3

RAM_EN

0

2

1

0

PROG_SEL

0 →1

CPU_RST

0 →1

PAR_SEL

0 →1

R/WZ

1 →0

CLR_PTR

0 →1 →0

0

The same sequence is required to read the Parity with the exception that the R/WZ bit needs to be set to “1".

An I²C write to 0x61h following this sequence actively programs the Parity memory starting from the address set

in registers 0x62h and 63h.

SPACE

0x60h setup to run from SRAM Program Memory: Upon completion of programming, the following bits

sequence needs to be completed in register 0x60h in order to enable the device to run properly out of SRAM:

7

6

5

-

4

3

2

1

R/WZ

0

CLR_PTR

0

PROG_SEL

1 →0

CPU_RST

1 →0

PAR_EN

0 →1

RAM_EN

0 →1

PAR_SEL

1 →0

0

Within 1ms of the completion of the above sequence, the device will complete a compatibility check on the

SRAM

If the SRAM load is determined to be “Valid”: Register 0x41h will have a value between 0x01h and 0xFEh,

and the device will return to normal operation.

If the SRAM load is determined to be “Invalid”:

•0x41h will be set to 0xFFh

•The RAM_EN bit will be internally cleared

•The device will operating in “safe mode”until another programming attempt is completed

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10 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

The TPS23882B is an 8-channel, IEEE 802.3bt ready PoE PSE controller and can be used in high port count

semiauto or fully micro-controller managed applications (TI recommends the MSP430FR5969 micro-controller

for most applications). Subsequent sections describe detailed design procedures for applications with different

requirements including host control.

The schematic of 图 10-1 depicts semiauto mode operation of the TPS23882B, providing functionality to power

PoE loads. The TPS23882B can do the following:

1. Performs load detection

2. Performs classification including the 100-ms long finger for Autoclass discovery and 80.23bt reduce T_MPS

support

3. Enables power on with protective foldback current limiting, and port power policing (P_CUT) value

4. Shuts down in the event of fault loads and shorts

5. Performs Maintain Power Signature function to insure removal of power if load is disconnected

6. Undervoltage lockout occurs if VPWR falls below V_{PUV_F}(typical 26.5 V)

Following a power-off command, disconnect or shutdown due to a Start, P_CUTor I_LIMfault, the port powers down.

Following port power off due to a disconnect, the TPS23882B immediates restart the detection and classification

cycles if the DETE and CLE bits are set in register 0x14. If the shutdown is due to a start, P_CUTor I_LIMfault, the

TPS23882B enters into a cool-down period during which any Detect/Class Enable Command for that port is

delayed. At the end of cool down cycle, one or more detection/class cycles are automatically restarted if the

class and/or detect enable bits are set. If a port is disabled using the power off command, the DETE and CLE

bits are cleared and these bits must be reset over I²C for detection and classification to resume.

10.1.1 Autonomous Operation

Unlike Auto mode, which still requires a host to initialize the TPS23882B operation through a a series of I²C

commands, there is no host or I²C communication required when the TPS23882B in configured in autonomous

mode.

Connecting a resistor between the AUTO pin and GND based on the table below 表 10-1 enables autonomous

mode and configure all of the ports to the same Power Allocation settings. In the event a PD is connected with a

higher requested class than the autonomous mode configuration, the port powers demote the PD to the selected

autonomous mode configuration power level. The port automatically performs detection and classification (if

valid detection occurs) continuously on all ports. Port power is automatically turned on based on Power

Allocation settings in register 0x29 if a valid classification is measured.

表10-1. AUTO Pin Programming

Auto Pin

Open/Floating

124 kΩ

Autonomous Mode Configuration

Disabled

2-pair 15 W

2-pair 30 W

62 kΩ

SPACE

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备注

A 10-nF capacitor is required in parallel with R_AUTOto ensure stability in the autonomous mode

selection.

10.1.2 Introduction to PoE

Power-over-Ethernet (PoE) is a means of distributing power to Ethernet devices over the Ethernet cable using

either data or spare pairs. PoE eliminates the need for power supplies at the Ethernet device. Common

applications of PoE are security cameras, IP Phones and wireless access points (WAP). The host or mid-span

equipment that supplies power is the power source equipment (PSE). The load at the Ethernet connector is the

powered device (PD). PoE protocol between PSE and PD controlling power to the load is specified by IEEE

802.3bt standard. Transformers are used at Ethernet host ports, mid-spans and hubs, to interface data to the

cable. A DC voltage can be applied to the center tap of the transformer with no effect on the data signals. As in

any power transmission line, a relatively high voltage (approximately 50 V) is used to keep currents low and

minimize the effects of IR drops in the line to preserve power delivery to the load. Standard 2-Pair PoE delivers

approximately 13 W to a type 1 PD, and 25.5 W to a type 2 PD, whereas standard 4-Pair PoE are capable of

delivering approximately 51 W to a type 3 PD and 71 W to a type 4 PD.

10.1.2.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard

The IEEE 802.3at-2009 standard previously expanded PoE power delivery from 15.4 W (commonly referred to

as .af or Type-1 PoE) to 30 W (.at or Type-2 PoE) of sourced power from the PSE (Power Sourcing Equipment)

over 2-pairs of Ethernet wires (commonly known as either the Alt-A or Alt-B pair sets). The IEEE 802.3bt

standard further expands power delivery up to 90 W sourced from a PSE by allowing for power delivery over

both the ALT-A and ALT-B pairsets in parallel. Two new PoE equipment "Types" have also been created as part

of the new standard. Type 3 PSE equipment is capable of sourcing up to 60 W of power over 4 pair or 30 W over

2 pair while supporting the new MPS requirements. Type 4 PSE equipment is capable of sourcing up to 90 W of

power over 4 pair. The TPS23882B has been designed to be comply with the 2-Pair Type-3 requirements.

The Maintain Power Signature (or MPS) requirements have also been updated for the new standard. The

previous version of the standard only required PSEs to maintain power on a port if the PD (Powered Device)

current exceeded 10 mA for at least 60 ms every 300 ms to 400 ms. By decreasing these requirements to 6 ms

every 320 ms to 400 ms, the minimum power requirement to maintain PoE power have been reduced by a factor

of nearly 10.

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10.2 Typical Application

This typical application shows an eight (2-Pair) port, semiauto mode application using a MSP430 or similar

micro-controller. Operation in any mode requires I²C host support. The TPS23882B provides useful telemetry in

multi-port applications to aid in implementing port power management.

VPWR

VDD

TPS23882

C_VPWR

C_VDD

VPWR

43 VDD

VPWR 17

P3

P2

+

RJ45

&

RJ45

&

D_P3

D_P2

C_P3

C_P2

XFMR

F_P3

F_P2

œ

10 DRAIN3

DRAIN2

5

8

9

GAT3

SEN3

Q_P3

Q_P2

GAT2

SEN2

7

6

R_S3

R_S2

11 KSENSB

KSENSA

4

R_S1

R_S4

13 SEN4

SEN1

GAT1

2

1

3

14 GAT4

Q_P4

Q_P1

P4

P1

12 DRAIN4

DRAIN1

œ

F_P4

F_P1

RJ45

&

RJ45

&

C_P4

C_P1

D_P4

D_P1

XFMR

VDD

XFMR

+

55

SDAO

VPWR

R_RST

R_INT

R_SCL

R_SDA

54

53

44

45

56

SDAI

SCL

A1 48

A2 49

A3 50

A4 51

I2C Host Device

RESET

INT

OSS

VPWR

P7

P6

21

46

AGND

DGND

+

RJ45

&

RJ45

&

D_P7

D_P6

C_P7

C_P6

XFMR

F_P7

F_P6

œ

38 DRAIN7

36 GAT7

37 SEN7

DRAIN6 33

GAT6 35

SEN6 34

Q_P7

R_S6

R_S7

39 KSENSD

KSENSC 32

R_S8

R_S5

41 SEN8

SEN5 30

Q_P8

42 GAT8

GAT5

29

Q_P5

P8

P5

40 DRAIN8

DRAIN5 31

-

œ

F_P8

F_P5

RJ45

&

RJ45

&

C_P8

C_P5

D_P8

D_P5

XFMR

+

VPWR

图10-1. Eight 2-Pair Port Application

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10.2.1 Design Requirements

TPS23882B devices are used in the eight port configuration and are managed by the I²C host device. The I²C

address for TPS23882B is programmed using the A4..A1 pins. When using multiple TPS23882B devices in a

system, each device requires by a unique I²C address. See PIN STATUS Register for more information on how

to program the TPS23882B I²C address.

A MCU is not required to operate the TPS23882B device, but some type of I²C controller and host controller

device is required to program the internal SRAM and initialize the basic I²C register configuration of the

TPS23882B.

TI recommends that the RESET pin be connected to a micro-controller or other external circuitry.

备注

The RESET pin must be held low until both VPWR and VDD are above their UVLO thresholds.

Refer to the TPS23882EVM: PoE, PSE, TPS23882 Evaluation Module user's guide for more detailed

information.

10.2.2 Detailed Design Procedure

Refer to the TPS23882EVM: PoE, PSE, TPS23882 Evaluation Module user's guide for more detailed information

on component selection and layout recommendations.

10.2.2.1 Connections on Unused Channels

On unused channels, TI recommends to ground the SENx pin and leave the GATx pin open. DRAINx pins can

be grounded or left open (leaving open can slightly reduce power consumption). 图 10-2 shows an example of

an unused PORT2.

DRAIN2

GAT2

5

7

6

4

SEN2

KSENSA

TPS23882

R_S1

SEN1

GAT1

2

1

3

P1

DRAIN1

œ

F_P1

RJ45

&

C_P1

D_P1

XFMR

+

VPWR

图10-2. Unused PORT2 Connections

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10.2.2.2 Power Pin Bypass Capacitors

• C_VPWR: 0.1-μF, 100-V, X7R ceramic at pin 17 (VPWR)

• C_VDD: 0.1-μF, 5-V, X7R ceramic at pin 43 (VDD)

10.2.2.3 Per Port Components

• C_Pn: 0.1-μF, 100-V, X7R ceramic between VPWR and Pn-

• R_Sn: Each channel's current sense resistor is a 0.2-Ω. TI recommends a 1%, 0.25-W resistor in an 0805

SMT package. If a 30-W Policing (P_CUT) threshold is selected, the maximum power dissipation for the resistor

becomes approximately 93.3 mW.

备注

For systems requiring either more accurate system power monitoring or precise Port Power

Policing accuracy, TI recommends that 0.1% R_SENSEresistors be used.

• Q_Pn: The port MOSFET can be a small, inexpensive device with average performance characteristics. BV_DSS

should be 100-V minimum. Target a MOSFET R_DS(on)at V_GS= 10 V of between 50 mΩand 150 mΩ. The

MOSFET GATE charge (Q_G) and input capacitance (C_ISS) should be less than 50 nC and 2000 pF

respectively. The maximum power dissipation for Q_Pnwith RDS(on) = 100 mΩat 640 mA nominal policing

(I_CUT) threshold is approximately 45 mW.

备注

In addition to the MOSFET R_DS(on)and BV_DSScharacteristics, the power MOSFET SOA ratings

also must be taken into consideration when selecting these components for your system design. TI

recommends that a MOSFET be chosen with an SOA rating that exceeds the inrush and

operational foldback characteristic curves as shown in 图9-2 and 图9-3. When using the standard

current foldback (ALTIRn or ALTFBn = 0) options, TI recommends the CSD19538Q3A 100V N-

Channel MOSFET.

• F_Pn: The port fuse must be a slow blow type rated for at least 60 VDC and above approximately 2 × P_CUT

(maximum). The cold resistance must be below 200 mΩto reduce the DC losses. The power dissipation for

FPn with a cold resistance of 180 mΩat maximum P_CUTis approximately 150 mW.

• D_PnA: The port TVS must be rated for the expected port surge environment. D_PnAmust have a minimum

reverse standoff voltage of 58 V and a maximum clamping voltage of less than 95 V at the expected peak

surge current.

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10.2.2.4 System Level Components (not Shown in the Schematic Diagrams)

The system TVS and bulk VPWR capacitance work together to protect the PSE system from surge events which

can cause VPWR to surge above 70 V. The TVS and bulk capacitors must be placed on the PCB such that all

TPS23882B ports are adequately protected.

• TVS: The system TVS must be rated for the expected peak surge power of the system and have a minimum

reverse standoff voltage of 58 V. Together with the VPWR bulk capacitance, the TVS must prevent the VPWR

rail from exceeding 70 V.

• Bulk Capacitor: The system bulk capacitors must be rated for 100 V and can be of aluminum electrolytic

type. Two 47-μF capacitors can be used for each TPS23882B on board.

• Distributed Capacitance: In higher port count systems, it can be necessary to distribute 1-uF, 100-V, X7R

ceramic capacitors across the 54-V power bus. TI recommends one capacitor per each TPS23882B pair.

• Digital I/O Pullup Resistors: RESET and A1-A4 are internally pulled up to VDD, while OSS is internally

pulled down, each with a 50-kΩ(typical) resistor. A stronger pullup and down resistor can be added

externally such as a 10 kΩ, 1%, 0.063 W type in a SMT package. SCL, SDAI, SDAO, and INT require

external pullup resistors within a range of 1 kΩto 10 kΩdepending on the total number of devices on the

bus .

• Ethernet Data Transformer (per port): The Ethernet data transformer must be rated to operate within the

IEEE802.3bt standard in the presence of the DC port current conditions. The transformer is also chosen to be

compatible with the Ethernet PHY. The transformer may also be integrated into the RJ45 connector and cable

terminations.

• RJ45 Connector (per port): The majority of the RJ45 connector requirements are mechanical in nature and

include tab orientation, housing type (shielded or unshielded), or highly integrated. An integrated RJ45

consists of the Ethernet data transformer and cable terminations at a minimum. The integrated type may also

contain the port TVS and common mode EMI filtering.

• Cable Terminations (per port): The cable terminations typically consist of series resistor (usually 75 Ω) and

capacitor (usually 10 nF) circuits from each data transformer center tap to a common node which is then

bypassed to a chassis ground (or system earth ground) with a high-voltage capacitor (usually 1000 pF to

4700 pF at 2 kV).

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10.2.3 Application Curves

Unless otherwise noted, measurements taken on the TPS23882B EVM and Sifos PSA-3000 PowerSync

Analyzer with PSA3202 test cards. Test conditions are T_J= 25 °C, V_VDD= 3.3 V, V_VPWR= 54 V, V_DGND= V_AGND

,

DGND, KSENSA, KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn =

0. Positive currents are into pins. R_S= 0.200 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to

KSENSC (SEN5 or SEN6) or to KSENSD (SEN7 or SEN8). All voltages are with respect to AGND unless

otherwise noted. Operating registers loaded with default values unless otherwise noted.

DRAIN_ALT-A

GATE_ALT-A

图10-3. I_LIMFoldback and Turn-Off

图10-4. Backoff Due to PCut Fault

DRAIN_ALT-A

GATE_ALT-A

图10-5. Open Circuit Detection Signature

图10-6. Semiauto Mode Discovery with a Valid

Class 0-3 Load

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DRAIN_ALT-A

GATE_ALT-A

图10-7. 1-Finger Classification and Turn-On

图10-8. 3-Finger Classification and Turn-On

11 Power Supply Recommendations

11.1 VDD

The recommended VDD supply voltage requirement is 3.3 V, ±0.3 V. The TPS23882B requires approximately 6-

mA typical and 12-mA maximum from the VDD supply. The VDD supply can be generated from VPWR with a

buck-type regulator (TI recommends a LM5017 based device for a higher port count PSE using multiple

TPS23882B devices operating in semiauto mode. The power supply design must ensure the VDD rail rises

monotonically through the VDD UVLO thresholds without any droop under the UVLO_fall threshold as the loads

are turned on. This action is accomplished with proper bulk capacitance across the VDD rail for the expected

load current steps over worst case design corners. Furthermore, the combination of decoupling capacitance and

bulk storage capacitance must hold the VDD rail above the UVLO_fall threshold during any expected transient

outages after power is applied.

11.2 VPWR

Although the supported VPWR supply voltage range is 44 V to 57 V, as with the 802.3at standard for Type-2

PoE, a 50-V minimum supply is required to comply with 2-Pair Type-3 (up to 30W) IEEE requirements. The

TPS23882B requires approximately 10-mA typical and 12-mA maximum from the VPWR supply, but the total

output current required from the VPWR supply depends on the number and type of ports required in the system.

The TPS23882B can be configured to support either 15.5 W, or 30 W per port and the power limit is set

proportionally at turn-on. The port power limit, P_CUT, is also programmable to provide even greater system

design flexibility. However, size the VPWR supply accordingly to the PoE Type to be supported. As an example,

TI recommends a 130-W or greater power supply for eight type 1 (15.5 W each) ports, or TI recommends a 250-

W or greater power supply for eight 2-pair type 3 (30 W) ports, assuming maximum port and standby currents.

备注

In IEEE complaint applications, only 4-pair configured ports are capable of supporting power levels

greater than 30 W.

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12 Layout

12.1 Layout Guidelines

12.1.1 Kelvin Current Sensing Resistors

Load current in each PSE channel is sensed as the voltage across a low-end current-sense resistor with a value

of 200 mΩ. For more accurate current sensing, kelvin sensing of the low end of the current-sense resistor is

provided through pins KSENSA for channels 1 and 2, KSENSB for channels 3 and 4, KSENSC for channels 5

and 6 and KSENSD for channels 7 and 8.

VPWR

P2

+

RJ45

&

XFMR

C_P2

D_P2

F_P2

œ

DRAIN2

GAT2

5

7

Q_P2

6

4

SEN2

R_S2

KSENSA

Note: only two channels shown

TPS23882

R_S1

SEN1

GAT1

2

1

3

P1

DRAIN1

œ

F_P1

RJ45

&

XFMR

C_P1

D_P1

+

VPWR

图12-1. Kelvin Current-Sense Connection

KSENSA is shared between SEN1 and SEN2, KSENSB is shared between SEN3 and SEN4, KSENSC is

shared between SEN5 and SEN6, and KSENSD is shared between SEN7 and SEN8. To optimize the accuracy

of the measurement, the PCB layout must be done carefully to minimize impact of PCB trace resistance. Refer

to 图12-2 as an example.

to SENSE1 pin

Shape Connecting R_S1and

R_S1

R_S2to KSENSA

KSENSA Route

to TPS23882

R_S2

Vias Connecting

Shape to GND Layer

to SENSE2 pin

图12-2. Kelvin Sense Layout Example

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12.2 Layout Example

R_S8A

KSENSD

KSENSA

Q_P1

Q_P8

R_S8

R_S1

R_S7

R_S2

Q_P2

Q_P7

R_S2A

R_S7A

R_S6A

R_S6

TPS23882

R_S3A

Q_P3

Q_P6

KSENSC

F_P3

KSENSB

R_S3

R_S4

R_S5

Q_P4

Q_P5

C_P2

P2

R_S4A

R_S5A

P3

GND

Note: PCB layout includes footprints for optional parallel R_SENSEresistors

图12-3. Eight Port Layout Example (Top Side)

12.2.1 Component Placement and Routing Guidelines

12.2.1.1 Power Pin Bypass Capacitors

• C_VPWR: Place close to pin 17 (VPWR) and connect with low inductance traces and vias according to 图12-3.

• C_VDD: Place close to pin 43 (VDD) and connect with low inductance traces and vias according to 图12-3.

12.2.1.2 Per-Port Components

• R_SnA/ R_SnB: Place according to in a manner that facilitates a clean Kelvin connection with KSENSEA/B/C/D.

• Q_Pn: Place Q_Pnaround the TPS23882B as illustrated in 图12-3. Provide sufficient copper from Q_Pndrain to

F_Pn.

• F_Pn, C_Pn, D_PnA, D_PnB: Place this circuit group near the RJ45 port connector (or port power interface if a

daughter board type of interface is used as illustrated in 图12-3). Connect this circuit group to Q_Pndrain or

GND (TPS23882B- AGND) using low inductance traces.

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13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

For related documentation see the following:

• Texas Isntruemnts, How to Load TPS2388x SRAM and Parity Code Over I ²C application brief

• Texas Instruments, TPS23882BEVM user's guide

• IEEE 802.3bt Ready PSE Daughter Card for 24-port PSE System

• Texas Instruments, How to Load TPS2388x SRAM and Parity Code Over I²application report

• TI mySecure Software

13.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

13.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RTQ 56

8 x 8, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224653/A

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PACKAGE OUTLINE

RTQ0056E

VQFN - 1 mm max height

S

C

A

L

E

1

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

8.15

7.85

A

B

PIN 1 INDEX AREA

8.15

7.85

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2X 6.5

5.7 0.1

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

28

15

14

29

SYMM

57

2X 6.5

5.7 0.1

1

42

52X 0.5

PIN 1 ID

0.30

0.18

56

43

56X

0.5

0.3

0.1

C A B

56X

0.05

4224191/A 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RTQ0056E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(5.7)

(2.6) TYP

SEE SOLDER MASK

DETAIL

43

(1.35) TYP

56X (0.6)

56X (0.24)

56

1

42

52X (0.5)

(2.6) TYP

(R0.05) TYP

(1.35) TYP

57

SYMM

(7.8)

(5.7)

(

0.2) TYP

VIA

14

29

28

15

SYMM

(7.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224191/A 03/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RTQ0056E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.675) TYP

(1.35) TYP

43

56X (0.6)

56X (0.24)

56

1

42

52X (0.5)

(1.35) TYP

(R0.05) TYP

57

(0.675) TYP

(7.8)

SYMM

16X (1.15)

14

29

15

28

SYMM

16X (1.15)

(7.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 10X

EXPOSED PAD 57

65% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4224191/A 03/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	TPS23882B1RTQR
厂家：	TEXAS INSTRUMENTS
描述：	具有自主模式、SRAM 和 200mΩ RSENSE 的 3 类、2 线对、8 通道 PoE PSE 控制器 \| RTQ \| 56 \| -40 to 125 控制器静态存储器
文件：	总123页 (文件大小：3363K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS23882B1RTQR [TI]

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