TPS22811LRPWR [TI]
具有快速过压保护和电流监控功能的 2.7V 至 16V、10A、6mΩ 负载开关 | RPW | 10 | -40 to 125;
| 型号： | TPS22811LRPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有快速过压保护和电流监控功能的 2.7V 至 16V、10A、6mΩ 负载开关 | RPW | 10 | -40 to 125 开关 监控 |
| 文件： | 总40页 (文件大小：3569K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS22811
ZHCSQA4A –APRIL 2022 –REVISED JULY 2022
TPS22811x 具有可调节过压保护和电流监控功能的2.7V 至16V、10A、6mΩ 负
载开关
1 特性
3 说明
• 宽工作输入电压范围：2.7V 至16V
TPS22811x 是一款采用小型封装的高度集成配电解决
方案。该器件允许使用数量尽可能少的外部组件来控制
和监控电源轨。
– 绝对最大值为20V
• 具有低导通电阻的集成FET：RON = 6mΩ（典型
值）
• 可调节的输出压摆率控制(dVdt)
• 具有可调节欠压锁定阈值(UVLO) 的高电平有效使
能输入
• 具有可调节欠压锁定阈值(UVLO) 的低电平有效使
能输入
• 快速过压保护
可以使用单个外部电容器来调节输出压摆率和浪涌电
流。通过在输入超过可调过压阈值时切断输出，可以保
护负载免受输入过压情况的影响。该器件集成了快速跳
变响应，可提供保护，防止在稳态期间输出侧出现严重
故障。
此类器件可提供输出负载电流的准确模拟检测以及数字
电源正常状态指示，从而帮助进行系统监控和诊断。
– 可调节过压锁定(OVLO)，响应时间为1.2μs
（典型值）
• 模拟负载电流监测器输出(IMON)
器件采用 2mm × 2mm 10 引脚 HotRod™ QFN 封装，
旨在改善热性能并减小系统尺寸。
– • IOUT > 3A 时精度为±9%
• 在稳态条件下通过快速跳变响应实现短路保护
– 响应时间为640ns（典型值）
– 固定阈值
此类器件的额定工作结温范围为–40°C 至+125°C。
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TPS22811
RPW（VQFN-HR、
10）
• 过热保护
2.00mm × 2.00mm
• 具有可调节阈值(PGTH) 的电源正常状态(PG) 指
示
• 快速输出放电
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 小尺寸：QFN 2mm × 2mm，0.45mm 间距
VOUT
VIN = 2.7 to 16 V
IN
OUT
2 应用
COUT
• 光学模块
EN
EN/UVLO
PGTH
VLOGIC
• 服务器/PC 主板/附加卡
• 企业路由器/数据中心交换机
• 工业PC
TPS22811x
EN/OVLO
PG
IMON
dVdt
GND
• UHDTV
CDVDT
RIMON
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGU5
TPS22811
ZHCSQA4A –APRIL 2022 –REVISED JULY 2022
www.ti.com.cn
Table of Contents
8 Application and Implementation..................................23
8.1 Application Information............................................. 23
8.2 Typical Application.................................................... 25
9 Power Supply Recommendations................................30
9.1 Transient Protection..................................................30
9.2 Output Short-Circuit Measurements......................... 31
10 Layout...........................................................................32
10.1 Layout Guidelines................................................... 32
10.2 Layout Example...................................................... 33
11 Device and Documentation Support..........................34
11.1 Documentation Support.......................................... 34
11.2 接收文档更新通知................................................... 34
11.3 支持资源..................................................................34
11.4 Trademarks............................................................. 34
11.5 Electrostatic Discharge Caution..............................34
11.6 术语表..................................................................... 34
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................7
6.7 Switching Characteristics............................................8
6.8 Typical Characteristics................................................9
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................22
Information.................................................................... 35
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (April 2022) to Revision A (July 2022)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
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5 Pin Configuration and Functions
IN
OUT
1
EN/UVLO
10
DNC
IMON
9
EN/OVLO
2
5
6
PG
GND
8
3
DVDT
PGTH
7
4
图5-1. TPS22811x RPW Package 10-Pin QFN Top View
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
Active high enable for the device. A resistor divider on this pin from input supply to GND can
be used to adjust the Undervoltage Lockout threshold. Do not leave floating. Refer to
Undervoltage Lockout (UVLO and UVP) for details.
Analog
Input
EN/UVLO
1
A resistor divider on this pin from supply to GND can be used to adjust the overvoltage lockout
threshold. This pin can also be used as an active low enable for the device. Do not leave
floating. Refer to Overvoltage Lockout (OVLO) for more details.
Analog
Input
EN/OVLO
2
Power-good indication. This pin is an open-drain signal which is asserted high when the
internal power path is fully turned ON and PGTH input exceeds a certain threshold. Refer to
Power-Good Indication (PG) for more details.
Digital
Output
PG
3
4
Analog
Input
PGTH
Power-good threshold. Refer to Power-Good Indication (PG) for more details.
IN
5
6
Power Power input
Power Power output
OUT
A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for
the fastest turn on slew rate. Refer to Slew Rate (dVdt) and Inrush Current Control for more
details.
Analog
Output
DVDT
GND
7
8
Ground This pin is the ground reference for all internal circuits and must be connected to system GND.
Analog load current monitor output. An external resistor from this pin to GND sets the gain for
the current monitor. This pin also provides a secondary function of setting the current limit
Analog
IMON
DNC
9
during start-up. Connect to GND if neither of these features are used. Do not leave floating.
Output
Refer to Analog Load Current Monitor and Active Current Limiting During Start-Up for more
details.
10
X
Do not connect anything to this pin.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Parameter
Pin
MIN
–0.3
–0.3
–0.8
–0.3
–0.3
MAX
20
UNIT
VIN
IN
V
Maximum input voltage range, –40℃≤TJ ≤125℃
Maximum output voltage range, –40℃≤TJ ≤125℃
Minimum output voltage pulse (< 1 µs)
Maximum Enable pin voltage range
VOUT
OUT
OUT
VIN + 0.3
VOUT,PLS
VEN/UVLO
VOV
EN/UVLO
EN/OVLO
dVdt
6.5
6.5
V
V
V
V
V
Maximum EN/OVLO pin voltage range
Maximum dVdT pin voltage range
VdVdT
VPG
Internally limited
–0.3
Maximum PG pin voltage range
PG
6.5
6.5
VPGTH
Maximum PGTH pin voltage range
PGTH
–0.3
Internally limited
VIMON
Maximum IMON pin voltage range
IMON
V
IMAX
TJ
TLEAD
Tstg
Maximum continuous switch current
Junction temperature
IN to OUT
10
A
Internally limited
°C
°C
°C
Maximum lead temperature
Storage temperature
300
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Parameter
Pin
MIN
MAX
16
UNIT
V
VIN
Input voltage range
IN
2.7
VOUT
VEN/UVLO
VOV
Output voltage range
OUT
VIN
5(1)
1.5
V
EN/UVLO pin voltage range
EN/OVLO pin voltage range
dVdT pin capacitor voltage rating
PGTH pin voltage range
EN/UVLO
EN/OVLO
dVdt
V
0.5
V
VdVdT
VPGTH
VPG
VIN + 5 V
V
PGTH
5
5
V
PG pin voltage range
PG
V
IMAX
IN to OUT
10
A
Continuous switch current, TJ ≤125℃
Junction temperature
TJ
125
°C
–40
(1) For supply voltages below 5 V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5 V , TI recommends
to use a resistor divider with minimum pullup resistor value of 350 kΩ.
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6.4 Thermal Information
TPS25981xx
THERMAL METRIC (1)
RPW (QFN)
10 PINS
49.7(2)
71.8(3)
15.7
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-top characterization parameter
2.1(2)
1.3(3)
23 (2)
Junction-to-board characterization parameter
ΨJB
14.5 (3)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device.
(3) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device.
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6.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤TJ ≤125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V,
RIMON = 600 Ω, dVdT = Open, PGTH = Open, PG = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
INPUT SUPPLY (IN)
IQ(ON)
IQ(OFF)
ISD
IN supply quiescent current
381
68
470
90
µA
µA
µA
V
IN supply OFF state current (VSD(F) < VEN < VUVLO(F)
)
IN supply shutdown current (VEN < VSD(F)
)
3
25
VUVP(R)
VUVP(F)
IN supply UVP rising threshold
2.44
2.35
2.53
2.42
2.64
2.55
IN supply UVP falling threshold
V
OUTPUT LOAD CURRENT MONITOR (IMON)
Analog load current monitor gain (IMON : IOUT), IOUT = 1.5 A,
IOUT < ILIM
82.9
87
95.3
95.3
95.3
95.3
95.3
107.6
104.5
103.1
102.6
102.4
µA/A
µA/A
µA/A
µA/A
µA/A
Analog load current monitor gain (IMON : IOUT), IOUT = 3 A,
IOUT < ILIM
Analog load current monitor gain (IMON : IOUT), IOUT = 4.5 A,
IOUT < ILIM
GIMON
87.6
87.7
87.8
Analog load current monitor gain (IMON : IOUT), IOUT = 8 A,
IOUT < ILIM
Analog load current monitor gain (IMON : IOUT), IOUT = 10 A,
IOUT < ILIM
SHORT-CIRCUIT PROTECTION (OUT)
IFT Fixed fast-trip current threshold
ON RESISTANCE (IN - OUT)
2.7 ≤VIN ≤4 V, IOUT = 3 A, TJ = 25℃
39.5
A
6.07
5.81
mΩ
mΩ
mΩ
RON
4 < VIN ≤16 V, IOUT = 3 A, TJ = 25℃
8.4
2.7 ≤VIN ≤16 V, IOUT = 3 A, -40℃≤TJ ≤125℃
ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO)
VUVLO(R)
VUVLO(F)
VSD(F)
EN/UVLO rising threshold
1.176
1.073
0.45
1.20
1.09
0.75
1.224
1.116
V
V
EN/UVLO falling threshold
EN/UVLO falling threshold for lowest shutdown current
EN/UVLO pin leakage current
V
IENLKG
0.1
µA
–0.1
OVERVOLTAGE LOCKOUT (EN/OVLO)
VOV(R)
VOV(F)
IOVLKG
OVLO rising threshold
1.176
1.074
–0.1
1.20
1.09
1.224
1.116
0.1
V
V
OVLO falling threshold
OVLO pin leakage current (0.5 V < VOVLO < 1.5 V)
µA
POWER GOOD INDICATION (PG)
PG pin voltage while de-asserted. VIN < VUVP(F), VEN
<
<
0.66
0.80
0.90
V
V
VSD(F), Weak pullup (IPG = 26 μA)
VPGD
PG pin voltage while de-asserted. VIN < VUVP(F), VEN
0.78
0
VSD(F), Strong pullup (IPG = 242 μA)
PG pin voltage while de-asserted, VIN > VUVP(R)
PG pin leakage current, PG asserted
0.60
3
V
IPGLKG
µA
POWER GOOD THRESHOLD (PGTH)
VPGTH(R)
VPGTH(F)
IPGTHLKG
PGTH rising threshold
PGTH falling threshold
PGTH leakage current
1.178
1.071
–1
1.20
1.09
1.224
1.116
1
V
V
µA
OVERTEMPERATURE PROTECTION (OTP)
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6.5 Electrical Characteristics (continued)
(Test conditions unless otherwise noted) –40°C ≤TJ ≤125°C, VIN = 12 V, OUT = Open, VEN/UVLO = 2 V, VOVLO = 0 V,
RIMON = 600 Ω, dVdT = Open, PGTH = Open, PG = Open. All voltages referenced to GND.
Test
Parameter
Description
MIN
TYP
MAX
UNITS
TSD
154
10
°C
°C
Thermal Shutdown rising threshold, TJ↑
Thermal Shutdown hysteresis, TJ↓
TSDHYS
DVDT
IdVdt
dVdt pin internal charging current
1.4
3.45
488
5.7
µA
QUICK OUTPUT DISCHARGE (OUT)
RQOD
Quick Output Discharge Resistance, VEN < VUVLO(F)
455
530
Ω
6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
µs
tOVLO
tFT
tPGA
tPGD
Overvoltage lock-out response time
1.2
640
14
VOVLO > VOV(R) to VOUT
IOUT > IFT to IOUT
↓
Fixed fast-trip response time
PG assertion de-glitch time
PG de-assertion de-glitch time
ns
↓
µs
14
µs
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6.7 Switching Characteristics
The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn
on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin
to ground. As CdVdt is increased it slows the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt) section
for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load capacitance
(COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up sequence where the supply
is available in steady-state condition and the load voltage is completely discharged before the device is enabled. Typical
values are taken at TJ = 25°C unless specifically noted otherwise. RL = 100 Ω, COUT = 1 µF.
CdVdt
3300 pF
=
PARAMETER
VIN
CdVdt = Open CdVdt = 1800 pF
UNITS
2.7 V
5 V
8.19 0.78
1.30
1.42
1.68
0.46
0.60
0.93
1.66
2.82
5.74
2.11
3.42
6.67
24.90
21.10
18.80
SRON
tD,ON
tR
Output rising slew rate
11.28
19.71
0.14
0.14
0.14
0.26
0.36
0.49
0.40
0.50
0.63
24.90
21.10
18.80
0.84
0.98
0.70
0.96
1.57
2.77
4.78
9.84
3.47
5.74
11.41
24.90
21.10
18.80
V/ms
12 V
2.7 V
5 V
Turn-on delay
Rise time
ms
ms
ms
µs
12 V
2.7 V
5 V
12 V
2.7 V
5 V
tON
Turn-on time
Turn-off delay
12 V
2.7 V
5 V
tD,OFF
12 V
VEN/UVLO
EN/UVLO
VUVLO(R)
VUVLO(F)
0
tON
SRON
tD,OFF
90%
VIN
OUT
10%
0V
tR
tF
tD,ON
Time
图6-1. TPS22811x Switching Times
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6.8 Typical Characteristics
6.1
6.05
6
8
7.5
7
IOUT(A)
1.5
VIN(V)
2.7
3
4.5
6
3.3
4
5
12
16
5.95
5.9
6.5
6
5.85
5.8
5.5
5
5.75
5.7
4.5
-40
2
4
6
8
10
VIN (V)
12
14
16
-20
0
20
40
60
80
100 120 140
TA (C)
图6-2. ON-Resistance vs Supply Voltage (TA = 25°C)
图6-3. ON-Resistance vs Temperature (IOUT = 3 A)
77.5
410
400
390
380
VIN(V)
2.7
75
72.5
70
5
12
16
VIN(V)
2.7
67.5
65
370
360
350
340
330
320
310
5
12
16
62.5
60
57.5
55
52.5
-40
-20
0
20
40
TA(C)
60
80
100 120 140
-40
-20
0
20
40
TA (C)
60
80
100 120 140
图6-5. IN OFF State (UVLO) Current vs Temperature
2.54
图6-4. IN Quiescent Current vs Temperature
3.9
3.6
3.3
3
2.52
2.5
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
VIN(V)
2.7
2.48
2.46
2.44
2.42
2.4
Rising
Falling
5
12
16
-40
-20
0
20
40
TA (C)
60
80
100 120 140
-40
-20
0
20
40
TA(C)
60
80
100 120 140
图6-7. IN Undervoltage Threshold vs Temperature
图6-6. IN Shutdown Current vs Temperature
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6.8 Typical Characteristics (continued)
1.20195
1.2019
1.20185
1.2018
1.20175
1.2017
1.20165
1.2016
1.20155
1.2015
1.20145
1.2014
1.20135
1.2013
1.20195
1.2019
1.20185
1.2018
1.20175
1.2017
1.20165
1.2016
1.20155
1.2015
1.20145
1.2014
1.20135
1.2013
VIN(V)
2.7
VIN(V)
2.7
5
5
12
16
12
16
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
图6-8. EN/UVLO Rising Threshold vs Temperature
0.8
图6-9. EN/UVLO Falling Threshold vs Temperature
1.20205
VIN(V)
2.7
1.202
1.20195
1.2019
1.20185
1.2018
1.20175
1.2017
1.20165
1.2016
1.20155
1.2015
1.20145
1.2014
0.78
0.76
0.74
0.72
0.7
5
12
16
0.68
0.66
0.64
0.62
0.6
VIN(V)
2.7
5
12
16
0.58
-40
-20
0
20
40
TA (C)
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
图6-11. EN/OVLO Rising Threshold vs Temperature
44
图6-10. EN/UVLO Shutdown Falling Threshold vs Temperature
1.09525
1.0952
1.09515
1.0951
1.09505
1.095
1.09495
1.0949
1.09485
1.0948
1.09475
1.0947
1.09465
1.0946
1.09455
1.0945
VIN(V)
2.7
5
12
16
41
38
35
32
VIN(V)
2.7
5
12
16
-40
-20
0
20
40
TA (C)
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA(C)
图6-12. EN/OVLO Falling Threshold vs Temperature
图6-13. Fixed Fast-Trip Threshold vs Temperature
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6.8 Typical Characteristics (continued)
18
15
12
9
3.8
3.75
3.7
3.65
3.6
VIN(V)
2.7
5
Min
Typ
Max
12
16
6
3.55
3.5
3
3.45
3.4
3.35
3.3
0
-3
-6
-9
3.25
3.2
3.15
3.1
-12
-15
-18
-40
-20
0
20
40
60
80
100 120 140
1
2
3
4
5
6
7
8
9
10
11
TA (C)
IOUT (A)
图6-15. DVDT Charging Current vs Temperature
图6-14. Analog Current Monitor Gain Accuracy
1.2006
0.84
VIN(V)
2.7
IPG(A)
1.20055
1.2005
1.20045
1.2004
1.20035
1.2003
1.20025
1.2002
1.20015
1.2001
0.81
0.78
0.75
0.72
0.69
0.66
0.63
0.6
26
5
12
16
242
0.57
0.54
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA (C)
TA (C)
图6-17. PGTH Rising Threshold vs Temperature
0.08
图6-16. PG Pin Voltage vs Temperature (VIN = 0 V)
1.09505
VIN(V)
1.095
1.09495
1.0949
2.7
5
12
16
0.06
0.04
0.02
0
1.09485
1.0948
1.09475
1.0947
1.09465
1.0946
VIN(V)
2.7
1.09455
1.0945
5
12
23
-0.02
1.09445
-0.04
-40
-20
0
20
40
TA (C)
60
80
100 120 140
-40
-20
0
20
40
TA (C)
60
80
100 120 140
图6-18. PGTH Falling Threshold vs Temperature
图6-19. PGTH Pin Leakage Current vs Temperature
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6.8 Typical Characteristics (continued)
502
500
498
496
494
492
490
488
486
484
482
10000
5000
2000
1000
500
200
100
50
20
10
5
VIN(V)
2.7
2
1
0.5
5
12
16
0.2
0.1
0
20
40
60
80
PD (W)
100
120
140
-40
-20
0
20
40
TA (C)
60
80
100 120 140
图6-21. Time to Thermal Shutdown During Inrush State
图6-20. Quick Output Discharge Resistance vs Temperature
VIN = 12 V, COUT = 10 μF, CdVdt = Open, VEN/UVLO stepped up
to 3.3 V
图6-23. Start-Up with Enable
图6-22. Time to Thermal Shutdown During Steady-State
VEN/UVLO = 3.3 V, COUT = 10 μF, CdVdt = Open, VIN ramped
VIN = 12 V, COUT = 220 μF, CdVdt = 3300 pF, VEN/UVLO
up to 12 V
stepped up to 1.4 V
图6-24. Start- Up with Supply
图6-25. Inrush Current with Capacitive Load
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6.8 Typical Characteristics (continued)
VIN Overvoltage threshold set to 13.6 V using resistor ladder
connected on OVLO pin, VIN ramped up from 12 V to 16 V
VIN = 12 V, COUT = 220 μF, ROUT = 5 Ω, CdVdt = 3300 pF,
VEN/UVLO stepped up to 1.4 V
图6-27. Overvoltage Lockout Response
图6-26. Inrush Current with Resistive and Capacitive Load
VIN = 12 V, COUT = Open, OUT short circuit to GND, RIMON
=
VIN = 12 V, OUT stepped from open →short circuit to GND
649 Ω, VEN/UVLO stepped from 0 V to 3.3 V
图6-28. Output Short Circuit During Steady-State (Zoomed In)
图6-29. Power Up into Short-Circuit
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7 Detailed Description
7.1 Overview
TPS22811x is an integrated load switch with protection and monitoring. The device starts its operation by
monitoring the IN bus. When the input supply voltage (VIN) exceeds the undervoltage protection threshold
(VUVP), the device samples the EN/UVLO pin. A high level (> VUVLO) on this pin enables the internal power path
to start conducting and allow current to flow from IN to OUT. When EN/UVLO is held low (< VUVLO), the internal
power path is turned off.
After a successful start-up sequence, the device now actively monitors its load current and input voltage, and
controls the internal FET to ensure that the fast-trip current threshold is not exceeded and overvoltage spikes are
cut-off after they cross the user adjustable overvoltage lockout threshold (VOVLO). This feature keeps the system
safe from harmful levels of voltage and current.
The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device
temperature (TJ) exceeds the recommended operating conditions.
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7.2 Functional Block Diagram
FFT
TPS22811x
229 mV
Temp Sense and
Overtemperature
protection
TSD
5
6
7
OUT
IN
INRUSH_DONE
HFET
DVDT
CP
3.4 ꢀA
2.8 V
+
UVPb
UVLOb
2.53 V9
95.3 ꢀA/A
-
2.42 V;
GHI
-
2
1
EN/OVLO
EN/UVLO
OVLOb
UVLOb
1.20 V9
1.09 V;
+
+
HFET Control
IMON
9
1.20 V9
1.09 V;
INRUSH_DONE
-
SWEN
-
SD
+
0.75 V;
SD
R
S
/Q
Q
UVPb
10
DNC
PG_int
TSD
FLT
PG_int
8
GND
R
Q
S
/Q
GHI FFT
1.2 V9
1.09 V;
3
4
PG
PGTH
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7.3 Feature Description
The TPS22811x eFuse is a compact, feature rich power management device that provides detection, protection
and indication in the event of system faults.
7.3.1 Undervoltage Lockout (UVLO and UVP)
The TPS22811x implements undervoltage protection on IN in case the applied voltage becomes too low for the
system or device to properly operate. The undervoltage protection has a default lockout threshold of VUVP which
is fixed internally. Also, the UVLO comparator on the EN/UVLO pin allows the undervoltage protection threshold
to be externally adjusted to a user defined value. 图7-1 and 方程式1 show how a resistor divider can be used to
set the UVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/UVLO
R2
GND
图7-1. Adjustable Undervoltage Protection
V
× R + R
1 2
UVLO
V
=
(1)
IN UV
R
2
7.3.2 Overvoltage Lockout (OVLO)
The TPS22811x allows the user to implement overvoltage lockout to protect the load from input overvoltage
conditions. The OVLO comparator on the EN/OVLO pin allows the overvoltage protection threshold to be
adjusted to a user defined value. After the voltage at the EN/OVLO pin crosses the OVLO rising threshold
VOV(R), the device turns off the power to the output. Thereafter, the devices wait for the voltage at the EN/OVLO
pin to fall below the OVLO falling threshold VOV(F) before the output power is turned ON again. The rising and
falling thresholds are slightly different to provide hysterisis. 图 7-2 and 方程式 2 show how a resistor divider can
be used to set the OVLO set point for a given voltage supply.
Power
Supply
IN
R1
EN/OVLO
R2
GND
图7-2. Adjustable Overvoltage Protection
V
× R + R
1 2
OV
V
=
(2)
IN OV
R
2
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Input Overvoltage Event
Input Overvoltage Removed
IN
0
VOV(R)
VOV(F)
EN/OVLO
tOVLO
0
OUT
dVdt Limited Start-up
tPGA
0
VPG
0
tPGD
PG
Time
图7-3. TPS22811x Overvoltage Lockout and Recovery
While recovering from a OVLO event, the TPS22811x starts up with inrush control (dVdt).
7.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
TPS22811x incorporates three levels of protection against overcurrent:
1. Adjustable slew rate (dVdt) for inrush current control
2. Fixed threshold (IFT) for fast-trip response to quickly protect against hard output short circuits during steady-
state
3. Adjustable current limit (ILIM) for protection against overcurrent or short circuit during start-up
7.3.3.1 Slew Rate (dVdt) and Inrush Current Control
During hot-plug events or while trying to charge a large output capacitance at start-up, there can be a large
inrush current. If the inrush current is not managed properly, it can damage the input connectors and cause the
system power supply to droop leading to unexpected restarts elsewhere in the system. The inrush current during
turn on is directly proportional to the load capacitance and rising slew rate. 方程式3 can be used to find the slew
rate (SR) required to limit the inrush current (IINRUSH) for a given load capacitance (COUT):
I
mA
V
ms
INRUSH
SR
=
(3)
C
µF
OUT
A capacitor can be connected to the dVdt pin to control the rising slew rate and lower the inrush current during
turn on. Use 方程式4 to calculate the required CdVdt capacitance to produce a given slew rate.
3300
C
pF =
(4)
dVdt
V
SR
ms
The fastest output slew rate is achieved by leaving the dVdt pin open.
备注
For CdVdt > 10 nF, TI recommends to add a 100-Ωresistor in series with the capacitor on the dVdt pin.
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7.3.3.2 Short-Circuit Protection
During an output short-circuit event, the current through the device increases very rapidly. When a severe
overcurrent condition is detected, the TPS22811x triggers a fast-trip response to cut off the power path. The
device employs a fixed fast-trip threshold (IFT) to protect fast protection against hard short circuits during steady-
state. After the current exceeds IFT, the FET is turned off completely within tFT. Thereafter, the device remains off
till the device is power cycled or re-enabled using EN/UVLO pin.
Transient overcurrent
during steady state
Device latched-off
Device enabled
Device re-enabled
Load step
VUVLO(R)
EN/UVLO
VSD(F)
0
IN
0
tFT
IFT
Fast-trip
IOUT
IINRUSH
0
VIN
OUT
0
tPGA
tPGA
tPGD
VPG
0
PG
Time
图7-4. TPS22811x Short-Circuit Response
7.3.3.3 Active Current Limiting During Start-Up
The TPS22811x devices respond to output overcurrent conditions during start-up by actively limiting the current.
If the load current exceeds the set overcurrent threshold (ILIM) set by the IMON pin resistor (RIMON), but stays
lower than the fast-trip threshold (IFT), the current limit loop starts regulating the FET to actively limit the current
to the set overcurrent threshold (ILIM). 方程式 5 can be used to calculate the RIMON value for a desired
overcurrent threshold.
6595
R
Ω =
(5)
IMON
I
A
LIM
备注
1. Leaving the IMON pin open sets the current limit to nearly zero and results in the part entering
current limit with the slightest amount of loading at the output.
2. The current limit circuit employs a foldback mechanism. The current limit threshold in the foldback
region (0 V < VOUT < VFB) is lower than the target current limit threshold (ILIM).
3. Connecting the IMON pin to GND disables the active current limit protection during start-up.
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During active current limit, the output voltage drops, resulting in increased device power dissipation across the
FET. If the device internal temperature (TJ) exceeds the thermal shutdown threshold (TSD), the FET is turned
off. After the part shuts down due to TSD fault, it stays latched off. For more details on device response to
overtemperature, see Overtemperature Protection (OTP).
7.3.4 Analog Load Current Monitor
The TPS22811x allows the system to accurately monitor the output load current by providing an analog current
sense output on the IMON pin which is proportional to the current through the FET. The user can sense the
voltage (VIMON) across the RIMON to get a measure of the output load current.
V
µV
IMON
µA/A × R
I
A =
(6)
LOAD
G
Ω
IMON
IMON
The waveform below shows the IMON signal response to a load step at the output.
VIN = 12 V, RIMON = 649 Ω, IOUT varied dynamically between 8 A and 14 A
图7-5. Analog Load Current Monitor Response
7.3.5 Overtemperature Protection (OTP)
The device monitors the internal die temperature (TJ) at all times and shuts down the part as soon as the
temperature exceeds a safe operating level (TSD) thereby protecting the device from damage. The device does
turn back on until the junction cools down sufficiently, that is the die temperature falls below (TSD –TSDHYS).
When the TPS22811x detects thermal overload, it shuts down and remains latched-off until the device is power
cycled or re-enabled.
表7-1. Thermal Shutdown
Enter TSD
Exit TSD
TJ < TSD –TSDHYS
VIN cycled to 0 V and then above VUVP(R) or EN/UVLO toggled below VSD(F)
TJ ≥TSD
7.3.6 Fault Response
The following table summarizes the device response to various fault conditions.
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表7-2. Fault Summary
Event
Overtemperature
Protection Response
Fault Latched Internally
Shutdown
Y
N
N
Y
Undervoltage (UVP or UVLO)
Input overvoltage
Shutdown
Shutdown
Fast-trip
Output short circuit to GND
Faults which are latched internally can be cleared either by power cycling the part (pulling VIN to 0 V) or by
pulling the EN/UVLO pin voltage below VSD
.
During a latched fault, pulling the EN/UVLO just below the UVLO threshold has no impact on the device.
7.3.7 Power-Good Indication (PG)
The TPS22811x provides an active high digital output (PG) which serves as a power-good indication signal and
is asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an
open-drain pin and must be pulled up to an external supply.
After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on
in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush
sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time
(tPGA).
PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device
detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD
.
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Device Enabled
VUVLO(R)
0
EN/UVLO
IN
Slew rate (dVdt) controlled
startup/Inrush current limiting
0
VIN
OUT
0
VPGTH(R)
VPGTH(F)
PGTH
0
VPG
PG
tPGA
0
VIN
dVdt
0
VOUT + 2.8 V
VHGate
0
ILIM
IINRUSH
IOUT
0
Time
图7-6. TPS22811xx PG Timing Diagram
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表7-3. TPS22811x PG Indication Summary
Event
Protection Response
PG Pin
PG Delay
Undervoltage (UVP or UVLO)
Shutdown
L
L (If PGTH pin voltage <
VPGTH(F)
Overvoltage (OVLO)
Steady-state
Shutdown
NA
tPGD
)
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
)
tPGA
tPGD
)
H (If PGTH pin voltage >
VPGTH(R)
L (If PGTH pin voltage <
VPGTH(F)
)
tPGA
tPGD
Output short circuit to GND
Overtemperature
Fast-trip followed by current limit
Shutdown
)
L (If PGTH pin voltage <
VPGTH(F)
tPGD
)
When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pulldown
in this condition to drive this pin all the way down to 0 V. If the PG pin is pulled up to an independent supply
which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the
pin sink current, which is a function of the pullup supply voltage and resistor. Minimize the sink current to keep
this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.
7.3.8 Quick Output Discharge (QOD)
The TPS22811x has an integrated output discharge function which can be helpful in quickly removing residual
charge left on the large output capacitors and avoids bus floating at some undefined voltage. The internal QOD
pulldown FET on the OUT pin is activated when the EN/UVLO is held low (VEN < VUVLO(F)). The output discharge
function can result in excess power dissipation inside the device leading to increase in junction temperature. The
output discharge is disabled if the junction temperature (TJ) crosses the thermal shutdown threshold (TSD) to
avoid long term degradation of the part.
7.4 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS22811x is a 2.7-V to 16-V, 10-A load switch that is typically used for power rail protection applications.
The device operates from 2.7 V to 16 V with adjustable overvoltage and undervoltage protection. The device
provides ability to control inrush current. The device can be used in a variety of systems such as server
motherboard/add-on cards/NIC, optical modules, enterprise switches/routers, Industrial PC, UHDTV. The design
procedure explained in the subsequent sections can be used to select the supporting component values based
on the application requirement. Additionally, a spreadsheet design tool, TPS22811xx Design Calculator, is
available in the web product folder.
8.1.1 Single Device, Self-Controlled
VOUT
IN
OUT
VIN = 2.7 to 16 V
COUT
PGTH
VLOGIC
EN/UVLO
TPS22811x
EN/OVLO
PG
dVdt
GND
IMON
图8-1. Single Device, Self-Controlled
Other variations:
In a Host MCU controlled system, EN/UVLO or OVLO can also be driven from the host GPIO to control the
device.
IMON pin can be connected to the MCU ADC input for current monitoring purpose.
8.1.2 Parallel Operation
Applications which need higher steady current can use two TPS22811x devices connected in parallel as shown
in 图 8-2 below. In this configuration, the first device turns on initially to provide the inrush current limiting. The
second device is held in an OFF state by driving its EN/UVLO pin low using the PG signal of the first device.
After the inrush sequence is complete, the first device asserts its PG pin high and turns on the second device.
The second device asserts its PG signal to indicate when it has turned on fully, thereby indicating to the system
that the parallel combination is ready to deliver the full steady-state current.
After in steady-state, both devices share current nearly equally. There can be a slight skew in the currents
depending on the part-to-part variation in the RON as well as the PCB trace resistance mismatch.
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IN
OUT
VLOGIC
PGTH
EN/UVLO
TPS22811x
EN/OVLO
PG
dVdt
IMON
GND
VOUT
VIN = 2.7 to 16 V
COUT
IN
OUT
To ADC
IMON
PGTH
EN/UVLO
TPS22811x
EN/OVLO
PG
To downstream enable
dVdt
GND
图8-2. Two Devices Connected in Parallel for Higher Steady-State Current Capability
The waveforms below illustrate the behavior of the parallel configuration during start-up as well as during steady-
state.
图8-3. Parallel Devices Sequencing During Start-Up
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图8-4. Parallel Devices Load Current During Steady-State
8.2 Typical Application
The TPS22811 device can be used in an industrial PC for input power protection of PCIe card. Industrial PCs
provide flexible PCIe expansion slots with different combination of PCIe x16, PCIe x4 and PCI. PCIe x16 slot
draws maximum current of up to 5.5 A from on board a 12-V rail. Load switch devices like TPS22811 can
support the power requirements of these PCIe expansion slots and can be used for switching 12-V supply to
PCIe card. During plugging or unplugging the PCIe card power pin of PCIe slot can short to ground that can
cause the 12-V rail to droop or even damage the power tree due to very high current draw. The TPS22811
device can quickly respond to fault events like short circuit and isolate supply from load side thus preventing
supply from drooping. The controlled rise time for the device greatly reduces inrush current caused by large bulk
load capacitances, thereby reducing or eliminating power-supply droop.
The TPS22811 device can also be used for switching the 12-V bulk power rail of DDR5 DIMM. The PG pin of
TPS22811 device can be used to enable downstream DC-DC converters after the 12-V rail is fully up.
VOUT
VIN = 12 V
IN
OUT
Load Switch
EN
VCC
PCIe
Card
Plug / Unplug
GND
图8-5. Power Path Protection Block Diagram of a Typical PCIe Slot
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VOUT
VIN = 12 V
IN
OUT
R4
R1
COUT
47 kꢁ
470 kꢁ
470 ꢀF
1 ꢀF
D2*
EN/UVLO
PGTH
TPS22811
3.3 V
R5
R2
5.6 kꢁ
11 kꢁ
CIN
D1*
47 kꢁ
1 ꢀF
EN/OVLO
PG
dVdt
IMON
GND
R3
RIMON
953 ꢁ
CdVdt
3300 pF
47 kꢁ
* Optional circuit components needed for transient protection depending on input and output inductance. Please
refer to Transient Protection section for details.
图8-6. PCIe Expansion Slot Protection
8.2.1 Design Requirements
表8-1. Design Parameters
PARAMETER
VALUE
Input supply voltage (VIN)
Undervoltage threshold (VIN(UV)
12 V
)
10.8 V
13.2 V
Overvoltage threshold (VIN(OV)
)
Output power-good threshold (VPG
Maximum continuous current
)
11.4 V
5.5 A
Analog load current monitor voltage range (VIMONmax
)
0.5 V
Output capacitance (COUT
Output rise time (tR)
)
470 μF
12 ms
8.2.2 Detailed Design Procedure
8.2.2.1 Setting Undervoltage and Overvoltage Thresholds
The supply undervoltage and overvoltage thresholds are set using the resistors R1, R2 and R3. Use 方程式7
and 方程式8 to calculate these values:
V
×
R + R + R
1 2 3
UVLO R
V
=
(7)
IN UV
R
+ R
2
3
V
×
R + R + R
1 2 3
OV R
V
=
(8)
IN OV
R
3
Where VUVLO(R) is the UVLO rising threshold and VOV(R) is the OVLO rising threshold. Because R1, R2 and R3
leak the current from input supply VIN, these resistors must be selected based on the acceptable leakage current
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from input power supply VIN. The current drawn by R1, R2 and R3 from the power supply is IR123 = VIN / (R1 +
R2 + R3). However, leakage currents due to external active components connected to the resistor string can add
error to these calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the
leakage current expected on the EN/UVLO and OVLO pins.
From the device electrical specifications, both the EN/UVLO and OVLO leakage currents are 0.1 μA
(maximum), VOV(R) = 1.2 V and VUVLO(R) = 1.2 V. From design requirements, VIN(OV) = 13.2 V and VIN(UV) = 10.8
V. To solve the equation, first choose the value of R1 = 470 kΩ and use the above equations to solve for R2 =
10.7 kΩand R3 = 48 kΩ.
Using the closest standard 1% resistor values, we get R1 = 470 kΩ, R2 = 11 kΩ, and R3 = 47 kΩ.
8.2.2.2 Setting Output Voltage Rise Time (tR)
For a successful design, the junction temperature of device must be kept below the absolute maximum rating
during both dynamic (start-up) and steady-state conditions. Dynamic power stresses often are an order of
magnitude greater than the static stresses, so it is important to determine the right start-up time and inrush
current limit required with system capacitance to avoid thermal shutdown during start-up.
The slew rate (SR) needed to achieve the desired output rise time can be calculated as:
V
t
V
V
ms
IN
12 V
12 ms
V
ms
SR
=
=
= 1
(9)
ms
R
The CdVdt needed to achieve this slew rate can be calculated as:
3300
3300
C
pF =
=
= 3300 pF
(10)
dVdt
V
V
SR
1
ms
ms
Choose the nearest standard capacitor value as 3300 pF.
For this slew rate, the inrush current can be calculated as:
V
ms
V
I
mA = C
µF × SR
= 470 µF × 1
= 470 mA
ms
(11)
(12)
INRUSH
OUT
The average power dissipation inside the part during inrush can be calculated as:
PD
= 0.5 × V
V
× I
mA = 0.5 × 12 V × 470 mA = 2.82 W
INRUSH
IN
INRUSH
For the given power dissipation, the thermal shutdown time of the device must be greater than the ramp-up time
tR to avoid start-up failure. 图8-7 shows the thermal shutdown limit, for 2.82 W of power, the shutdown time is
more than 10 s which is very large as compared to tR = 12 ms. Therefore, it is safe to use 12 ms as the start-up
time for this application.
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20000
10000
1000
100
10
1
0.1
0
20
40
60
80
100
120
140
Power Dissipation (W)
图8-7. Thermal Shutdown Plot During Inrush
8.2.2.3 Setting Power-Good Assertion Threshold
The power-good assertion threshold can be set using the resistors R4 and R5 connected to the PGTH pin whose
values can be calculated as:
V
× R + R
4 5
PGTH R
V
=
(13)
PG
R
5
Because R4 and R5 leak the current from the output rail VOUT, these resistors must be selected to minimize the
leakage current. The current drawn by R4 and R5 from the power supply is IR45 = VOUT / (R4 + R5). However,
leakage currents due to external active components connected to the resistor string can add error to these
calculations. So, the resistor string current, IR123 must be chosen to be 20 times greater than the PGTH
leakage current expected. From the device electrical specifications, PGTH leakage current is 1 μA (maximum),
VPGTH(R) = 1.2 V and from design requirements, VPG = 11.4 V. To solve the equation, first choose the value of
R4 = 47 kΩand calculate R5 = 5.52 kΩ. Choose nearest 1% standard resistor value as R5 = 5.6 kΩ.
8.2.2.4 Setting Analog Current Monitor Voltage (IMON) Range
The analog current monitor voltage range can be set using the RIMON resistor whose value can be calculated
as:
6
V
µV
IMON
µA/A × I
0.5 × 10
R
Ω =
=
= 957 Ω
(14)
IMON
95 × 5.5
G
A
OUTmax
IMON
Choose nearest 1% standard resistor value as 953 Ω.
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8.2.3 Application Curves
图8-8. Power Up
图8-9. Overvoltage Response
图8-10. Output Short-Circuit During Steady-State
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9 Power Supply Recommendations
The TPS22811x devices are designed for a supply voltage range of 2.7 V ≤ VIN ≤ 16 V. TI recommends an
input ceramic bypass capacitor higher than 0.1 μF if the input supply is located more than a few inches from the
device. The power supply must be rated higher than the set current limit to avoid voltage droops during
overcurrent and short-circuit conditions.
9.1 Transient Protection
In the case of a short-circuit or device turn off during steady-state when the device interrupts current flow, the
input inductance generates a positive voltage spike on the input, and the output inductance generates a negative
voltage spike on the output. The peak amplitude of voltage spikes (transients) is dependent on the value of
inductance in series to the input or output of the device. Such transients can exceed the absolute maximum
ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients
include:
• Minimize lead length and inductance into and out of the device.
• Use a large PCB GND plane.
• Connect a Schottky diode from the OUT pin ground to absorb negative spikes.
• Connect a low ESR capacitor larger than 1 μF at the OUT pin very close to the device.
• Use a low-value ceramic capacitor CIN = 1 μF to absorb the energy and dampen the transients. The
capacitor voltage rating must be at least twice the input supply voltage to be able to withstand the positive
voltage excursion during inductive ringing.
Use 方程式15 to estimate the approximate value of input capacitance:
L
IN
V
= V + I ×
LOAD
(15)
SPIKE Absolute
IN
C
IN
where
– VIN is the nominal supply voltage.
– ILOAD is the load current.
– LIN equals the effective inductance seen looking into the source.
– CIN is the capacitance present at the input.
• Some applications can require the addition of a Transient Voltage Suppressor (TVS) to prevent transients
from exceeding the absolute maximum ratings of the device. In some cases, even if the maximum amplitude
of the transients is below the absolute maximum rating of the device, a TVS can help to absorb the excessive
energy dump and prevent it from creating very fast transient voltages on the input supply pin of the IC, which
can couple to the internal control circuits and cause unexpected behavior.
图9-1 shows the circuit implementation with optional protection components.
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VIN = 2.7 to 16 V
VOUT
IN
OUT
R1
COUT
CLOAD
D2
EN/UVLO
PGTH
TPS22811
R2
CIN
D1
EN/OVLO
dVdt
PG
GND
IMON
R3
RIMON
CDVDT
图9-1. Circuit Implementation with Optional Protection Components
9.2 Output Short-Circuit Measurements
Obtaining repeatable and similar short-circuit testing results is difficult. The following contribute to variation in
results:
• Source bypassing
• Input leads
• Circuit layout
• Component selection
• Output shorting method
• Relative location of the short
• Instrumentation
The actual short exhibits a certain degree of randomness because it microscopically bounces and arcs. Ensure
that configuration and methods are used to obtain realistic results. Do not expect to see waveforms exactly like
those in this data sheet because every setup is different.
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10 Layout
10.1 Layout Guidelines
• For all applications, TI recommends a ceramic decoupling capacitor of 0.1 μF or greater between the IN
terminal and GND terminal.
• The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care
must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the
GND terminal of the IC.
• High current-carrying power-path connections must be as short as possible and must be sized to carry at
least twice the full-load current.
• The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible
trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate
ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground
reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the
system power ground plane using a star connection.
• The IN and OUT pins are used for heat dissipation. Connect to as much copper area on top and bottom PCB
layers using as possible with thermal vias. The vias under the device also help to minimize the voltage
gradient across the IN and OUT pads and distribute current uniformly through the device, which is essential
to achieve the best on-resistance and current sense accuracy.
• Locate the following support components close to their connection pins:
– RIMON
– CdVdT
– Resistors for the EN/UVLO, EN/OVLO pins
• Connect the other end of the component to the GND pin of the device with shortest trace length. The trace
routing for the RIMON and CdVdt components to the device must be as short as possible to reduce parasitic
effects on the current monitor and soft start timing. These traces must not have any coupling to switching
signals on the board.
• Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the
device they are intended to protect. These protection devices must be routed with short traces to reduce
inductance. For example, TI recommends a protection Schottky diode to address negative transients due to
switching of inductive loads. TI also recommends to add a ceramic decoupling capacitor of 1 μF or greater
between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to
minimize the loop area formed by the Schottky diode/bypass-capacitor connection, the OUT pin and the GND
terminal of the IC.
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10.2 Layout Example
Inner GND layer
Top Power layer
Bottom Power layer
6
OUT
IN
OUT
5
IN
图10-1. Layout Example
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS22811EVM eFuse Evaluation Board
• Texas Instruments, TPS22811x Design Calculator
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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27-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS22811LRPWR
ACTIVE
VQFN-HR
RPW
10
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2KZH
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
2.1
1.9
A
B
2.1
1.9
PIN 1 IDENTIFICATION
(0.1) TYP
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.45
PKG
4X
SQ (0.15) TYP
4X 0.475
4
2X 0.25
6
5
7
0.35
4X
4X 0.475
0.25
0.1
C A B
C
0.05
2.1
1.9
2X
2X 0.45
PKG
4X
0.3
0.2
0.1
0.05
C A B
C
1
10
0.3
0.2
PIN 1 ID
(OPTIONAL)
4X
0.5
0.3
0.35
0.25
8X
2X
0.1
C A B
C
0.1
C A B
0.05
0.05
C
4225183/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.45)
4X (0.475)
2X (0.25)
1
10
4X (0.25)
4X
(0.225)
PKG
2X
2X
(1.75)
(2.4)
4X (0.3)
4X (0.475)
7
4
4X
(0.65)
(R0.05) TYP
6
5
2X (0.3)
4X (0.25)
PKG
8X (0.6)
LAND PATTERN EXAMPLE
SCALE: 30X
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225183/A 08/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
RPW0010A
(1.8)
(1.425)
4X (0.4625)
2X (0.25)
METAL TYP
1
10
4X (0.25)
4X
(0.63)
PKG
2X
(1.75)
4X (0.225)
4X (0.275)
4X
4X (0.4625)
(1.06)
7
4
4X
(0.65)
(R0.05)
TYP
6
5
4X (0.28)
4X (0.225)
PKG
8X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
PADS 1, 4,7 & 10: 93%; PADS 5 & 6: 82%
SCALE: 30X
4225183/A 08/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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