TPS1HC30-Q1 [TI]
汽车类 30mΩ、5A 单通道智能高侧开关;
| 型号： | TPS1HC30-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 30mΩ、5A 单通道智能高侧开关 开关 |
| 文件： | 总55页 (文件大小：3364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS1HC30-Q1
ZHCSP75A –JULY 2022 –REVISED DECEMBER 2022
TPS1HC30-Q1 30mΩ、5A 单通道汽车智能高侧开关
1 特性
2 应用
• 具有全面诊断功能的单通道智能汽车高侧电源开关
– 开漏状态输出
– 电流检测模拟输出
• 汽车显示模块
• ADAS 模块
• 座椅舒适模块
• HVAC 控制模块
• 车身控制模块
• 宽工作电压范围：3V 至28V
• 低待机电流：85°C 下为2.5µA
• 工作结温范围：–40°C 至150°C
• 支持1.8V、3.3V 和5V 逻辑电压
• 通过故障检测电压调节功能实现ADC 保护
• 可编程电流限制和精度±15%（3.5A 时）
• 高精度电流检测，1A 时精度为±6%
• 保护
3 说明
TPS1HC30-Q1 器件是一款具有全方位保护的高侧电源
开关，它集成有NMOS 功率FET 和电荷泵，专用于对
各类负载进行智能控制。该器件凭借着精确的电流检测
和可编程电流限制特性在市场上脱颖而出。
– 过载和短路保护
– 感性负载负电压钳位
– 欠压锁定(UVLO) 保护
– 具备自恢复功能的热关断和热振荡
– 接地失效保护和失电保护
– 反向电池保护
由于输入引脚具有 1.5V 低逻辑高电平阈值 VIH，可以
使用低至 1.8V 的 MCU。高精度电流检测功能可实现
更好的实时监测效果和更准确的诊断，无需进一步校
准。外部高精度电流限制功能允许根据应用设置电流限
制值。该器件通过在启动或短路条件下有效地钳制浪涌
电流，极大地提高了系统的可靠性。TPS1HC30-Q1 器
件可用作各种阻性、感性和容性负载（包括低瓦数灯
泡、LED、继电器、电磁阀和加热器）的高侧电源开
关。
• 诊断
– 开启和关闭状态输出的开路负载和电池短路检测
– 过载和接地短路检测
– 热关断和热振荡检测
封装信息
封装(1)
• 资格认证
封装尺寸（标称值）
器件型号
– 符合面向汽车应用的AEC-Q100 标准：
PWP（HTSSOP、
14）
• 温度等级1：–40°C 至+125°C，TA
– 通过ISO7637-2 和ISO16750-2 电瞬变抗扰度
认证
TPS1HC30-Q1
4.40mm × 5.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 14 引脚热增强型PWP 封装
VOU
RILIM
电流限制应用
功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGL6
TPS1HC30-Q1
ZHCSP75A –JULY 2022 –REVISED DECEMBER 2022
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................37
9 Application and Implementation..................................39
9.1 Application Information............................................. 39
9.2 Typical Application.................................................... 39
9.3 Power Supply Recommendations.............................43
9.4 Layout....................................................................... 44
10 Device and Documentation Support..........................46
10.1 Documentation Support.......................................... 46
10.2 接收文档更新通知................................................... 46
10.3 支持资源..................................................................46
10.4 Trademarks.............................................................46
10.5 静电放电警告.......................................................... 46
10.6 术语表..................................................................... 46
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 建议运行条件.............................................................. 4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 SNS Timing Characteristics........................................ 8
6.7 Switching Characteristics............................................8
6.8 Typical Characteristics..............................................10
7 Parameter Measurement Information..........................15
8 Detailed Description......................................................17
8.1 Overview...................................................................17
Information.................................................................... 46
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (July 2022) to Revision A (December 2022)
Page
• 将器件状态从预告信息更改为量产数据.............................................................................................................1
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5 Pin Configuration and Functions
14
13
GND
EN
1
2
3
4
NC
VBB
VBB
DIAG_EN
12
11
10
9
Thermal
Pad
FAULT
LATCH
SNS
NC
5
6
7
VOUT
VOUT
NC
8
ILIM
图5-1. PWP Package, 14-Pin HTSSOP (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
Ground of device. Connect to resistor-diode ground network to have
reverse battery protection.
1
GND
Power
2
3
4
5
6
EN
DIAG_EN
FAULT
LATCH
SNS
I
I
Input control for channel activation, internal pulldown
Enable-disable pin for diagnostics, internal pulldown
O
I
Open-drain global fault output. Referred to FAULT, FLT, or fault pin.
Thermal shutdown behavior, latch-off or auto-retry, internal pulldown
Output corresponding sense value based on sense ratio
O
Adjustable current limit. Short to ground or leave floating if external
current limit is not used.
7
ILIM
O
8, 11, 14
9, 10
NC
VOUT
VBB
Pad
N/A
Power
Power
—
No internal connection
Output of high-side switch, connected to load
Power supply
12, 13
Thermal Pad
Thermal Pad, internally shorted to ground
Recommended Connection for Unused Pins
The TPS1HC30-Q1 is designed to provide an enhanced set of diagnostic and protection features. However, if
the system design only allows for a limited number of I/O connections, some pins can be considered as optional.
表5-2. Connections For Optional Pins
PIN NAME
CONNECTION IF NOT USED
IMPACT IF NOT USED
SNS
Analog sense is not available.
Ground through 1-kΩresistor
With LATCH unused, the device auto-retries after a fault. If latched
Float or ground through RPROT behavior is desired, but the system describes limited I/O, it is possible to
LATCH
resistor
use one microcontroller output to control the latch function of several high
side channels.
If the ILIM pin is left floating, the device is set to the default internal current-
limit threshold. This impact is considered a fault state for the device.
ILIM
Float
Float or ground through RPROT With DIA_EN unused, the analog sense, open-load, and short-to-battery
DIA_EN
resistor
diagnostics are not available.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Maximum continuous supply voltage, VBB
28
35
Load dump voltage, VLD
Reverse Polarity Voltage
ISO16750-2:2010(E)
V
Maximum duration of 3 minutes and with the
application circuit
V
–18
Enable pin current, IEN
Enable pin current, IEN
20
7
mA
V
–1
–1
Enable pin voltage, VEN
Diagnostic Enable pin current, IDIA_EN
Diagnostic Enable pin voltage, VDIA_EN
Sense pin current, ISNS
20
7
mA
V
–1
–1
10
5.5
10
7
mA
V
–100
–1
Sense pin voltage, VSNS
Latch pin current, ILATCH
Latch pin voltage, VLATCH
FLT pin current, IFLT
-1
mA
V
–1
-30
10
7
mA
V
FLT pin voltage, VFLT
–0.3
Reverse ground current, IGND
Storage temperature, Tstg
VBB < 0 V
mA
°C
–50
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±4000
UNIT
All pins except VS and VOUT
VS and VOUT
Human-body model (HBM), per AEC Q100-002
Classification Level 2(2)
Electrostatic
discharge(1)
V(ESD)
V
Charged-device model (CDM), per AEC Q100-011
Classification Level C5
All pins
±750
(1) All ESD strikes are with reference from the pin mentioned to GND
(2) AEC-Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specifications.
6.3 建议运行条件
在自然通风条件下的工作温度范围内测得（除非另有说明）(1)
最小值
最大值
单位
标称电源电压(1)
扩展电源电压(2)
短路电源电压能力
使能电压
VVBB_NOM
VVBB_EXT
VVBB_SC
VEN
3.5
18
V
V
2.6
28
28
V
-1
-1
5.5
5.5
5.5
7
V
VDIA_EN
VLATCH
VSNS
V
诊断使能电压
闩锁电压
-1
V
-1
V
检测电压
TA
-40
125
°C
自然通风工作温度
(1) 所有工作电压条件均以器件GND 为基准进行测量。
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(2) 器件将在更广的工作电压范围工作，但某些时序参数值可能不适用。有关使用的电压，请参阅相应章节。此外，有关更多说明，请参见
节9.3。
6.4 Thermal Information
TPS1HC30-Q1
THERMAL METRIC(1) (2)
PWP (HTSSOP)
UNIT
14 PINS
44.2
33.8
19.2
1.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
19.2
5.0
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the SPRA953 application report.
(2) The thermal parameters are based on a 4-layer PCB according to the JESD51-5 and JESD51-7 standards.
6.5 Electrical Characteristics
VBB = 6 V to 28 V, TA = –40°C to 125°C (unless otherwise noted); Typical application is 13.5 V, 10 Ω, RILIM=Open (unless
otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE AND CURRENT
TJ=25°C
35
33
43
45
V
V
VClamp
VDS clamp voltage
TJ = –40°C to 150°C
VBB undervoltage lockout
rising
VUVLOR
VUVLOF
3.0
2.4
3.5
2.6
4.0
3.0
V
V
Measured with respect to the GND pin of the device
VBB undervoltage lockout
falling
TJ = 25°C
0.3
2.5
9
µA
µA
µA
µA
µA
Standby current (total
device leakage including
MOSFET channel)
VBB ≤18 V, VEN
VDIA_EN = 0 V, VOUT = 0 V
=
ISB
TJ = 85°C
TJ = 125°C
TJ = 25°C
TJ = 85°C
0.01
0.3
2.5
VBB ≤18 V, VEN
VDIA_EN = 0 V, VOUT = 0 V
=
IOUT(standby) Output leakage current
Current consumption in
diagnostic mode
VBB ≤18 V, ISNS = 0 mA
VEN = 0 V, VDIA_EN = 5 V, VOUT = 0V
IDIA
1.3
1.6
3
3
mA
mA
Quiescent current
channel enabled
VBB ≤28 V
VEN = VDIA_EN = 5 V, IOUTx = 0 A
IQ
ILNOM
tSTBY
Continuous load current Channel enabled, TAMB = 85°C
Standby mode delay time VENx = VDIA_EN = 0 V to standby
4.5
20
A
ms
RON CHARACTERISTICS
TJ = 25°C
TJ = 150°C
TJ = 25°C
TJ = 150°C
TJ = 25°C
TJ = 150°C
30
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
6 V ≤VBB ≤28 V,
IOUT= 1 A
On-resistance
(Includes MOSFET
channel and metallization
on die)
57
57
75
RON
3 V ≤VBB ≤6 V,
IOUT =1 A
30
On-resistance during
reverse polarity
RON(REV)
-18 V ≤VBB ≤-6 V
57
1
Source-to-drain body
diode voltage
VF
0.3
0.7
V
VEN = 0 V IOUT = –1 A
CURRENT SENSE CHARACTERISTICS
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6.5 Electrical Characteristics (continued)
VBB = 6 V to 28 V, TA = –40°C to 125°C (unless otherwise noted); Typical application is 13.5 V, 10 Ω, RILIM=Open (unless
otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
1560
3.8
MAX
UNIT
Current sense ratio
IOUT / ISNS
KSNS
IOUT = 1.5 A
mA
%
IOUT = 6 A
3
4
–3
–4
1.92
0.96
mA
%
IOUT = 3 A
mA
%
IOUT = 1.5 A
IOUT = 750 mA
IOUT = 300 mA
4
–4
0.48
mA
%
6
–6
0.192
0.096
0.0481
0.0192
0.0096
0.0048
mA
%
10
15
25
40
60
80
–10
–15
–25
–40
–60
-80
Current sense current
and accuracy
VBB > VBB_ISNS, VEN
VDIA_EN = 5 V
=
ISNSI
mA
%
IOUT = 150 mA
IOUT = 75 mA
IOUT = 30 mA
IOUT = 15 mA
IOUT = 7.5 mA
mA
%
mA
%
mA
%
mA
%
SNS CHARACTERISTICS
VDIA_EN = 5 V
VDIA_EN = 3.3 V
VDIA_EN = VIH
4.2
3.3
2.8
5
3.5
5.77
3.75
3.5
V
V
VSNSFH
VSNS fault high-level
3.15
6.6
V
ISNSFH
ISNS fault high-level
VDIA_EN > VIH,DIAG_EN
mA
VBB headroom needed
VBB_ISNS
for full current sense and VDIAG_EN = 3.3 V
fault functionality
5.3
6.5
V
V
VBB headroom needed
for full current sense and VDIAG_EN = 5 V
fault functionality
VBB_ISNS
CURRENT LIMIT CHARACTERISTICS
RILIM = 7.15 kΩto
71.5 kΩ
TJ = –40°C to
150°C dI/dt < 0.01 A/ms
ICL_LINPK
Linear Mode peak
1.4 × ICL
2 × ICL
A
A
Peak current enabling
into permanent short
RILIM = 7.15 kΩto
71.5 kΩ
ICL_ENPS
TJ = –40°C to 150°C
TJ = –40°C to 150°C
15
23
A
A
A
A
OVCR Peak current
threshold when short is
applied while switch
enabled
RILIM ≥35 kΩ
IOVCR
15 kΩ ≤RILIM < 35 kΩ
RILIM < 15kΩ
33
RILIM = GND
9.1
13
5
16.9
ICL Current Limit
Threshold(1)
TJ = –40°C to 150°C,
VDS = 3 V
RILIM = open, or out of
range
ICL
A
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6.5 Electrical Characteristics (continued)
VBB = 6 V to 28 V, TA = –40°C to 125°C (unless otherwise noted); Typical application is 13.5 V, 10 Ω, RILIM=Open (unless
otherwise specified)
PARAMETER
TEST CONDITIONS
RILIM = 7.15 kΩ
MIN
65.6
76.5
69
TYP
87.5
90
MAX
109.4
103.5
115
UNIT
A * kΩ
A * kΩ
A * kΩ
TJ = –40°C to 150°C,
KCL
Current Limit Ratio(1)
RILIM = 25 kΩ
VDS = 3 V
95
RILIM = 71.5 kΩ
FAULT CHARACTERISTICS
Open-load (OL) detection
RVOL
VEN = 0 V, VDIA_EN = 5 V
150
400
kΩ
internal pull-up resistor
Open-load (OL) detection
deglitch time
VEN = 0 V, VDIA_EN = 5 V, When VBB –VOUT < VOL
duration longer than tOL. Openload detected.
,
tOL
1000
µs
Open-load (OL) detection
voltage
VOL
VFLT
tOL1
VEN = 0 V, VDIA_EN = 5 V
IFLT = 2.5 mA
1.5
0.5
V
V
FLT low output voltage
OL and STB indication-
time from EN falling
VEN = 5 V to 0 V, VDIA_EN = 5 V
IOUT = 0 mA, VOUT = VBB - VOL
500
1000
µs
OL and STB indication-
time from DIA_EN rising IOUT = 0 mA, VOUT = VBB - VOL
VEN = 0 V, VDIA_EN = 0 V to 5 V
tOL2
1000
µs
°C
°C
TABS
TREL
Thermal shutdown
165
85
Relative thermal
shutdown
Thermal shutdown
hysteresis
THYS
25
°C
µs
µs
ms
VDIA_EN = 5 V
Time between fault and FLT asserting
tFAULT_FLT Fault indication-time
tFAULT_SNS Fault indication-time
60
60
3
VDIA_EN = 5 V
Time between fault and ISNS settling at VSNSFH
Time from fault shutdown until switch re-enable
(thermal shutdown).
tRETRY
Retry time
1
2
EN PIN CHARACTERISTICS
VIL, EN
VIH, EN
VIHYS, EN
REN
Input voltage low-level
Input voltage high-level
Input voltage hysteresis
Internal pulldown resistor
Input current low-level
Input current high-level
No GND Network
No GND Network
0.8
V
1.5
V
280
350
2.2
14
mV
kΩ
µA
µA
200
500
IIL, EN
VEN = 0.8 V
VEN = 5 V
IIH, EN
DIA_EN PIN CHARACTERISTICS
VIL, DIA_EN Input voltage low-level
VIH, DIA_EN Input voltage high-level
No GND Network
No GND Network
0.8
V
V
1.5
VIHYS,
Input voltage hysteresis
280
mV
DIA_EN
RDIA_EN
Internal pulldown resistor
Input current low-level
Input current high-level
100
250
2.2
14
500
kΩ
µA
µA
IIL, DIA_EN
IIH, DIA_EN
VDIA_EN = 0.8 V
VDIA_EN = 5 V
LATCH PIN Characteristics
VIL, LATCH
Input voltage low-level
No GND Network
No GND Network
0.8
1.3
V
V
VIH, LATCH Input voltage high-level
1.5
0.7
VIHYS,
Input voltage hysteresis
280
1
mV
LATCH
RLATCH
Internal pulldown resistor
MΩ
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6.5 Electrical Characteristics (continued)
VBB = 6 V to 28 V, TA = –40°C to 125°C (unless otherwise noted); Typical application is 13.5 V, 10 Ω, RILIM=Open (unless
otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
2.2
14
MAX
UNIT
µA
IIL, LATCH
IIH, LATCH
Input current low-level
Input current high-level
VLATCH = 0.8 V
VLATCH = 5 V
µA
(1) Current limit regulation value will vary with increase of VDS voltage. For more information, see 节8.3.2
6.6 SNS Timing Characteristics
VBB = 6 V to 18 V, TJ = –40°C to +150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SNS TIMING - CURRENT SENSE
VENx= 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, IL = 1A
30
30
µs
µs
Settling time from rising edge of DIA_EN
50% of VDIA_EN to 90% of settled ISNS
tSNSION1
VEN = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, IL = 30 mA
VEN = VDIA_EN = 0 V to 5 V
VBB = 13.5 V RSNS = 1 kΩ, RLOAD
10 Ω
Settling time from rising edge of EN and
DIA_EN
50% of VDIA_EN VEN to 90% of settled ISNS
tSNSION2
tSNSION3
tSNSIOFF
=
150
150
20
µs
µs
µs
VEN = 0 V to 5 V, VDIA_EN = 5 V VBB =
13.5 V
RSNS = 1 kΩ, RLOAD = 10 Ω
Settling time from rising edge of EN with
DIA_EN HI;
50% of VDIA_EN VEN to 90% of settled ISNS
VEN = 5 V, VDIA_EN = 5 V to 0 V VBB
= 13.5 V
Settling time from falling edge of DIA_EN
RSNS = 1 kΩ, RL = 10 Ω
VEN = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 0.5 A to 3 A
tSETTLEH
tSETTLEL
Settling time from rising edge of load step
Settling time from falling edge of load step
20
20
µs
µs
VEN = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 3 A to 0.5 A
6.7 Switching Characteristics
VBB = 13.5 V, TJ = –40°C to +150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Channel Turn-on delay time (from
Standby)
VBB = 13.5 V, RL = 10 Ω50% of EN
to 10% of VOUT
tDR
tDR
tDF
10
40
35
55
µs
Channel Turn-on delay time (from
Active)
VBB = 13.5 V, RL = 10 Ω50% of EN
to 10% of VOUT
10
10
45
45
µs
µs
VBB = 13.5 V, RL = 10 Ω50% of EN
to 90% of VOUT
Channel Turn-off delay time
VOUT rising slew rate
30
VBB = 13.5 V, 20% to 80% of VOUT
RL = 10 Ω
,
,
SRR
0.1
0.1
0.3
0.6
V/µs
VBB = 13.5 V, 80% to 20% of VOUT
SRF
fmax
tON
VOUT falling slew rate
Maximum PWM frequency
Channel Turn-on time
0.3
0.4
70
0.6
2
V/µs
kHz
µs
RL = 10 Ω
VBB = 13.5 V, RL = 10 Ω 50% of EN
to 80% of VOUT
30
30
145
VBB = 13.5 V, RL = 10 Ω 50% of EN
to 20% of VOUT
tOFF
Channel Turn-off time
70
145
µs
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6.7 Switching Characteristics (continued)
VBB = 13.5 V, TJ = –40°C to +150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1-ms enable pulse VBB = 13.5 V, RL
= 10 Ω
40
µs
–40
Turn-on and off matching
t
ON –tOFF
200-µs enable pulse, VBB = 13.5 V,
40
25
12
µs
%
%
RL = 10 Ω
–40
–25
–12
200-µs enable pulse (1-ms
period), VBB = 13.5 V, RL = 10 Ω
PWM accuracy - average load
current
ΔPWM
≤500 Hz, 50% Duty cycle VBB
13.5 V, RL = 10 Ω
=
Switching energy losses during turn-
on
EON
0.5
0.5
mJ
mJ
VBB = 13.5 V, RL = 10 Ω
VBB = 13.5 V, RL = 10 Ω
Switching energy losses during turn-
off
EOFF
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6.8 Typical Characteristics
All the following data are based on the mean value of the three lots samples, VVBB = 13.5 V if not specified.
45
40
35
30
25
20
15
10
5
2.2
2
3 V
6 V
8 V
13.5 V
18 V
24 V
28 V
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
0
-40 -20
0
20
40
60
80 100 120 140 160
1E-6 1E-5 0.0001
0.01 0.1
Time (s)
1 2 510
100 1000
Temperature (C)
VOUT = 0 V
VBB Varied
VEN = 0 V
VDIAG_EN = 0 V
图6-1. Transient Thermal Impedance
图6-2. Standby Current ISB vs Temperature
2.2
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
3 V
6 V
8 V
13.5 V
18 V
24 V
28 V
1.8
1.6
1.4
1.2
1
3 V
6 V
8 V
13.5 V
18 V
24 V
28 V
0.8
0.6
0.4
0.2
0
0.9
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
VOUT = 0 V
VBB Varied
VEN = 0 V
VDIAG_EN = 0 V
IOUT = 0 A
VBB Varied
VEN = 5 V
VDIAG_EN = 5 V
图6-3. Output Leakage Current IOUT,STBY vs Temperature
图6-4. Quiescent Current IQ vs Temperature
1.45
1.4
47.5
45
42.5
40
1.35
1.3
37.5
35
1.25
1.2
32.5
30
1.15
1.1
27.5
25
3 V
6 V
8 V
13.5 V
18 V
24 V
28 V
1.05
1
3 V
4 V
5 V
6 V
8 V
13.5 V
18 V
24 V
28 V
22.5
20
0.95
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
IOUT = 0 A
VBB Varied
VEN = 0 V
VDIAG_EN = 5 V
IOUT = 1 A
VBB Varied
VEN = 5 V
VDIAG_EN = 5 V
图6-5. Diagnostic Current IDIA vs Temperature
图6-6. RDSON vs Temperature
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6.8 Typical Characteristics (continued)
All the following data are based on the mean value of the three lots samples, VVBB = 13.5 V if not specified.
47.5
45
45
42.5
40
-40C
25C
85C
105C
125C
150C
-6 V
-13.5 V
-18 V
42.5
40
37.5
35
37.5
35
32.5
30
32.5
30
27.5
25
27.5
25
22.5
20
22.5
-40 -20
0
20
40
60
80 100 120 140 160
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
VBB (V)
Temperature (C)
IOUT = 1 A
VBB Varied
VEN = 5 V
VDIAG_EN = 5 V
IOUT = 1 A
VBB Varied
图6-7. RDSON vs VBB
VEN = 5 V
VDIAG_EN = 5 V
图6-8. RONREV vs Temperature
40
30
20
10
0
-40C
25C
85C
95C
105C
125C
150C
-10
-20
-30
2
3 45 7 10 20 30 50 100 200 500 1000
ILOAD (mA)
10000
VEN = 5 V
VDIAG_EN = 5 V
ROUT = 5 μH and 100 mΩ
ROUT varied
VBB = 13.5 V
VEN = 5 V
VDIAG_EN = 5 V
VDS = 3 V
RSNS = 1 kΩ
图6-9. KCL vs RILIM
图6-10. KSNS Error vs Load Current
2.25
2
3.5
3.48
3.46
3.44
3.42
3.4
-40C
25C
85C
105C
125C
150C
-40C
25C
85C
105C
125C
150C
1.75
1.5
1.25
1
0.75
0.5
0.25
0
3.38
3.36
-0.25
-0.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
VBB (V)
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
VBB (V)
IOUT = 1.5 A
VBB varied
VEN = 5 V
VDIAG_EN = 5 V
VEN = 5 V
VDIAG_EN = 5 V
ROUT = 5 μH and 100
mΩ
RSNS = 1 kΩ
VBB varied
图6-11. KSNS Error vs VBB
RSNS = 1 kΩ
图6-12. VSNSFH (3.3 V) vs VBB
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6.8 Typical Characteristics (continued)
All the following data are based on the mean value of the three lots samples, VVBB = 13.5 V if not specified.
75
72.5
70
5.1
5
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
67.5
65
62.5
60
6 V
13.5 V
18 V
24 V
28 V
57.5
55
-40C
25C
85C
105C
125C
150C
52.5
50
-40 -20
0
20
40
60
80 100 120 140 160
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
VBB (V)
Temperature (C)
VEN = 5 V
VDIAG_EN = 5 V
ROUT = 10 Ω
VEN = 5 V
VDIAG_EN = 5 V
ROUT = 5 μH and 100
mΩ
VBB varied
RSNS = 1 kΩ
图6-14. Turn-On Time TON vs Temperature
VBB varied
RSNS = 1 kΩ
图6-13. VSNSFH (5 V) vs VBB
80
75
70
65
60
55
50
45
40
35
0.54
0.51
0.48
0.45
0.42
0.39
0.36
0.33
0.3
6 V
13.5V
18 V
24 V
28 V
6 V
13.5 V
18 V
24 V
28 V
0.27
0.24
0.21
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
VEN = 5 V
VDIAG_EN = 5 V
ROUT = 10 Ω
VEN = 5 V
VDIAG_EN = 5 V
ROUT = 10 Ω
VBB varied
RSNS = 1 kΩ
VBB varied
RSNS = 1 kΩ
图6-16. Rising Slew Rate SRR vs Temperature
图6-15. Turn-Off Time TOFF vs Temperature
0.54
0.51
0.48
0.45
0.42
0.39
0.36
0.33
0.3
1.32
1.3
3 V
6 V
13.5 V
18 V
24 V
28 V
1.28
1.26
1.24
1.22
1.2
0.27
0.24
6 V
13.5 V
20 40
18 V
60
24 V
28 V
1.18
-40 -20
0
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
VEN = 5 V
VDIAG_EN = 5 V
VEN = 0 to 3.3 V
VDIAG_EN = 0 to 3.3 V
ROUT = 10 Ω
ROUT = 1 kΩ
VBB varied
VBB varied
RSNS = 1 kΩ
RSNS = 1 kΩ
图6-17. Falling Slew Rate SRF vs Temperature
图6-18. VIH vs Temperature
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6.8 Typical Characteristics (continued)
All the following data are based on the mean value of the three lots samples, VVBB = 13.5 V if not specified.
1.02
1.01
1
0.99
0.98
0.97
0.96
0.95
0.94
0.93
0.92
0.91
3 V
6 V
13.5 V
18 V
24 V
28 V
-40 -20
0
20
40
60
80 100 120 140 160
Temeprature (C)
VEN = 0 to 5 V
VDIAG_EN = 0 V
ROUT = 10 Ω
VEN = 3.3 to 0 V
VDIAG_EN = 3.3 to 0 V
ROUT = 1 kΩ
VBB varied
VBB = 13.5 V
RSNS = 1 kΩ
RSNS = 1 kΩ
图6-20. Turn-On Time (tON
)
图6-19. VIL vs Temperature
VEN = 5 to 0 V
VDIAG_EN = 0 V
IOUT = 1 A to 5 A
VBB = 13.5 V
VEN = 5 V
VDIAG_EN = 5 V
ROUT = 10 Ω
VBB = 13.5 V
RSNS = 1 kΩ
RSNS = 1 kΩ
图6-22. ISNS Settling Time (tSNSION) on Load Step
图6-21. Turn-Off Time (tOFF
)
VEN = 5 V
VDIAG_EN = 5 V
ROUT = 5 mH
VBB = 13.5 V
VEN = 5 V
VDIAG_EN = 5 V
RILIM = GND
ROUT = 5 μH and
100 mΩ
RSNS = 1 kΩ
VBB = 13.5 V
RSNS = 1 kΩ
RILIM = 7.15 kΩ
图6-24. 5-mH Inductive Load Driving
图6-23. Short Circuit With ILIM Shorted to Ground
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6.8 Typical Characteristics (continued)
All the following data are based on the mean value of the three lots samples, VVBB = 13.5 V if not specified.
VEN = 5 V
VDIAG_EN = 5 V
ROUT = 470 μF and 20 Ω
VBB = 13.5 V
RSNS = 1 kΩ
RILIM = 71.5 kΩ
图6-25. 470-μF Capacitive Load Driving
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7 Parameter Measurement Information
IEN
EN
IVBB
VBB
IDIAG_EN
DIAG_EN
FLT
IFLT
ILATCH
ISNS
IILIM
VOUT
IOUT
LATCH
SNS
ILIM
GND
图7-1. Parameter Definitions
(1)
VEN
50%
50%
90%
90%
tDR
tDF
VOUT
10%
10%
tON
tOFF
Rise and fall time of VEN is 100 ns.
图7-2. Switching Characteristics Definitions
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VEN
VDIA_EN
IOUT
ISNS
tSNSION1
tSNSION2
tSNSION3
tSNSIOFF1
VEN
VDIA_EN
IOUT
ISNS
tSETTLEH
tSETTLEL
VEN
VDIA_EN
TJ
ISNS
tSNSTON1
tSNSTON2
tSNSTOFF
Rise and fall times of control signals are 100 ns. Control signals include: EN, DIA_EN.
图7-3. SNS Timing Characteristics Definitions
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8 Detailed Description
8.1 Overview
The TPS1HC30-Q1 is a single-channel, fully-protected, high side power switch with an integrated NMOS power
FET and charge pump. Full diagnostics and high-accuracy current-sense features enable intelligent control of
the load. Low logic high threshold, VIH, of 1.5 V on the input pins allow use of MCUs down to 1.8 V. A
programmable current-limit function greatly improves the reliability of the whole system. The device diagnostic
reporting has two pins to support both digital status and analog current-sense output, both of which can be set to
the high-impedance state when diagnostics are disabled, for multiplexing the MCU analog or digital interface
among devices.
The digital status report is implemented with an open-drain structure on the fault pin. When a fault condition
occurs, the pin is pulled down to GND. An external pullup is required to match the microcontroller supply level.
High-accuracy current sensing allows a better real-time monitoring effect and more-accurate diagnostics without
further calibration. A current mirror is used to source 1 / KSNS of the load current, which is reflected as voltage on
the SNS pin. KSNS is a constant value across the temperature and supply voltage. The current-sensing function
operates normally within a wide linear region from 0 V to 4 V. The SNS pin can also report a fault by forcing a
voltage of VSNSFH that scales with the diagnostic enable voltage so that the maximum voltage seen by the
system ADC is within an acceptable value. This action removes the need for an external Zener diode or resistor
divider on the SNS pin.
The external high-accuracy current limit allows setting the current limit value by application. The current limit
highly improves the reliability of the system by clamping the inrush current effectively under start-up or short-
circuit conditions. Also, the current limit can save system costs by reducing PCB trace, connector size, and the
preceding power-stage capacity. An internal current limit is also implemented in this device. The lower value of
the external or internal current-limit value is applied.
An active drain and source voltage clamp is built in to address switching off the energy of inductive loads, such
as relays, solenoids, pumps, motors, and so forth. During the inductive switching-off cycle, both the energy of the
power supply (EBAT) and the load (ELOAD) are dissipated on the high side power switch itself. With the benefits of
process technology and excellent IC layout, the TPS1HC30-Q1 device can achieve excellent power dissipation
capacity, which can help save the external free-wheeling circuitry in most cases. For more details, see Inductive-
Load Switching-Off Clamp.
Short-circuit reliability is critical for smart high side power-switch devices. The standard of AEC-Q100-012 is to
determine the reliability of the devices when operating in a continuous short-circuit condition. Different grade
levels are specified according to the pass cycles. This device is qualified with the highest level, Grade A, 1
million times short-to-GND certification.
The TPS1HC30-Q1 device can be used as a high side power switch for a wide variety of resistive, inductive, and
capacitive loads, including the low-wattage bulbs, LEDs, relays, solenoids, and heaters.
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8.2 Functional Block Diagram
VOUT
RILIM
8.3 Feature Description
8.3.1 Accurate Current Sense
The high-accuracy current-sense function is internally implemented, which allows a better real-time monitoring
effect and more-accurate diagnostics without further calibration. A current mirror is used to source 1 / KSNS of the
load current, flowing out to the external resistor between the SNS pin and GND, and reflected as voltage on the
SNS pin.
KSNS is the ratio of the output current and the sense current. The accuracy values of KSNS quoted in the
electrical characteristics do take into consideration temperature and supply voltage. Each device was internally
calibrated while in production, so post-calibration by users is not required in most cases.
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4 A
1 A
dK/K = 3%
100 mA
dK/K = 5%
50 mA
dK/K = 7%
25 mA
dK/K = 10%
5 mA
dK/K = 80%
0 A
图8-1. Current-Sense Accuracy
The maximum voltage out on the SNS pin is clamped to VSNSFH, which is the fault voltage level. To make sure
that this voltage is not higher than the system can tolerate, TI has correlated the voltage coming in on the
DIAG_EN pin with the maximum voltage out on the SNS pin. If DIAG_EN is between VIH and 3.3 V, the
maximum output on the SNS pin is approximately 3.3 V. However, if the voltage at DIAG_EN is above 3.3 V,
then the fault SNS voltage, VSNSFH, tracks that voltage up to 5 V. Tracking is done because the GPIO voltage
output that is powering the diagnostics through DIAG_EN is close to the maximum acceptable ADC voltage
within the same microcontroller. Therefore, the sense resistor value, RSNS, can be chosen to maximize the range
of currents needed to be measured by the system. The RSNS value must be chosen based on application need.
The maximum usable RSNS value is bounded by the ADC minimum acceptable voltage, VADC,min, for the smallest
load current needed to be measured by the system, ILOAD,min. The minimum acceptable RSNS value has to
ensure the VSNS voltage is below the VSNSFH value so that the system can determine faults. This difference
between the maximum readable current through the SNS pin, ILOAD,max × RSNS, and the VSNSFH is called the
headroom voltage, VHR. The headroom voltage is determined by the system but is important so that there is a
difference between the maximum readable current and a fault condition. Therefore, the minimum RSNS value has
to be the VSNSFH minus the VHR times the sense current ratio, KSNS divided by the maximum load current the
system must measure, ILOAD,max. Use the following equation to see the boundary equation.
(VSNSFH –VHR) × KSNS / ILOAD,max ≤RSNS ≤VADC,min × KSNS / ILOAD,min
(1)
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Current Sense
Voltage
VSNSFH
ADC Full Scale Range, VADC,max
Headroom, VHR
Over Current
Max Measurable Current
Max Nominal Current
1
Normal
RSNS
Open Load Current, VADC,min
Sense Current
图8-2. Voltage Indication on the Current-Sense Pin
The maximum current the system wants to read, ILOAD,max, must be below the current-limit threshold because
after the current-limit threshold is tripped the VSNS value goes to VSNSFH. Additionally, currents being measured
must be below 6 A to ensure that the current sense output is not saturated.
VBAT
VBB
Iout/K
Iout/KILIM
VSNSFH
Iout
Voltage
Scaling
–
+
DIAG_EN
VOUT
CURRENT
CLAMP
Vcl,th
SNS
ILIM
RSNS
RILIM
图8-3. Current-Sense and Current-Limit Block Diagram
Because this scheme adapts based on the voltage coming in from the MCU, there is no need to have a Zener
diode on the SNS pin to protect from high voltages.
8.3.2 Programmable Current Limit
A high-accuracy current limit allows higher reliability, which protects the power supply during short circuit or
power up. Also, a current limit can save system costs by reducing PCB traces, connector size, and the capacity
of the preceding power stage.
Current limit offers protection from over-stressing to the load and integrated power FET. Current limit holds the
current at the set value, and pulls up the SNS pin to VSNSFH and asserts the FLT pin as diagnostic reports. The
three current-limit thresholds are:
• External programmable current limit –An external resistor, RILIM, is used to set the channel current limit.
When the current through the device exceeds ICL (current limit threshold), a closed loop steps in immediately.
VGS voltage regulates accordingly, leading to the VDS voltage regulation. When the closed loop is set up, the
current is clamped at the set value. The external programmable current limit provides the capability to set the
current-limit value by application.
Additionally, this value can be dynamically changed by changing the resistance on the ILIM pin. This
information can be seen in the Applications section.
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• Internal current limit: ILIM pin shorted to ground –If the external current limit is out of range on the lower end
or the ILIM pin is shorted to ground, the internal current limit is fixed and typically 12 A. To use the internal
current limit for large-current applications, tie the ILIM pin directly to the device GND.
• Internal current limit: ILIM pin open –If the external resistor is out of range on the higher end or the ILIM pin
is open, the current limit reverts to 6 A or half the current limit range. This level is still above the nominal
operation for the device to operate in DC STEADY state, but is low enough that if a pin fault occurs and the
RILIM opens up, the current does not default to the highest rating and put additional stress on the power
supply.
Both the internal current limit (Ilim,nom) and external programmable current limit are always active when VBB is
powered and EN is high. The lower value one (of ILIM and the external programmable current limit) is applied as
the actual current limit. The typical deglitch time for the current limit to assert is 2.5 µs.
Note that if a GND network is used (which leads to the level shift between the device GND and board GND), the
ILIM pin must be connected with device GND. Use Equation 2 to calculate RILIM
.
RILIM = KCL / ILIM
(2)
For better protection from a "hot short" condition (when VBB is high, channel is on, and a short to GND happens
suddenly), an overcurrent protection, OVCR, circuit is triggered that makes sure to limit the maximum current the
device allows to go through. With this OVCR, the device is protected during "hot short" events.
For more information about the current limiting feature, see the Short-Circuit and Overload Protection section.
Current Limit Accuracy Across VDS
The TPS1HC30-Q1 has very tight accuracy of the current limit regulation level across the full range of currents
and temperature. This accuracy is defined at several defined RILIM values, 7.15 kΩ, 25 kΩ, and 71.5 kΩ
specified in the Electrical Characteristics at VDS = 3 V. However, as VDS (VBB – VOUT) increases , the current
regulation value also slightly increases. Taking a typical device, at the 3 different current limits ranges specified,
sweeping the VDS voltage, and plotting the regulation value gives the graphs below.
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
-1
5 V VDS
6 V VDS
9 V VDS
13.5 V VDS
18 V VDS
24 V VDS
28 V VDS
0
0.0001
0.0002
0.0003
0.0004
0.0005
Time (s)
图8-4. Current Limit Regulation With Varying VDS, RILIM = 25 kΩ
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3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
5 V VDS
6 V VDS
9 V VDS
13.5 V VDS
18 V VDS
24 V VDS
28 V VDS
-0.3
0
0.0002
0.0004
0.0006
0.0008
0.001
Time (s)
图8-5. Current Limit Regulation With Varying VDS, RILIM = 71.5 kΩ
20
17.5
15
12.5
10
7.5
5 V VDS
6 V VDS
5
2.5
0
9 V VDS
13.5 V VDS
18 V VDS
24 V VDS
28 V VDS
-2.5
-5
0
0.0001
0.0002
0.0003
0.0004
Time (s)
图8-6. Current Limit Regulation With Varying VDS, RILIM = 7.15 kΩ
Using a point during the regulation time of each of the different RILIM settings, the graph can be normalized to
the specification in the electrical characteristics of VDS = 3 V which results in graph below.
图8-7. Current Limit Regulation Percentage Change With Varying VDS
Using this figure, the current limit regulation value can be estimated for any current limit value desired based on
the VDS value seen in the application. These graphs were taken on a typical device and should be used as
reference when accounting for current limit tolerances. As an example see table below for regulation values
based on setting the current limit close to the maximum load current. Note that RILIM tolerances are not factored
into analysis below.
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Max Load Current for
Application
RILIM
KCL
Minimum Current Limit
(at VDS = 3 V)
Short Circuit Regulation
value at VBB = VDS = 18 V
1.5 A
3 A
1.53 A (1.94 A -21%)
3.06 A (3.6 A - 15%)
6.03 A (7.8 A - 23%)
2.5 A, +11%
4.6A, +13%
10.6 A, +11%
47.5 kΩ
25 kΩ
92.4 A × kΩ
90 A × kΩ
88.2A × kΩ
6A
11.3 kΩ
8.3.2.1 Capacitive Charging
The following figure shows the typical setup for a capacitive load application and the internal blocks that function
when the device is used. Note that all capacitive loads have an associated "load" in parallel with the capacitor
that is described as a resistive load but in reality it can be inductive or resistive.
VBAT
VBB
Smart High Side Switch
EN
Gate Driver
KCL
ILIM1
=
RILIM
ILIM
Current Limiting
Circuit
(VBB – VOUT
RLOAD
)
INOM
=
VOUT
RILIM
CLOAD
GND
RLOAD
ILIM = CLOAD x dVDS/dt
图8-8. Capacitive Charging Circuit
The first thing to check is that the nominal DC current, INOM, is acceptable for the TPS1HC30-Q1 device. This
check can easily be done by taking the RθJA from the Thermal Information section and multiplying the RON of
the TPS1HC30-Q1 and the INOM with it, add the ambient temperature and if that value is below the thermal
shutdown value the device can operate with that load current. For an example of this calculation see the
Applications section.
The second key care about for this application is to make sure that the capacitive load can be charged up
completely without the device hitting thermal shutdown. The reason is because if the device hits thermal
shutdown during the charging, the resistive nature of the load in parallel with the capacitor starts to discharge the
capacitor over the duration the TPS1HC30-Q1 is off. Note that there are some application with high enough load
impedance that the TPS1HC30-Q1 hitting thermal shutdown and trying again is acceptable; however, for the
majority of applications, the system must be designed so that the TPS1HC30-Q1 does not hit thermal shutdown
while charging the capacitor.
With the current clamping feature of the TPS1HC30-Q1, capacitors can be charged up at a lower inrush current
than other high current limit switches. This lower inrush current means that the capacitor takes a little longer to
charge all the way up. The time that it takes to charge up follows the equation below.
ILIM = C × d(VBB –VDS) / dt
(3)
However, because the VDS for a typical 3.3-A application is much less than the VBB voltage (VDS ≅ 3.3A × 0.03
Ω= 100 mV, VBB ≅ 13.5 V), the equation can be rewritten and approximated as
dt = C × dVBB / ILIM
(4)
The following figure pictures charge timing.
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Voltage (V)
VBB
VBB - VDS
Time (s)
Current (A)
ICL_ENPS
ICL
INOM
dt
Time (s)
图8-9. Capacitive Charging Timing
Using this dt calculated based on the current limit, and finding the transient thermal impedance value at half the
dt value, the junction temperature rise can be approximated by the 方程式5.
ΔTJ ≅ 2/3 × VBB × ILIM × RθJA(dt/2)
(5)
For more information about capacitive charging with high-side switches, see the How to Drive Resistive,
Inductive, Capacitive, and Lighting Loads application note. This application note has information about the
thermal modeling available along with quick ways to estimate if a high-side switch can charge a capacitor to a
given voltage.
8.3.3 Inductive-Load Switching-Off Clamp
When an inductive load is switching off, the output voltage is pulled down to negative, due to the inductance
characteristics. The power FET can break down if the voltage is not clamped during the current-decay period. To
protect the power FET in this situation, internally clamp the drain-to-source voltage, namely VDS,clamp, the clamp
diode between the drain and gate.
VDS,clamp = VBAT œ VOUT
(6)
During the current-decay period (TDECAY), the power FET is turned on for inductance-energy dissipation. Both
the energy of the power supply (EBAT) and the load (ELOAD) are dissipated on the high side power switch itself,
which is called EHSD. If resistance is in series with inductance, some of the load energy is dissipated in the
resistance.
EHSD = EBAT + ELOAD = EBAT +EL œ ER
(7)
From the high side power switch view, EHSD equals the integration value during the current-decay period.
TDECAY
EHSD
=
VDS,clamp ì IOUT(t)dt
—
0
(8)
(9)
≈
’
R ì IOUT(MAX) + VOUT
L
∆
∆
«
÷
÷
◊
TDECAY
=
ì ln
R
VOUT
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»
ÿ
Ÿ
VBAT + VOUT
≈ R ì IOUT(MAX) + VOUT
’
…
ì R ì IOUT(MAX) œ VOUT ln
EHSD = L ì
∆
÷
÷
◊
R2
∆
VOUT
…
Ÿ
⁄
«
(10)
(11)
When R approximately equals 0, EHSD can be given simply as:
VBAT + VOUT
1
2
EHSD
=
ì L ì I2
OUT(MAX)
R2
VBAT
DRAIN
IN
L
-
-
SOURCE
+
GND
图8-10. Driving Inductive Load
INPUT
VBAT
VOUT
IOUT
VDS, clamp
EHSD
tDECAY
图8-11. Inductive-Load Switching-Off Diagram
As discussed previously, when switching off, battery energy and load energy are dissipated on the high side
power switch, which leads to the large thermal variation. For each high side power switch, the upper limit of the
maximum safe power dissipation depends on the device intrinsic capacity, ambient temperature, and board
dissipation condition. TI provides the upper limit of single-pulse energy that devices can tolerate under the test
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condition: VVS = 13.5 V, inductance from 0.1 mH to 400 mH, R = 0 Ω, FR4 2s2p board, 2- × 70-μm copper, 2- ×
35-μm copper, thermal pad copper area 600 mm2.
8.3.4 Full Protections and Diagnostics
表 8-1 is when DIAG_EN is enabled. When DIAG_EN is low, current sense and FLT are disabled. The output is
in high-impedance mode. For details, refer to the following table.
表8-1. Diagnostic Enable Logic Table
DIAG_EN IN Condition
Protections and Diagnostics
ON
HIGH
OFF
See Fault Table
ON
Diagnostics disabled, protection normal
SNS and FLT are high impedance
LOW
OFF
表8-2. Fault Table
Conditions
EN
VOUT
Latch
FLT
SNS
Behavior
Recovery
L
L
x
Hi-Z
Hi-Z
0
Normal
Normal
ILOAD
RON
×
H
H
x
x
ILoad / Ksns Normal
Holds the current at the current limit
VBB –
Overcurrent
L
L
VSNSFH until thermal shutdown or when the
overcurrent event is removed
ILIM
×
RLOAD
Auto retries when THYS
STG, Relative
Thermal
Shuts down when devices hits relative is met and it has been
H
H/L
L
VSNSFH
or absolute thermal shutdown
longer than tRETRY
amount of time
Shutdown,
Absolute Thermal
Shutdown
Shuts down when devices hits relative Stays off until latch or
H
H
L
H/L
H
H
x
L
Hi-Z
L
VSNSFH
or absolute thermal shutdown
enable is toggled
Normal behavior, user can judge
through the SNS pin output if it is an
open load or not
ILoad
/
KSNS = ~0
Open load, STB
Reverse Polarity
Internal pullup resistor is active. If VBB Clears when fault goes
H
x
VSNSFH
away
–VOUT < VOL then fault active.
Channel turns on to lower power
dissipation. Current into ground pin is
limited by external ground network.
x
x
x
x
x
表8-3. Deglitch Time for Each Fault Condition
Fault Condition
Deglitch Time
ILIM
2.5 µs
TREL
2.5 µs
TABS
20 µs
Open Load
500 µs
8.3.4.1 Short-Circuit and Overload Protection
TPS1HC30-Q1 provides output short-circuit protection to ensure that the device prevents current flow in the
event of a low impedance path to GND, removing the risk of damage or significant supply droop. The device is
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assured to protect against short-circuit events regardless of the state of the ILIM pins and with up to 28-V supply
at 125°C.
The following figure shows the behavior of the TPS1HC30-Q1 when the device is enabled into a short circuit.
Current (A)
ICL_ENPS
ICL
Thermal Shutdown
tRETRY
Time (s)
图8-12. Enable into Short-Circuit Behavior (LATCH=0)
Due to the low impedance path, the output current rapidly increases until it hits the current limit threshold. Due to
the response time of the current limiting circuit, the measured maximum current can temporarily exceed the ICL
value defined as ICL_ENPS, however, it settles to the current limit regulation value.
In this state, high power is dissipated in the FET, so eventually the internal thermal protection temperature for the
FET is reached and the device safely shuts down. Then, if LATCH pin is low, the part waits tRETRY amount of
time and turns back on.
图 8-13 shows the behavior of the TPS1HC30-Q1 when a short circuit occurs when the device is in the on-state
and already outputting current. When the internal pass FET is fully enabled, the current clamping settling time is
slower so to ensure overshoot is limited the device implements a fast-trip level at a level IOVCR. When this fast-
trip threshold is hit, the device immediately shuts off for a short period of time before quickly re-enabling and
clamping the current to ICL level after a brief transient overshoot to the higher peak current (ICL_ENPS) level. The
device then keeps the current clamped at the regulation current limit until the thermal shutdown temperature is
hit and the device safely shuts off.
Current (A)
IOVCR
ICL_ENPS
ICL
Thermal Shutdown
tRETRY
INOM
Time (s)
图8-13. On-State Short-Circuit Behavior
Overload Behavior shows the behavior of the TPS1HC30-Q1 when there is a small change in impedance that
sends the load current above the ICL threshold. The current rises to ICL_LINPK above the regulation level. Then
the current limit regulation loop kicks in and the current drops to the ICL value.
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Current (A)
ICL_ENPS
ICL_LINPK
ICL
INOM
tRETRY
Thermal Shutdown
Time (s)
图8-14. Overload Behavior
In all of these cases, the internal thermal shutdown is safe to hit repetitively. There is no device risk or lifetime
reliability concerns from repeatedly hitting this thermal shutdown level.
8.3.4.2 Open-Load and Short-to-Battery Detection
When the main channel is enabled, faults are diagnosed by reading the voltage on the SNS or FLT pin and
judged by the user. A benefit of high-accuracy current sense is that this device can achieve a very low open-load
detection threshold, which correspondingly expands the normal operation region. TI suggests 15 mA as the
upper limit for the open-load detection threshold and 30 mA as the lower limit for the normal operation current. In
图 8-15, the recommended open-load detection region is shown as the dark-shaded region and the light-shaded
region is for normal operation. As a guideline, do not overlap these two regions.
Normal Operation
Region
27.5 mA
10% Tolerance
25 mA
22.5 mA
18 mA
80% Tolerance
On State, Open Load/
Short to Battery
10 mA
2 mA
图8-15. On-State Open-Load Detection and Normal-Operation Diagram
In the off state, if a load is connected, the output voltage is pulled to 0 V. In the case of an open load, the output
voltage is close to the supply voltage, VBB – VOUT < Vol,off. The FLT pin goes low to indicate the fault to the
MCU, and the SNS pin is pulled up to VSNSFH. There is always a leakage current Iol,off present on the output, due
to the internal logic control path or external humidity, corrosion, and so forth. Thus, TI implemented an internal
pullup resistor to offset the leakage current. This pullup current must be less than the output load current to avoid
false detection in the normal operation mode. To reduce the standby current, TI implemented a switch in series
with the pullup resistor controlled by the DIAG_EN pin. The pullup resistor value is Rpu = 150 kΩ.
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VBAT
VBB
DIAG_EN
OPEN LOAD
SNS
FLT
Vol,off
FAULT
Rpu
OUT
EN
GND
图8-16. Open-Load Detection Circuit
8.3.4.3 Short-to-Battery Detection
Short-to-battery detection has the same detection mechanism and behavior as open-load detection, both in the
on-state and off-state. There is no way to differentiate between open load and short-to-battery in this device, but
the system detects the fault and protects accordingly. See 表8-2 for more details.
8.3.4.4 Reverse-Polarity and Battery Protection
Reverse-polarity, commonly referred to as reverse battery, occurs when the ground of the device goes to the
battery potential, VGND = VBAT, and the supply pin goes to ground, VBB = 0 V. In this case, if the EN pin has a
path to the "ground" plane, then the FET turns on to lower the power dissipation through the main channel and
prevent current flow through the body diode. Note that the resistor, diode ground network (if there is not a central
blocking diode on the supply) must be present for the device to protect itself during a reverse battery event.
Smart High Side Switch
VBB
MCU
RPROT
EN
GPIO
Gate Driver
VOUT
GND
RLOAD
RGND
图8-17. Reverse Battery Circuit
For more external protection circuitry information, see Reverse Current Protection. See the fault truth table for
more details.
8.3.4.5 Latch-Off Mode
The TPS1HC30-Q1 comes with a latch functionality that decides after the channel is shut down due to a fault,
whether or not to automatically try and turn back on, or stay off until other action is taken. This functionality is
done by holding the LATCH pin high for latch-off functionality or holding LATCH low for auto-retry functionality.
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The order the events occur is:
1. The device shuts down due to fault (thermal shutdown)
2. Wait tRETRY
3. If LATCH = 0
a. Turn back on the channel
4. If LATCH = 1
a. Keep off until LATCH = 0 || EN = 0
i. Then if LATCH = 0 and EN = 1
1. Turn on channel into auto-retry mode
ii. If LATCH = 1 and EN = 1
1. Turn on channel into latch mode where if another fault occurs then output is latched off again
For more information, see Thermal Protection Behavior.
8.3.4.6 Thermal Protection Behavior
The thermal protection behavior can be split up into three categories of events that can happen. 图 8-18 shows
each of these categories.
1. Relative thermal shutdown: The device is enabled into an overcurrent event. The DIAG_EN pin is high so
that diagnostics can be monitored on SNS and FLT (however, DIAG_EN being high is not necessary for all
protection features to function). The output current rises up to the IILIM level and the FLT goes low while the
SNS goes to VSNSFH. With this large amount of current going through, the junction temperature of the FET
increases rapidly with respect to the controller temperature. When the power FET temperature rises TREL
amount above the controller junction temperature ΔT = TFET –TCON > TREL, the device shuts down. The
faults are continually shown on SNS and FLT and the part waits for the tRETRY timer to expire. When tRETRY
timer expires, because the LATCH pin is low and EN is still high, the device comes back on into this IILIM
condition.
2. Absolute thermal shutdown: The device is still enabled in an overcurrent event with DIAG_EN high and
LATCH still low. However, in this case the junction temperature rises up and hits an absolute reference
temperature, TABS, and then shuts down. The device does not recover until both TJ < TABS –Thys and the
tRETRY timer has expired.
3. Latch-off mode: The device is enabled into an overcurrent event. The DIAG_EN pin is high so that
diagnostics can be monitored on SNS and FLT. The output current rises up to the IILIM level and the FLT
goes low while the SNS goes to VSNSFH. If the part shuts down due to a thermal fault, either relative thermal
shutdown or absolute thermal shutdown, the device does not enable the channel until either the LATCH pin
OR the EN pin is toggled.
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1
2
3
DIAG_EN
LATCH
EN
TABS
TABS
THYS
Junction
Temperature
tRETRY
tRETRY
tRETRY
tRETRY
tRETRY
TREL
Output
ILIM
Current
VSNSFH
VSNS
FLT
图8-18. Thermal Behavior
8.3.4.7 UVLO Protection
The device monitors the supply voltage VBB to prevent unpredicted behaviors in the event that the supply
voltage is too low. When the supply voltage falls down to VUVLOF, the output stage is shut down automatically.
When the supply rises up to VUVLOR, the device turns on. If an overcurrent event trips the UVLO threshold, the
device shuts off and comes back on into a current limit safely.
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8.3.4.8 Loss of GND Protection
When loss of GND occurs, output is turned off regardless of whether the input signal is high or low.
Case 1 (Loss of Device GND): Loss of GND protection is active when the thermal pad (Tab), IC_GND, and
current limit ground are one trace connected to the system ground, as shown in the following figure.
Smart High Side Switch
VBB
EN
5V
FLT
LATCH
VOUT
MCU
DIAG_EN
SNS
ILIM
Load
GND
图8-19. Loss of Device GND
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Case 2 (Loss of Module GND): When the whole ECU module GND is lost, protections are also active. At this
condition, the load GND remains connected.
Smart High Side Switch
VBB
EN
5V
FLT
LATCH
VOUT
MCU
DIAG_EN
SNS
ILIM
Load
GND
图8-20. Loss of Module GND
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8.3.4.9 Loss of Power Supply Protection
When loss of supply occurs, output is turned off regardless of whether the input is high or low. For a resistive or
capacitive load, loss of supply protection is easy to achieve due to no more power. The worst case is a charged
inductive load. In this case, the current is driven from all of the IOs to maintain the inductance output loop. TI
recommends either the MCU serial resistor plus the GND network (diode and resistor in parallel) or external free-
wheeling circuitry.
Smart High Side Switch
VBB
EN
5V
FLT
LATCH
VOUT
MCU
DIAG_EN
D
Z
SNS
ILIM
L
GND
RGND
DGND
图8-21. Loss of Battery
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8.3.4.10 Reverse Current Protection
Method 1: Blocking diode connected with VBB. Both the device and load are protected when in reverse polarity.
The blocking diode does not allow any of the current to flow during reverse battery condition.
B
5V
UT
MCU
图8-22. Reverse Protection with Blocking Diode
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Method 2 (GND Network Protection): Only the high side device is protected under this connection. The load
reverse current is limited by the impedance of the load itself. Note when reverse polarity happens, the
continuous reverse current through the power FET must not make the heat build up be greater than the absolute
maximum junction temperature. This can be calculated using the RON(REV) value and the RθJA specification. No
matter what types of connection are between the device GND and the board GND, if a GND voltage shift
happens, ensure the following proper connections for the normal operation:
• Connect the current limit programmable resistor to the device GND.
2
VBAT
T
=
R
R
B
5V
UT
MCU
RGND
DGND
图8-23. Reverse Protection with GND Network
• Recommendation - Resistor and Diode in Parallel: A peak negative spike can occur when the inductive
load is switching off, which can damage the HSD or the diode. So, TI recommends a resistor in parallel with
the diode when driving an inductive load. The recommended selections are a 1-kΩresistor in parallel with an
IF > 100-mA diode. If multiple high side switches are used, the resistor and diode can be shared among
devices.
If multiple high side power switches are used, the resistor can be shared among devices.
• Ground Resistor: The higher resistor value contributes to a better current limit effect when the reverse
battery or negative ISO pulses.
œV
(
)
CC
RGND
í
œI
GND
(12)
where
– –VCC is the maximum reverse battery voltage (typically –16 V).
– –IGND is the maximum reverse current the ground pin can withstand, which is available in the Absolute
Maximum Ratings.
• Ground Diode: A diode is needed to block the reverse voltage, which also brings a ground shift based on the
forward voltage of the diode. The ground diode must be ≤400 mV to have full current limit capability. If the
forward voltage becomes higher, the current limit can also increase from what the RILIM resistor is set to.
Additionally, the diode must be approximately 200-V reverse voltage for the ISO 7637 pulse 1 testing so that
it does not get biased.
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8.3.4.11 Protection for MCU I/Os
In many conditions, such as the negative ISO pulse, or the loss of battery with an inductive load, a negative
potential on the device GND pin can damage the MCU I/O pins (more likely, the internal circuitry connected to
the pins). Therefore, the serial resistors between MCU and HSS are required.
Also, for proper protection against loss of GND, TI recommends 5-kΩresistance for the RPROT resistors.
Smart High Side Switch
VBB
5k
EN
5V
5k
5k
FLT
Reverse FET
Turn On
LATCH
5k
VOUT
MCU
DIAG_EN
5k
SNS
ILIM
Load
GND
RGND
DGND
图8-24. MCU I/O Protections
8.3.5 Diagnostic Enable Function
The diagnostic enable pin, DIAG_EN, offers multiplexing of the microcontroller diagnostic input for current sense
or digital status, by sharing the same sense resistor and ADC line or I/O port among multiple devices.
In addition, during the output-off period, the diagnostic disable function lowers the current consumption for the
standby condition. The three working modes in the device are normal mode (IQ), standby mode (ISTBY), and
standby mode with diagnostic (IDIA). If off-state power saving is required in the system, the standby current is <
500 nA with DIAG_EN low. If the off-state diagnostic is required in the system, the typical standby current is
around 1 mA with DIAG_EN high.
8.4 Device Functional Modes
8.4.1 Working Mode
The three working modes in the device are normal mode, standby mode, and standby mode with diagnostic. If
an off-state power saving is required in the system, the standby current is less than 500 nA with EN and
DIAG_EN low. If an off-state diagnostic is required in the system, the typical standby current is around 1.2 mA
with DIAG_EN high. Note that entering standby mode requires IN low and t > tSTBY. tSTBY is the standby mode
deglitch time, which is used to avoid false triggering or interfere with PWM switching. The following figure shows
a work mode state-machine state diagram.
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Standby Mode
(EN Low, DIAG_EN Low)
DIAG_EN low and
EN high to low and
t > tSTBY
DIAG_EN
high to Low
and t > tSTBY
EN low to high
DIAG_EN
low to high
IN high to low and
DIAG_EN high
Normal Mode
(EN high)
Diagnostic Mode
(EN low, DIAG_EN high)
EN low to high
图8-25. Work Mode State Machine
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The following discussion notes how to implement the device to distinguish the different fault modes and
implement a transient-pulse immunity test.
In some applications, open load, short-to-battery, and short to GND must be distinguished from each other. This
action requires two steps.
9.2 Typical Application
图9-1 shows an example of how to design the external circuitry parameters.
CVBB
CIC
+
TVS
CBULK
LDO
(DC/DC)
RPROT
VCC
I/O
VOUT
RPROT
I/O
I/O
CVOUT
RPROT
MCU
RPROT
RPROT
I/O
ADC
RILIM
CFILTER RSNS
GND
RGND
图9-1. Typical Application Circuitry
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9.2.1 Design Requirements
Component
Description
Purpose
TVS
CVBB
CIC
SMBJ36CA (optional)
220 nF (optional)
100 nF
Filter voltage transients coming from battery (ISO7637-2)
Better EMI performance
Minimal amount of capacitance on input for EMI mitigation
There to hold the rail for the LDO; however, helps to filter voltage
transients on supply rail. Not a requirement but can be useful for
ISO7637-2 transients.
CBULK
2–10 μF (optional)
RPROT
RILIM
5 k
Protection resistor for microcontroller and device I/O pins
Set current limit threshold
7 k–70 k
1 k
RSNS
Translate the sense current into sense voltage.
Coupled with RPROT on the SNS line creates a low pass filter to
filter out noise going into the ADC of the MCU
CFILTER
100 nF
CVOUT
RGND
DGND
22 nF
Improves EMI performance, filtering of voltage transients
Stabilize GND potential during turn-off of inductive load
Keeps GND close to system ground during normal operation
1 kΩ
BAS21 Diode
9.2.2 Detailed Design Procedure
To keep maximum voltage on the SNS pin at an acceptable range for the system, use the following equation to
calculate the RSNS. To achieve better current sense accuracy. A 1% accuracy or better resistor is preferred.
(VSNSFH –VHR) × KSNS / ILOAD,max ≤RSNS ≤VADC,min × KSNS / ILOAD,min
(13)
表9-1. Typical Application
Parameter
Value
5 V
VDIAG_EN
ILOAD,max
ILOAD,min
VADC,min
VHR
6 A
20 mA
5 mV
1 V
For this application, an RSNS value of approximately 1 kΩcan be chosen to satisfy the equation requirements.
(5 V –1 V) × 1814 / 6 A ≤≅1 kΩ≤5 mV × 11814 / 20 mA
(14)
In other applications, more emphasis can be put on the lower end measurable values which increases RSNS.
Likewise, if the higher currents are of more interest the RSNS can be decreased. Note that the maximum current
that can be measured without saturation is 12 A.
Having the maximum SNS voltage scale with the DIAG_EN voltage removes the need for a Zener diode on the
SNS pin going to the ADC.
To set the programmable current limit value at 7 A, use the following equation to calculate the RLIM
.
RLIM = KCL / ILIM = 90 / 7 = 12.8 kΩ
(15)
TI recommends RPROT = 5 kΩto ensure the current going into the digital pins (EN, DIAG_EN, LATCH) is limited.
TI recommends a 1-kΩresistor and 200-V, 0.2-A diode (BAS21 for example) for the GND network.
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9.2.2.1 Dynamically Changing Current Limit
The current limit threshold can be changed dynamically by altering the resistance going from the current limit pin
to the ground of the device on the fly. This alteration allows the system to have a different current limit for start-
up, when there can be significant inrush current, and during normal operation. The way this is commonly done is
by putting two resistors in parallel on the ILIM pin and having a switch to enable or disable one of the resistors.
This set-up can be seen in 图 9-2. Alternatively, a digital potentiometer can be used to adjust the impedance on
the ILIM pin on the fly. Care must be taken so that the capacitance on the ILIM pin is below approximately 100
pF to keep the current regulation loop stable. The most common application where this feature is useful is
capacitive loads.
VBAT
VBB
Smart High Side Switch
EN
Gate Driver
KCL
KCL (RILIM1 + RILIM2
RILIM1 RILIM2
)
ILIM1
=
ILIM2
=
SW
RILIM
ILIM
Current Limiting
Circuit
(VBB – VOUT
RLOAD
)
INOM
=
VOUT
RILIM2
RILIM1
CLOAD
GND
RLOAD
ILIM = CLOAD x dVDS/dt
图9-2. Dynamic Changing Current Limit Setup
In a capacitive charging case, the initial current to charge the capacitor is the inrush current. Depending on the
system requirements, dynamically changing the current limit can help either charge up a capacitor faster or
charge up a larger capacitor. To allow a higher inrush level of current through in the beginning, the switch can be
closed making the current limit be according to the equation below.
ILIM2 = KCL(RILIM1 + RILIM2) / (RILIM1 × RILIM2
)
(16)
When the inrush event is over and the output voltage is charged up, the switch opens and the current limit is just
the RILIM1 equivalent level. This timing can be seen in 图9-3.
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VOUT (V)
VBB
VBB - VDS
Time (s)
Current (A)
IILIM2
IILIM1
INOM
dt
Time (s)
tSW
图9-3. Capacitive Charging Changing Current Limit
Alternatively, if the switch is open, the current limit starts out at a lower value and then the switch can be closed
when the capacitance gets charged up. This lower current limit level allows higher value capacitance to be
charged up. The timing diagram can be seen in 图9-4.
VOUT (V)
VBB
VBB - VDS
Time (s)
Current (A)
IILIM2
INOM
IILIM1
dt
Time (s)
tSW
图9-4. Large Capacitive Charging Changing Current Limit
9.2.2.2 EMC Transient Disturbances Test
Due to the severe electrical conditions in the automotive environment, immunity capacity against electrical
transient disturbances is required, especially for a high side power switch, which is connected directly to the
battery. Detailed test requirements are in accordance with the ISO 7637-2:2011 and ISO 16750-2:2010
standards. The TPS1HC30-Q1 device is tested and certificated by a third-party organization.
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表9-2. ISO 7637-2:2011(E) in 12-V System(1) (2) (3) (4)
Test Pulse Severity Level
and vs Accordingly
Minimum
Number of
Duration (td) Pulses or Test
Time
Burst-Cycle Pulse-
Repetition Time
Function
Performance
Status
Input
Resistance
(Ω)
Test
Item
Pulse
Level
Vs/V
MIN
MAX
Classification
1
III
III
IV
IV
IV
2 ms
50 µs
500 pulses
500 pulses
10 pulses
1 h
0.5 s
0.2 s
10
Status II
Status II
Status II
Status II
Status II
–112
55
—
5 s
2a
2b
3a
3b
2
0 to 0.05
50
10
0.2 to 2 s
0.1 µs
0.5 s
5 s
90 ms
90 ms
100 ms
100 ms
–220
150
0.1 µs
1 h
50
(1) Tested both under input low condition and high condition.
(2) The pulse 2-A voltage is 54-V maximum from VBB with respect to ground. A voltage suppressing mechanism must be used to pass
Level III. This test was run with an 2-μF capacitor from VBB to ground.
(3) GND pin network is a 1-kΩresistor in parallel with a diode BAS21-7-F.
(4) Status II: The function does not perform as designed during the test, but returns automatically to normal operation after the test.
表9-3. ISO 16750-2:2010(E) Load Dump Test B in 12-V System(1) (2) (3) (4) (5)
Test Pulse Severity Level
and vs Accordingly
Minimum
Number of
Pulses or Test
Time
Function
Performance
Status
Input
Resistance
(Ω)
Test
Item
Pulse
Duration (td)
Burst-Cycle Pulse-
Repetition Time
Level
Vs/V
Classification
Test B
35
40 to 400 ms
5 pulses
60 s
0.5 to 4
Status II
(1) Tested both under input low condition and high condition (DIAG_EN, EN, and VBB are all classified as inputs).
(2) Considering the worst test condition, the device is tested without any filter capacitors on VBB and VOUT.
(3) The GND pin network is a 1-kΩresistor in parallel with a diode BAS21-7-F.
(4) Status II: The function does not perform as designed during the test, but returns automatically to normal operation after the test.
(5) Select a 36-V external suppressor.
9.3 Power Supply Recommendations
The device is qualified for both automotive and industrial applications. The normal power supply connection is a
12-V automotive system. The supply voltage must be within the range specified in the Recommended Operating
Conditions.
表9-4. Voltage Operating Ranges
VBB Voltage Range
Note
Extended lower 12-V automotive battery operation such as cold crank and start-stop. Device
is fully functional and protected but some parametrics such as RON, current sense accuracy,
current limit accuracy and timing parameters can deviate from specifications. Check the
individual specifications in the Electrical Characteristics to confirm the voltage range it is
applicable for.
3 V to 6 V
Nominal 12-V automotive battery voltage range. All parametric specifications apply and the
device is fully functional and protected.
6 V to 18 V
18 V to 24 V
35 V
Extended upper 12-V automotive battery operation such as double battery. Device is fully
functional and protected but some parametrics such as RON, current sense accuracy, current
limit accuracy, and timing parameters can deviate from specifications. Check the individual
specifications in the Electrical Characteristics to confirm the voltage range it is applicable for.
Load dump voltage. Device is operational and lets the pulse pass through without being
damaged but does not protect against short circuits.
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9.4 Layout
9.4.1 Layout Guidelines
To prevent thermal shutdown, TJ must be less than 150°C. If the output current is very high, the power
dissipation can be large. The HTSSOP package has good thermal impedance. However, the PCB layout is very
important. Good PCB design can optimize heat transfer, which is absolutely essential for the long-term reliability
of the device.
• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-
flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when there are not any heat sinks attached to the PCB on the other side of the board opposite the
package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• Plate shut or plug and cap all thermal vias on both sides of the board to prevent solder voids. To ensure
reliability and performance, the solder coverage must be at least 85%.
9.4.2 Layout Example
9.4.2.1 Without a GND Network
Without a GND network, tie the thermal pad directly to the board GND copper for better thermal performance.
RPROT
14
CVBB
GND
NC
1
2
3
4
5
6
7
RPROT
13
VBB
VBB
EN
DIAG_EN
FAULT
12
11
RPU
RPROT
Thermal
Pad
NC
RPROT
10
LATCH
SNS
VOUT
VOUT
NC
RPROT
9
8
RSNS
CFILTER
CVOUT
ILIM
RLIM
图9-5. Layout Without a GND Network
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9.4.2.2 With a GND Network
With a GND network, tie the thermal pad with one trace through the GND network to the board GND copper.
RGND
DGND
RPROT
CVBB_IC
CVBB
G
RPROT
DIAG_
FAU
LAT
S
RPU
RPROT
RPROT
RPROT
CVOUT
RSNS
CFILTER
ILIM
RLI
图9-6. Layout With a GND Network
9.4.3 Thermal Considerations
This device possesses thermal shutdown (TABS) circuitry as a protection from overheating. For continuous
normal operation, the junction temperature must not exceed the thermal-shutdown trip point. If the junction
temperature exceeds the thermal-shutdown trip point, the output turns off. When the junction temperature falls
below the thermal-shutdown trip point, the output turns on again.
Use the following equation to calculate the power dissipated by the device.
PT = IOUT2 ì RDSON + VS ìInom
PT = IOUT 2 × RDSON + VBB × INOM
(17)
where
• PT = Total power dissipation of the device
After determining the power dissipated by the device, calculate the junction temperature from the ambient
temperature and the device thermal impedance.
TJ = TA + RqJA ìPT
TJ = TA + RθJA × PT
(18)
For more information, please see the How to Drive Resistive, Inductive, Capacitive, and Lighting Loads
application note.
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation, see the following:
Texas Instruments, How to Drive Resistive, Inductive, Capacitive, and Lighting Loads application note
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS1HC30BQPWPRQ1
TPS1HC30BQPWPRQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
14
14
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
Samples
Samples
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
1HC30Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Dec-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS1HC30BQPWPRQ1 HTSSOP PWP
TPS1HC30BQPWPRQ1 HTSSOP PWP
14
14
3000
3000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS1HC30BQPWPRQ1
TPS1HC30BQPWPRQ1
HTSSOP
HTSSOP
PWP
PWP
14
14
3000
3000
350.0
367.0
350.0
367.0
43.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 14
4.4 x 5.0, 0.65 mm pitch
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224995/A
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