TPL1401 [TI]
具有缓冲刷的 256 抽头高精度数字电位器;
| 型号： | TPL1401 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有缓冲刷的 256 抽头高精度数字电位器 电位器 |
| 文件： | 总42页 (文件大小：4171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPL1401
ZHCSLY4 –APRIL 2020
具有缓冲电刷的TPL1401 256 抽头高精度数字电位器
1 特性
3 说明
• 适用于分压器应用的256 抽头数字电位器
• 1 LSB INL 和DNL
• 宽工作范围
TPL1401 是一款具有缓冲电刷的数字电位器。与标准
数字电位器不同，该器件具有集成缓冲电刷，可帮助分
压器应用实现较高负载调节。
– 电源：1.8V 至5.5V
TPL1401 集成了非易失性存储器 (NVM)，可以让工厂
校准和修整变得更加轻松，另外还提供用于器件通信的
简单 I2C 数字接口。该器件支持 I2C 标准模式
(100kbps) 、快速模式 (400kbps) 和快速+ 模式
(1Mbps)。
– 温度范围：–40°C 至+125°C
• 用于改善负载调节的缓冲刷
• 用于精密电流吸收器应用的反馈引脚
• 电刷锁定功能可防止对数字电位器意外写入
• I2C 接口
TPL1401 在内部基准或电源基准下运行，提供1.8V 至
5.5V 的满量程输出。该器件还具备电刷锁定特性，具
有用于电流吸收器应用的反馈 (FB) 引脚，以及 2 字节
的用户可编程 NVM 空间。TPL1401 具有上电复位
(POR) 电路，可确保所有寄存器以默认设置或使用
NVM 的用户编程设置启动。数字电位器输出在高阻抗
模式下通电（默认）；可以使用 NVM 将此设置编程为
10kΩ-GND。
– 标准、快速和快速+ 模式
– 1.62V VIH (VDD = 5.5V)
• 用户可编程的非易失性存储器
(NVM/EEPROM)
– 保存和撤销所有寄存器设置
• 内部基准
• 功耗极低：在1.8V 时为0.2 mA
• 灵活启动：高阻抗或10K-GND
• 微型封装：8 引脚WSON (2mm × 2mm)
TPL1401 是一款小巧型构建块器件，功能丰富，简单
易用，可集成到许多应用中。
2 应用
• 出口和紧急照明
• 条形码扫描仪
• 条形码读取器
• 智能扬声器
• 可视门铃
TPL1401 的工作温度范围为–40°C 至+125°C。
器件信息(1)
封装尺寸（标称值）
器件型号
TPL1401
封装
WSON (8)
2.00mm × 2.00mm
• 无线真空吸尘器
• 割草机器人
• 激光测距仪
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
功能方框图
通过TPL1401 实现可编程电流限制
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS806
TPL1401
ZHCSLY4 –APRIL 2020
www.ti.com.cn
Table of Contents
7.2 Functional Block Diagram.........................................17
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................21
7.5 Programming............................................................ 22
7.6 Register Map.............................................................26
8 Application and Implementation..................................30
8.1 Application Information............................................. 30
8.2 Typical Application.................................................... 30
9 Power Supply Recommendations................................32
10 Layout...........................................................................32
10.1 Layout Guidelines................................................... 32
10.2 Layout Example...................................................... 32
11 Device and Documentation Support..........................33
11.1 Documentation Support.......................................... 33
11.2 接收文档更新通知................................................... 33
11.3 支持资源..................................................................33
11.4 Trademarks............................................................. 33
11.5 静电放电警告...........................................................33
11.6 术语表..................................................................... 33
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Timing Requirements: I2C Standard Mode ................ 7
6.7 Timing Requirements: I2C Fast Mode ........................7
6.8 Timing Requirements: I2C Fast Mode Plus ................7
6.9 Typical Characteristics: VDD = 1.8 V (Reference
= VDD) or VDD = 2 V (Internal Reference)......................8
6.10 Typical Characteristics: VDD = 5.5 V (Reference
= VDD) or VDD = 5 V (Internal Reference)....................10
6.11 Typical Characteristics............................................ 12
7 Detailed Description......................................................17
7.1 Overview...................................................................17
Information.................................................................... 33
4 Revision History
DATE
REVISION
NOTES
September 2020
*
Initial release.
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5 Pin Configuration and Functions
A0
SCL
SDA
CAP
1
2
3
4
8
7
6
5
OUT
FB
VDD
AGND
Not to scale
图5-1. DSG Package, 8-Pin WSON, Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
A0
NO.
1
Input
Four-state address input
AGND
5
Ground
Ground reference point for all circuitry on the device
External capacitor for the internal LDO. Connect a capacitor (around 1.5 µF) between CAP and
AGND.
CAP
4
Input
FB
7
8
Input
Voltage feedback pin
OUT
Output
Analog output voltage from digipot buffer
Serial interface clock. This pin must be connected to the supply voltage with an external pullup
resistor.
SCL
SDA
2
3
Input
Data are clocked into or out of the input register. This pin is a bidirectional, and must be connected to
the supply voltage with an external pullup resistor.
Input/output
Power or
VDD
6
reference Analog supply voltage: 1.8 V to 5.5 V
input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–10
–40
–65
MAX
6
UNIT
V
VDD
Supply voltage / reference, VDD to AGND
Digital input(s) to AGND
CAP to AGND
VDD + 0.3
1.65
V
V
VFB to AGND
VDD + 0.3
VDD + 0.3
10
V
VOUT to AGND
V
Current into any pin
Junction temperature
Storage temperature
mA
°C
°C
TJ
150
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
pins 1, 4, 5, 8(2)
Electrostatic
discharge
±750
±500
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
pins 2, 3, 6, 7(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
1.62
NOM
MAX UNIT
VDD
VIH
VIL
TA
Positive supply voltage to ground (AGND
)
5.5
V
V
V
Digital input high voltage, 1.7 V < VDD ≤5.5 V
Digital input low voltage
0.4
Ambient temperature
125 °C
–40
6.4 Thermal Information
TPL1401
THERMAL METRIC(1)
DSG (WSON)
UNIT
8 PINS
49
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
50
24.1
1.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
24.1
8.7
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
reference tied to VDD, gain = 1x, digipot output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive load
(CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
8
–1
–1
Bits
LSB
LSB
INL Relative accuracy(1)
DNL Differential nonlinearity(1)
1
1
Code 0d into digipot
6
6
12
15
Zero code error
mV
Internal VREF, gain = 4x, VDD = 5.5 V
Zero code error temperature
coefficient
±10
0.25
µV/°C
%FSR
VREF tied to VDD, measured between end-point codes
2d and 254d, output unloaded
Offset error
0.5
0.5
–0.5
–0.5
Offset error temperature
coefficient
VREF tied to VDD, measured between end-point codes
2d and 254d, output unloaded
±0.0003
0.25
%FSR/°C
%FSR
VREF tied to VDD, measured between end-point codes
2d and 254d, output unloaded
Gain error
Gain error temperature
coefficient
VREF tied to VDD, measured between end-point codes
2d and 254d, output unloaded
±0.0008
0.5
%FSR/°C
1.8 V ≤VDD < 2.7 V, code 511d into digipot,
no headroom
1
–1
Full scale error
%FSR
2.7 V ≤VDD ≤5.5 V, code 511d into digipot,
no headroom
0.25
0.5
–0.5
Full scale error temperature
coefficient
±0.0008
%FSR/°C
OUTPUT CHARACTERISTICS
Output voltage
Reference tied to VDD
0
5.5
1
V
RL = Infinite, phase margin = 30°
RL = 5 kΩ, phase margin = 30°
CL
Capacitive load(2)
Load regulation
nF
2
Digipot at midscale, –10 mA ≤IOUT ≤10 mA,
VDD = 5.5 V
0.4
10
25
50
mV/mA
VDD = 1.8 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
Short circuit current
mA
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
To VDD (digipot output unloaded, internal reference =
1.21 V), VDD ≥1.21 ☓ gain + 0.2 V
0.2
0.8
V
To VDD (digipot output unloaded)
Output voltage headroom(1)
To VDD (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at
VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), digipot code
= full scale
%FSR
10
Digipot output enabled and digipot code = midscale
Digipot output enabled and digipot code = 2d
Digipot output enabled and digipot code = 254d
Digipot output enabled
0.25
0.25
0.26
200
VOUT dc output impedance
VFB dc output impedance(3)
Ω
ZO
160
240
5
kΩ
VOUT + VFB dc output
leakage(2)
At start up, measured when digipot output is disabled
and held at VDD / 2 for VDD = 5.5 V
nA
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all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
reference tied to VDD, gain = 1x, digipot output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive load
(CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power supply rejection ratio
(dc)
Internal VREF, gain = 2x, digipot at midscale;
VDD = 5 V ±10%
0.25
mV/V
DYNAMIC PERFORMANCE
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V
8
tsett Output voltage settling time
µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V, internal VREF, gain = 4x
12
1
Slew rate
VDD = 5.5 V
V/µs
mV
At start up (buffer output disabled), RL = 5 kΩ,
CL = 200 pF
75
Power on glitch magnitude
200
250
34
At start up (buffer output disabled), RL = 100 kΩ
Buffer output disabled to enabled (digipot registers at
zero scale, RL = 100 kΩ
Output enable glitch
magnitude
mV
0.1 Hz to 10 Hz, digipot at midscale, VDD = 5.5 V
Output noise voltage (peak to
peak)
Vn
µVPP
Internal VREF, gain = 4x, 0.1 Hz to 10 Hz, digipot at
midscale, VDD = 5.5 V
70
Measured at 1 kHz, digipot at midscale, VDD = 5.5 V
0.2
0.7
Output noise density
µV/√Hz
Internal VREF, gain = 4x, measured at 1 kHz, digipot at
midscale, VDD = 5.5 V
Internal VREF, gain = 4x, 200-mV 50 or 60 Hz sine
wave superimposed on power supply voltage, digipot
at midscale
Power supply rejection ratio
(ac)(3)
dB
–71
±1 LSB change around mid code (including
feedthrough)
Code change glitch impulse
10
15
nV-s
mV
Code change glitch impulse
magnitude
±1 LSB change around mid code (including
feedthrough)
VOLTAGE REFERENCE
Initial accuracy
TA = 25°C
1.212
V
Reference output temperature
coefficient(2)
50 ppm/°C
EEPROM
20000
1000
50
–40°C ≤TA ≤85°C
TA > 85°C
Endurance
Cycles
Years
Data retention(2)
TA = 25°C
EEPROM programming write
cycle time(2)
10
20
ms
DIGITAL INPUTS
Digipot output static at midscale, fast mode plus, SCL
toggling
Digital feedthrough
20
10
nV-s
pF
Pin capacitance
POWER
Per pin
Load capacitor - CAP pin(2)
0.5
15
µF
mA
µA
Normal mode, digipot at full scale, digital pins static
Digipot power-down, internal reference power down
0.5
80
0.8
IDD
Current flowing into VDD
(1) Measured with digipot output unloaded. For external reference between end-point codes 2d and 254d. For internal reference VDD ≥
1.21 x gain + 0.2 V, between end-point codes 2d and 254d.
(2) Specified by design and characterization, not production tested.
(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.
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6.6 Timing Requirements: I2C Standard Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and
1.8 V ≤Vpull-up ≤VDD (unless otherwise specified)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
0.1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
4.7
4
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
4.7
4
µs
µs
0
ns
Data setup time
250
4700
4000
ns
SCL clock low period
ns
SCL clock high period
Clock and data fall time
Clock and data rise time
ns
300
ns
tR
1000
ns
6.7 Timing Requirements: I2C Fast Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and
1.8 V ≤Vpull-up ≤VDD (unless otherwise specified)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
0.4
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
1.3
0.6
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
0.6
µs
0.6
µs
0
ns
Data setup time
100
1300
600
ns
SCL clock low period
ns
SCL clock high period
Clock and data fall time
Clock and data rise time
ns
300
300
ns
tR
ns
6.8 Timing Requirements: I2C Fast Mode Plus
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and
1.8 V ≤Vpull-up ≤VDD (unless otherwise specified)
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
0.5
0.26
0.26
0.26
0
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
µs
µs
ns
Data setup time
50
ns
SCL clock low period
0.5
µs
SCL clock high period
Clock and data fall time
Clock and data rise time
0.26
µs
120
120
ns
tR
ns
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6.9 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
at TA = 25°C and digipot outputs unloaded (unless otherwise noted)
图6-1. Integral Linearity Error vs Digital Input Code
图6-2. Differential Linearity Error vs Digital Input Code
图6-3. Total Unadjusted Error vs Digital Input Code
图6-4. Integral Linearity Error vs Temperature
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
TUE max, reference = VDD, gain = 1x
TUE min, reference = VDD, gain = 1x
TUE max, internal reference, gain = 1.5x
-0.6
-0.8
TUE min, internal reference, gain = 1.5x
-1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图6-6. Total Unadjusted Error vs Temperature
图6-5. Differential Linearity Error vs Temperature
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6.9 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
(continued)
at TA = 25°C and digipot outputs unloaded (unless otherwise noted)
8
7
6
5
4
3
2
1
0
0.5
0.3
0.1
-0.1
-0.3
-0.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Reference = VDD
图6-7. Zero Code Error vs Temperature
Reference = VDD
图6-8. Offset Error vs Temperature
0.5
0.5
0.4
0.3
0.2
0.1
0
Reference = VDD, gain = 1x
Internal reference, gain = 1.5x
0.3
0.1
-0.1
-0.3
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Reference = VDD, gain = 1x
Internal reference, gain = 1.5x
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
图6-9. Gain Error vs Temperature
图6-10. Full-Scale Error vs Temperature
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6.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
at TA = 25°C and digipot outputs unloaded (unless otherwise noted)
图6-11. Integral Linearity Error vs Digital Input Code
图6-12. Differential Linearity Error vs Digital Input Code
图6-13. Total Unadjusted Error vs Digital Input Code
图6-14. Integral Linearity Error vs Temperature
0.5
TUE max, reference = VDD, gain = 1x
TUE min, reference = VDD, gain = 1x
TUE max, internal reference, gain = 4x
0.4
0.3
TUE min, internal reference, gain = 4x
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图6-16. Total Unadjusted Error vs Temperature
图6-15. Differential Linearity Error vs Temperature
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6.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
(continued)
at TA = 25°C and digipot outputs unloaded (unless otherwise noted)
2
1.5
1
0.5
0.3
0.5
0
0.1
-0.1
-0.3
-0.5
-0.5
-1
-1.5
-2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Reference = VDD
图6-17. Zero Code Error vs Temperature
Reference = VDD
图6-18. Offset Error vs Temperature
0.5
0.5
Reference = VDD, gain = 1x
Internal reference, gain = 4x
Reference = VDD, gain 1x
Internal reference, gain 4x
0.3
0.3
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
图6-19. Gain Error vs Temperature
图6-20. Full-Scale Error vs Temperature
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6.11 Typical Characteristics
at TA = 25°C and digipot outputs unloaded (unless otherwise noted)
Reference = VDD
Reference = VDD
图6-22. Differential Linearity Error
图6-21. Integral Linearity Error
vs Supply Voltage
vs Supply Voltage
Reference = VDD
Reference = VDD
图6-23. Total Unadjusted Error
图6-24. Zero-Code Error
vs Supply Voltage
vs Supply Voltage
Reference = VDD
Reference = VDD
图6-26. Gain Error vs Supply Voltage
图6-25. Offset Error vs Supply Voltage
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6.11 Typical Characteristics (continued)
at TA = 25°C and digipot outputs unloaded (unless otherwise noted)
VDD = 1.8 V
图6-28. Supply Current vs Digital Input Code
Reference = VDD
图6-27. Full-Scale Error vs Supply Voltage
0.4
0.35
0.3
IDD, VDD = 1.8 V
IDD, VDD = 3.3 V
IDD, VDD = 5.5 V
0.25
0.2
0.15
0.1
0.05
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD = 5.5 V
Reference = VDD, digipot at midscale
图6-29. Supply Current vs Digital Input Code
图6-30. Supply Current vs Temperature
0.4
IDD, VDD = 3.3 V
IDD, VDD = 5.5 V
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Digipot at midscale
Internal reference (gain = 4x), digipot at midscale
图6-32. Supply Current vs Supply Voltage
图6-31. Supply Current vs Temperature
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6.11 Typical Characteristics (continued)
at TA = 25°C and digipot outputs unloaded (unless otherwise noted)
0.1
0.0875
0.075
6
5
4
0.0625
0.05
3
2
0.0375
1
0.025
0
IDD, VDD = 1.8 V
IDD, VDD = 3.3 V
IDD, VDD = 5.5 V
0.0125
0
-1
-2
Reference = VDD = 1.8 V
Reference = VDD = 5.5 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-20
-15
-10
-5
0
5
Load Current (mA)
10
15
20
Reference = VDD, digipot powered down
图6-33. Power-Down Current vs Temperature
图6-34. Source and Sink Capability
Reference = VDD = 5.5 V, digipot code transition from
Reference = VDD = 5.5 V, digipot code transition from
midscale to midscale + 1 LSB, digipot load = 5kΩ|| 200pF
midscale to midscale –1 LSB, digipot load = 5kΩ|| 200pF
图6-35. Glitch Impulse, Rising Edge,
图6-36. Glitch Impulse, Falling Edge,
1-LSB Step
1-LSB Step
Reference = VDD = 5.5 V, digipot load = 5kΩ|| 200pF
图6-37. Full-Scale Settling Time, Rising Edge
Reference = VDD = 5.5 V, digipot load = 5kΩ|| 200pF
图6-38. Full-Scale Settling Time, Falling Edge
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6.11 Typical Characteristics (continued)
at TA = 25°C and digipot outputs unloaded (unless otherwise noted)
VDD (1 V / div)
VOUT unloaded (500 mV / div)
VOUT 10K-GND (15 mV / div)
VDD (1 V / div)
VOUT unloaded (500 mV / div)
VOUT 10K-GND (15 mV / div)
0
5
10
15
20
25
Time (ms)
30
35
40
45
50
0
5
10
15
20
25
Time (ms)
30
35
40
45
50
Reference = VDD = 5.5 V
图6-39. Power-on Glitch
Reference = VDD = 5.5 V
图6-40. Power-off Glitch
-40
VOUT (6 mV / div)
SCL (4 V / div)
-50
-60
-70
-80
-90
-100
10
20 30 50 70100 200
500 1000 2000 5000 10000
0
1
2
3
4
5
Frequency (Hz)
Time (ms)
Internal reference (gain = 4x), VDD = 5.25 V + 0.25 VPP
,
Reference = VDD = 5.5 V, fast mode plus, digipot at midscale,
digipot at midscale, digipot load = 5kΩ|| 200pF
digipot load = 5kΩ|| 200pF
图6-42. Output AC PSRR vs Frequency
图6-41. Clock Feedthrough
Reference = VDD = 5.5 V
Internal reference (gain = 4x), VDD = 5.5 V
图6-43. Output Noise Spectral Density
图6-44. Output Noise Spectral Density
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6.11 Typical Characteristics (continued)
at TA = 25°C and digipot outputs unloaded (unless otherwise noted)
Reference = VDD = 5.5 V, digipot at midscale
Internal reference (gain = 4x), VDD = 5.5 V, digipot at midscale
图6-45. Digipot Output Noise: 0.1 Hz to 10 Hz
图6-46. Digipot Output Noise: 0.1 Hz to 10 Hz
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7 Detailed Description
7.1 Overview
The TPL1401 is a digital potentiometer with buffered wiper. The buffered wiper helps achieve a higher load
regulation as compared to standard digital potentiometers used in voltage-divider applications. This digipot
contains nonvolatile memory (NVM) and an I2C interface. This makes the TPL1401 easy to use for factory
trimming and calibration device in analog set-point applications. The TPL1401 operates with either the internal
reference or the power supply as the reference, and provides a full-scale output of 1.8 V to 5.5 V.
The TPL1401 communicates through an I2C interface. This device supports I2C standard mode (100 kbps), fast
mode (400 kbps), and fast mode plus (1 Mbps). This device also includes a wiper lock feature, an FB pin for
current sink application, and 2 bytes of user-programmable NVM space.
The TPL1401 has a power-on-reset (POR) circuit that makes sure all the registers start with default or user-
programmed settings using NVM. The digipot output powers on in high-impedance mode (default); this setting
can be programmed to 10kΩ-GND using NVM.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Digital Potentiometer (Digipot) Architecture
The TPL1401 consists of string architecture with an output buffer amplifier. 节 7.2 shows the digipot architecture
within the block diagram. This digipot architecture operates from a 1.8-V to 5.5-V power supply. This device
consume only 0.2 mA of current when using a 1.8-V power supply. The digipot output gets loaded from the NVM
at power up. Write the required code so that the load circuit starts with a predictable operating point at power up.
7.3.1.1 Reference Selection and Digipot Transfer Function
The device writes the input data to the DPOT_POSITION register in straight-binary format. After a power-on or a
reset event, the device sets all digipot registers to the values set in the NVM.
7.3.1.1.1 Power Supply as Reference
By default, the TPL1401 operates with the power-supply pin (VDD) as a reference. 方程式 1 shows the digipot
transfer function when the power-supply pin is used as a reference.
(1)
where:
• DPOT_POS is the decimal equivalent of the binary code that is loaded to the digipot register.
• DPOT_POS ranges from 0 to 255.
• VDD is used as the digipot reference voltage.
7.3.1.1.2 Internal Reference
The TPL1401 also contains an internal reference that is disabled by default. Enable the internal reference by
writing 1 to REF_EN (address D1h). The internal reference generates a fixed 1.21-V voltage (typical). Using the
OUT_SPAN (address D1h) bits, a gain of 1.5x, 2x, 3x, 4x can be achieved for the digipot output voltage (VOUT
)
方程式2 shows digipot transfer function when the internal reference is used.
(2)
where:
• DPOT_POS is the decimal equivalent of the binary code that is loaded to the digipot register
• DPOT_POS ranges from 0 to 255.
• VREF is the internal reference voltage = 1.21 V.
• GAIN = 1.5x, 2x, 3x, 4x based on OUT_SPAN (address D1h) bits.
7.3.2 Digipot Update
The digipot output pin (OUT) is updated at the end of I2C digipot write frame.
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7.3.3 Nonvolatile Memory (EEPROM or NVM)
The TPL1401 contains nonvolatile memory (NVM) bits. These NVM bits are user programmable and erasable,
and retain the set values in the absence of a power supply. All the register bits, as shown in 表 7-1, can be
stored in the device NVM by setting NVM_PROG = 1 (address D3h). The NVM_BUSY bit (address D0h) is set to
1 by the device when an NVM write or reload operation is ongoing. During this time, the device blocks all write
operations to the device. The NVM_BUSY bit is set to 0 after the write or reload operation is complete; at this
point, all write operations to the device are allowed. The default value for all the registers in the TPL1401 is
loaded from NVM as soon as a POR event is issued. Do not perform a read operation from the digipot register
while NVM_BUSY = 1.
The TPL1401 also implements NVM_RELOAD bit (address D3h). Set this bit to 1 for the device to start an NVM
reload operation. After the operation is complete, the device autoresets this bit to 0. During the NVM_RELOAD
operation, the NVM_BUSY bit is set to 1.
表7-1. NVM Programmable Registers
REGISTER ADDRESS
REGISTER NAME
BIT ADDRESS
BIT NAME
DEVICE_LOCK
13
4:3
2
DPOT_PDN
D1h
GENERAL_CONFIG
REF_EN
1:0
11:2
11:4
11:4
OUT_SPAN
10h
25h
26h
DPOT_POSITION
USER_BYTE1
USER_BYTE2
DPOT_POS
USER_BYTE1 (8 most significant bits)
USER_BYTE2 (8 most significant bits)
7.3.3.1 NVM Cyclic Redundancy Check
The TPL1401 implements a cyclic redundancy check (CRC) feature to make sure that the data stored in the
device NVM are uncorrupted. There are two types of CRC alarm bits implemented in TPL1401:
• NVM_CRC_ALARM_USER (address D0h) —This bit indicates the status of the user-programmable NVM
bits.
• NVM_CRC_ALARM_INTERNAL (address D0h) —This bit indicates the status of the internal NVM bits.
The CRC feature is implemented by storing a 10-bit CRC (CRC-10-ATM) along with the NVM data each time
NVM program operation (write or reload) is performed and during the device start up. The device reads the NVM
data and validates the data with the stored CRC. The CRC alarm bits report any errors after the data are read
from the device NVM.
7.3.3.1.1 NVM_CRC_ALARM_USER Bit
A logic 1 on NVM_CRC_ALARM_USER bit indicates that the user-programmable NVM data is corrupt. During
this condition, all registers in the digipot are initialized with factory reset values, and any digipot registers can be
written to or read from. To reset the alarm bits to 0, issue a Software Reset command, or cycle power to the
digipot. A power cycle reloads the user-programmable NVM bits. After the reset, write the desired data to the
registers and assert the NVM_PROG bit in the PROTECT register to program the NVM.
7.3.3.1.2 NVM_CRC_ALARM_INTERNAL Bit
A logic 1 on NVM_CRC_ALARM_INTERNAL bit indicates that the internal NVM data is corrupt. During this
condition, all registers in the digipot are initialized with factory reset values, and any digipot registers can be
written to or read from. To reset the alarm bits to 0, issue a Software Reset command, or cycle power to the
digipot. The NVM_PROG bit in the PROTECT register (address D3h) is blocked when the
NVM_CRC_ALARM_INTERNAL bit is set. The device reset or power cycle does not reset the CRC error if there
is a permanent NVM failure.
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7.3.4 Power-On Reset (POR)
The TPL1401 includes a power-on reset (POR) function that controls the output voltage at power up. After the
VDD supply has been established, a POR event is issued. The POR causes all registers to initialize to default
values, and communication with the device is valid only after a 30-ms POR delay. The default value for all the
registers in the TPL1401 is loaded from NVM as soon as the POR event is issued.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific
VDD levels, as indicated in 图 7-1, in order to make sure that the internal capacitors discharge and reset the
device on power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD
drops to less than 1.65 V, but remains greater than 0.7 V (shown as the undefined region), the device may or
may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR. When
VDD remains greater than 1.65 V, a POR does not occur.
VDD (V)
5.5 V
Specified supply
voltage range
No power-on reset
1.71 V
1.65 V
Undefined
0.7 V
Power-on reset
0 V
图7-1. Threshold Levels for VDD POR Circuit
7.3.5 Software Reset
To initiate a device software reset event, write reserved code 1010 to the SW_RESET bits (address D3h). A
software reset initiates a POR event.
7.3.6 Device Lock Feature
The TPL1401 implements a device lock feature that prevents an accidental or unintended write to the digipot
registers. The device locks all the registers when the DEVICE_LOCK bit (address D1h) is set to 1. To bypass the
DEVICE_LOCK setting, write 0101 to the DEVICE_UNLOCK_CODE bits (address D3h).
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7.4 Device Functional Modes
7.4.1 Power Down Mode
The TPL1401 output amplifier and internal reference can be independently powered down through the
DPOT_PDN bits (address D1h).
At power up, the digipot output and the internal reference are disabled by default.
In power-down mode, the digipot output (OUT pin) is in a high-impedance state.
To change this state to 10kΩ-AGND (at power up), use the DPOT_PDN bits (address D1h).
The digipot power-up state can be programmed to any state (power-down or normal mode) using the NVM. 表
7-2 shows the digipot power-down bits.
表7-2. Digipot Power-Down Bits
REGISTER ADDRESS AND NAME
DPOT_PDN[1]
DPOT_PDN[0]
DESCRIPTION
0
0
0
1
Power up
Power down to 10 kΩ
D1h, GENERAL_CONFIG
Power down to high impedance (HiZ)
(default)
1
1
0
1
Power down to 10 kΩ
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7.5 Programming
The TPL1401 devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0), as shown in 节
5. The I2C bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle,
both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through the open
drain I/O pins, SDA and SCL.
The I2C specification states that the device that controls communication is called a master, and the devices that
are controlled by the master are called slaves. The master device generates the SCL signal. The master device
also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus
to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device
on an I2C bus is typically a microcontroller or digital signal processor (DSP). The TPL1401 operates as a slave
device on the I2C bus. A slave device acknowledges master commands, and upon master control, receives or
transmits data.
Typically, the TPL1401 operates as a slave receiver. A master device writes to the TPL1401, a slave receiver.
However, if a master device requires the TPL1401 internal register data, the TPL1401 operate as a slave
transmitter. In this case, the master device reads from the TPL1401. According to I2C terminology, read and
write refer to the master device.
The TPL1401 is a slave and supports the following data transfer modes:
• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast mode plus (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred
to as F/S-mode in this document. The fast mode plus protocol is supported in terms of data transfer speed, but
not output current. The low-level output current would be 3 mA; similar to the case of standard and fast modes.
The TPL1401 supports 7-bit addressing. The 10-bit addressing mode is not supported. The device supports the
general call reset function. Sending the following sequence initiates a software reset within the device: start or
repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the ACK bit,
following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock
cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low during the
high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high period of
the ninth clock cycle as shown in 图7-2.
Data output
by transmitter
Not acknowledge
Data output
by receiver
Acknowledge
2
9
1
8
SCL from
master
S
Clock pulse for
acknowledgement
Start
condition
图7-2. Acknowledge and Not Acknowledge on the I2C Bus
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7.5.1 F/S Mode Protocol
The following steps explain a complete transaction in F/S mode.
1. The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in 图7-3. All I2C-compatible devices
recognize a start condition.
2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
(R/W) on the SDA line. During all transmissions, the master makes sure that data are valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in 图
7-4. All devices recognize the address sent by the master and compare the address to the respective
internal fixed address. Only the slave device with a matching address generates an acknowledge by pulling
the SDA line low during the entire high period of the ninth SCL cycle, as shown in 图7-2. When the master
detects this acknowledge, the communication link with a slave has been established.
3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In
either case, the receiver must acknowledge the data sent by the transmitter. The acknowledge signal can be
generated by the master or by the slave, depending on which is the receiver. The 9-bit valid data sequences
consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary.
4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from
low-to-high while the SCL line is high (see 图7-4). This action releases the bus and stops the
communication link with the addressed slave. All I2C-compatible devices recognize the stop condition. Upon
receipt of a stop condition, the bus is released, and all slave devices then wait for a start condition followed
by a matching address.
SDA
SDA
SCL
SCL
S
P
Start
condition
Stop
condition
Change of data
allowed
Data line stable
Data valid
图7-3. Start and Stop Conditions
图7-4. Bit Transfer on the I2C Bus
7.5.2 I2C Update Sequence
For a single update, the TPL1401 requires a start condition, a valid I2C address byte, a command byte, and two
data bytes, as listed in 表7-3.
表7-3. Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
Address (A) byte
Command byte
Data byte - MSDB 节
Data byte - LSDB 节
节7.5.3
节7.5.4
8.2.3
8.2.3
DB [31:24]
DB [23:16]
DB [15:8]
DB [7:0]
After each byte is received, the TPL1401 acknowledges the byte by pulling the SDA line low during the high
period of a single clock pulse, as shown in 图 7-5. These four bytes and acknowledge cycles make up the 36
clock cycles required for a single update to occur. A valid I2C address byte selects the TPL1401 device.
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Recognize
START or
REPEATED
START
Recognize
STOP or
REPEATED
START
Generate ACKNOWLEDGE
signal
condition
condition
P
SDA
MSB
Sr
Acknowledgement
signal from Slave
Address
R/W
1
SCL
S
1
7
8
9
2 - 8
9
Sr
or
P
or
Sr
ACK
ACK
START or
REPEATED
START
REPEATED
START or
STOP
Clock line held low while
interrupts are serviced
condition
condition
图7-5. I2C Bus Protocol
The command byte sets the operating mode of the selected TPL1401. For a data update to occur when the
operating mode is selected by this byte, the TPL1401 must receive two data bytes: the most significant data byte
(MSDB) and least significant data byte (LSDB). The TPL1401 performs an update on the falling edge of the
acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum digipot update rate is limited to 10 kSPS. Using the fast
mode plus (clock = 1 MHz), the maximum digipot update rate is limited to 25 kSPS. When a stop condition is
received, the TPL1401 releases the I2C bus and awaits a new start condition.
7.5.3 Address Byte
The address byte, as shown in 表 7-4, is the first byte received from the master device following the start
condition. The first four bits (MSBs) of the address are factory preset to 1001. The next three bits of the address
are controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is
sampled during the first byte of each data frame to determine the address. The device latches the value of the
address pin, and consequently responds to that particular address according to 表7-5.
The TPL1401 supports broadcast addressing, which is used for synchronously updating or powering down
multiple TPL1401 devices. When the broadcast address is used, the TPL1401 responds regardless of the
address pin state. Broadcast is supported only in write mode.
表7-4. Address Byte
COMMENT
MSB
LSB
AD6
1
AD5
0
AD4
0
AD3
AD2
AD1
AD0
R/ W
—
See 表7-5
General address
1
0
0 or 1
0
(slave address column)
Broadcast address
1
0
0
1
1 1
表7-5. Address Format
SLAVE ADDRESS
A0 PIN
AGND
VDD
000
001
010
011
SDA
SCL
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7.5.4 Command Byte
表7-6 lists the command byte.
表7-6. Command Byte (Register Names)
ADDRESS
REGISTER NAME
D0h
STATUS
D1h
GENERAL_CONFIG
PROTECT
D3h
21h
DPOT_POSITION
USER_BYTE1
USER_BYTE2
25h
26h
7.5.5 I2C Read Sequence
To read any register, the following command sequence must be used, as shown in 表7-7:
1. Send a start or repeated start command with a slave address and the R/W bit set to 0 for writing. The device
acknowledges this event.
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the slave address and the R/W bit set to 1 for reading. The device acknowledges
this event.
4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register.
An alternative reading method allows for reading back the value of the last register written. The sequence is a
start or repeated start with the slave address and the R/ W bit set to 1, and the two bytes of the last register are
read out.
The broadcast address cannot be used for reading.
表7-7. Read Sequence
R/ W
(0)
R/ W
(1)
S
MSB
ACK MSB
LSB ACK Sr MSB
ACK MSB
LSB
ACK
MSB
LSB
ACK
…
…
…
…
…
ADDRESS
BYTE
节7.5.3
COMMAND
BYTE
节7.5.4
ADDRESS
BYTE
节7.5.3
Sr
MSDB
From Slave
LSDB
From Master
Slave
From Master
Slave
From Master
Slave
Master
From Slave
Master
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7.6 Register Map
表7-8. Register Map
MOST SIGNIFICANT DATA BYTE (MSDB)
LEAST SIGNIFICANT DATA BYTE (LSDB)
ADDRESS
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
NVM_CRC_ NVM_CRC_
D0h
D1h
D3h
ALARM_
USER
ALARM_
INTERNAL
NVM_BUSY
X(1)
X
DEVICE_ID
VERSION_ID
OUT_SPAN
DEVICE_
LOCK
RESERVED
RESERVED
DEVICE_
DPOT_PDN
REF_EN
NVM_
RELOAD
NVM_
PROG
DEVICE_UNLOCK_CODE
X
CONFIG_
RESET
RESERVED
SW_RESET
21h
25h
26h
X
X
X
DPOT_POS[7:0]
X
X
X
USER_BYTE1[7:0]
USER_BYTE2[7:0]
(1) X = Don't care.
表7-9. Register Names
ADDRESS
D0h
REGISTER NAME
SECTION
STATUS
GENERAL_CONFIG
PROTECT
节7.6.1
节7.6.2
节7.6.3
节7.6.4
节7.6.5
节7.6.6
D1h
D3h
21h
DPOT_POSITION
USER_BYTE1
USER_BYTE2
25h
26h
表7-10. Access Type Codes
Access Type
Code
Description
X
X
Don't care
Read Type
R
R
W
Read
Write
Write Type
W
Reset or Default Value
-n
Value after reset or the default value
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7.6.1 STATUS Register (address = D0h) (reset = 000Ch or 0014h)
表7-11. STATUS Register
15
14
13
12
X
11
10
9
8
7
6
5
4
3
2
1
0
NVM_CRC_
ALARM_
USER
NVM_CRC_
ALARM_
INTERNAL
NVM_
BUSY
X
DEVICE_ID
VERSION_ID
R-0h
R-0h
R-0h
R-0h
X-00h
R-14h
R-0h
表7-12. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
NVM_CRC_ALARM_USER
NVM_CRC_ALARM_INTERNAL
NVM_BUSY
R
0
0 : No CRC error in user NVM bits
1: CRC error in user NVM bits
14
13
R
R
0
0
0 : No CRC error in internal NVM
1: CRC error in internal NVM bits
0 : NVM write or load completed, Write to digipot registers
allowed
1 : NVM write or load in progress, Write to digipot registers
not allowed
12
X
R
X
R
R
0
Don't care
11 - 6
5 - 2
1 - 0
X
00h
14h
Don't care
DEVICE_ID
VERSION_ID
14h
Version ID as per the silicon version
7.6.2 GENERAL_CONFIG Register (address = D1h) (reset = 01F0h)
图7-5. GENERAL_CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
DEVICE_
LOCK
RESERVED
R-0Fh
DPOT_PDN REF_EN OUT_SPAN
R-0h
W-0h
R/ W-2h R/ W-0h R/ W-0h
表7-13. GENERAL_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15 - 14 RESERVED
R
00
Always write 00b
0 : Device not locked
13
DEVICE_LOCK
W
0
1: Device locked, the device locks all the registers. This bit can be
reset (unlock device) by writing 0101 to the
DEVICE_UNLOCK_CODE bits (address D3h)
12 - 5
4 - 3
RESERVED
DPOT_PDN
R
0Fh
10
Always write 0Fh
R/ W
00: Power up
01: Power down to 10K
10: Power down to high impedance (default)
11: Power down to 10K
2
REF_EN
R/ W
R/ W
0
0: Internal reference disabled, VDD is digipot reference voltage,
digipot output range from 0 V to VDD
.
1: Internal reference enabled, digipot reference = 1.21 V
1 - 0
OUT_SPAN
00
Only applicable when internal reference is enabled.
00: Reference to VOUT gain 1.5x
01: Reference to VOUT gain 2x
10: Reference to VOUT gain 3x
11: Reference to VOUT gain 4x
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7.6.3 PROTECT Register (address = D3h) (reset = 0008h)
图7-6. PROTECT Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEVICE_UNLOCK_CODE
X
X
DEVICE_
CONFIG_
RESET
RESERVED
NVM_
RELOAD PROG
NVM_
SW_RESET
W-0h
W-0h
R-0h
W-0h W-0h
W-8h
表7-14. PROTECT Register Field Descriptions
Bit
Field
Type
Reset
0000
0h
Description
15 - 12 DEVICE_UNLOCK_CODE
W
Write 0101 to unlock the device to bypass DEVICE_LOCK bit.
Don't care
11 - 10
9
X
X
DEVICE_CONFIG_RESET
W
0
0: Device configuration reset not initiated
1: Device configuration reset initiated. All registers loaded with
factory reset values.
8 - 6
5
RESERVED
R
000
0
Always write 000b
NVM_RELOAD
W
0: NVM reload not initiated
1: NVM reload initiated, applicable digipot registers loaded with
corresponding NVM. NVM_BUSY bit set to 1 while this operation
is in progress. This bit is self-resetting.
4
NVM_PROG
SW_RESET
W
W
0
0: NVM write not initiated
1: NVM write initiated, NVM corresponding to applicable digipot
registers loaded with existing register settings. NVM_BUSY bit
set to 1 while this operation is in progress. This bit is self-
resetting.
3 - 0
1000
1000: Software reset not initiated
1010: Software reset initiated, digipot registers loaded with
corresponding NVMs, all other registers loaded with default
settings.
7.6.4 DPOT_POSITION Register (address = 21h) (reset = 0000h)
表7-15. DPOT_POSITION Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
DPOT_POS[7:0] –MSB Left aligned
X-0h
R/W-000h
X-0h
表7-16. DPOT_DATA Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-2
X
X
0h
Don't care
DPOT_POS[7:0]
R/W
000h
Writing to the DPOT_POSITION register forces the digipot to
update the active register data to the DPOT_POS.
Data are in straight binary format and use the following format:
{ DPOT_POS[7:0], X, X }
X = Don’t care bits
1-0
X
X
0h
Don't care
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7.6.5 USER_BYTE1 Register (address = 25h) (reset = 0000h)
表7-17. USER_BYTE1 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
USER_BYTE1[7:0] –MSB Left aligned
X-0h
R/W-000h
X-0h
表7-18. USER_BYTE1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-2
X
X
0h
Don't care
R/W
000h
USE_BYTE1[7:0] –MSB Left
8-bit user-programmable data.
aligned
Data are in straight binary format and use the following format:
{ USER_BYTE1[7:0], X, X }
X = Don’t care bits
1-0
X
X
0h
Don't care
7.6.6 USER_BYTE2 Register (address = 26h) (reset = 0000h)
表7-19. USER_BYTE2 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
USER_BYTE2[7:0] –MSB Left aligned
X-0h
R/W-000h
X-0h
表7-20. USER_BYTE2 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-2
X
X
0h
Don't care
R/W
000h
USER_BYTE2[7:0] –MSB Left
8-bit user-programmable data.
aligned
Data are in straight binary format and follows the format below:
{ USER_BYTE2[7:0], X, X }
X = Don’t care bits
1-0
X
X
0h
Don't care
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8 Application and Implementation
备注
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPL1401 is a buffered, force-sense-output, single-channel, digipot that includes an internal reference and
NVM, and is available in a tiny 2 mm × 2 mm package. This device interfaces to a processor using I2C. There
are 4 I2C addresses possible by configuring the A0 pin as shown in 表 7-5. The NVM allows processor-less
operation of this device after programming at factory. The force-sense output can work with a transitor to create
a programmable current sink that can bias LEDs. These digipots are designed for general-purpose applications
in a wide range of end equipment. Some of the most common applications for these devices are programmable
current limits, adjustable power supplies, and offset and gain trimming in precision circuits.
8.2 Typical Application
Many analog and power devices, such as LED drivers, power amplifiers, high-side switches, e-fuses, and DC-
DC converters, provide an analog input for an adjustable output current limit. Some of these devices recommend
a resistor from this pin to ground for static settings. The TPL1401 is a very compact way to address the
adjustable current limit requirements of such devices enabling scalability and configurability of these power
devices. The integrated EEPROM makes sure the setting is retained even after power cycling, allowing the
current limit to work without a processor. This section explains the design details of a programmable current limit
application with an example LED driver, the TPS92692. 图 8-1 shows the simplified circuit diagram of this
application.
图8-1. Programmable Current Limit
8.2.1 Design Requirements
• LED driver: TPS92692
• LED driver current limit: 100 mA
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8.2.2 Detailed Design Procedure
The TPS92692 data sheet provides the equation for the voltage required to set a given LED current limit. Use a
sense resistor of 1-Ω for the TPS92692.The voltage at the IADJ pin, VIADJ, must be 1.4 V for an LED current of
100 mA. The range for VIADJ is 2.5 V. Enable the internal reference with 2x gain to set the digipot output range to
2.42 V that will fairly be in the range of current adjustment for the LED driver. Calculate the code needed to set
the digipot output to 1.4 V using the following equation:
(3)
The hex value for 148 is 0x94. Shift this value by 4 bits before writing to the DPOT_POSITION register, resulting
in 0x940.
The pseudocode for the programmable current limit application is as follows:
//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Power-up the device, enable internal reference with 2x output span
WRITE GENERAL_CONFIG(0xD1), 0x11, 0xE5
//Write digipot code (12-bit aligned)
WRITE DPOT_POSITION(0x21), 0x09, 0x40
//Write settings to the NVM
WRITE PROTECT(0xD3), 0x00, 0x10
8.2.3 Application Curves
图8-2. Digipot Code vs LED Current
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9 Power Supply Recommendations
The TPL1401 does not require specific supply sequencing. The device requires a single power supply, VDD. Use
a 0.1-µF decoupling capacitor for the VDD pin. Use a bypass capacitor with a value greater than 1.5-µF for the
CAP pin.
10 Layout
10.1 Layout Guidelines
The TPL1401 pin configuration separates the analog, digital, and power pins for an optimized layout. For signal
integrity, separate the digital and analog traces, and place decoupling capacitors close to the device pins.
10.2 Layout Example
图10-1 shows an example layout drawing with decoupling capacitors and pullup resistors.
图10-1. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Texas, Instruments TPL1401EVM user's guide
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPL1401DSGR
TPL1401DSGT
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
14_1
14_1
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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30-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPL1401DSGR
TPL1401DSGT
WSON
WSON
DSG
DSG
8
8
3000
250
180.0
180.0
8.4
8.4
2.3
2.3
2.3
2.3
1.15
1.15
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPL1401DSGR
TPL1401DSGT
WSON
WSON
DSG
DSG
8
8
3000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
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PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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