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TPIC2010

ZHCSEF8 –DECEMBER 2015

TPIC2010 具有双通道 DC-DC 转换器、由串行接口控制的 9 通道电机驱动

器

1 特性

2 应用

1

•

串行外设接口

•

蓝光碟™播放器

DVD 播放器

CD 播放器

光盘驱动器

–

最大读写频率 35MHz

3.3V 数字 I/O

•

执行器和电机驱动器

–

具有 H 桥输出的脉冲宽度调制 (PWM) 控制

3 说明

具有 12 位数模转换器 (DAC) 控制的聚焦/跟踪/

倾斜执行器驱动器

TPIC2010 是一款适用于薄型或超薄 ODD 的超低噪声

电机驱动器集成电路 (IC)。该驱动器 IC 有 9 条通道且

由串行接口控制，非常适用于驱动主轴电机、滑动电机

（适用的步进电机）、负载电机以及针对准直透镜的聚

焦/跟踪/倾斜执行器和步进电机。该驱动器 IC 具有 1

个双通道同步 DC-DC 转换器。

–

具有电流模式、10 位 DAC 控制的滑动电机驱

动器

–

具有 12 位 DAC 控制的负载驱动器

具有 8 位 PWM 控制的步进电机驱动器

无需位置传感器即可检测准直透镜和滑动结束位

置

器件信息⁽¹⁾

•

主轴电机驱动器

器件型号

封装

封装尺寸（标称值）

–

无传感器反电动势 (BEMF) 位置反馈

12 位主轴 DAC

带散热片薄型小外

形尺寸封装

(HTSSOP) (56)

TPIC2010DFD

14.00mm x 6.10mm

独立的感应位置感测和启动

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

通过自动控制制动实现急停：主动制动和短制动

最大持续电流为 0.7A，不存在散热问题

LS 模式：25% 速度

简化框图

MCOM

TPIC2010

•

片上温度计（15°C 至 172.5°C）

U

V

5 V

SPM

5 V

开关

Driver

3.3 V

W

–

两个可由软件控制的开关电路

SLED1+

SLED1-

SLED2+

SLED2-

5 V

SPI

发光二极管 (LED)：具有 0.1A 过流保护 (OCP)

的 LED 驱动器开关

SLED1

5 V

–

CSW：具有 0.1A OCP 的低 R_DS(ON)电流开关

SLED2

1PX V

output

TLT+

TLT-

•

DC-DC 转换器

REG1PX

FB1PX

5 V

TLT

DCDC

V1PX

–

V1Px：可通过引脚选择的转换电压

1.0V/1.2V/1.5V；0.9A 输出能力，1.85A 过流保

护

FCS+

FCS-

5 V

10 mF

FCS

TRK+

3.3 V

output

5 V

REG3P3

–

V3P3：固定 3.3V DC-DC 转换器；0.5A 输出能

力，1.15A 过流保护

TRK-

TRK

DCDC

V3P3

FB3P3

LOAD+

LOAD-

STP1+

STP1-

STP2+

STP2-

5 V

LOAD

10 mF

–

2.5MHz 开关频率

5 V

STP1

通过断续稳压模式在低电流下提高效率

•

保护

LED

LEDO

Output

5 V

–

LED/CSW、开关、DCDC 转换器、SPM 和执

行器上均配有独立的热保护电路

STP2

–

两个警报级别：热保护中的预检测和检测

ACTTEMP：监视由过去累积的 DAC 值计算得

出的执行器温度

–

欠压锁定 (UVLO) 和过压保护 (OVP)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLIS170

TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

7.16 Electrical Characteristics – LED Switch Part ........ 11

7.17 Electrical Characteristics – Thermometer Part ..... 12

7.18 Electrical Characteristics – Actuator Protection.... 12

7.19 Serial Port I/F Write Timing Requirements ........... 12

7.20 Serial Port I/F Read Timing Requirements........... 13

7.21 Typical Characteristics.......................................... 14

Detailed Description ............................................ 15

8.1 Overview ................................................................. 15

8.2 Functional Block Diagram ....................................... 16

8.3 Feature Description................................................. 17

8.4 Device Functional Modes........................................ 23

8.5 Programming........................................................... 28

8.6 Register Maps......................................................... 30

Application and Implementation ........................ 48

9.1 Application Information............................................ 48

9.2 Typical Application .................................................. 59

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）............................................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

8

9

7.5 Electrical Characteristics – Serial Port Voltage

Levels......................................................................... 7

7.6 Electrical Characteristics – Common Part ................ 8

7.7 Electrical Characteristics – Charge Pump ................ 8

7.8 Electrical Characteristics – V1pXV DC-DC

Converter ................................................................... 9

10 Power Supply Recommendations ..................... 61

11 Layout................................................................... 61

11.1 Layout Guidelines ................................................. 61

11.2 Layout Example .................................................... 61

12 器件和文档支持 ..................................................... 62

12.1 器件支持 ............................................................... 62

12.2 社区资源................................................................ 62

12.3 商标....................................................................... 62

12.4 静电放电警告......................................................... 62

12.5 Glossary................................................................ 62

13 机械、封装和可订购信息....................................... 62

7.9 Electrical Characteristics – 3.3-V DC-DC Converter 9

7.10 Electrical Characteristics – Spindle Motor Driver

Part........................................................................... 10

7.11 Electrical Characteristics – Sled Motor Driver

Part........................................................................... 10

7.12 Electrical Characteristics –

Focus/Tilt/Tracking/Driver Part................................. 10

7.13 Electrical Characteristics – Load Driver Part ........ 11

7.14 Electrical Characteristics – Stepping Motor Driver

Part........................................................................... 11

7.15 Electrical Characteristics – Current Switch Part ... 11

4 修订历史记录

日期

修订版本

注释

2015 年 12 月

*

最初发布。

2

TPIC2010

www.ti.com.cn

ZHCSEF8 –DECEMBER 2015

5 说明（续）

DC-DC 转换器的断续稳压模式能够以较低功耗显著提升效率。主轴电机驱动器利用 BEMF 反馈来进行启动、控制

和低噪声操作，无需外部传感器。此外，TPIC2010 还具有诸多保护特性，包括主轴输出电流限制、热关断、滑动

和准直透镜结束检测、执行器保护以及电源复位电路。TPIC2010 还内置有温度计，以便于测量 IC 温度。

6 Pin Configuration and Functions

DFD Package

56-Pin HTSSOP

Top View

1

LOAD+

LOAD–

STP1+

STP1–

P5V_ 2 56

SLED2– 55

2

3

SLED2+

SLED1– 53

SLED1+ 52

54

4

5

STP2+

STP2–

6

PGND_ 2 51

ISENSE 50

7

CP3

8

CP2

ICOM2

W

49

48

9

CP1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

SSZ

P5V_ SPM2 47

SCLK

U

46

45

44

SIMO

ICOM1

SOMI

V

SIOV

P5V_ SPM1 43

42

XRESET

XFG

M-COM

PGND_ 1 41

TRK– 40

XMUTE

SW R_ SEQ1

SW R_ SEQ2

V1PXSEL

CV3P3

A5V

TRK+

39

FCS– 38

FCS+

37

36

35

TLT–

TLT+

AGND

GPOUT

FB1PX

P5V_ SW

REG1PX

PGND_ SW

P5V_ 1 34

LEDO 33

CSW I 32

CSW O 31

FB3P3 30

REG3P3 29

3

TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

A5V

22

23

9

PS

MISC

PS

O

Power supply terminal for internal logic 5 V

Ground terminal for internal logic

AGND

CP1

Capacitance connection for charge pump

Power supply terminal for 5-V OEIC power switch

Power switch output for 5-V OEIC in OPU

Capacitance terminal for internal 3.3-V core

Feedback input terminal for 1PX converter

Feedback input terminal for 3.3-V DC-DC converter

Focus negative output terminal

CP2

8

CP3

7

CSWI

32

31

21

25

30

38

37

24

45

49

50

33

2

CSWO

CV3P3

FB1PX

FB3P3

FCS–

MISC

I

O

FCS+

O

Focus positive output terminal

GPOUT

ICOM1

ICOM2

ISENS

O

General-purpose output (test monitor)

Current sense resister terminal for spindle driver

Current sense input terminal for spindle drivers

LED output terminal

MISC

I

LEDO

O

LOAD–

LOAD+

M-COM

P5V_1

O

Load negative output terminal

1

O

Load positive output terminal

42

34

56

43

47

26

41

51

28

27

29

11

12

14

53

52

55

54

13

10

4

I

Motor center tap connection

PS

O

Power supply terminal for TI/F/T drivers

Power supply terminal for SLED channel drivers

Power supply terminal for spindle driver

Power supply input for spindle driver

Power supply terminal for DCDC converters

GND terminal for Ti/F/T channel drivers

GND terminal for SLED channel drivers

GND terminal for DCDC converters

P5V_2

P5V_SPM1

P5V_SPM2

P5V_SW

PGND_1

PGND_2

PGND_SW

REG1PX

REG3P3

SCLK

REG1PX DCDC converter switching outputꢀ(GPOUT1⁽²⁾

)

O

REG3P3 DCDC converter switching output terminal (GPOUT2)

SIO serial clock input terminal

I

SIMO

I

SIO slave input master output terminal

Power supply terminal for serial port 3.3-V typical

Sled1 negative output terminal

SIOV

PS

O

SLED1–

SLED1+

SLED2–

SLED2+

SOMI

O

Sled1 positive output terminal

O

Sled2 negative output terminal

O

Sled2 positive output terminal

O

SIO slave output master input terminal

SIO slave select low active input terminal

STP1 negative output terminal for collimator

STP1 positive output terminal for collimator

STP2 negative output terminal for collimator

STP2 positive output terminal for collimator

Internal DC/DC converter startup sequence setting

SSZ

I

STP1–

STP1+

STP2–

STP2+

SWR_SEQ1

SWR_SEQ2

O

3

O

6

O

5

O

18

19

I

(1) I: Input; O: Output; PS: Power; MISC: Miscellaneous

(2) To use as a GPOUT output pin, disable both DC-DC converters' output.

4

TPIC2010

www.ti.com.cn

ZHCSEF8 –DECEMBER 2015

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

TLT–

NO.

36

35

40

39

46

44

20

48

16

17

15

O

I

Tilt negative output terminal

Tilt positive output terminal

TLT+

TRK–

TRK+

U

Tracking negative output terminal

Tracking positive output terminal

U phase output terminal for spindle motor

V phase output terminal for spindle motor

V1Px output voltage setting

V

V1PXSEL

W

O

I

W phase output terminal for spindle motor

Motor speed signal output, internally pulled up to SIOV

XMUTE input terminal to reset the driver IC (optional)

Power-on reset output Internally pulled up to SIOV

XFG

XMUTE

XRESET

O

7 Specifications

7.1 Absolute Maximum Ratings

(1)(2)

see

MIN

MAX

UNIT

V

5-V supply voltage A5V, P5V

Spindle output peak voltage⁽³⁾

Input/output voltage

6

7

V

–0.3

V_CC+ 0.3 V

1.0

V

Spindle output current

A

Spindle output peak current (PW ≦ 2 ms, Duty ≦ 30%)

Sled output peak current

2.5

A

0.8

A

Focus/tilt/tracking driver output peak current

Load driver output peak current

Power dissipation⁽⁴⁾

1.5

A

0.8

A

1344

75

mW

°C

Operating temperature

–20

–50

T_stg

Storage temperature

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the GND.

(3) The output voltage generated with regeneration current at the time of output is off states.

(4) A lower R_θJCis attainable if the exposed pad is connected to a large copper ground plane.ꢀR_θJCand R_θJAare values for 56-pin TSSOP

without a exposed heat slug (HSL) on bottom. ꢀActual thermal resistance would be better than the above values.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5

TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

7.3 Recommended Operating Conditions

MIN

4.5

NOM

5.0

MAX

UNIT

V

A5V

Operating supply voltage (apply for A5V)

Driver 5V supply voltage (apply for P5V)

CSWI input voltage (apply for P5V)

SIOV voltage

5.5

A5V + 0.2

3.6

P5V

A5V – 0.2

3.0

A5V

3.3

V

CSWIV

V_SIOV

V_SIFH

V_SIFL

V

SIMO, SSZ, SCLK pin “H” level input voltage range

SIMO, SSZ, SCLK pin “L” level input voltage range

2.2

SIOV + 0.2

0.8

V

–0.2

V

XMUTE, SWR_SEQ1, SWR_SEQ2, V1pXSEL

pin “H” level input voltage

V_IHB

V_ILB

2.2

A5V + 0.1

0.8

V

XMUTE, SWR_SEQ1, SWR_SEQ2, V1pXSEL

pin “L” level input voltage range

–0.1

I_SPMOA

I_SPMO

I_SLDOA

I_Ld1Px

I_Ld3P3

I_ACTOA

I_CSWOA

I_STPOA

F_ck

Spindle output average current (U, V, W total)

Spindle output current

700

400

900

500

400

200

35

mA

MHz

°C

Sled output average current

1pXV switching regulator load current

3p3V switching regulator load current

Focus / tracking / tilt / loading output average current

CSWO output average current

STP output average current

SCLK frequency

30

33.8688

25

T_O

Operating temperature range

–20

75

7.4 Thermal Information

TPIC2010

THERMAL METRIC⁽¹⁾

DFD (HTSSOP)

UNIT

56 PINS

16.9

0.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

5.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.0

ψ_JB

5.2

R_θJC(bot)

0.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

TPIC2010

www.ti.com.cn

ZHCSEF8 –DECEMBER 2015

7.5 Electrical Characteristics – Serial Port Voltage Levels

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SOMI

High-level output voltage, V_OH

Low-level output voltage, V_OL

High-level input voltage, V_IH

Low level input voltage, V_IL

I_OH= 1 mA

80%

SPIOV

V

SOMI

SIMO

I_OL= 1 mA

20%

SPIOV

V

70%

SPIOV

20%

SPIOV

V

SIMO

Input rise/fall time

Output rise/fall time⁽¹⁾

10% → 90% PIOV

3.5

ns

Cload = 30 pF,10% → 90%

SPIOV

10

SCLK

SSZ

Internal pulldown resistance

Internal pullup resistance

200

kΩ

(1) Specified by design

7

TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

7.6 Electrical Characteristics – Common Part

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SWR_SEQ1 = SWR_SEQ2 =

V1PxSEL = A5V

ISTBY

Stand by Supply current

1

mA

VCV3

CV3P3 Output voltage

Iload = 25 mA

3.135

100

3.3

200

33

3.465

300

49.5

0.3

V

RXM

XMUTE pulldown resistor

SWR_SEQ1 pulldown resistor

SWR_SEQ2 pulldown resistor

V1PxSEL pulldown resistor

XRESET pullup resistor

kΩ

V

RSW1

RSW2

RSELS1

RXRST

VXRST

TPOR

RXFG

100

16.5

XRESET low level output voltage SIOV = 3.3 V, I_OL= –100 µA

Power-On Reset delay

15

20

25

ms

Ω

XFG output resistor

100

200

300

SIOV = 3.3 V, XSLEEP = 1,

XFG high level output voltage

VXFGH

2.7

V

I_OH= 100 µA

SIOV = 3.3 V, XSLEEP = 1,

XFG low level output voltage

VXFGL

RGPO

0.3

V

I_OL= –100 µA

GPOUT output resistor

100

2.7

200

300

Ω

SIOV = 3.3 V, XSLEEP = 1,

VGPOH

VGPOL

GPOUT high level output voltage

GPOUT low level output voltage

GPOUT_ENA = 1, GPOUT_HL =

1, I_OH= 100 µA

V

SIOV = 3.3 V, XSLEEP = 1,

GPOUT_ENA = 1,GPOUT_HL =

0, I_OH= 100 µA

0.3

tTSD

Thermal protect on temperature

Thermal protect hys temperature

A5V Reset on voltage

Design ensured value

130

5

145

15

165

25

ºC

V

hytTSD

Vonvcc

3.6

3.8

2.6

2.68

35

3.7

3.9

2.7

2.8

85

3.8

4

Voffvcc

A5V Reset off voltage

V

VonCV3

VoffCV3

HysCV3

VovpspmOn

VovpspmOff

VovpSpmHys

CV3P3 reset on voltage

2.8

2.88

135

6.4

6.2

340

V

CV3P3 reset off voltage

V

CV3P3 reset voltage Hys

OVP detection voltage (Spindle)⁽¹⁾

OVP release voltage (Spindle)⁽¹⁾

OVP voltage Hys (Spindle)⁽¹⁾

mV

V

6

6.2

6

5.8

140

V

240

mV

OVP detection voltage

(except Spindle)⁽¹⁾

VovpOn

VovpOff

VovpHys

6.3

6.1

6.5

6.3

6.7

6.5

V

OVP release voltage

(except Spindle)⁽¹⁾

OVP voltage Hys

(except Spindle)⁽¹⁾

140

240

340

mV

(1) Those are value as protection functions only, and stress beyond those listed under Recommended Operating Conditions may cause

permanent damage to the device.

7.7 Electrical Characteristics – Charge Pump

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

XSLEEP=1

MIN

TYP

MAX

UNIT

FCHGP

VCHGP

Frequency

132.6

156

179.4

kHz

Ccp1 = Ccp3 = 0.1 µF

Io = –1 mA

Output Voltage

7.76

9.7

11.64

V

8

TPIC2010

www.ti.com.cn

ZHCSEF8 –DECEMBER 2015

7.8 Electrical Characteristics – V1pXV DC-DC Converter

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FB1PXV = 0 V REG1PXV + 100

mA, +300 mA

Rds1pxH

Rds1pxL

VO1p0

High-side FET RDSON

0.42

0.62

Ω

FB1PXV = 1.2 V REG1PXV –100

mA , –300 mA

Low-side FET RDSON

Output voltage (1p0V)

Output voltage (1p2V)

Output voltage (1p5V)

Soft start time

0.2

1

0.4

1.05

Ω

V

[V1PxSEL,SWR_SEQ1,SWR_SE

Q2] = 011

0.95

1.14

[V1PxSEL,SWR_SEQ1,SWR_SE

Q2] = 000

VO1p2

1.2

1.5

0.82

1.26

V

[V1PxSEL,SWR_SEQ1,SWR_SE

Q2] = 100

VO1p5

1.425

0.656

1.575

0.984

V

[SWR_SEQ1,SWR_SEQ2] = 00

From A5V reset off to target 90%

Tdly1px

ms

RdsO1px

Fsw1px

Output pulldown transistor Rdson At Reset On (TSD, A5V_Reset)

Switching frequency

616

2.125

75%

85%

5%

880

2.5

1144

2.875

85%

Ω

MHz

Vrston1px

Vrstoff1px

VrstHys

Reset on voltage threshold level

80%

90%

10%

Reset off voltage threshold level

95%

Reset off voltage threshold Hys

15%

P5V_SW = 5 V + 200 mVpp,

PSRR1px

PSRR ratio

Io = 200 mA,

26

dB

F ≈ 100 kHz

Iovc1px

Overcurrent protective level⁽¹⁾

1.3

1.85

1

2.4

A

Mask time of overcurrent

protection⁽¹⁾

TMskovc1px

0.72

1.32

ms

(1) Those are value as protection functions only, and stress beyond those listed under Recommended Operating Conditions may cause

permanent damage to the device.

7.9 Electrical Characteristics – 3.3-V DC-DC Converter

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FB3P3V = 0 V REG3P3V + 100

mA + 300 mA

Rds3p3H

High-side FET RDSON

0.45

0.65

Ω

FB3P3V = 3.3 V REG3P3V –100

mA – 300 mA

Rds3p3L

VO3p3

Low-side FET RDSON

Output voltage

0.42

3.3

0.62

3.4

Ω

V

3.2

[SWR_SEQ1,SWR_SEQ2] = 00

From A5V reset off to target 90%

Tdly3p3

Soft start time

0.656

0.82

0.984

ms

Rds3p3

Output pull down transistor Rdson At reset on (TSD, A5V_Reset)

Switching frequency

616

2.125

75%

85%

5%

880

2.5

1144

2.875

85%

Ω

Fsw3p3

MHz

Vrston3p3

Vrstoff3p3

Vrst3p3Hys

Reset on voltage threshold level

Reset off voltage threshold level

Reset off voltage threshold Hys

80%

90%

10%

95%

15%

P5V_SW = 5 V + 200 mVpp,

PSRR3p3

PSRR ratio

Io = 200 mA,

26

dB

F ≈ 100 kHz

Iovc3p3

Overcurrent protective level⁽¹⁾

0.65

0.72

1.15

1

1.65

1.32

A

Mask time of overcurrent

protection⁽¹⁾

Tmskovc3p3

ms

(1) Data are value as protection functions only, and stress beyond those listed under “Recommended Operating Condition” may cause

permanent damage to the device.

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TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

7.10 Electrical Characteristics – Spindle Motor Driver Part

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Total output resistance

High side + low side

RttlSPM

I_OUT= 0.1 A

0.25

0.5

Ω

VIsns

ISENSE detected voltage

Resolution

ISENSE voltage

181

196

12

211

mV

bit

V

ResSPM

VSPM(REG8h) = 400h

VSPM(REG8h) = C00h

Forward

2.6

–1.55

+12h

–92h

–40h

3

3.4

–0.95

+92h

–12h

40h

VoutSPM

Spindle voltage

–1.25

+52h

–52h

0h

V

WidDZSPM

Spindle dead band

Reverse

WidDZSPMLS

Spindle dead band (LS mode)

7.11 Electrical Characteristics – Sled Motor Driver Part

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Ω

Total output resistance

High side + low side

RttlSLD

ResSLD

I_O= 0.1 A

0.7

1.1

Resolution

10

+51h

–51h

bit

Forward

Reverse

+4h

+90h

–4h

WidDZSLD

GnSLD

Input dead band

–90h

A5V = 5 V, 5 V = 5 V

R_L= 10 Ω, 2.2 mH

VSLED = 7FFh

Sled current gain

380

26

440

46

500

66

mA

mV

ENDDET_SLCT = 0,

SLEDENDTH<1:0> = 00, SLED

Enable

END_DET BEMF threshold

voltage

VthEdetSLD

7.12 Electrical Characteristics – Focus/Tilt/Tracking/Driver Part

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Total output resistance

High side + low side

RttlAct

I_O= 0.1 A

0.7

1.1

Ω

ResACT

Resolution

12

0

bit

VOfstACT

Each channel output offset voltage DAC_code = 000h

–30

–50

30

50

mV

Output offset voltage Focus and

VOfstDACT

GnDAct

DIFF_TLT = 1

Tilt

0

mV

db

Difference gain Focus and Tilt

DIFF_TLT = 1

–1

2.6

0

3

1

3.4

DAC_code = 400h

DAC_code = C00h

GnAct

Voltage gain

V

–3.4

–3

–2.6

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TPIC2010

www.ti.com.cn

ZHCSEF8 –DECEMBER 2015

7.13 Electrical Characteristics – Load Driver Part

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Ω

Total output resistance

High side + low side

RttlLOD

ResLOD

I_O= 0.1 A

0.7

1.1

Resolution

12

3

bit

VLOAD = 400h

VLOAD = C00h

Forward

2.6

–3.4

2h

3.4

–2.6

40h

–3h

0.96

375

0.96

GnLOD

Voltage gain

V

–3

20h

–21h

0.8

250

0.8

WidDZLOD

Dead band

Reverse

–41h

0.64

125

TocpLOD

IocpLOD

Output 100% limit time

LOAD_05CH = 0

LOAD_05CH = 1

s

mA

s

Overcurrent protective level

DlyocpLOD

Overcurrent protection delay time LOAD_05CH = 1

0.64

7.14 Electrical Characteristics – Stepping Motor Driver Part

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Total output resistance

High Side + Low Side

RttlSTP

I_O= 0.1 A

1.0

1.5

Ω

ResSTP

Resolution

8

850

1

bit

mA

us

IocpSTP

Overcurrent protection level⁽¹⁾

OCP Monitor delay time⁽¹⁾

OCP hold time⁽¹⁾

595

0.7

1105

1.3

DlyocpSTP

ThlocpSTP

18.2

26

33.8

ms

ENDDET_SLCT = 1,

STPDENDTH<1:0> = 00, STP

Enable

VthEdetSTP

END_DET threshold level

19

39

59

mV

(1) The data are value as protection functions only, and stress beyond those listed under Recommended Operating Conditions may cause

permanent damage to the device.

7.15 Electrical Characteristics – Current Switch Part

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_O= 0.1 A

MIN

TYP

200

1.1

MAX

500

1.43

2.0

UNIT

mΩ

A

RdsCSW

IlmtCSW

ThlCSW

Rds(on)

Current limit threshold level

Protection hold time

0.77

1.47

1.6

ms

7.16 Electrical Characteristics – LED Switch Part

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_O= 10 mA

MIN

TYP

4.4

0.1

0.4

MAX

10

UNIT

Ω

RdsLED

IlmtLED

ThlLED

Rds(on)

Current limit threshold level

Protection hold time

0.07

0.37

0.13

0.66

A

ms

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TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

7.17 Electrical Characteristics – Thermometer Part

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

6

MAX

UNIT

ResTEMP

TEMPrng

FTEMP

Resolution

bit

CHIPTEMP[5:0] = 00

CHIPTEMP[5:0] = 3Fh

8

155

8

15

22

175

12

Temperature range

Update cycle

°C

165

10

kHz

7.18 Electrical Characteristics – Actuator Protection

over recommended operating free-air temperature range (A5V ≈ 4.5 to 5.5 V, P5V_1, P5V_2, P5V_STP, P5V_SPM1,

P5V_SPM2 = A5V, VREF = 1.65 V, T_A≈ –20°C to 75°C; unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TintACTTEMP

Update cycle

21

26

31

ms

7.19 Serial Port I/F Write Timing Requirements

MIN

NOM

MAX

35

UNIT

MHz

ns

F_ck

t_ckl

SCLK clock frequency

SCLK low time

PIOV = 3.3 V

11

7

t_ckh

t_sens

t_senh

t_sl

SCLK high time

ns

SSZ setup time

ns

SSZ hold time

7

ns

SSZ disable high time

SIMO setup time (Write)

SIMO hold time (Write)

11

7

ns

t_ds

ns

t_dh

7

ns

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TPIC2010

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ZHCSEF8 –DECEMBER 2015

7.20 Serial Port I/F Read Timing Requirements

MIN

NOM

MAX

UNIT

MHz

ns

F_ck

t_ckl

SCLK clock frequency

SCLK low time

PIOV = 3.3 V

35

11

7

t_ckh

t_sens

t_senh

t_sl

SCLK high time

ns

SSZ setup time

ns

SSZ hold time

7

ns

SSZ disable high time

SIMO setup time (Write)

SIMO hold time (Write)

SOMI delay time (Read)

SOMI hold time (Read)

11

7

ns

t_ds

ns

t_dh

7

ns

t_rdly

t_sendl

CLOAD = 10 pF, PIOV = 3.3 V

2

9

ns

2

ns

CLOAD = 10 pF, PIOV = 3.3 V

From SSZ rise to SOMI HIZ

t_rls

SOMI release time (Read)

0

9

ns

Tsl

SSZ

Fck

Tsens

Tsenh

SCLK

SIMO

Tckl

Tckh

Tds

Tdh

SOMI

Hi-Z

Figure 1. Serial Port Write Timing

Tsl

SSZ

Tsenh

Fck

Tsens

SCLK

Trls

Tdh

Tds

Tckh Tckl

SIMO

R

SOMI

Hi-Z

Trdly

Tsendl

Figure 2. Serial Port Read Timings

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TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

Tsl

SSZ

Tsenh

Fck

Tsens

SCLK

Tdh

Tds

Tckh Tckl

SIMO

SOMI

R

Trls

Hi-Z

Trdly

Tsendl

Figure 3. Serial Port Read Timings (ADVANCE_RD Mode)

7.21 Typical Characteristics

120

100

80

60

40

20

0

120

100

80

60

40

20

0

STP1-

STP2-

STP1+

STP2+

-3000

-2000

-1000

0

1000

2000

3000

D001

-3000

-2000

-1000

0

1000

2000

3000

D002

DAC Code

Figure 4. DAC Code vs Duty Cycle for STP1 Outputs

Figure 5. DAC Code vs Duty Cycle for STP2 Outputs

14

TPIC2010

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ZHCSEF8 –DECEMBER 2015

8 Detailed Description

8.1 Overview

TPIC2010 is low noise type motor driver IC suitable for 5V optical disk drives. The 9-channel driver IC controlled

by SPI is optimum for driving a spindle motor, a sled motor (stepping motor applicable), a load motor, and Focus

/ Tracking / Tilt actuators and stepping motor for collimator lens. This IC requires an external current sense

resistance to measure SPM current. The spindle motor driver part uses integrated sensorless logic to attain low-

noise operation during startup and runtime. By using BEMF feedback, external sensors, such as a Hall device,

are not needed to carry out self-starting by the starting circuit or perform position detection. By using the efficient

PWM drivers, low-power operation can be achieved by controlling the PWM outputs. Dead zone less control is

possible for a Focus / Tracking / Tilt actuator driver. In addition, the spindle part output current limiting circuit, the

thermal shut down circuit, the sled end detection circuit, collimator lens end detection circuits offer protection for

all actuators and motors.

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TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

8.2 Functional Block Diagram

P5V

A5V

P5V

1u

0.1u

ICOM1

ICOM2

Charge

pum p

10V(P5Vx2)

XSLEEP

0.22

SPM

Current lim it

ISENSE

XFG

M_ COM

SPM Logic

DAC PW M

BEMF

detector

SPM _ ENA

SPM _ LSM ODE

On chip

therm om eter

U

SIOV

pre- power

driver FET

V

SSZ

SCLK

SIMO

SOMI

SSZ

W

SCLK

SIMO

SOMI

SLED1+

SLED1-

DAC

PW M

pre- power

driver FET

SIOV

3.3V

SLD_ ENA

F/B

SLED END

detection

Digital core

ENDDET_ ENA

ENDDET_ SLCT

GPOUT

XMUTE

GPOUT

SLED2+

SLED2-

DAC

PW M

pre- power

driver FET

F/B

XMUTE

TLT+

TLT-

DAC

PW M

pre- power

driver FET

A5V

CV3P3V

TLT_ ENA

FCS_ ENA

F/B

int 3.3V

Regulator

0.1u

FCS+

FCS-

SIOV

DAC

PW M

pre- power

driver FET

Power

m onitor

XRESET

F/B

XRESET

TRK+

TRK-

A5V

pre- power

driver FET

SW R_ SEQ1

SW R_ SEQ2

GND

A5V

F/B

DAC

PW M

LOAD+

TRK_ ENA

pre- power

driver FET

LOAD_ ENA

LOAD-

GND

A5V

F/B

10000pF

V1PXSEL

P5V

STP1+

GND

DAC

PW M

A5V

pre- power

driver FET

P5V_ SW

REG1PX

STP_ ENA

DC-DC

V1PX

STP1-

STP2+

10u

DAC

PW M

pre- power

driver FET

1.xV

FB1PX

A5V

DC-DC

V3P3

10u

STP2-

STEP END

detection

REG3P3

FB3P3

ENDDET_ ENA

ENDDET_ SLCT

CSW

3.3V

CSW _ ON

10u

LED

LED_ ON

TPIC2010

CSW O CSW I

LEDO

P5V

CSWO

0.1u

LEDO

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TPIC2010

www.ti.com.cn

ZHCSEF8 –DECEMBER 2015

8.3 Feature Description

8.3.1 Protection Functions

TPIC2010 has five protection features: undervoltage lockout, overvoltage protection (OVP), over

currentprotection (OCP), thermal protection (TSD), and actuator temperature protection (ACTTIMER) in order to

protect target equipment. A protect behavior differ by generated events.

8.3.1.1 Undervoltage Lockout (UVLO)

Power Faults are reported in the UVLOMon register. Each UVLOMon bit will be initialized to zero upon a cold

power up. After a fault is detected the appropriate fault bit will be latched high. Writing to the RST_ERRFLG

(REG77) will clear all UVLOMon bits. The power device faults and actions are summarized in Table 1.

Table 1. Power Fault Monitor

LATCHED

REGISTER

FAULT TYPE

XRESET

CRITERIA

SPM

ACTUATOR

DC-DC

Hi-Z

Feedback pin to

GND

A5V under voltage

UVLO_A5V

Yes

<3.7 V

Hi-Z

internal 3.3V under

voltage

UVLO_INT3P3

UVLO_SWR3P3

UVLO_SWR1PX

Yes

<2.7 V

<80%

Hi-Z

3.3V DC-DC output

under voltage

1.xV DC-DC output

under-voltage

>6.2 V

>6.5 V

Brake

Hi-Z

—

P5V over-voltage

OVP_P5V

Hi-Z

8.3.1.2 Overvoltage Protection (OVP)

Over voltage protect function is aimed to protect the unit from the supplying hi-voltage.

When the supply voltage exceeds 6.5 V, all driver and DC-DC converter output goes Hi-Z. When the supply

voltage falls below typical 6.2 V, (6.0 V for SPM) all output start to operate again. The OVP and POR (XRESET)

function is not interlocking. However, DC-DC converter output falls by Hi-Z operations, output voltage falls to

80% then XRESET signal goes low.

Moreover, when power supply exceeds 6.2 V, especially SPM enter short brake mode. This operation is offered

supposing a voltage rising by motor BEMF of the high velocity revolution.

This function is for insurance, so it can not assure that the device is safety in the condition. Because the absolute

maximum ratings range of the supply voltage is 6 V. When this function works, the feed back terminals are not

shorted to GND.

Figure 6 shows the behavior of OVP.

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TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

5 Vsupply

6.5 V

6.3 V

6.2 V

6.0 V

SPM

Short Brake

Hi-Z

Actuator

DCDC

LED/CSW

Hi-Z

Figure 6. Overvoltage Protection

8.3.1.3 Overcurrent Protection (OCP)

The OCP function serve to protect the device from break down by large current. The OCP is provided for five

circuit blocks, and each threshold are in Table 2.

Table 2. OCP Threshold

BLOCK

DETECTION CURRENT

1850 mA

MONITOR TIME

1 ms

HI-Z HOLD TIME

POR

DC-DC conv V1PX

V3P3

1150 mA

1 ms

POR

LOAD driver 1 ch

0.5 ch

100%

800 ms

1 µs

Forever

25 ms

260 mA

STEP driver

LED driver

CSW driver

850 mA

100 mA

20 µs

0.4 ms

1000 mA

20 µs

1.6 ms

When the large current is detected on each block, device put the output FET to Hi-Z.

The amounts of currents and time have specified the detection threshold for every circuit block.

When OCP occurs, it returns automatically after expiring set Hi-Z period. However, it restricts, the POR is

performed at OCP for DC-DC converter. It keeps XRESET=L and does not return forever. It’s necessary power

ON/OFF actuation in order to make it release.

OCPERR (REG7F) and OCP flag (REG7B) are set at OCP detection.

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TPIC2010

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ZHCSEF8 –DECEMBER 2015

detect 1 ms

DC-DCconv Load- I

1.8 A(V1.x) /1.1 A(V3 p3)

0 mA

Hi-Z

output 3.3 V

output 1.x V

XRESET

No release

(until 5-Vsupply recycle)

Figure 7. OCP DC-DC Converter

detect 800 ms

260 mA

LOAD load - I

0 mA

Hi-Z

LOAD + voltage

LOAD – voltage

XRESET

Figure 8. OCP Load 1-Channel

LOADload-I

0 mA

Hi-Z

LOAD + voltage

100%

800 ms

LOAD – voltage

XRESET

Figure 9. OCP Load 0.5-Channel

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TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

Detect 1 µs

850 mA

0 mA

STEP load-I

Hi-Z

STEP + voltage

STEP – voltage

25 ms

XRESET

STP1 and STP2 channel has current trip function. The output of STEP channel will be changed Hi-Z if current exceed

current limit threshold (850-mA typ). When the trip period 25ms is expired, trip state is automatically released.

Figure 10. OCP Step

LED_ ON (REG71)

Detect 20 µs

LED load-I

100 mA

0 mA

Hi-Z

LED voltage

0.4 ms

XRESET

Figure 11. OCP LED Driver

CSW _ ON (REG71)

Detect 20 µs

1000 mA

CSW load-I

0 mA

Hi-Z

CSW voltage

1.6 ms

XRESET

Figure 12. OCP Current Switch

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TPIC2010

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ZHCSEF8 –DECEMBER 2015

8.3.1.4 Thermal Protection (TSD)

The thermal protection (TSD) is a protect function which intercepts an output and suspends an operation when

the IC temperature exceed a maximum permissible on a safety. TSD makes an output Hi-Z when the

temperature rises up and a threshold value is exceeded. There’re two levels for threshold “Alert” and “Trip”.

Alarm is given by status register “TSD_FAULT_” on “Alert” level with 135°C. It continues rising up temperature,

the register “TSD_” is set at 150°C and the driver output changes HI-Z. If temperature falls and is reached

135°C, it will output again. TPIC2010 has total 12 temperature sensors in each circuit block. Particular sensor is

assigned to appropriate status flag in List 10 OCP threshold.

Table 3. Thermal Sensor Assignment

CIRCUIT

U

ALERT (°C)

130

TRIP (°C)

145

RELEASE (°C)

ALERT FLAG

TSD_FAULT_SPM

TSD_FAULT_ACT

TSD_FAULT_LEDCSW

TSD_FAULT_SWR

TRIP FLAG

TSD_SPM

TSD_ACT

TSD_ LEDCSW

TSD_SWR

130

V

130

145

W

130

145

TLT

130

145

FCS

130

145

TRC

130

145

SLED1

SLED2

STP

130

145

130

145

130

145

LOAD

LED/CSW

2ch DCDC

130

145

130

145

130

145

8.3.1.5 Actuator Temperature Protection (ACTTIMER)

TPIC2010 has Actuator protect function named ACTTIMER. This function enables to avoid from being broken by

setting actuator channel output to HIZ when actuator coil current exceeds the specific value. Up to now, be used

a simple actuator protect function such like exceeding max current with continuous time. However these types

were not accurate. This new protection enables to calculate heat accumulation and judge correctly. When this

function operates, load channel output will be Hi-Z, too. And spindle channel will be forced “Auto short brake”

and disc motor will stop.

It’s able to know the protection has occurred by checking Fault register ACTTIMER_FAULT (REG7F) and

ACT_TIMER_PROT (REG78). ACTTIMER_FAULT has a character of advance notice, is set before detecting

ACT_TIMER_PROT. Once an ACT_TIMER_PROT is set, even if temperature falls, it will not release protection

automatically. It’s necessary to clear the flag by setting RST_ERR_FLAG (REG77) or setting 0 to ACTTEMPTH

(REG72). ACTTIMER function is able to disable by setting H to ACTPROT_OFF (REG72) or setting 0 to

ACTTEMPTH (REG72).

In order to acquire the optimal value for ACTTEMPTH, you should set device into the condition of the detection

level, and reading the value of ACTTEMP. Because of the present value can be read from ACTTEMP (REG78).

(1)

(1) The ACTTEMP data is updated on Register in ACTPROT_OFF = 0 and ACTTEMPTH > 0.

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RST_ ERR_ FLAG

ACTTIMER_ FAULT

ACT_ TIMER_ PROT

ACTTEMPTH

ACTTEMPTH-1

ACTTEMPcount

Hi-Z

FCS+ , TRK+ , TLT+

FCS-, TRK-, TLT-

Load+

Hi-Z

Load-

Motor rpm

0

auto short brake

XFG

disable 300m s

Figure 13. Actuator Temperature Protections

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8.4 Device Functional Modes

8.4.1 Power-On Reset (POR)

8.4.1.1 Power-Up Sequences

The power up sequence is described in Table 4.

In TPIC2010, the normal sequence is to wait for 5-V supply to come up to 3.9 V. After 5 V establish, the internal

3.3 V will stabilize. Now the voltage monitors start to work and begin to look for the DC-DC V1Px and V3P3.

Start up sequence for internal DC-DC converter is selected by external pin, SWR_SEQ1 and SWR_SEQ2. All

DC-DC converters stabilize the power up sequence finishes and the part starts to function. Once the part finishes

all of its power up tasks, it takes XRESET high to indicate that the part is no longer in reset and ready to

communicate to the outside world. All the DC-DC converter have soft-start features to avoid rush current and

voltage over shoot. Each soft-start sequence takes about 0.8 ms.

Table 4. DC-DC Start-Up Sequence and Output

SEQUENCE

V1PXSEL

SWR_SEQ2

SWR_SEQ1

REG1PX(V)

REG3P3(V)

REG1PX

REG3P3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.2

1.0

1.5

3.3

Same

2^nd

1^st

2^nd

Same

2^nd

1^st

2^nd

Disable⁽¹⁾

(1) This setting is able to use REG1PX, REG3P3 pin as GPOUT pin.

A5V supply

5.0 V

3.9 V

V3P3 output

V1PX output

90%of V3P3

90%of V1PX

Time

XRESET

800 µs

20 ms

Figure 14. Simultaneously Start Up (SWR_SEQ[1:0] = 00)

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A5V supply

5.0 V

3.9 V

90%of V3P3

90%of V1PX

V3P3 output

V1PX output

Time

XRESET

800 µs

20 ms

Figure 15. V1Px Start First (SWR_SEQ[1:0] = 10)

A5V supply

5.0 V

3.9 V

V3P3 output

V1PX output

90%of V3P3

90%of V1PX

Time

XRESET

800 µs

20 ms

Figure 16. V3P3 Start First (SWR_SEQ[1:0] = 01)

8.4.1.2 XRESET

TPIC2010 is preparing XRESET pin in order to notify an own status to DSP. TPIC2010 set XRESET to L when

the event which has a serious effect on DSP occurs such like the power failure, the over temperature and the

drop of DC-DC converter output. If all the exception is removed, it will tell that XRESET pin would be set to H

and it would be in the ready state. The POR (power on reset) condition is shown in Figure 17. All the behavior of

XRESET is shown in Figure 21.

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A5V

P5V

SIOV

< 6.5 V

> 3.9 V

> 2.8 V

> 90%

DC-DC

V1PX

Delay

Tim er

Int 3.3-V

Regulator

> 2.2 V

DC-DC

V3P3

XRESET

Therm al

Protection

V1PXSEL

SW R_ SEQ1,2

Figure 17. POR Block Diagram

A5Vsupply

5.0 V

3.9 V

3.7 V

V3P3 output

V1PXoutput

90% ofV3P3

90% ofV1Px

20 ms

XRESET

Figure 18. 5-V Supply Voltage Drop

A5V supply

5.0 V

V3P3 output

V1PX output

90%of V3P3

80%of V3P3

V1PX

Time

20 ms

XRESET

Figure 19. 3.3-V Output Voltage Drops (SWR_SEQ = 00, 11)

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A5V supply

5.0 V

V3P3 output

V1PX output

V3P3

90%of V1PX

80%of V1PX

Time

XRESET

20 ms

Figure 20. 1.x V Output Voltage Drops (SWR_SEQ = 00, 11)

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XRESET: High

Register Reset

RST_REGS_WO3 = 1

(Write Data)

Register Valid Data

Keep XSLEEP,

LED_ON, CSW_ON

XMUTE = L (Note 1)

or RST_ REGS = 1

or SIF_ TIMEOUTERR_ MON = 1

20 ms

A5V< 3.7 V

or CV3P3 < 2.7 V

or SIOV< 2.0 V

A5V> 3.9 V

A5V > 3.9 V

and CV3P3 > 2.8 V

and SIOV> 2.2 V

or DC-DCconv output < 80% (DC-DCenable)

or P5V> 6.5 V(*3)

and CV3P3 > 2.8 V

and SIOV> 2.2 V

and DC-DCconv Disable (Note 2)

or TSD > 150 degree (only TSD_ SWR = 1)

or OCP_ SW R = 1 (> 1.85 A /> 1.15 A [V1PX /V3P3])

and DC-DCconv output > 90%

and P5V < 6.3 V(Note 3)

XRESET: Low

TSD < 135 Degrees

Power on Reset

OCP_SWR = 1

Hold XRESET

(1) The period of XMUTE = L cannot be communicated with device.

(2) DC-DC converter disable is V1PXSEL = H, SWR_SEQ1 = H, SWR_SEQ2 = H

(3) When exceed 6.5 V, DC-DC converter output changed Hi-Z and output falling < 80%. Consequently force RESET

event. (Released > 90%)

Figure 21. XRESET Behavior

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8.5 Programming

8.5.1 Function and Operation

8.5.1.1 Serial Port Functional Description

The serial communication of TPIC2010 is based on a SPI communications protocol. TPIC2010 is put on the

slave side. All 16-bit transmission data is effective in SSZ = L period.

The bit stream sent through SIMO from a master (DSP) is latched to an internal shift register by the rising edge

of SCLK. All the data is transmitted in a total of 16-bit format of a command and data. A format has two types of

data, 8 bits and 12 bits length. In order to access specific registers, an address and R/W flag are specified as a

command part. In addition, 12 bit data do not have R/W flag in the packet because DAC registerꢀ(= 12-bit data

form) are Write only. A transfer packet, command and data, is transmitted sequentially from MSB to LSB. A

packet is distinguished in MSB 2 bits of command. In the case of 11, it handles a packet for control register

access, and the other processed as a packet for a DAC data setting.

There are the following four kinds of serial-data communication packets.

1. Write 12 bits DAC data (MSB two bit ≠ 11)

2. Write 8 bits control register (MSB two bit = 11)

3. Read 8 bits control register (MSB two bit = 11)

4. Write 12 bits Focus DAC data＋Read 8 bits status register at the same time (MSB two bit ≠ 11)

8.5.1.2 Write Operation

For write operation, DSP transmits 16 bit (command + address + data) data a bit every in an order from MSB.

Only the 16-bit data which means 16 SCLK sent from the master during SSZ = L becomes effective. If more than

17 or less than 15 SCLK pulses are received during the time that SSZ is low, the whole packet will be ignored.

For all valid write operations, the data of the shift register is latched into its designated internal register at rising

edge of 16th SCLK. All internal register bits, except indicated otherwise, are reset to their default states upon

power-on-reset.

SSZ

SCLK

C3

C2

C1

C0 D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SIMO

SOMI

Hi-Z

Figure 22. Write 12 Bits DAC Data

SSZ

SCLK

SIMO

SOMI

A4

A3

A2

A1

A0

W

D7

D6

D5

D4

D3

D2

D1

D0

A6

A5

Hi-Z

Figure 23. Write 8 Bits Control Register

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ZHCSEF8 –DECEMBER 2015

Programming (continued)

8.5.1.3 Read Operation

DSP sends 8-bit header through SIMO, in order to perform Read operation. TPIC2010 will start to drive the

SOMI line upon the eighth falling edge of SCLK and shift out eight data bits. The master DSP inputs 8bits data

from SOMI after the ninth rising edge of SCLK. ꢀ There’s optional read mode that SOMI data is advanced a half

clock cycle of SCLK. This mode becomes effective by setting “ADVANCE_RD” (REG74) = H.

SSZ

SCLK

SIMO

SOMI

A6

A5

A4

A3

A2

A1

A0

R

D7

D6

D5

D4

D3

D2

D1

D0

Hi-Z

Figure 24. Read 8 Bits Control Register

8.5.1.4 Write and Read Operation

Optionally, the master DSP can read Status register during writing 12 bits DAC (Focus DAC) packet. It’s enabled

by setting bit “RDSTAT_ON_VFCS” (REG74) = H.

SSZ

SCLK

SIMO

C3

C2

C1

C0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SOMI

Hi-Z

Figure 25. Write 12 Bits Focus DAC Data + Read 8 Bits Status Data

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8.6 Register Maps

All registers are in WRITE-protect mode after XRESET release. “WRITE_ENA” bit (REG76) = H is required

before writing data in register.

8.6.1 Register State Transition

Version Data

(REG7E)

Device Power On

Initial Value

XMUTE = L

orA5V< 3.7 V

orCV3P3 < 2.7 V

orSIOV< 2.0 V

A5V< 2.0 V

orCV3P3 < 2.0 V

or RST_ ERR_ FLAG = 1

XMUTE = H

(@XRESET= H)

or DC-DCconverter < 80%

orP5V> 6.5 V(*1)

or RST_ REGS = 1

W RITE_ ENABLE = 0

or XSLEEP= 0

or RST_ REGS_ W O3 = 1

(keep LED, CSW, and XSLEEP *2)

or SIF_ TIMEOUT_ ERR = 1

RST_ REGS_ WO3= 1 (*2)

LED,CSW and XSLEEP

A5V< 3.7 V

orCV3P3 < 2.7 V

orSIOV< 2.0 V

(REG70[0], REG71[4,3])

or DC-DC converter < 80%

orP5V> 6.5 V(*1)

or XMUTE = L

or SIF_ TIMEOUT_ ERR = 1

or RST_ REGS = 1

VDAC Reg data

(REG01-09)

Control Reg data

(REG70,71,72,73,74,

76,77,7C,7F[7,6,0]

6D, 6E)

Error latched Reg data

(REG78,79,7A,7B,7F[5:1])

Initial (000)

Vxxx Write

RST_ INDAC = 1

or XXX_ ENA= 0

(error occur)

set Value

Set / State Value

(*1) When exceed 6.5 V, DCDC converter output

chaged Hi–Z and output falling < 80%.

Consequently force RESET event. (Released > 90%)

(*2) All register except CSW, LED and XSLEEP is initialized.

(1) When exceed 6.5 V, DC-DC converter output changed Hi-Z and output falling <80%.

(2) All register except CSW, LED, and XSLEEP is initialized.

Figure 26. Register State Transition Chart

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8.6.4 Detailed Description of Register

8.6.4.1 REG01 12-Bit DAC for Tilt

Figure 27. Tilt (REG01) 12-Bit DAC for Tilt (VDAC_MAPSW = 0)

15

14

13

12

11

10

9

8

VTLT

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VTLT

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. Tilt (REG01) Field Descriptions

Bit

Field

Type

Default

Description

11-0

VTLT

w-0

Digital input code for Tilt.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Output is changed by “differential Tilt mode (REG74[7])”

TLT_OUT = VTLT × (6.0 / 2048) (DIFF_TLT = 0)

TLT_OUT = (VFCS-VTLT) × (6.0 / 2048) (DIFF_TLT = 1)

TLT_OUT should be changed after writing VFCS.

In DIFF_TLT mode (DIFF_TLT = 1), TLT_OUT should be changed

after writing VFCS.

8.6.4.2 REG02 12-Bit DAC for Focus

Figure 28. Focus (REG02) 12-Bit DAC for Focus (VDAC_MAPSW = 0)

15

14

13

12

11

10

9

8

VFCS

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VFCS

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. Focus (REG02) Field Descriptions

Bit

Field

Type

Default

Description

11-0

VFCS

w-0

Digital input code for Focus

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Output is changed by “differential Tilt mode (REG74[7])”

FCS_OUT = VFCS × (6.0 / 2048) (DIFF_TLT = 0)

FCS_OUT = (VFCS – VTLT) × (6.0 / 2048) (DIFF_TLT = 1)

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8.6.4.3 REG03 12-Bit DAC for Tracking

Figure 29. Tracking (REG03) 12-Bit DAC for Tracking (VDAC_MAPSW = 0)

15

14

13

12

11

10

9

8

VTRK

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VTRK

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. Tracking (REG03) Field Descriptions

Bit

Field

Type

Default

Description

11-0

VTRK

w-0

Digital input code for Tracking.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

TRK_OUT = VTRK × (6.0 / 2048)

8.6.4.4 REG04 12-Bit DAC for Sled1

Figure 30. Sled1 (REG04) 10bit DAC for Sled1 (VDAC_MAPSW = 0)

15

14

13

12

11

10

9

8

VSLD1

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VSLD1

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. Sled1 (REG04) Field Descriptions

Bit

Field

Type

Default

Description

11-2

VSLD1

w-0

Digital input code for Sled1.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Two bits on LSB, VSLD1[1:0], will be handled with zero.

SLD1_OUT = VSLD1 × (440mA/2048)

8.6.4.5 REG05 12-Bit DAC for Sled2

Figure 31. Sled2 (REG05) 10bit DAC for Sled2 (VDAC_MAPSW = 0)

15

14

13

12

11

10

9

8

VSLD2

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VSLD2

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. Sled2 (REG05) Field Descriptions

Bit

Field

Type

Default

Description

11-2

VSLD2

w-0

Digital input code for Sled2.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Two bits on LSB, VSLD2[1:0], will be handled with zero.

SLD2_OUT = VSLD2 × (440mA/2048)

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8.6.4.6 REG06 12-Bit DAC for Stepping1

Figure 32. Stepping1 (REG06) 8bit DAC for Stepping1 (VDAC_MAPSW = 0)

15

14

13

12

11

10

9

8

VSTP1

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VSTP1

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. Stepping1 (REG06) Field Descriptions

Bit

Field

Type

Default

Description

11-4

VSTP1

w-0

Digital input code for Stepping1.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Four bits on LSB, VSTP1[3:0], will be handled with zero.

VSTP1_OUT = VSTP1 × (5.0/2048) @P5V=5.0V

8.6.4.7 REG07 12-Bit DAC for Stepping2

Figure 33. Stepping2 (REG07) 8bit DAC for Stepping2 (VDAC_MAPSW = 0)

15

14

13

12

11

10

9

8

VSTP2

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VSTP2

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. Stepping2 (REG07) Field Descriptions

Bit

Field

Type

Default

Description

11-4

VSTP2

w-0

Digital input code for Stepping1.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

Four bits on LSB, VSTP2[3:0], will be handled with zero.

VSTP2_OUT = VSTP2 × (5.0/2048) @P5V=5.0V

8.6.4.8 REG08 12-Bit DAC for Spindle

Figure 34. Spindle (REG08) 12-Bit DAC for Spindle (VDAC_MAPSW = 0)

15

14

13

12

11

10

9

8

VSPM

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VSPM

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. Spindle (REG08) Field Descriptions

Bit

Field

Type

Default

Description

11-0

VSPM

w-0

Digital input code for Spindle.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

SPM_OUT = VSPM × (6.0 / 2048)

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8.6.4.9 REG09 12-Bit DAC for Load

Figure 35. Load (REG09) 12-Bit DAC for Load (VDAC_MAPSW = 0)

15

14

13

12

11

10

9

8

VLOAD

w-0

3

w-0

2

w-0

1

w-0

0

7

6

5

4

VLOAD

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. Load (REG09) Field Descriptions

Bit

Field

Type

Default

Description

11-0

VLOAD

w-0

Digital input code for Load.

2’s complement format 0x800(-2048) to 0x7ff(+2047)

LOAD_OUT = VLOAD × (6.0 / 2048)

8.6.4.10 REG63 8-Bit Control Register for SpinAdj

Figure 36. SpinAdj (REG63)

7

6

5

4

3

2

1

0

TI reserved

Mask_Plus

rw-0

TI reserved

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. SpinAdj (REG63) Field Descriptions

Bit

7-2

1

Field

Type

r-0

Default

Description

TI reserved

Mask_Plus

r-0

0

Mask Plus bit enables fly back robustness by optimizing masking time.

0: Default masking time

1: Extended masking time for large inductance motor

0

TI reserved

r-0

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ZHCSEF8 –DECEMBER 2015

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8.6.4.11 REG6C 8-Bit Control Register for EDetCfg

Figure 37. EDetCfg (REG6C)

7

6

5

4

3

2

1

0

TI reserved

STP_WIND_HI STP_WIND_H

Z

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. EDetCfg (REG6C) Field Descriptions

Bit

7-2

1

Field

Type

r-0

Default

Description

TI reserved

STP_WIND_HIZ

r-0

0

0: normal end detection

1: when detecting BEMF, set STP1 and STP2 FET HIZ to reduce

mutual noise.

0

STP_WIND_H

r-0

0

0: normal end detection

1: when detecting BEMF, set driving phase to Hi ( Detecting phase

put Hi-Z ) to reduce mutual noise.

8.6.4.12 REG6D 8-Bit Control Register for DCCfg

Figure 38. DCCfg (REG6D)

7

6

5

4

3

2

1

0

SWR1_MD_BU SWR2_MD_BU

SWR1_VOUTUP

TI reserved

SWR1_BST_H

EFF

TI reserved

RST

rw-0

rw-0 rw-0

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. DCCfg (REG6D) Field Descriptions

Bit

Field

Type

Default

Description

7

SWR1_MD_BURST

rw-0

0

0: V1Px normal regulation

1: V1Px discontinuous mode

6

SWR2_MD_BURST

SWR1_VOUTUP

rw-0

0

0: V3P3 normal regulation

1: V3P3 discontinuous mode

5-4

V1Px DC-DC converter voltage up

For 1.2 V or 1.5 V:

00: 0%

01: 2%

10: 3.6%

11: 5.5%

For 1.0 V:

00: 0%

01: 1.3%

10: 2.4%

11: 3.3%

3

2

TI reserved

rw-0

SWR1_BST_HEFF

0

1: V1Px High efficiency mode on discontinuous mode

This bit will be enabled in SWR1_MD_BURST=1

1-0

TI reserved

rw-0

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ZHCSEF8 –DECEMBER 2015

8.6.4.13 REG6E 8-Bit Control Register for UtilCfg

Figure 39. UtilCfg (REG6E)

7

6

5

4

3

2

1

0

GPOUT_HL

GPOUT_ENA

SWROCP_SELCLK

TI reserved

SWR1_GPIO_ SWR2_GPIO_

CNTL

rw-0

rw-0 rw-0

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. UtilCfg (REG6E) Field Descriptions

Bit

Field

Type

Default

Description

7

GPOUT_HL

rw-0

0

GPOUT (general-purpose output) pin output selection

0: low output

1: high output

valid only REG6F = 00h

6

GPOUT_ENA

rw-0

0

Enable monitor signal output to GPOUT pin

0: No signal output, Hi-Z

1: output signal selected in REG6F with CMOS output

Output is Logical OR when selected two more signals

5-4

SWROCP_SELCLK

Over current protection monitoring frequency

5 counts by

00: 5 kHz (= exceed 1 ms)

01: 20 kHz

10: 50 kHz

11: 500 kHz

3-2

1

TI reserved

rw-0

SWR1_GPIO_CNTL

0

Set REG1PX pin as GPIO1 pin.

0: REG1PX pin as 1.xV DC-DC converter output

1: Open drain control for GPOUT1 pin (at V1Px DC-DC disable)

0

SWR2_GPIO_CNTL

rw-0

Set REG3P3 pin as GPIO2 pin.

0: REG3P3 pin as 3.3V DC-DC converter output

1: Open drain control for GPOUT1 pin (at V1Px DC-DC disable)

Open drain control for GPOUT2 pin (at V3P3 DC-DC disable)

8.6.4.14 REG6F 8-Bit Control Register for MonitorSet

Figure 40. MonitorSet (REG6F)

7

6

5

4

3

2

1

0

ACTTIMER_FL ENDDET_MON SIF_TIMEOUT PWRERR_MO TSDERR_MON OCPERR_MO TSDFAULT_M

TI reserved

T_MON

ERR_MON

N

ON

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. MonitorSet (REG6F) Field Descriptions

Bit

7

Field

Type

rw-0

Default

Description

ACTTIMER_FLT_MON

ENDDET_MON

SIF_TIMEOUTERR_MON

PWRERR_MON

TSDERR_MON

OCPERR_MON

TSDFAULT_MON

0

1: ACTTIMER fault output to GPOUT pin

1: ENDDET monitor output to GPOUT pin

6

5

1: SIF timeout monitor output to GPOUT pin

1: PWRERR monitor output to GPOUT pin

1: TSDERR fault output to GPOUT pin

1: OCPERR fault output to GPOUT pin

1: TSDFAULT fault output to GPOUT pin

4

3

2

1

39

TPIC2010

ZHCSEF8 –DECEMBER 2015

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8.6.4.15 REG70 8bit Control Register for DriverEna

Figure 41. REG70 8bit Control Register

7

6

5

4

3

2

1

0

TLT_ENA

rw-0

FCS_ENA

rw-0

TRK_ENA

rw-0

SPM_ENA

rw-0

SLD_ENA

rw-0

STP_ENA

rw-0

LOAD_ENA

rw-0

XSLEEP

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. DriverEna (REG70) Field Descriptions

Bit

7

Field

Type

rw-0

Default

Description

TLT_ENA

FCS_ENA

TRK_ENA

SPM_ENA

SLD_ENA

STP_ENA

LOAD_ENA

1 : Tilt enable (with XSLEEP=1)

1: Focus enable (with XSLEEP=1)

1: Track enable (with XSLEEP=1)

1: Spindle enable (with XSLEEP=1)

1: Sled enable (with XSLEEP=1)

1: Step enable (with XSLEEP=1)

1 : LOAD enable (with XSLEEP=1)

6

5

4

3

2

1

Track (bit5:TRK_ENA) will be disabled at LOAD_ENA=1 because of

sharing the DAC PWM module. Load priority is higher than TRK_ENA.

0

XSLEEP

rw-0

1: Operation mode

0: Power save mode

Charge pump enable bit.

All driver enable bit (Bit[7:1]) change disabled and output change to

Hi-Z (regardless of setting xxx_ENA bit is 1 when setting XSLEEP to

0. Therefore set 1 to XSLEEP before setting each enable bits.

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TPIC2010

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ZHCSEF8 –DECEMBER 2015

8.6.4.16 REG71 8-Bit Control Register for FuncEna

Figure 42. REG71 8-Bit Control Register for FuncEna (REG71)

7

6

5

4

3

2

1

0

SPM_LSMODE ENDDET_ENA ENDDET_SLC

T

LED_ON

CSW_ON

TEMPMON_EN

A

TI reserved

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. FuncEna (REG71) Field Descriptions

Bit

Field

Type

Default

Description

7

SPM_LSMODE

rw-0

0 : Spindle Normal rotation mode

1 : Light Scribe mode (slow rotation mode)

6

5

ENDDET_ENA

ENDDET_SLCT

rw-0

1 : use sled/step End detection enable ( with STP_ENA=1 or

SLD_ENA=1)

0 : Sled End detection monitor

1 : Step End detection monitor

4

3

LED_ON

rw-0

1 : LEDO enable ( with XSLEEP=1)

1 : CSWO enable ( with XSLEEP=1)

1: enable chip temperature monitoring ( with XSLEEP=1)

Reserved

CSW_ON

2

TEMPMON_ENA

TI reserved

1-0

8.6.4.17 REG72 8-Bit Control Register for ACTCfg

Figure 43. ACTCfg (REG72)

7

6

5

4

3

2

1

0

LOAD_O5CH_ LOADPROT_O ACTPROT_OF

ACTTEMPTH

HIGH

FF

F

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. ACTCfg (REG72) Field Descriptions

Bit

Field

Type

Default

Description

7

LOAD_05CH_HIGH

rw-0

0

LOAD output polarity at 0.5CH ( REG74h[6]=1 )

0: LOADP=Low

1: LOADP=High

6

5

LOADPROT_OFF

ACTPROT_OFF

rw-0

0

1: Load Over Current Protection OFF

0 : Actuator protection ON

1 : Actuator Fault monitor disable (No protection for ACT channel)

4-0

ACTTEMPTH

rw-0

0

Actuator thermal protection (=ACT Timer) threshold level

ACT Timer Protection enable except ACTTEMPTH[4:0] = 0x00

ACTTEMPTH = 0x00 equal to ACTPROT_OFF = 1

By writing value 0x00, ACTTIMER_PROT flag is cleared.

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TPIC2010

ZHCSEF8 –DECEMBER 2015

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8.6.4.18 REG73 8-Bit Control Register for Parm0

Figure 44. Parm0 (REG73)

7

6

5

4

3

2

1

0

SIF_TIMEOUT_TH

SLEDEND_HZ

TIME

SLDENDTH

STPEND_HZTI

ME

STPENDTH

rw-0 rw-0

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. Parm0 (REG73) Field Descriptions

Bit

Field

Type

Default

Description

7-6

SIF_TIMEOUT_TH

rw-0

0

Watch dog timer for Serial communication

0: disable 1: 1 ms 2: 100 µs 3: 10 µs

Set SIF_TIMEOUTERR (REG7F) if communication is suspended for

this time period. XRESET processing will be performed if a

SIF_TIMEOUTERR occurs.

5

SLEDEND_HZTIME

SLDENDTH

rw-0

0

Time window for sled end detection.

0: 400 µs 1: 200 µs

Caution) Need to recycle ENDDET_ENA = 0 → 1 after writing this bit.

4-3

2

Sled end detection sensibility setting. Detection threshold for motor

BEMF

00: 46 mV 01: 86 mV 10: 0 mV 11: 22 mV

STPEND_HZTIME

STPENDTH

Step High-Z detection period in End detection

0: 400 µs 1: 200 µs

Caution) Need to recycle ENDDET_ENA = 0 → 1 after writing this bit.

1-0

Step end detection sensibility setting

00: 39 mV 01: 60 mV 10: 0 mV 11: 19 mV

42

TPIC2010

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ZHCSEF8 –DECEMBER 2015

8.6.4.19 REG74 8-Bit Control Register for SIFCfg

Figure 45. SIFCfg (REG74)

7

6

5

4

3

2

1

0

DIFF_TLT

LOAD_05CH

RDSTAT_ON_

VFCS

VSLD2_POL

VSTP2_POL

ADVANCE_RD

SOMI_HIZ

VDAC_MAPSW

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. SIFCfg (REG74) Field Descriptions

Bit

Field

Type

Default

Description

7

DIFF_TLT

rw-0

0

1 : Differential Tilt mode enable (with TLT_ENA=FCS_ENA=1)

Differential Tilt mode (DIFF_TLT=1), DAC value setting as follows

FCS_OUT=(VFCS+VTLT) × 6/2048

TLT_OUT=(VFCS-VTLT) × 6/2048

In DIFF_TLT mode (DIFF_TLT=1), TLT_OUT should be changed after

writing VFCS.

6

5

LOAD_05CH

rw-0

0

The setting of Load motor driving type. Load output changes as follow

0: 1ch mode (LOAD output is controlled by DAC code, VLOAD)

Use for Slot-in model or 1ch tray model.

1: 0.5Ch mode (LOAD is only controlled by LOAD_05CH_HIGH)

Use for Tray model

RDSTAT_ON_VFCS

Set Read status data (REG7F) at VFCS write command (REG02)

1: enable Write and Read mode

(Write 12bits Focus DAC data + Read 8bits status data)

4

3

2

VSLD2_POL

VSTP2_POL

ADVANCE_RD

rw-0

0

change direction of SLED rotation

change direction of STEP rotation

Advanced serial read timing

1: Read back timing changes half clock advance.

1

0

SOMI_HIZ

rw-0

0

0: SOMI line High-Z at bus idling time.

1: SOMI line Pull Down at bus idling time.

VDAC_MAPSW

1: change channel assignments of DAC register (REG01~09)

8.6.4.20 REG76 8-Bit Control Register for WriteEna

Figure 46. WriteEna (REG76)

7

6

5

4

3

2

1

0

WRITE_ENABL

E

TI reserved

REG6X_WR

rw-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. WriteEna (REG76) Field Descriptions

Bit

Field

Type

Default

Description

7

WRITE_ENABLE

rw-0

0

0: Register Write disable except REG76

1: Write enable for registers REG01~0B, REG70~7F

6-1

0

TI reserved

rw-0

REG6X_WR

0

0: Register REG63 write disable

1: Register REG63 write enable

43

TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

8.6.4.21 REG77 8-Bit Control Register for ClrReg

Figure 47. ClrReg (REG77)

7

6

5

4

3

2

1

0

RST_INDAC

RST_REGS

RST_ERR_FLA RST_REGS_W

TI reserved

G

O3

w-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. ClrReg (REG77) Field Descriptions

Bit

Field

Type

Default

Description

7

RST_INDAC

w-0

0

1 : Reset all 12bit input DAC register (REG01~0B)

*Self clear bit

6

5

4

RST_REGS

w-0

0

1 : Reset all 8bit R/W Registers (REG70h~77h, 60h-6Fh)

*Self clear bit

RST_ERR_FLAG

RST_REGS_WO3

1 : Reset Fault Flag Latch (REG7F[5:1], REG79~REG7B)

*Self clear bit

1 : Reset all 8bit R/W Registers w/o XSLEEP, CSW_ON, LED_ON

(REG70h~76h, REG60h~66h)

*Self clear bit

3-0

TI reserved

w-0

8.6.4.22 REG78 8-Bit Control Register for ActTemp

Figure 48. ActTemp (REG78)

7

6

5

4

3

2

1

0

TI reserved

ACT_TIMER_P

ROT

ACTTEMP

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. ActTemp (REG78) Field Descriptions

Bit

7-6

5

Field

Type

r-0

Default

Description

TI reserved

ACT_TIMER_PROT

r-0

0

ACT timer protection flag

1: ACT Timer Protection has detected and latched.

(ACTTEMP > ACTTEMPTH)

This bit holds data after temperature change to low since this is a

latch bit. Also driver output keep Hi-Z until setting RST_ERR_FLAG or

ACTTEMPTH = 0.

4-0

ACTTEMP

r-0

0

An integrated value of ACT_TIMER counters at present.

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TPIC2010

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ZHCSEF8 –DECEMBER 2015

8.6.4.23 REG79 8-Bit Control Register for UVLOMon

Figure 49. UVLOMon (REG79)

7

6

5

4

3

2

1

0

TI reserved

UVLO_A5V

UVLO_INT3P3 UVLO_SWR3P UVLO_SWR1P

OVP_P5V

3

X

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. UVLOMon (REG79) Field Descriptions

Bit

7-5

4

Field

Type

r-0

Default

Description

TI reserved

UVLO_A5V

UVLO_INT3P3

UVLO_SWR3P3

UVLO_SWR1PX

OVP_P5V

r-0

0

UVLO flag for detection Low A5V supply⁽¹⁾

UVLO flag for detection Low internal 3.3V regulator⁽¹⁾

3

r-0

(1)

2

r-0

UVLO flag for detection Low DC-DC 3.3V

(1)

1

r-0

UVLO flag for detection Low DC-DC 1.xV

(1)

0

r-0

Over voltage protection flag for P5Vsply

(1) Latched first reset event only. Cleared by “RST_ERR_FLG” (REG77)

8.6.4.24 REG7A 8-Bit Control Register for ThPMon

Figure 50. ThPMon (REG7A)

7

6

5

4

3

2

1

0

TSD_FAULT_S TSD_FAULT_S TSD_FAULT_A TSD_FAULT_L

TSD_SWR

TSD_SPM

TSD_ACT

TSD_

WR

PM

CT

EDCSW

LEDCSW

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. ThPMon (REG7A) Field Descriptions

Bit

7

Field

Type

r-0

Default

Description

TSD_FAULT_SWR

TSD_FAULT_SPM

TSD_FAULT_ACT

0

Pre alert of thermal protection for DC-DC converter block*.

Pre alert of thermal protection of Spindle block*

6

r-0

5

r-0

Pre alert of thermal protection of Focus /Track /Tilt Sled1 /Sled2

/Step1 /Step2 /Load *

4

3

TSD_FAULT_LEDCSW

TSD_SWR

r-0

0

Pre alert of thermal protection of CSW/LED *

Thermal protection flag for DC-DC converter block *

DC-DC converter output Hi-Z until temperature falls on release level

1: detect (latch)

2

1

TSD_SPM

TSD_ACT

r-0

0

Thermal protection flag for Spindle *

SPM output Hi-Z until temperature falls on release level

1: detect (latch)

Thermal protection flag for Focus /Track /Tilt Sled1 /Sled2 /Step1

/Step2 /Load *

Actuator output Hi-Z until temperature falls on release level

1: detect (latch)

0

TSD_ LEDCSW

r-0

0

Thermal protection flag for CSW/LED *

LED/CSW output Hi-Z until temperature falls on release level

1: detect (latch)

45

TPIC2010

ZHCSEF8 –DECEMBER 2015

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8.6.4.25 REG7B 8-Bit Control Register for OCPMon

Figure 51. OCPMon (REG7B)

7

6

TI reserved

r-0

5

4

OCP_SWR

r-0

3

OCP_STP

r-0

2

OCP_LOAD

r-0

1

OCP_LED

r-0

0

OCP_CSW

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. OCPMon (REG7B) Field Descriptions

Bit

7-5

4

Field

Type

r-0

Default

Description

TI reserved

OCP_SWR

OCP_STP

OCP_LOAD

OCP_LED

OCP_CSW

(1)

r-0

0

Over current protection flag bit for DC-DC converter block.

(1)

3

r-0

Over current protection flag bit for step block.

(1)

2

r-0

Over current protection flag bit for Load block.

(1)

1

r-0

Over current protection flag bit for LED block.

(1)

0

r-0

Over current protection flag bit for CSW block.

(1) Cleared by “RST_ERR_FLAG” bit (REG77)

8.6.4.26 REG7C 8-Bit Control Register for TempMon

Figure 52. TempMon (REG7C)

7

6

5

4

3

2

1

0

TI reserved

CHIPTEMP_ST

ATUS

CHIPTEMP

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 33. TempMon (REG7C) Field Descriptions

Bit

7

Field

Type

r-0

Default

Description

TI reserved

6

CHIPTEMP_STATUS

r-0

0

1: New data CHIPTEMP[5:0] is updated

It will be cleared after reading.

5-0

CHIPTEMP

r-0

Chip temperature monitor (2.5deg/LSB)

15(0) to 172.5(63) degrees.

For monitoring, TEMPMON_ENA=1 and XSLEEP=1 is required

8.6.4.27 REG7E 8-Bit Control Register for Version (REG7E)

Figure 53. Version (REG7E)

7

6

5

4

3

2

1

0

Version

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. Version (REG7E) Field Descriptions

Bit

Field

Type

Default

Description

7-0

Version

r-0

Version[7:4] = revision number of TPIC2010

Version[3:0]=option

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TPIC2010

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ZHCSEF8 –DECEMBER 2015

8.6.4.28 REG7F 8-Bit Control Register for Status (REG7F)

Figure 54. Status (REG7F)

7

6

5

4

3

2

1

0

ACTTIMER_FA

ULT

ENDDET

SIF_TIMEOUT

ERR

PWRERR

TSDERR

OCPERR

TSDFAULT

FG

r-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. Status (REG7F) Field Descriptions

Bit

Field

Type

Default

Description

7

ACTTIMER_FAULT

r-0

0

Status flag of ACTTIMER protection

1: Pre alert of ACTTIMER protection. It is close to the threshold level.

You can get current ACTTIMER value in REG78.

Both of this bit and ACT_TIMER_PROT (REG78) will be set when

over the threshold.

6

5

4

3

2

1

0

ENDDET

r-0

0

status flag of END detection

1: end position detected (not latch bit)

SIF_TIMEOUTERR

PWRERR

TSDERR

error flag of serial I/F watch dog timer

1: SIF communication was interrupted, expired watch dog timer

error flag of Power

1 : Voltage problem occurred, details in REG79

error flag of any over thermal protections

1: Dispatched thermal protection, details in REG7A

OCPERR

TSDFAULT

FG

error flag of any over current protection

1: Dispatched OCP, details in REG7Bh

warning of TSD of any thermal protection

1 : Detect pre thermal protection details in REG7A

FG signal. Spindle rotation pulse for speed monitor

47

TPIC2010

ZHCSEF8 –DECEMBER 2015

www.ti.com.cn

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

NOTE

•

Operate every driver channel after 5 V power supplied and stable.

To calculate spindle motor driver over current limit (I_Limit), use the following equation.

I_Limit= Internal REF voltage / RCS = 196 mV / 0.22 Ω ≈ 890 mA

•

Appropriate capacity of decoupling capacitor is required enough value of over 10 μF

due to reduce influence of PWM switching noise. And the A5V pin needs to connect a

filter of 1 μF. It is effective to put bypass capacitor (about 0.1 µF) near power pin

(P5V_1, P5V_2, P5V_SW, P5V_SPM1, P5V_SPM2) for PWM switching noise

reduction on power and GND line.

•

Much current flow to driver circuits, to consider as below matters.

–

Pattern-layout and line-impedance. And noise influence from supply line.

9.1 Application Information

9.1.1 DAC Type

TPIC2010 has nine channels of Actuator. Each channel is assigned to the most suitable DAC engine with a

different type respectively. ACT(F/T/Ti) has 12-bit DAC. Upper 8 (MSB sign bit) are converted at a time in 5MHz

and LSB 4 bits are output in sequence with 1.25-MHz PWM. SPIN, SLED and Load DAC has same DAC types

and sampling rate with 312kHz. All channel (except SLED and STP) have x6 gain. The DAC for STP is 8-bits

resolution output with 40 kHz PWM, no Feed Back. The Gain for STP is 5x relative to P5V voltage. Table 36

shows configuration of each actuator.

Table 36. List 5 DAC Type

FCS/TRK/TLT

12bit

SLED

10bit

SPIN

12bit

LOAD

12bit

STP

Resolution

Type

8bit

8-bit over sampling

1 bit Direct Duty

PWM

Sampling

1.25M / 10bit

312K / 12bit

1.25M / 10bit

312K / 12bit

312K

40 kHz

PWM freq

Out range

Feed back

312 kHz

±6 V

78 kHz

±440 mA

156 kHz

±6 V

312 kHz

±6 V

40 kHz

±(P5V*1)

Voltage feedback

Current feedback

Power supply

compensation

Voltage feedback

shared with TRK

Direct PWM no

feedback

9.1.2 Example Sampling Rate of 12-Bit DAC for FCS/TRK/TLT

The input data is separated in the upper 8 bits and the lower 4 bits. Upper 8 bits (MSB sign 1 bit) will be put into

8-bit current DAC in every 5 MHz. The lower 4 bits will be put into one bit current DAC in sequence from upper to

lower bit. This one bit DAC output with PWM in 1.25 MHz. At any PWM duty, 100%, 75%, 50%, 25%, or 0%, will

be summed in 8-bit current DAC in every 1.25 MHz. Thus it takes 3.2 µs for all lower 4 bits summing to PWM

output. As a result, 12-bit data is sampled in every PWM cycle. Example of sampling rate for FCS/TRK/TLT is

Figure 55.

48

TPIC2010

www.ti.com.cn

ZHCSEF8 –DECEMBER 2015

White DAC

8

5 MHz

1.25 MHz

625 kHz

312 kHz

10 bit

11 bit

12 bit

LSB 4-bit width

PWM duty

12-bit DAC (8-bit DAC + 4-bit PWM DAC) output

One PWM cycle (312 kHz = 3.2 µs)

Figure 55. Example of 12-Bit DAC Conversion Time (FCS/TRK/TLT)

9.1.3 Digital Input Coding

The output voltage (current) is commanded via programming to the DAC. All of the DAC input format is 12bit in

two’s complement though some DAC has a low resolution. When 12 bits data is input 8 bits DAC, TPIC2010

recognizes four subordinate position bits (LSB) as 0. To arrange for 12bit DAC format, DSP should shift 8bit or

10 bit data to an appropriate bit position. The full scale is +/-1.0 V and driver gain is set 6. The output voltage

(Vout) is given by the following equation:

6 .0

V o u t = D A C c o d e ì

2 0 4 8

(1)

V d a c = 1 .0 ì b it[1 0 ] ì 0 .5¹+ b it[9 ] ì 0 .5 ²+ b it[8 ] ì 0 .5 ³+ ... + b it[0 ] ì 0 .5^{1 1}

(

)

V d a c = (œ 1 .0 ) ì b it[1 0 ] ì 0 .5 ¹+ b it[9 ] ì 0 .5 ²+ b it[8 ] ì 0 .5 ³+ .. . + b it[0 ] ì 0 .5^{1 1}+ 0 .5^{1 2}

(

)

V o u t = V d a c ì 6 .0 ( V )

S T P V o u t = V d a c ì (P 5 V ) ( V )

S L E D Io u t = V d a c ì 0 .4 4 ( A )

where

•

bit[11:0] is the digital input value, range 000000000000b to 111111111111b.

(2)

Table 37. DAC Format

LSB

^MSBDIGITAL INPUT (BIN)

1000_0000_0000

1000_0000_0001

1111_1111_1111

0000_0000_0000

0000_0000_0001

0111_1111_1110

HEX

DEC

–2048

–2047

–1

VDAC

–0.9995

–0.0005

0

ANALOG OUTPUT

0x800

0x801

0xFFF

0x000

0x001

0x7FE

–5.997

–0.003

0.000

0

+1

+0.0005

+0.9990

+0.003

+5.994

+2046

49

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ZHCSEF8 –DECEMBER 2015

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Table 37. DAC Format (continued)

LSB

^MSBDIGITAL INPUT (BIN)

0111_1111_1111

HEX

DEC

VDAC

ANALOG OUTPUT

0x7FF

+2047

+0.9995

+5.997

Analog output(V)

VDAC

+ 6.0

+ 5.0

+ 1.000

*

800h

7FFh

DAC code

000

-5.0

-6.0

*

-1.000

*follow ing P5Vinput voltage

Figure 56. Output Voltage vs DAC Code

9.1.4 Example Timing of Target Control System

TPIC2010 is designed for that meets the requirements updating control data in 400 kHz. The example of control

system parameter is Table 38. It takes 0.51 µs for transmit a 16-bit data packet to TPIC2010 with 35-MHz SCLK.

Therefore, DSP can be sent four packets a 400-kHz interval. If SCLK is lower than 28.8 MHz, the system

designer must reduce the packet quantity under three. For example, Focus/Truck command is updating in every

2.5 µs (400 kHz), and it is able to send another two kind of packet in this same slot. Figure 57 shows the

example of the control timing when TPIC2010 is used.

Table 38. Example Timing of Target Control System

UPDATE CYCLE

SIGNAL

BIT

(kHz)

400

100

—

Focus

Track

Tilt

12

10

12

8

Sled1

Sled2

Spindle

Load

Step1

Step2

40

8

40

50

TPIC2010

www.ti.com.cn

ZHCSEF8 –DECEMBER 2015

312 kHz /3.2 µs (PW M 1 cycle)

Track

Focus

Tilt

R

Sled1

Sled2

SPM

Load

Step1

Step2

400 kHz /2.5 µs

Control

register

100 kHz /10 µs (1 control cycle)

PW M cycle

DAC command

R DAC command w/status read

Control register command

0.51 µs (SCLK: 35 MHz) for data transmit

Figure 57. Example DAC Control

9.1.5 Spindle Motor Driver Part

When VSPM is set a positive DAC code then it’ll be into acceleration mode. “IS” mode operates then the start-up

circuit offers the special start-up pattern sequence to the driver in start-up, and then switch to spin-up mode by

detecting the rotor position by BEMF signal from the spindle motor coil.

The spin-down and brake function also be controlled by DAC value VSPM. When it’s set the brake command to

VSPM, driver goes into active-brake mode, then switch to short-brake mode in slow revolution speed, and then

stop automatically. The FG signal is composed from EXOR of three-phase signal, and is output from XFG pin

shown below.

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Figure 58. Spindle Operating Sequence

It is recommended to use down-edge of FG signal for monitoring FG frequency. The FG terminal needs to be

•

pull up to the appropriate supply voltage by external resistor.

•

Short Brake mode is asserted after 300ms of FG signal stays L-level in deceleration.

The FG Output is set to H-level in Sleep Mode in order to reduce sleep mode current.

This value is the nominal number of using motor with 16-poles.

First of all, power supply voltage of A5V/P5V must be supplied before any signals input.

Internal circuit starts after 800 µs(TYP) since XMUTE changed to “H”. Recommended marginal delay value is

1ms for being ready.

9.1.5.1 Spindle PWM Control

The output PWM duty of Spindle is controlled by DAC code (VSPM). The gain in acceleration setting is always

six times. However, the maximum output is restricted to P5V voltage. A dead band which output = 0 exists in the

width of plus or minus 0x52 focusing on zero.

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PW M output duty

100%

output (V)

SPM_LSMODE = 0

P5V

25%

dead band

duty= 0%

slow down

speed up

0%

800h

FAEh

000

52h

7FFh

VSPM[11:0]

Figure 59. Spindle PWM Control

9.1.5.2 Auto Short Brake Function

TPIC2010 provides auto short brake function which is selecting brake mode automatically by motor speed. Auto

Short Brake is the intelligent brake function that includes two modes: short brake and active brake. When VSPM

value is controlled more than equivalent 75% duty brake, deceleration is done by short brake under the rotation

speed is over 3000 rpm. After deceleration, driver goes into Active-brake mode automatically by internal logic

circuit under rotation speed is lower 2000 rpm. This function enables low power consumption and silent during

braking.

Table 39. Brake Mode

ROTATION SPEED (RPM)

VSPM[11:0]

≈ 0 TO 2000

2-phase short brake

Active brake

≈ 3000

0x000 - 0xFAE

0xFAE - 0xA00

0xA00 - 0x800

2-phase short brake

Active brake

3-phase short brake

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rpm

brake

speed up

4000

3-phase

short

3000

2000

1000

0

active

2-phase

short

active

800h

A00h

FAEh

000

VSPM[11:0]

This value is the nominal number of using motor with 16-poles motor.

Figure 60. Brake Mode Selections

9.1.5.3 Spindle Low Speed Mode

LS mode is the low rotation mode which made the maximum 25% duty. When using SPM_LSMODE = 1, brake

mode is always short brake. Figure 61 shows the output duty of LS mode.

(V)

output

PWM output duty

100%

SPM_LSMODE = 1

6.0 V

5.0 V

25%

duty = 0%

speed up

0%

800h

000

7FFh

VSPM[11:0]

Figure 61. Spindle PWM Control (Low Speed Mode)

9.1.5.4 Spindle Driver Current Limiting Circuit

The current limit circuit monitors the RCS voltage at ICOM pin, and limits the output current by reducing PWM

duty, when detecting overcurrent conditions.

9.1.6 Sled Driver Part

The Sled driver outputs the PWM pulse set as DAC code (VSLDx) with current feed back. The maximum output

is restricted to 440 mA at 0x7FF and 0x800. A dead band which output = 0 exists in the width of plus or minus

0x33 focusing on zero.

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Figure 62. Sled Output Current

Both outputs of SLED1/2 are “H” when input code is in dead band.

•

9.1.6.1 End Detect Function

This device has the function of end position detection for Sled and Collimator lens. This function aim to eliminate

the position switch at PUH inner and collimator lens end position. This function is enabled by ENDDET_ENA = 1

with setting object actuator (ENDDET_SLCT = 0: for Sled ENDDET_SLCT = 1: for Step). When this function is

enabled, internal logic will detect the sled out zero-cross point and at that time, internal BEMF detect circuit

measures the BEMF level of stepping motor. There’re four threshold levels. If BEMF is lower than selected

threshold, device recognizes motor at stop and ENDDET bit to 1. ENDDET bit will be cleared at the BEMF

voltage exceed threshold again.

ENDDET_ ENA= 1, ENDDET_ SEL= 0

1

ENDDET

I SLEDx

Sled m otor

BEMF

dead end

Figure 63. Timing of Sled End Detection

•

For the purpose of getting correct stepping motor BEMF, we recommend to choose more than 110Hz

(440pps) control frequency. However this control frequency depends on the stepping motor characteristic.

BEMF detection level is selectable 22, 46, 86 mV.

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Figure 64. Timing of Step End Detection

Recommended control speed is around 1200 pps for getting correct BEMF level. It depends on the stepping

motor characteristic. Please evaluate on your condition adequately.

BEMF detection level is selectable 19, 39, 60 mV.

•

9.1.7 Load Driver Part

Load driver outputs the voltage with voltage feed back corresponding to the input DAC value. This channel has

power voltage compensation thus it is suit for Slot-in type load control. This channel becomes active exclusively

to other actuator channels. Load driver is shared with the TRK driver.

Figure 65. Load Output Duty

•

Output voltage is controlled by PWM

Both LOAD+ and LOAD- are connected to PGND through the internal clamp diode respectively.

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9.1.8 Focus/Track/Tilt Driver Part

9.1.8.1 Input vs Output Duty

PW M output duty

100%

P5V

reverse

forw ard

ACT+ < ACT-

ACT+ > ACT-

0%

800h

000

7FFh

ACT(FCS/TRK/TLT)[11:0]

Figure 66. FCS/TRK/TLT Output Duty

9.1.8.2 Differential Tilt Mode

TPIC2010 support differential Tilt mode which output the value calculated from Focus and Tilt. Focus and Tilt can

be set in differential mode by DIFF_TLT (REG74) = 1. Because Focus and Tilt are updated at the same time, the

update interval of Tilt can be thinned out. Output data changes at after writing VFCS data. Therefore it’s

necessary to write VFCS data when set VTLT. In differential mode, the output value is calculated as follows.

FCS_OUT = (VFCS + VTLT) × 6

TLT_OUT = (VFCS – VTLT) × 6

(3)

(4)

9.1.9 2-Channel Synchronous DC-DC Converter

TPIC2010 has two channels synchronous step-down DC-DC converters. Two converters operate with a 120-

degree turn-on phase shift of the PMOS (high side) transistors. It prevents the high side switches of both

regulators to be turned on simultaneously, and therefore smooth the input current. This feature reduces the surge

current drawn from the supply.

Switching frequency is 2.5 MHz. Because the ripple current in the coil can reduce, the smaller inductor value can

be selected. And the inductor with lowest DC resistance can be selected for highest efficiency. And the

regulators have fast transient response.

9.1.9.1 V1Px DC-DC Converter

The V1Px is a DC-DC converter producing an output 1.0, 1.2, 1.5 V. It only requires an external inductor and

bypass capacitor(s). The gate drivers and compensations are all internal to the chip. The required input supply is

5 V for P5V_SW. It has a soft start approximately about 0.8ms to limit the in-rush current when the regulator

comes alive. The soft-start circuit uses the internal clock to profile its ramp.

It is able to up 2%, 3.8% and 5.5% of the output voltage by setting SWR1_VOUTUP[2] (REG6D) for 1.2 V, 1.5 V.

For 1.0 V, up to 1.3%, 2.4% and 3.3%.

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9.1.9.2 V3P3 DC-DC Converter

V3P3 is a DC-DC converter producing an output of 3.3 V. It only requires an external inductor and bypass

capacitor(s). The gate drivers and compensations are all internal to the chip. The required input supply is 5 V. It

has a 0.8ms soft start to limit the in-rush current when the regulator comes alive. The soft-start circuit uses the

internal clock to profile its ramp.

9.1.9.3 Setup When Not Using DC-DC Converter

When not using DC-DC converter, it recommends that each terminal makes the following connection.

Table 40. Not Using DC-DC Converter

PIN NAME

SWR_SEQ1

SWR_SEQ2

V1PXSEL

FB1PX

PIN NO.

18

CONNECTION

5V (H)

OPEN

5V

19

20

25

P5V_SW

REG1PX

PGND_SW

REG3P3

26

27

OPEN

GND

28

29

OPEN

FB3P3

30

9.1.9.4 Discontinuous Regulation Mode

The regulation mode called discontinuous regulation mode improves the conversion efficiency at a low current

loading by changing regulation timing. Discontinuous mode is able to set 1 to SWx_MD_BURST (REG6D) bit.

Figure 67 shows the discontinuous regulation action. The current consumption has been reduced by shortening

the energizing time of driving FET. On the other hand, DC voltage ripple grows.

CLK2.5 MHz

• • • •

SWR1_MD_BURST

Discontinuous Mode

FB1PX

• • • •

REG1PX

Output Hi-Z term

• • • •

REG1PX

Output Hi-Z

Figure 67. Discontinuous Regulation Mode

9.1.10 Monitor Signal on GPOUT

The device can output a specific signal to the GPOUT pin. To output a signal, choose a signal from REG6F by

enabling first, then enable GPOUT_ENA. When two or more signals are set for GPOUT, the output is a logical

sum

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9.2 Typical Application

P5V

TPIC2010

P5V_2

1

2

3

4

5

6

7

8

9

LOAD+

LOAD-

STP1+

STP1-

STP2+

STP2-

CP3

56

55

SLED2-

SLED2+ 54

SLED1- 53

SLED1+

PGND_2

52

51

ISENSE 50

ICOM2 49

0.22 Ω

0.1 µF

CP2

W

P5V_SPM2

U

CP1

48

47

46

0.1 µF

SSZ

10 SSZ

U

V

SCLK

SIMO

11 SCLK

12 SIMO

ICOM1 45

SOMI

3.3V

XRESET

V

13 SOMI

44

14 SIOV

P5V_SPM1 43

M-COM 42

PGND_1 41

TRK- 40

MCOM

15 XRESET

16 XFG

XFG

XMUTE

17 XMUTE

18 SWR_SEQ1

19 SWR_SEQ2

TRK+ 39

FCS- 38

V1PXSEL

CV3P3

20

21

FCS+ 37

TLT- 36

0.1 µF

22 A5V

TLT+ 35

1 µF

23 AGND

P5V_1 34

LEDO 33

CSWI 32

CSWO 31

FB3P3 30

LEDO

XFG

GPOUT

24

GPOUT

25 FB1PX

26 P5V_SW

27 REG1PX

28 PGND_SW

XMUTE

10 µF

1.x V

output

3.3 V

output

REG3P3

29

10 µF

Figure 68. Typical Application Circuit

9.2.1 Design Requirements

To begin the design process, determine the following:

1. Motor configuration: The user can use all motor channels or some of them.

2. Power up devices with a 5-V supply.

9.2.2 Detailed Design Procedure

After power up on 5-V supply, the following values may be written to the following registers to enable motors.

1. Set WRITE_ENABLE = 1 on REG76 via SPI.

2. Set XSLEEP = 1 at REG70

3. Enable motor channel by ENA_XXX bits on REG70

4. Change the DAC settings for each motor in REG01-0B. Then, output channels will start driving load.

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Typical Application (continued)

Table 41. Recommended External Components

A5V

TO

AGND

FUNCTION

Noise decoupling

VALUE (RATE)

1.0 (10%16V)

10.0 (10%16V)

1.0 (10%16V)

1.5 (20% 1.2A)

10.0 (10%10V)

0.1 (10%10V)

0.22 (1% 1W)

10000(10% 16V)

1.5 (20% 1.2A)

10.0 (10% 10V)

0.1 (10% 25V)

UNIT

μF

µH

μF

Ω

P5V1

PGND

Noise decoupling

P5V2

PGND

Noise decoupling

P5V_SW

P5V_SPM

SIOV

PGND_SW

PGND

Noise decoupling

AGND

Noise decoupling

REG1PX

FB1PX

CV3P3

ISENSE

LOAD+

LOAD-

REG3P3

FB3P3

CP1

FB1PX

PGND_SW

AGND

Inductor (ESR = 0.1 Ω) for DC-DC converter

Capacitor (ESR = 0.025 Ω)

Noise decoupling for internal 3.3V

Spindle current sense resistor

Prevent surge current

PGND

pF

µH

μF

PGND

Prevent surge current

FB3P3

PGND_SW

CP2

Inductor (ESR = 0.1 Ω)

Capacitor (ESR = 0.025 Ω)

Charge pump capacitor

CP3

P5V

Charge pump capacitor (P5V only, prohibit

other power supply)

Table 42. Specific for DC-DC Converter Components

COMPONENTS

RECOMMENDED VALUE

1.5 (µH)

RECOMMENDED SUPPLIER

TAIYO YUDEN

PART NUMBER

Inductor

BRL2518T1R5M

Capacitor

10 (µF)

MURATA

GRM21BB31A106KE18L

Table 43. Restriction of Selection Parts

CSWO

VALUE

GROUNDS

Less than 4.7 µF

Since voltage will not rise within monitoring time if a big capacitance is connected on

CSWO, the protected operation operates and repeat On / Off .

9.2.3 Application Curves

120

100

80

60

40

20

0

120

100

80

60

TLT1-

LOAD-

40

20

0

TLT1+

LOAD+

-3000

-2000

-1000

0

1000

2000

3000

D003

-3000

-2000

-1000

0

1000

2000

3000

D004

DAC Code

Figure 69. DAC Code vs Duty Cycle for TLT Outputs

Figure 70. DAC Code vs Duty Cycle for LOAD Outputs

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10 Power Supply Recommendations

All driver channels should be operated after the required power is supplied and stable.

The appropriate capacity of the decoupling capacitor requires a value over 10 μF to reduce the influence of PWM

switching noise. The P5V1, P5V2,P5V_SW, and P5V_SPM pins must connect to 10-μF decoupling capacitors.

Current flow to the driver circuits takes both pattern-layout, line-impedance, and noise influence from the supply

line into consideration.

11 Layout

11.1 Layout Guidelines

1. CV3P3V requires an external capacitor. Because this is a reference voltage for device, locate the capacitor

as close to device as possible. Keep away from noise sources.

2. TI recommends SCLK ground shielding.

3. Place the inductors for the DC-DC converters as close to the chip as possible, and keep the feedback lines

to the FB3P3 and FB1PX pins as short as possible.

11.2 Layout Example

To MPU

GPOUT

To MPU

XFG

XMUTE

SSZ

GND Shield

SCLK

To MPU

GND Shield

SIMO

SOMI

SIOV

To MPU

To 3.3-V supply

1.x V output

Figure 71. Layout Recommendation

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12 器件和文档支持

12.1 器件支持

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 商标

E2E is a trademark of Texas Instruments.

蓝光碟 is a trademark of Blu-ray Disc Association.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

62

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型号：	TPIC2010RDFDRG4
厂家：	TEXAS INSTRUMENTS
描述：	具有 2 通道直流/直流的串行接口 9 通道控制电机驱动器 \| DFD \| 56 \| -20 to 75 电动机控制电机驱动光电二极管驱动器
文件：	总68页 (文件大小：1173K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPIC2010RDFDRG4 [TI]

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