TPA6211A1DGNR [TI]
3.1-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER; 3.1 W单声道全差分音频功率放大器
| 型号： | TPA6211A1DGNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.1-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER |
| 文件： | 总29页 (文件大小：1084K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA6211A1
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SLOS367B–AUGUST 2003–REVISED AUGUST 2004
3.1-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER
FEATURES
APPLICATIONS
•
Ideal for Wireless Handsets, PDAs, and
Notebook Computers
•
Designed for Wireless or Cellular Handsets
and PDAs
•
3.1 W Into 3Ω From a 5-V Supply at
THD = 10% (Typ)
DESCRIPTION
The TPA6211A1 is a 3.1-W mono fully-differential
amplifier designed to drive a speaker with at least
3-Ω impedance while consuming only 20 mm2 total
printed-circuit board (PCB) area in most applications.
The device operates from 2.5 V to 5.5 V, drawing
•
•
•
•
Low Supply Current: 4 mA Typ at 5 V
Shutdown Current: 0.01 µA Typ
Fast Startup With Minimal Pop
Only Three External Components
only
4 mA of quiescent supply current. The
– Improved PSRR (-80 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) for Direct Battery
Operation
TPA6211A1 is available in the space-saving
3-mm × 3-mm QFN (DRB) and the 8-pin MSOP
(DGN) PowerPAD™ packages.
– Fully Differential Design Reduces RF
Rectification
Features like -80 dB supply voltage rejection from
20 Hz to 2 kHz, improved RF rectification immunity,
small PCB area, and a fast startup with minimal pop
makes the TPA6211A1 ideal for PDA/smart phone
applications.
– -63 dB CMRR Eliminates Two Input
Coupling Capacitors
APPLICATION CIRCUIT
8-PIN QFN (DRB) PACKAGE
(TOP VIEW)
V
DD
6
1
2
3
4
8
7
6
5
To Battery
SHUTDOWN
BYPASS
IN+
V
O-
GND
C
s
40 kΩ
V
DD
R
R
I
4
3
-
IN-
_
+
V
5
8
O+
IN-
V
O+
In From
DAC
V
O-
I
+
IN+
DGN PACKAGE
(TOP VIEW)
40 kΩ
7
GND
1
2
SHUTDOWN
SHUTDOWN
BYPASS
IN+
V
1
2
3
4
8
7
6
5
Bias
Circuitry
O-
GND
V
DD
V
O+
100 kΩ
(1)
(BYPASS)
C
IN-
(1)
C
is optional.
(BYPASS)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
TPA6211A1
www.ti.com
SLOS367B–AUGUST 2003–REVISED AUGUST 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGED DEVICES(1)
TA
EVALUATION MODULES
SMALL OUTLINE
(DRB)
MSOP PowerPAD™
(DGN)
-40°C to 85°C
TPA6211A1DRB
TPA6211A1DGN
TPA6211A1EVM
(1) The DGN and DRB are available taped and reeled. To order taped and reeled parts, add the suffix R
to the part number (TPA6211A1DGNR or TPA6211A1DRBR).
Terminal Functions
TERMINAL
NAME DRB, DGN
I/O
DESCRIPTION
IN-
4
3
6
5
7
8
1
2
I
I
Negative differential input
Positive differential input
Power supply
IN+
VDD
VO+
GND
VO-
I
O
I
Positive BTL output
High-current ground
O
I
Negative BTL output
SHUTDOWN
BYPASS
Shutdown terminal (active low logic)
Mid-supply voltage, adding a bypass capacitor improves PSRR
Connect to ground. Thermal pad must be soldered down in all applications to properly secure
device on the PCB.
Thermal Pad
-
-
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
-0.3 V to 6 V
VDD
VI
Supply voltage
Input voltage
-0.3 V to VDD + 0.3 V
See Dissipation Rating Table
-40°C to 85°C
-40°C to 150°C
-65°C to 85°C
260°C
Continuous total power dissipation
Operating free-air temperature
Junction temperature
Storage temperature
TA
TJ
Tstg
DRB
DGN
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds
235°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS
T
A ≤ 25°C
DERATING
FACTOR(1)
TA= 70°C
POWER RATING
TA= 85°C
POWER RATING
PACKAGE
POWER RATING
DGN
DRB
2.13 W
17.1 mW/°C
21.8 mW/°C
1.36 W
1.7 W
1.11 W
1.4 W
2.7 W
(1) Derating factor based on high-k board layout.
2
TPA6211A1
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SLOS367B–AUGUST 2003–REVISED AUGUST 2004
RECOMMENDED OPERATION CONDITIONS
MIN
2.5
TYP
MAX UNIT
VDD
VIH
VIL
TA
Supply voltage
5.5
V
V
High-level input voltage
Low-level input voltage
Operating free-air temperature
SHUTDOWN
SHUTDOWN
1.55
0.5
85
V
-40
°C
ELECTRICAL CHARACTERISTICS
TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output offset voltage (measured
differentially)
VOS
VI = 0 V differential, Gain = 1 V/V, VDD = 5.5 V
-9
0.3
-85
9
mV
PSRR
VIC
Power supply rejection ratio
Common mode input range
VDD = 2.5 V to 5.5 V
VDD = 2.5 V to 5.5 V
-60
dB
V
0.5
VDD-0.8
-40
VDD = 5.5 V,
VDD = 2.5 V,
VIC = 0.5 V to 4.7 V
VIC = 0.5 V to 1.7 V
-63
-63
0.45
0.37
0.26
4.95
3.18
2.13
58
CMRR Common mode rejection ratio
dB
-40
VDD = 5.5 V
RL = 4 Ω,
Gain = 1 V/V,
Low-output swing
VIN+ = VDD
,
VIN- = 0 V or VDD = 3.6 V
V
VIN+ = 0 V,
VIN- = VDD
VDD = 2.5 V
0.4
VDD = 5.5 V
RL = 4 Ω,
Gain = 1 V/V,
High-output swing
VIN+ = VDD
,
VIN- = 0 V or VDD = 3.6 V
V
VIN- = VDD
VIN+ = 0 V
VDD = 2.5 V
2
| IIH
| IIL
IQ
|
High-level input current, shutdown
Low-level input current, shutdown
Quiescent current
VDD = 5.5 V,
VDD = 5.5 V,
VI = 5.8 V
VI = -0.3 V
100
100
5
µA
µA
|
3
VDD = 2.5 V to 5.5 V, no load
4
mA
V(SHUTDOWN) ≤ 0.5 V, VDD = 2.5 V to 5.5 V,
RL = 4Ω
I(SD)
Supply current
0.01
1
µA
38 kW
RI
40 kW
RI
42 kW
RI
Gain
RL = 4Ω
V/V
Resistance from shutdown to GND
100
kΩ
3
TPA6211A1
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SLOS367B–AUGUST 2003–REVISED AUGUST 2004
OPERATING CHARACTERISTICS
TA = 25°C, Gain = 1 V/V
PARAMETER
TEST CONDITIONS
MIN
TYP
2.45
MAX
UNIT
VDD = 5 V
THD + N= 1%, f = 1 kHz, RL = 3 Ω
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
1.22
0.49
2.22
1.1
PO
Output power
THD + N= 1%, f = 1 kHz, RL = 4 Ω
THD + N= 1%, f = 1 kHz, RL = 8 Ω
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
W
0.47
1.36
0.72
0.33
0.045%
0.05%
0.06%
0.03%
0.03%
0.04%
0.02%
0.02%
0.03%
-80
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
PO = 2 W
f = 1 kHz, RL = 3 Ω PO = 1 W
PO = 300 mW
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
PO = 1.8 W
Total harmonic distortion plus
noise
THD+N
f = 1 kHz, RL = 4 Ω PO = 0.7 W
PO = 300 mW
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
PO = 1 W
f = 1 kHz, RL = 8 Ω PO = 0.5 W
PO = 200 mW
VDD = 3.6 V
VDD = 2.5 V
f = 217 Hz
VDD = 3.6 V, Inputs ac-grounded with
Ci = 2 µF, V(RIPPLE) = 200 mVpp
kSVR
SNR
Vn
Supply ripple rejection ratio
Signal-to-noise ratio
dB
dB
f = 20 Hz to 20 kHz
-70
VDD = 5 V, PO = 2 W, RL = 4 Ω
105
No weighting
A weighting
f = 217 Hz
15
VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs ac-grounded with Ci = 2 µF
Output voltage noise
µVRMS
12
CMRR Common mode rejection ratio
VDD = 3.6 V, VIC = 1 Vpp
-65
dB
kΩ
µs
ZI
Input impedance
38
40
44
VDD = 3.6 V, No CBYPASS
4
Start-up time from shutdown
VDD = 3.6 V, CBYPASS = 0.1 µF
27
ms
4
TPA6211A1
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SLOS367B–AUGUST 2003–REVISED AUGUST 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Supply voltage
vs Load resistance
vs Output power
1
PO
PD
Output power
2
Power dissipation
3, 4
vs Output power
5, 6, 7
THD+N Total harmonic distortion + noise
vs Frequency
8-12
vs Common-mode input voltage
vs Frequency
13
KSVR
KSVR
Supply voltage rejection ratio
Supply voltage rejection ratio
GSM Power supply rejection
GSM Power supply rejection
14, 15, 16, 17
vs Common-mode input voltage
vs Time
18
19
20
21
22
23
24
25
26
27
vs Frequency
vs Frequency
CMRR Common-mode rejection ratio
vs Common-mode input voltage
vs Frequency
Closed loop gain/phase
Open loop gain/phase
vs Frequency
vs Supply voltage
vs Shutdown voltage
vs Bypass capacitor
IDD
Supply current
Start-up time
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
LOAD RESISTANCE
3.5
3.5
f = 1 kHz
Gain = 1 V/V
f = 1 kHz
Gain = 1 V/V
V
DD
= 5 V, THD 10%
P
O
= 3 Ω, THD 10%
3
3
V
DD
= 5 V, THD 1%
P
O
= 4 Ω, THD 10%
2.5
2.5
2
P
= 3 Ω, THD 1%
O
V
DD
= 3.6 V, THD 10%
P
O
= 4 Ω, THD 1%
2
P
O
= 8 Ω, THD 10%
V
DD
= 3.6 V, THD 1%
P
O
= 8 Ω, THD 1%
1.5
1.5
1
V
DD
= 2.5 V, THD 10%
V
DD
= 2.5 V, THD 1%
1
0.5
0
0.5
0
3
8
13
18
23
28
2.5
3
3.5
4
4.5
5
V
DD
- Supply Voltage - V
R
L
- Load Resistance - Ω
Figure 1.
Figure 2.
5
TPA6211A1
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SLOS367B–AUGUST 2003–REVISED AUGUST 2004
POWER DISSIPATION
vs
OUTPUT POWER
POWER DISSIPATION
vs
OUTPUT POWER
1.4
1.2
0.8
V
DD
= 3.6 V
4 Ω
V
DD
= 5 V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4 Ω
1
0.8
8 Ω
8 Ω
0.6
0.4
0.2
0
0
0.3
0.6
0.9
1.2
1.5
1.8
0
0.3
0.6
0.9
1.2
1.5
1.8
P
O
- Output Power - W
P
O
- Output Power - W
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
20
10
5
R
C
= 4 Ω
,
R
C
= 3 Ω
,
L
L
10
5
= 0 to 1 µF,
= 0 to 1 µF,
(BYPASS)
(BYPASS)
Gain = 1 V/V
Gain = 1 V/V
2
2
1
1
0.5
0.5
0.2
0.1
2.5 V
2.5 V
3.6 V
3.6 V
0.2
0.1
5 V
5 V
0.05
0.05
0.02
0.01
0.02
0.01
20m
50m 100m 200m 500m
1
2
3
10m 20m
50m 100m 200m 500m 1
2 3
P
O
- Output Power - W
P
O
- Output Power - W
Figure 5.
Figure 6.
6
TPA6211A1
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SLOS367B–AUGUST 2003–REVISED AUGUST 2004
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
FREQUENCY
20
10
5
V
DD
= 5 V,
R
C
= 8 Ω
,
L
10
5
R
C
= 3 Ω,
= 0 to 1 µF,
L
,
(BYPASS)
= 0 to 1 µF,
Gain = 1 V/V
(BYPASS)
Gain = 1 V/V,
C = 2 µF
2
1
I
2
1
0.5
1 W
2.5 V
0.5
0.2
0.1
3.6 V
0.2
0.1
2 W
5 V
0.05
0.05
0.02
0.01
0.02
0.01
0.005
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
10m 20m
50m 100m 200m 500m 1
2 3
P
O
- Output Power - W
Figure 7.
Figure 8.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY
FREQUENCY
10
5
10
V
R
C
= 3.6 V,
= 4 Ω,
,
V
R
C
= 5 V,
= 4 Ω,
,
DD
DD
L
5
2
L
= 0 to 1 µF,
= 0 to 1 µF,
(BYPASS)
(BYPASS)
2
1
Gain = 1 V/V,
C = 2 µF
Gain = 1 V/V,
C = 2 µF
1 W
I
I
1
0.5
2 W
0.1 W
0.5 W
0.5
0.2
0.1
1.8 W
1 W
0.2
0.1
0.05
0.02
0.01
0.05
0.005
0.02
0.01
0.002
0.001
0.005
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
20
50 100 200 500
1k 2k
5k 10k 20k
f - Frequency - Hz
Figure 9.
Figure 10.
7
TPA6211A1
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SLOS367B–AUGUST 2003–REVISED AUGUST 2004
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY
FREQUENCY
10
5
10
5
V
R
C
= 2.5 V,
V
R
C
= 3.6 V,
DD
DD
= 4 Ω,
= 8 Ω,
L
,
L
,
= 0 to 1 µF,
= 0 to 1 µF,
(BYPASS)
(BYPASS)
2
1
2
1
Gain = 1 V/V,
C = 2 µF
Gain = 1 V/V,
C = 2 µF
I
I
0.5
0.5
0.25 W
0.4 W
0.6 W
0.2
0.1
0.2
0.1
0.1 W
0.28 W
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
0.002
0.001
0.002
0.001
20 50 100 200
500 1k 2k
5k 10k 20k
20 50 100 200
500 1k 2k
5k 10k 20k
f - Frequency - Hz
f - Frequency - Hz
Figure 11.
Figure 12.
TOTAL HARMONIC DISTORTION + NOISE
SUPPLY VOLTAGE REJECTION RATIO
vs
vs
COMMON MODE INPUT VOLTAGE
FREQUENCY
0.06
0.058
0.056
0.054
0.052
0.05
+0
R
C
= 4 Ω,
,
L
f = 1 kHz
-10
= 0.47 µF,
(BYPASS)
P
R
= 200 mW,
= 1 kHz
O
Gain = 1 V/V,
L
-20
-30
-40
-50
-60
-70
-80
C = 2 µF,
I
Inputs ac Grounded
V
= 2.5 V
= 3.6 V
DD
V
DD
= 5 V
0.048
0.046
0.044
0.042
0.04
V
= 3.6 V
DD
V
DD
= 2.5 V
V
DD
-90
V
DD
= 5 V
-100
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
0
1
2
3
4
5
V
IC
- Common Mode Input Voltage - V
Figure 13.
Figure 14.
8
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SLOS367B–AUGUST 2003–REVISED AUGUST 2004
SUPPLY VOLTAGE REJECTION RATIO
SUPPLY RIPPLE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
+0
R
+0
= 4 Ω,
R
C
= 4 Ω,
L
,
L
,
-10
-10
C
= 0.47 µF,
= 0.47 µF,
(BYPASS)
(BYPASS)
Gain = 5 V/V,
C = 2 µF,
I
-20
-30
-40
-50
-60
-70
-80
-20
-30
-40
-50
-60
-70
-80
C = 2 µF,
V
DD
= 2.5 V to 5 V
I
Inputs ac Grounded
Inputs Floating
V
DD
= 3.6 V
V
DD
= 2.5 V
V
DD
= 5 V
-90
-90
-100
-100
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
Figure 15.
Figure 16.
SUPPLY VOLTAGE REJECTION RATIO
SUPPLY VOLTAGE REJECTION RATIO
vs
vs
FREQUENCY
DC COMMON MODE INPUT
+0
0
R
L
= 4 Ω,
,
R
= 4 Ω,
,
L
C = 2 µF,
Gain = 1 V/V,
−10
I
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
C = 2 µF,
I
Gain = 1 V/V,
−20
−30
−40
−50
−60
−70
−80
V
DD
= 3.6 V
C
= 0.47 µF
(BYPASS)
V
DD
= 3.6 V,
f = 217 Hz,
Inputs ac Grounded
V
DD
= 2.5 V
V
DD
= 3.6 V
C
= 0.1 µF
(BYPASS)
No C
(BYPASS)
V
DD
= 5 V
C
= 1 µF
(BYPASS)
−90
C
= 0.47 µF
(BYPASS)
−100
20
50 100 200 500 1k 2k
f − Frequency − Hz
5k 10k 20k
0
1
2
3
4
5
6
DC Common Mode Input − V
Figure 17.
Figure 18.
9
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GSM POWER SUPPLY REJECTION
vs
TIME
V
DD
C1
Frequency
217 Hz
C1 − Duty
20%
C1 Pk−Pk
500 mV
R = 8 Ω
L
C = 2.2 µF
I
V
OUT
C
= 0.47 µF
(BYPASS)
2 ms/div
Ch1 100 mV/div
Ch4 10 mV/div
t − Time − ms
Figure 19.
GSM POWER SUPPLY REJECTION
vs
FREQUENCY
0
−50
−100
−150
V
Shown in Figure 19,
DD
L
I
R
= 8 Ω,
−100
−120
C = 2.2 µF,
Inputs Grounded
−140
−160
−180
C
= 0.47 µF
(BYPASS)
0
400
800
1200
1600
2000
f − Frequency − Hz
Figure 20.
10
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COMMON MODE REJECTION RATIO
COMMON-MODE REJECTION RATIO
vs
COMMON-MODE INPUT VOLTAGE
vs
FREQUENCY
0
+0
R
L
= 4 Ω,
,
R
= 4 Ω,
,
L
-10
-20
-30
-40
-50
-60
-70
-80
V
= 200 mV V
,
IC
p-p
-10
Gain = 1 V/V,
dc Change in V
Gain = 1 V/V,
IC
-20
-30
-40
-50
-60
-70
V
DD
= 2.5 V
V
DD
= 2.5 V
V
DD
= 5 V
V
DD
= 3.5 V
V
DD
= 5 V
-80
-90
-90
-100
20
50 100 200 500 1k 2k
f - Frequency - Hz
5k 10k 20k
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
IC
- Common Mode Input Voltage - V
Figure 21.
Figure 22.
CLOSED LOOP GAIN/PHASE
OPEN LOOP GAIN/PHASE
vs
vs
FREQUENCY
FREQUENCY
40
30
20
10
0
100
180
150
180
150
120
90
V
R
= 5 V,
= 8 Ω
DD
Phase
90
80
70
60
L
120
90
60
60
Gain
Gain
50
40
30
20
10
-10
30
30
-20
-30
-40
0
0
-30
−30
−60
−90
-60
Phase
0
−10
−20
-50
-60
-70
-80
-90
V
R
A
V
= 5 V
= 8 Ω
= 1
-120
DD
−120
−150
−180
L
-150
-180
−30
−40
1
10
100
1 k 10 k 100 k 1 M 10 M
100
1 k
10 k
100 k
1 M
f - Frequency - Hz
f − Frequency − Hz
Figure 23.
Figure 24.
11
TPA6211A1
www.ti.com
SLOS367B–AUGUST 2003–REVISED AUGUST 2004
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SHUTDOWN VOLTAGE
5
10
1
V
DD
= 5 V
T
= 125°C
= 25°C
A
4.5
V
DD
= 5 V
4
V
DD
= 3.6 V
T
3.5
A
0.1
V
DD
= 2.5 V
3
2.5
2
T
= -40°C
A
0.01
0.001
1.5
1
0.0001
0.00001
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1
0
2
3
4
5
V
DD
- Supply Voltage - V
Voltage on SHUTDOWN Terminal - V
Figure 25.
Figure 26.
START-UP TIME
vs
BYPASS CAPACITOR
300
250
200
150
100
50
0
0
0.2
0.4
0.6
0.8
1
C
- Bypass Capacitor - µF
(Bypass)
Figure 27.
12
TPA6211A1
www.ti.com
SLOS367B–AUGUST 2003–REVISED AUGUST 2004
APPLICATION INFORMATION
•
Mid-supply bypass capacitor, C(BYPASS), not
required: The fully differential amplifier does not
require a bypass capacitor. Any shift in the
mid-supply voltage affects both positive and
negative channels equally, thus canceling at the
differential output. Removing the bypass capaci-
tor slightly worsens power supply rejection ratio
(kSVR), but a slight decrease of kSVR may be
acceptable when an additional component can be
eliminated (See Figure 17).
FULLY DIFFERENTIAL AMPLIFIER
The TPA6211A1 is a fully differential amplifier with
differential inputs and outputs. The fully differential
amplifier consists of a differential amplifier and a
common- mode amplifier. The differential amplifier
ensures that the amplifier outputs a differential volt-
age that is equal to the differential input times the
gain. The common-mode feedback ensures that the
common-mode voltage at the output is biased around
VDD/2 regardless of the common- mode voltage at the
input.
•
Better RF-immunity: GSM handsets save power
by turning on and shutting off the RF transmitter
at a rate of 217 Hz. The transmitted signal is
picked-up on input and output traces. The fully
differential amplifier cancels the signal much
better than the typical audio amplifier.
Advantages of Fully Differential Amplifiers
•
Input coupling capacitors not required: A fully
differential amplifier with good CMRR, like the
TPA6211A1, allows the inputs to be biased at
voltage other than mid-supply. For example, if a
DAC has a lower mid-supply voltage than that of
the TPA6211A1, the common-mode feedback
circuit compensates, and the outputs are still
biased at the mid-supply point of the TPA6211A1.
The inputs of the TPA6211A1 can be biased from
0.5 V to VDD - 0.8 V. If the inputs are biased
outside of that range, input coupling capacitors
are required.
APPLICATION SCHEMATICS
Figure 28 through Figure 31 show application sche-
matics for differential and single-ended inputs. Typical
values are shown in Table 1.
Table 1. Typical Component Values
COMPONENT
VALUE
40 kΩ
RI
(1)
C(BYPASS)
0.22 µF
1 µF
CS
CI
0.22 µF
(1) C(BYPASS) is optional.
V
DD
6
To Battery
C
s
40 kΩ
R
R
I
4
3
−
+
IN−
_
+
V
5
8
O+
In From
DAC
V
O−
I
IN+
40 kΩ
7
GND
1
SHUTDOWN
Bias
Circuitry
100 kΩ
(1)
(BYPASS)
C
2
(1)
C
is optional
(BYPASS)
Figure 28. Typical Differential Input Application Schematic
13
TPA6211A1
www.ti.com
SLOS367B–AUGUST 2003–REVISED AUGUST 2004
V
DD
6
To Battery
C
s
40 kΩ
C
C
I
R
R
I
IN−
4
3
−
+
_
+
V
5
8
O+
V
O−
I
IN+
I
40 kΩ
7
GND
1
2
SHUTDOWN
Bias
Circuitry
100 kΩ
(1)
(BYPASS)
C
(1)
C
is optional
(BYPASS)
Figure 29. Differential Input Application Schematic Optimized With Input Capacitors
V
DD
6
To Battery
C
s
40 kΩ
C
I
R
R
I
IN−
4
3
_
+
V
5
8
O+
IN
V
O−
I
IN+
C
I
40 kΩ
7
GND
1
2
SHUTDOWN
Bias
Circuitry
100 kΩ
(1)
(BYPASS)
C
(1)
C
is optional
(BYPASS)
Figure 30. Single-Ended Input Application Schematic
14
TPA6211A1
www.ti.com
SLOS367B–AUGUST 2003–REVISED AUGUST 2004
C
F
C
F
V
DD
6
To Battery
R
R
a
C
s
40 kΩ
−
+
C
C
I
R
R
I
IN−
4
3
_
V
5
8
O+
C
C
a
V
O−
I
IN+
+
a
I
40 kΩ
7
GND
a
1
SHUTDOWN
Bias
Circuitry
100 kΩ
(1)
C
(BYPASS)
2
(1)
C
is optional
(BYPASS)
Figure 31. Differential Input Application Schematic With Input Bandpass Filter
Input Capacitor (CI)
Selecting Components
The TPA6211A1 does not require input coupling
capacitors when driven by a differential input source
biased from 0.5 V to VDD - 0.8 V. Use 1% tolerance
or better gain-setting resistors if not using input
coupling capacitors.
Resistors (RI)
The input resistor (RI) can be selected to set the gain
of the amplifier according to equation 1.
Gain = RF/RI
(1)
In the single-ended input application, an input capaci-
tor, CI, is required to allow the amplifier to bias the
input signal to the proper dc level. In this case, CI and
RI form a high-pass filter with the corner frequency
defined in Equation 2.
The internal feedback resistors (RF) are trimmed to
40 kΩ.
Resistor matching is very important in fully differential
amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors.
CMRR, PSRR, and the cancellation of the second
harmonic distortion diminishes if resistor mismatch
occurs. Therefore, 1%-tolerance resistors or better
are recommended to optimize performance.
1
f
+
c
2pR C
I
I
(2)
-3 dB
Bypass Capacitor (CBYPASS) and Start-Up Time
The internal voltage divider at the BYPASS pin of this
device sets a mid-supply voltage for internal refer-
ences and sets the output common mode voltage to
VDD/2. Adding a capacitor filters any noise into this
pin, increasing kSVR. C(BYPASS)also determines the rise
time of VO+ and VO- when the device exits shutdown.
The larger the capacitor, the slower the rise time.
f
c
15
TPA6211A1
www.ti.com
SLOS367B–AUGUST 2003–REVISED AUGUST 2004
The value of CI is an important consideration. It
directly affects the bass (low frequency) performance
of the circuit. Consider the example where RI is 10
kΩ and the specification calls for a flat bass response
down to 100 Hz. Equation 2 is reconfigured as
Equation 3.
Substituting RI into equation 6.
1
f
+
c(HPF)
Therefore,
2p 10 kW C
I
(8)
(9)
1
C
+
1
I
2p 10 kW f
C
+
c(HPF)
I
2pR f
c
I
(3)
Substituting 100 Hz for fc(HPF) and solving for CI:
CI = 0.16 µF
In this example, CI is 0.16 µF, so the likely choice
ranges from 0.22 µF to 0.47 µF. Ceramic capacitors
are preferred because they are the best choice in
preventing leakage current. When polarized capaci-
tors are used, the positive side of the capacitor faces
the amplifier input in most applications. The input dc
level is held at VDD/2, typically higher than the source
dc level. It is important to confirm the capacitor
polarity in the application.
At this point, a first-order band-pass filter has been
created with the low-frequency cutoff set to 100 Hz
and the high-frequency cutoff set to 10 kHz.
The process can be taken a step further by creating a
second-order high-pass filter. This is accomplished by
placing a resistor (Ra) and capacitor (Ca) in the input
path. It is important to note that Ra must be at least
10 times smaller than RI; otherwise its value has a
noticeable effect on the gain, as Ra and RI are in
series.
Band-Pass Filter (Ra, Ca, and Ca)
It may be desirable to have signal filtering beyond the
one-pole high-pass filter formed by the combination of
CI and RI. A low-pass filter may be added by placing
a capacitor (CF) between the inputs and outputs,
forming a band-pass filter.
Step 3: Additional Low-Pass Filter
Ra must be at least 10x smaller than RI,
Set Ra = 1 kΩ
An example of when this technique might be used
would be in an application where the desirable
pass-band range is between 100 Hz and 10 kHz, with
a gain of 4 V/V. The following equations illustrate how
the proper values of CF and CI can be determined.
1
f
+
c(LPF)
Therefore,
2p R
C
a
a
(10)
(11)
1
C
+
a
2p 1kΩ f
Step 1: Low-Pass Filter
c(LPF)
1
f
+
c(LPF)
Substituting 10 kHz for fc(LPF) and solving for Ca:
Ca = 160 pF
2pR C
F F
where R is the internal 40 kW resistor
F
(4)
(5)
Figure 32 is a bode plot for the band-pass filter in the
previous example. Figure 31 shows how to configure
the TPA6211A1 as a band-pass filter.
1
f
+
c(LPF)
2p 40 kW C
F
Therefore,
AV
1
C
+
F
2p 40 kW f
12 dB
9 dB
c(LPF)
(6)
Substituting 10 kHz for fc(LPF) and solving for CF:
CF = 398 pF
−20 dB/dec
+20 dB/dec
−40 dB/dec
Step 2: High-Pass Filter
f
= 100 Hz
f
= 10 kHz
c(LPF)
c(HPF)
1
f
f
+
c(HPF)
2pR C
I I
Figure 32. Bode Plot
where R is the input resistor
I
(7)
Since the application in this case requires a gain of
4 V/V, RI must be set to 10 kΩ.
16
TPA6211A1
www.ti.com
SLOS367B–AUGUST 2003–REVISED AUGUST 2004
V
Decoupling Capacitor (CS)
O(PP)
V
+
(rms)
The TPA6211A1 is a high-performance CMOS audio
amplifier that requires adequate power supply de-
coupling to ensure the output total harmonic distortion
(THD) is as low as possible. Power-supply decoupling
also prevents oscillations for long lead lengths be-
tween the amplifier and the speaker. For higher
frequency transients, spikes, or digital hash on the
line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF to 1 µF, placed as
close as possible to the device VDD lead works best.
For filtering lower frequency noise signals, a 10-µF or
greater capacitor placed near the audio power ampli-
fier also helps, but is not required in most applications
because of the high PSRR of this device.
Ǹ
2 2
2
V
(rms)
Power +
R
L
(12)
V
DD
V
O(PP)
2x V
O(PP)
R
L
V
DD
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout
this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in
series with an ideal capacitor. The voltage drop
across this resistor minimizes the beneficial effects of
the capacitor in the circuit. The lower the equivalent
value of this resistance the more the real capacitor
behaves like an ideal capacitor.
-V
O(PP)
Figure 33. Differential Output Configuration
In a typical wireless handset operating at 3.6 V,
bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 200
mW to 800 mW. This is a 6-dB improvement in sound
power—loudness that can be heard. In addition to
increased power, there are frequency-response con-
cerns. Consider the single-supply SE configuration
shown in Figure 34. A coupling capacitor (CC) is
required to block the dc-offset voltage from the load.
This capacitor can be quite large (approximately 33
µF to 1000 µF) so it tends to be expensive, heavy,
occupy valuable PCB area, and have the additional
drawback of limiting low-frequency performance. This
frequency-limiting effect is due to the high-pass filter
network created with the speaker impedance and the
coupling capacitance. This is calculated with
Equation 13.
DIFFERENTIAL OUTPUT VERSUS
SINGLE-ENDED OUTPUT
Figure 33 shows a Class-AB audio power amplifier
(APA) in
a fully differential configuration. The
TPA6211A1 amplifier has differential outputs driving
both ends of the load. One of several potential
benefits to this configuration is power to the load. The
differential drive to the speaker means that as one
side is slewing up, the other side is slewing down,
and vice versa. This in effect doubles the voltage
swing on the load as compared to
a
ground-referenced load. Plugging 2 × VO(PP) into the
power equation, where voltage is squared, yields 4×
the output power from the same supply rail and load
impedance Equation 12.
1
f
+
c
2pR C
L C
(13)
For example, a 68-µF capacitor with an 8-Ω speaker
would attenuate low frequencies below 293 Hz. The
BTL configuration cancels the dc offsets, which elim-
inates the need for the blocking capacitors.
Low-frequency performance is then limited only by
the input network and speaker response. Cost and
PCB space are also minimized by eliminating the
bulky coupling capacitor.
17
TPA6211A1
www.ti.com
SLOS367B–AUGUST 2003–REVISED AUGUST 2004
An easy-to-use equation to calculate efficiency starts
out as being equal to the ratio of power from the
power supply to the power delivered to the load. To
accurately calculate the RMS and average values of
power in the load and in the amplifier, the current and
voltage waveform shapes must first be understood
(see Figure 35).
V
DD
V
O(PP)
C
C
R
L
V
O(PP)
V
O
-3 dB
V
(LRMS)
I
DD
f
c
I
DD(avg)
Figure 34. Single-Ended Output and Frequency
Response
Figure 35. Voltage and Current Waveforms for
BTL Amplifiers
Increasing power to the load does carry a penalty of
increased internal power dissipation. The increased
dissipation is understandable considering that the
BTL configuration produces 4× the output power of
the SE configuration.
Although the voltages and currents for SE and BTL
are sinusoidal in the load, currents from the supply
are different between SE and BTL configurations. In
an SE application the current waveform is
a
FULLY DIFFERENTIAL AMPLIFIER
half-wave rectified shape, whereas in BTL it is a
full-wave rectified waveform. This means RMS con-
version factors are different. Keep in mind that for
most of the waveform both the push and pull transis-
tors are not on at the same time, which supports the
fact that each amplifier in the BTL device only draws
current from the supply for half the waveform. The
following equations are the basis for calculating
amplifier efficiency.
EFFICIENCY AND THERMAL INFORMATION
Class-AB amplifiers are inefficient, primarily because
of voltage drop across the output-stage transistors.
The two components of this internal voltage drop are
the headroom or dc voltage drop that varies inversely
to output power, and the sinewave nature of the
output. The total voltage drop can be calculated by
subtracting the RMS value of the output voltage from
VDD. The internal voltage drop multiplied by the
average value of the supply current, IDD(avg), deter-
mines the internal power dissipation of the amplifier.
18
TPA6211A1
www.ti.com
SLOS367B–AUGUST 2003–REVISED AUGUST 2004
P
L
Efficiency of a BTL amplifier +
P
SUP
Where:
2
2
V rms
V
V
L
P
P
P
+
, andV
+
, therefore, P
+
L
LRMS
L
Ǹ
R
2R
2
L
L
p
2V
V
p
V
P
1
p
P
1
p
P
+
+ *
sin(t) dt
[cos(t)]
0
ŕ
P
+ V
I
avg
and
I
avg +
and
p R
SUP
DD DD
DD
R
R
L
L
0
L
Therefore,
2 V
V
DD
P
P
+
SUP
p R
L
substituting PL and PSUP into equation 6,
2
V
P
P = Power delivered to load
L
2 R
p V
P
V
= Power drawn from power supply
L
SUP
P
Efficiency of a BTL amplifier +
+
= RMS voltage on BTL load
LRMS
4 V
2 V
V
DD
DD
p R
P
R = Load resistance
L
V = Peak voltage on BTL load
P
DD
L
Where:
V
I
avg = Average current drawn from the power supply
V
= Power supply voltage
= Efficiency of a BTL amplifier
DD
+ Ǹ2 P R
L
η
P
L
BTL
(14)
(15)
Therefore,
p Ǹ2 P
R
L
L
h
+
BTL
4 V
DD
Table 2. Efficiency and Maximum Ambient Temperature vs Output Power
(1)
Output Power
(W)
Efficiency
(%)
Internal Dissipation
(W)
Power From Supply
(W)
Max Ambient Temperature
(°C)
5-V, 3-Ω Systems
0.5
1
27.2
38.4
60.2
67.7
1.34
1.60
1.62
1.48
1.84
2.60
4.07
4.58
85(2)
76
2.45
3.1
75
82
5-V, 4-Ω BTL Systems
0.5
1
31.4
44.4
62.8
74.3
1.09
1.25
1.18
0.97
1.59
2.25
3.18
3.77
85(2)
85(2)
85(2)
85(2)
2
2.8
5-V, 8-Ω Systems
0.5
1
44.4
62.8
73.3
81.9
0.625
0.592
0.496
0.375
1.13
1.60
1.86
2.08
85(2)
85(2)
85(2)
85(2)
1.36
1.7
(1) DRB package
(2) Package limited to 85°C ambient
19
TPA6211A1
www.ti.com
SLOS367B–AUGUST 2003–REVISED AUGUST 2004
Table 2 employs Equation 15 to calculate efficiencies
for four different output power levels. Note that the
efficiency of the amplifier is quite low for lower power
levels and rises sharply as power to the load is
increased resulting in a nearly flat internal power
dissipation over the normal operating range. Note that
the internal dissipation at full output power is less
than in the half power range. Calculating the ef-
ficiency for a specific system is the key to proper
power supply design. For a 2.8-W audio system with
4-Ω loads and a 5-V supply, the maximum draw on
the power supply is almost 3.8 W.
The maximum ambient temperature depends on the
heat sinking ability of the PCB system. The derating
factor for the 3 mm x 3 mm DRB package is shown in
the dissipation rating table. Converting this to θJA:
1
1
θ
+
+
+ 45.9°CńW
JA
0.0218
Derating Factor
(17)
Given θJA, the maximum allowable junction tempera-
ture, and the maximum internal dissipation, the maxi-
mum ambient temperature can be calculated with
Equation 18. The maximum recommended junction
temperature for the TPA6211A1 is 150°C.
A final point to remember about Class-AB amplifiers
is how to manipulate the terms in the efficiency
equation to the utmost advantage when possible.
Note that in Equation 15, VDD is in the denominator.
This indicates that as VDD goes down, efficiency goes
up.
T
Max
T Max
θ
P
A
J
JA Dmax
(
)
+ 150 * 45.9 1.27 + 91.7°C
(18)
Equation 18 shows that the maximum ambient tem-
perature is 91.7°C (package limited to 85°C ambient)
at maximum power dissipation with a 5-V supply.
A simple formula for calculating the maximum power
dissipated, PDmax, may be used for a differential
output application:
Table 2 shows that for most applications no airflow is
required to keep junction temperatures in the speci-
fied range. The TPA6211A1 is designed with thermal
protection that turns the device off when the junction
temperature surpasses 150°C to prevent damage to
the IC. In addition, using speakers with an impedance
higher than 4-Ω dramatically increases the thermal
performance by reducing the output current.
2
DD
2V
P
+
Dmax
2
p R
L
(16)
PDmax for a 5-V, 4-Ω system is 1.27 W.
20
TPA6211A1
www.ti.com
SLOS367B–AUGUST 2003–REVISED AUGUST 2004
PCB LAYOUT
Use the following land pattern for board layout with the 8-pin QFN (DRB) package. Note that the solder paste
should use a hatch pattern to fill solder paste at 50% to ensure that there is not too much solder paste under the
package.
0.7 mm
0.33 mm plugged vias (5 places)
1.4 mm
0.38 mm
0.65 mm
1.95 mm
Solder Mask: 1.4 mm x 1.85 mm centered in package
Make solder paste a hatch pattern to fill 50%
3.3 mm
Figure 36. TPA6211A1 8-Pin QFN (DRB) Board Layout (Top View)
21
PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPA6211A1DGN
ACTIVE
MSOP-
Power
PAD
DGN
8
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPA6211A1DGNG4
TPA6211A1DGNR
TPA6211A1DGNRG4
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPA6211A1DRB
TPA6211A1DRBG4
TPA6211A1DRBR
TPA6211A1DRBRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
SON
SON
DRB
DRB
DRB
DRB
8
8
8
8
121 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
121 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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