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TPA3251D2

ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

TPA3251D2 175W 立体声/350W 单声道 PurePath™ 超高清模拟输入 D

类放大器

1 特性

•

采用推荐的系统设计时，符合电磁干扰 (EMI) 标准

1

•

差分模拟输入

2 应用

总谐波失真+噪声 (THD+N) 为 10% 时的总输出功

率

•

蓝光碟磁盘™ /DVD 接收器

高端 HTiB 系统

AV 接收机

–

175W/4Ω，桥接负载 (BTL) 立体声配置

220W/3Ω，桥接负载 (BTL) 立体声配置

350W/2Ω，并行桥接负载 (PBTL) 单声道配置

高端条形音箱

微型 Combo 系统

有源扬声器和低音炮

•

THD+N 为 1% 时的总输出功率

–

140W/4Ω，BTL 立体声配置

175W/3Ω，BTL 立体声配置

285W/2Ω，PBTL 单声道配置

3 说明

TPA3251D2 是一款高性能 D 类功率放大器，它具有

D 类效率并且能够带来真正的高端音质。该器件特有

高级集成反馈设计和专有高速栅极驱动器错误校正功能

（PurePath™ 超高清）。该技术可使器件在整个音频

频带内保持超低失真，同时展现完美音质。该器件最

多可驱动 2 个 175W/4Ω 负载和 2 个 220W/3Ω 负载，

并且特有一个 2 VRMS 模拟输入接口，支持与高性能

DAC（例如，TI 的 PCM5242）的无缝连接。除了出

色的音频性能外，TPA3251D2 还兼具高功率效率和超

低功率级空闲损耗（1W 以下）两大优点。这可以利用

60mΩ MOSFET 以及优化型栅极驱动器方案来实现，

该方案相比传统的分立实现方案可显著降低空闲损耗。

采用高级集成反馈设计，具有高速栅极驱动器错误

校正功能

（PurePath™ 超高清）

–

高达 100kHz 的单宽带，用于高清 (HD) 源的高

频成分

超低 THD+N：1W/4Ω 时为 0.005%；削波时

<0.01%

60dB 电源抑制比 (PSRR)（BTL，无输入信

号）

–

<60µV（A 加权）输出噪声

>111dB（A 加权）信噪比 (SNR)

•

多种可能配置：

立体声、单声道、2.1 和 4xSE

–

器件信息⁽¹⁾

•

启动和停止时无喀哒声和噼啪声

90% 高效 D 类操作 (4Ω)

器件型号

封装

封装尺寸（标称值）

TPA3251D2

HTSSOP (44)

6.10mm x 14.00mm

12V 至 36V 宽电源电压工作范围

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

具有错误报告功能的自保护设计（包括欠压、过

压、削波和短路保护）

简化电路原理图

总谐波失真

10

TPA3251D2

LC

4:

RIGHT

Filter

TAS5630

Audio

Source

And Control

LEFT

1

0.1

LC

Filter

/CLIP_OTW

/RESET

/FAULT

12V

M1:M2

Operation Mode Select

Switching Frequency Select

Master/Slave Synchronization

Power Supply

36V

FREQ_ADJ

OSC_IO

0.01

110VAC->240VAC

T_C= 75qC

0.001

10m

100m

1

10

100 200

Po - Output Power - W

D000

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLASE40

TPA3251D2

ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

9.1 Overview ................................................................. 14

9.2 Functional Block Diagrams ..................................... 15

9.3 Feature Description................................................. 17

9.4 Device Protection System....................................... 17

10 Application and Implementation........................ 21

10.1 Application Information.......................................... 21

10.2 Typical Applications .............................................. 21

11 Power Supply Recommendations ..................... 27

11.1 Power Supplies ..................................................... 27

11.2 Powering Up.......................................................... 28

11.3 Powering Down..................................................... 29

12 Layout................................................................... 29

12.1 Layout Guidelines ................................................. 29

12.2 Layout Examples................................................... 30

13 器件和文档支持 ..................................................... 33

13.1 文档支持................................................................ 33

13.2 社区资源................................................................ 33

13.3 商标....................................................................... 33

13.4 静电放电警告......................................................... 33

13.5 Glossary................................................................ 33

14 机械、封装和可订购信息....................................... 33

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Audio Characteristics (BTL) ...................................... 8

7.7 Audio Characteristics (SE) ....................................... 9

7.8 Audio Characteristics (PBTL) ................................... 9

7.9 Typical Characteristics, BTL Configuration............. 10

7.10 Typical Characteristics, SE Configuration............. 12

7.11 Typical Characteristics, PBTL Configuration ........ 13

Parameter Measurement Information ................ 14

Detailed Description ............................................ 14

8

9

4 修订历史记录

Changes from Revision B (June 2015) to Revision C

Page

•

已从单页“产品预览”更改为完整数据表.................................................................................................................................... 1

Changes from Revision A (June 2015) to Revision B

Page

•

已将特性列表项“80dB 电源抑制比 (PSRR)（BTL，无输入信号）”更改为“60dB 电源抑制比 (PSRR)（BTL，无输入信

号）” ....................................................................................................................................................................................... 1

已将特性列表项“>112dB（A 加权）信噪比 (SNR)”更改为“>111dB（A 加权）信噪比 (SNR)”............................................... 1

Changes from Original (May 2015) to Revision A

Page

•

已更改特性列表中的THD+N 为 1% 时的总输出功率 .............................................................................................................. 1

已更改特性列表项“高级集成反馈设计...”................................................................................................................................. 1

已将特性列表项“<65µV（A 加权）输出噪声”更改为“<60µV（A 加权）输出噪声” ................................................................. 1

已更改特性列表中的“多种可能配置：”.................................................................................................................................... 1

已更改说明 ............................................................................................................................................................................. 1

已添加简化电路原理图 ........................................................................................................................................................... 1

2

TPA3251D2

www.ti.com.cn

ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

5 Device Comparison Table

DEVICE NAME

TAS5630B

DESCRIPTION

300-W Stereo Class-D PurePath™ HD Analog Input Audio Power Amplifier

150-W Stereo Class-D PurePath™ HD Analog Input Audio Power Amplifier

125-W Stereo Class-D PurePath™ HD Analog Input Audio Power Amplifier

TAS5613A

TAS5611A

6 Pin Configuration and Functions

The TPA3251D2 is available in a thermally enhanced TSSOP package.

The package type contains a heat slug that is located on the top side of the device for convenient thermal

coupling to the heat sink.

DDV Package

HTSSOP 44-Pin

(Top View)

GVDD_AB

VDD

BST_A

BST_B

GND

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

2

M1

3

M2

GND

4

INPUT_A

INPUT_B

OC_ADJ

FREQ_ADJ

OSC_IOM

OSC_IOP

DVDD

5

OUT_A

PVDD_AB

OUT_B

GND

6

7

8

9

10

11

12

13

14

15

16

17

18

19

GND

OUT_C

PVDD_CD

OUT_D

GND

AVDD

C_START

INPUT_C

INPUT_D

/RESET

/FAULT

VBG

GND

20

21

22

BST_C

/CLIP_OTW

GVDD_CD

BST_D

3

TPA3251D2

ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

Pin Functions

NAME

NO.

14

44

43

24

23

21

15

11

19

8

I/O

P

DESCRIPTION

AVDD

Internal voltage regulator, analog section

BST_A

BST_B

BST_C

BST_D

P

HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.

HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.

HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.

HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.

Clipping warning and Over-temperature warning; open drain; active low

Startup ramp, requires a charging capacitor to GND

P

CLIP_OTW

C_START

DVDD

O

P

Internal voltage regulator, digital section

FAULT

O

P

Shutdown signal, open drain; active low

FREQ_ADJ

Oscillator freqency programming pin

12, 13, 25, 26,

33, 34, 41, 42

GND

Ground

GVDD_AB

GVDD_CD

INPUT_A

INPUT_B

INPUT_C

INPUT_D

M1

1

P

I

Gate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND

Gate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND

Input signal for half bridge A

22

5

6

I

Input signal for half bridge B

16

I

Input signal for half bridge C

17

I

Input signal for half bridge D

3

I

Mode selection 1 (LSB)

M2

4

I

Mode selection 2 (MSB)

OC_ADJ

OSC_IOM

OSC_IOP

OUT_A

7

I/O

O

P

I

Over-Current threshold programming pin

Oscillator synchronization interface

Output, half bridge A

9

10

39, 40

35

OUT_B

Output, half bridge B

OUT_C

32

Output, half bridge C

OUT_D

27, 28

36, 37, 38

29, 30, 31

18

Output, half bridge D

PVDD_AB

PVDD_CD

RESET

PVDD supply for half-bridge A and B

PVDD supply for half-bridge C and D

Device reset Input; active low

VDD

2

P

Power supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling.

Internal voltage reference requires a 0.1-µF capacitor to GND for decoupling.

Ground, connect to grounded heat sink

VBG

20

PowerPad™

Table 1. Mode Selection Pins

MODE PINS

OUTPUT

CONFIGURATION

INPUT MODE

DESCRIPTION

M2

0

M1

0

2N + 1

2N/1N + 1

2N + 1

2 × BTL

1 x BTL + 2 x SE

1 x PBTL

Stereo BTL output configuration

0

1

2.1 BTL + SE mode

1

0

Parallelled BTL configuration. Connect INPUT_C and INPUT_D to GND.

Single ended output configuration

1

1N +1

4 x SE

4

TPA3251D2

www.ti.com.cn

ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

-0.3

MAX

50

UNIT

V

BST_X to GVDD_X⁽²⁾

VDD to GND

GVDD_X to GND⁽²⁾

13.2

50

V

Supply voltage

PVDD_X to GND⁽²⁾

V

DVDD to GND

4.2

8.5

4.2

50

V

AVDD to GND

V

VBG to GND

V

OUT_X to GND⁽²⁾

BST_X to GND⁽²⁾

–0.3

V

62.5

4.2

7

V

OC_ADJ, M1, M2, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START, to GND

RESET, FAULT, CLIP_OTW, CLIP to GND

INPUT_X to GND

V

Interface pins

V

Continuous sink current, RESET, FAULT, CLIP_OTW, CLIP, RESET to

GND

9

mA

T_J

Operating junction temperature range

Storage temperature range

0

150

°C

T_stg

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins

±2000

V

(1)

V_ESD

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

±500

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5

TPA3251D2

ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

PVDD_x

GVDD_x

Half-bridge supply

DC supply voltage

12

36

38

13.2

V

Supply for logic regulators and gate-drive

circuitry

10.8

12

V

VDD

Digital regulator supply voltage

10.8

2.7

1.5

1.6

5

12

4

R_L(BTL)

R_L(SE)

Output filter inductance within

recommended value range

Load impedance

3

Ω

R_L(PBTL)

L_OUT(BTL)

L_OUT(SE)

L_OUT(PBTL)

2

Output filter inductance

Minimum output inductance at I_OC

5

μH

kHz

kΩ

5

Nominal

575

475

430

9.9

19.8

29.7

600

500

450

10

625

525

PWM frame rate selectable for AM

interference avoidance; 1% Resistor

tolerance

F_PWM

AM1

AM2

470

Nominal; Master mode

AM1; Master mode

AM2; Master mode

10.1

20.2

30.3

R_{(FREQ_ADJ)}

PWM frame rate programming resistor

20

30

C_PVDD

R_OC

PVDD close decoupling capacitors

Over-current programming resistor

1.0

μF

kΩ

Resistor tolerance = 5%

22

47

30

64

R_OC(LATCHED)Over-current programming resistor

Voltage on FREQ_ADJ pin for slave

mode operation

V_{(FREQ_ADJ)}

Slave mode

3.3

V

T_J

Junction temperature

0

125

°C

7.4 Thermal Information

TPA3251D2

DDV 44-PINS HTSSOP

THERMAL METRIC⁽¹⁾

UNIT

FIXED 85°C

JEDEC STANDARD

4 LAYER PCB

HEATSINK

TEMPERATURE⁽²⁾

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

50.7

0.36

24.4

0.19

24.2

n/a

2.5⁽²⁾

R_θJC(top)

R_θJB

0.2

n/a

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

n/a

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) Thermal data are obtained with 85°C heat sink temperature using thermal compound with 0.7W/mK thermal conductivity and 2mil

thickness. In this model heat sink temperature is considered to be the ambient temperature and only path for dissipation is to the

heatsink.

6

TPA3251D2

www.ti.com.cn

ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

7.5 Electrical Characteristics

PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, T_C(Case temperature) = 75°C, f_S= 600 kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

Voltage regulator, only used as reference

DVDD

VDD = 12 V

3

3.3

7.8

3.6

V

node

Voltage regulator, only used as reference

node

AVDD

VDD = 12 V

Operating, 50% duty cycle

Idle, reset mode

40

13

25

3

I_VDD

VDD supply current

mA

50% duty cycle

I_{GVDD_X}

Gate-supply current per full-bridge

PVDD idle current per full bridge

Reset mode

50% duty cycle with recommended output filter

Reset mode, No switching

12.5

1

mA

I_{PVDD_X}

ANALOG INPUTS

R_IN

Input resistance

24

20

kΩ

V

V_IN

Maximum input voltage swing

Maximum input current

Inverting voltage Gain

7

1

I_IN

mA

dB

G

V_OUT/V_IN

OSCILLATOR

Nominal, Master Mode

AM1, Master Mode

3.45

2.85

2.58

1.86

3.6

3

3.75

3.15

2.82

f_OSC(IO+)

F_PWM× 6

MHz

AM2, Master Mode

2.7

V_IH

V_IL

High level input voltage

Low level input voltage

V

1.45

OUTPUT-STAGE MOSFETs

Drain-to-source resistance, low side (LS)

60

100

mΩ

T_J= 25°C, Includes metallization resistance,

GVDD = 12 V

R_DS(on)

Drain-to-source resistance, high side (HS)

I/O PROTECTION

Undervoltage protection limit, GVDD_x and

VDD

V_uvp,VDD,GVDD

9.5

V

(1)

V_{uvp,VDD, GVDD,hyst}

OTW

0.6

V

Overtemperature warning, CLIP_OTW⁽¹⁾

115

145

125

135

165

°C

Temperature drop needed below OTW

temperature for CLIP_OTW to be inactive

after OTW event.

(1)

OTW_hyst

25

°C

OTE⁽¹⁾

Overtemperature error

OTE-OTW differential

155

30

°C

OTE-OTW_{(differential)}

(1)

A reset needs to occur for FAULT to be

released following an OTE event

(1)

OTE_hyst

25

1.7

14

°C

ms

A

OLPC

I_OC

Overload protection counter

Overcurrent limit protection

f_PWM= 600 kHz

Resistor – programmable, nominal peak current in

1Ω load, R_OCP= 22 kΩ

Resistor – programmable, peak current in 1Ω load,

R_OCP= 47kΩ

I_OC(LATCHED)

I_DCspkr

Overcurrent limit protection

14

1.5

150

A

DC Speaker Protection Current Threshold

Overcurrent response time

BTL current imbalance threshold

Time from switching transition to flip-state induced

by overcurrent.

I_OCT

ns

Connected when RESET is active to provide

bootstrap charge. Not used in SE mode.

I_PD

Output pulldown current of each half

3

mA

(1) Specified by design.

7

TPA3251D2

ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

Electrical Characteristics (continued)

PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, T_C(Case temperature) = 75°C, f_S= 600 kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

STATIC DIGITAL SPECIFICATIONS

V_IH

V_IL

I_lkg

High level input voltage

Low level input voltage

Input leakage current

1.9

V

M1, M2, OSC_IOP, OSC_IOM, RESET

0.8

100

μA

OTW/SHUTDOWN (FAULT)

Internal pullup resistance, CLIP_OTW to

R_{INT_PU}

20

3

26

32

kΩ

DVDD, FAULT to DVDD

High level output voltage

Low level output voltage

CLIP_OTW, FAULT

V_OH

Internal pullup resistor

I_O= 4 mA

3.3

200

30

3.6

V

V_OL

500

mV

Device fanout

No external pullup

devices

7.6 Audio Characteristics (BTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 36 V,

GVDD_X = 12 V, R_L= 4 Ω, f_S= 600 kHz, R_OC= 22 kΩ, T_C= 75°C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, mode = 00,

AES17 + AUX-0025 measurement filters,unless otherwise noted.

PARAMETER

TEST CONDITIONS

R_L= 3 Ω, 10% THD+N

MIN

TYP MAX UNIT

220

R_L= 4 Ω, 10% THD+N

R_L= 3 Ω, 1% THD+N

R_L= 4 Ω, 1% THD+N

1 W

175

P_O

Power output per channel

W

175

140

THD+N Total harmonic distortion + noise

0.005%

A-weighted, AES17 filter, Input Capacitor

Grounded

V_n

Output integrated noise

60

μV

|V_OS

|

Output offset voltage

Signal-to-noise ratio⁽¹⁾

Inputs AC coupled to GND

20

111

115

1

60

mV

dB

W

SNR

DNR

P_idle

Dynamic range

Power dissipation due to Idle losses (I_{PVDD_X}

)

P_O= 0, 4 channels switching⁽²⁾

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses also are affected by core losses of output inductors.

8

TPA3251D2

www.ti.com.cn

ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

7.7 Audio Characteristics (SE)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 36 V,

GVDD_X = 12 V, R_L= 2 Ω, f_S= 600 kHz, R_OC= 22 kΩ, T_C= 75°C, Output Filter: L_DEM= 15 μH, C_DEM= 1 µF, MODE = 11,

AES17 + AUX-0025 measurement filters, unless otherwise noted.

PARAMETER

TEST CONDITIONS

R_L= 2 Ω, 10% THD+N

MIN

TYP MAX UNIT

84

60

R_L= 3 Ω, 10% THD+N

R_L= 4 Ω, 10% THD+N

R_L= 2 Ω, 1% THD+N

R_L= 3 Ω, 1% THD+N

R_L= 4 Ω, 1% THD+N

1 W

47

P_O

Power output per channel

W

67

48

37

THD+N Total harmonic distortion + noise

0.015%

A-weighted, AES17 filter, Input Capacitor

Grounded

V_n

Output integrated noise

115

μV

SNR

DNR

P_idle

Signal to noise ratio⁽¹⁾

A-weighted

100

101

0.5

dB

W

Dynamic range

A-weighted

P_O= 0, 4 channels switching⁽²⁾

Power dissipation due to idle losses (IPVDD_X)

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

7.8 Audio Characteristics (PBTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 36 V,

GVDD_X = 12 V, R_L= 2 Ω, f_S= 600 kHz, R_OC= 22 kΩ, T_C= 75°C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, MODE = 10,

AES17 + AUX-0025 measurement filters, unless otherwise noted.

PARAMETER

TEST CONDITIONS

R_L= 2 Ω, 10% THD+N

MIN

TYP MAX UNIT

355

250

R_L= 3 Ω, 10% THD+N

R_L= 4 Ω, 10% THD+N

R_L= 2 Ω, 1% THD+N

R_L= 3 Ω, 1% THD+N

R_L= 4 Ω, 1% THD+N

1 W

195

W

P_O

Power output per channel

285

200

155

THD+N Total harmonic distortion + noise

0.05%

A-weighted, AES17 filter, Input Capacitor

Grounded

V_n

Output integrated noise

62

μV

SNR

DNR

P_idle

Signal to noise ratio⁽¹⁾

A-weighted

111

1

dB

W

Dynamic range

A-weighted

P_O= 0, 4 channels switching⁽²⁾

Power dissipation due to idle losses (IPVDD_X)

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

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7.9 Typical Characteristics, BTL Configuration

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, R_L= 4 Ω, f_S= 600 kHz, R_OC= 22 kΩ,

T_C= 75°C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise

noted.

10

1

10

1

T_C= 75qC

1W

20W

75W

T_C= 75qC

1W

20W

75W

0.1

0.01

0.1

0.01

0.001

0.0003

0.001

20

100

1k

10k 20k

20

100

1k

10k

40k

f - Frequency - Hz

D001

D002

R_L= 4 Ω

P = 1W, 20W, 75W

T_C= 75°C

R_L= 4 Ω

P = 1W, 20W, 75W

T_C= 75°C

AUX-0025 filter, 80 kHz analyzer BW

Figure 1. Total Harmonic Distortion+Noise vs Frequency

Figure 2. Total Harmonic Distortion+Noise vs Frequency

260

10

3:

240

3:

4:

8:

4:

220

8:

200

180

160

140

120

100

80

1

0.1

60

0.01

40

THD+N = 10%

T_C= 75qC

20

T_C= 75qC

0

0.001

10

15

20

25

30

35

40

10m

100m

1

10

100 300

PVDD - Supply Voltage - V

Po - Output Power - W

D004

D003

R_L= 3 Ω, 4 Ω, 8 Ω

THD+N = 10%

T_C= 75°C

R_L= 3 Ω, 4 Ω, 8 Ω

T_C= 75°C

Figure 4. Output Power vs Supply Voltage

Figure 3. Total Harmonic Distortion + Noise vs Output

Power

220

100

10

1

3:

4:

8:

200

4:

8:

180

160

140

120

100

80

60

40

THD+N = 1%

T_C= 75qC

20

T_C= 75qC

0

10

15

20

25

30

35

40

10m

100m

1

10

100

500

PVDD - Supply Voltage - V

2 Channel Output Power - W

D005

D006

R_L= 3 Ω, 4 Ω, 8 Ω

THD+N = 1%

T_C= 75°C

R_L= 3 Ω, 4 Ω, 8 Ω

THD+N = 10%

T_C= 75°C

Figure 5. Output Power vs Supply Voltage

Figure 6. System Efficiency vs Output Power

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Typical Characteristics, BTL Configuration (continued)

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, R_L= 4 Ω, f_S= 600 kHz, R_OC= 22 kΩ,

T_C= 75°C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise

noted.

70

60

50

40

30

20

10

0

250

225

200

175

150

125

100

75

3:

4:

8:

50

3:

4:

8:

25

T_C= 75qC

400 450

THD+N = 10%

75 100

0

100

200

300

0

25

50

2 Channel Output Power - W

T_C- Case Temperature - qC

D007

D008

R_L= 3 Ω, 4 Ω, 8 Ω

THD+N = 10%

T_C= 75°C

R_L= 3 Ω, 4 Ω, 8 Ω

THD+N = 10%

T_C= 75°C

Figure 7. System Power Loss vs Output Power

Figure 8. Output Power vs Case Temperature

0

T_C= 75qC

4:

V

_ref= 25.46 V

-20

-40

FFT size = 16384

-60

-80

-100

-120

-140

-160

0

5k 10k 15k 20k 25k 30k 35k 40k 45k48k

f - Frequency - Hz

D01009

4 Ω, V_REF= 25.46 V (1% Output power)

FFT = 16384

T_C= 75°C

AUX-0025 filter, 80 kHz analyzer BW

Figure 9. Noise Amplitude vs Frequency

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7.10 Typical Characteristics, SE Configuration

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, R_L= 3 Ω, f_S= 600 kHz, R_OC= 22 kΩ,

T_C= 75°C, Output Filter: L_DEM= 15 μH, C_DEM= 680 nF, MODE = 11, AES17 + AUX-0025 measurement filters, unless

otherwise noted.

10

1

10

1

T_C= 75qC

1W

10W

30W

2:

3:

4:

0.1

0.01

T_C= 75qC

0.001

20

100

1k

10k 20k

10m

R_L= 2Ω, 3Ω, 4Ω

100m

1

10

100

f - Frequency - Hz

D011

Po - Output Power - W

D010

R_L= 3Ω

P = 1W, 10W, 30W

T_C= 75°C

Figure 11. Total Harmonic Distortion+Noise vs Frequency

Figure 10. Total Harmonic Distortion+Noise vs Output

Power

100

2:

3:

10

T_C= 75qC

1W

10W

30W

4:

80

1

0.1

60

40

20

0.01

THD+N = 10%

T_C= 75qC

0

10

15

20

25

30

35

40

0.001

PVDD - Supply Voltage - V

D013

20

100

1k

10k

40k

R_L= 2Ω, 3Ω, 4Ω

THD+N = 10%

T_C= 75°C

f - Frequency - Hz

D012

R_L= 3Ω

P = 1W, 10W, 30W

T_C= 75°C

AUX-0025 filter, 80 kHz analyzer BW

Figure 13. Output Power vs Supply Voltage

Figure 12. Total Harmonic Distortion+Noise vs Frequency

80

100

75

50

25

0

2:

3:

4:

60

40

20

2:

3:

4:

THD+N = 1%

T_C= 75qC

THD+N = 10%

75 100

0

10

15

20

25

30

35

40

0

25

50

PVDD - Supply Voltage - V

T_C- Case Temperature - qC

D014

D015

R_L= 2Ω, 3Ω, 4Ω

THD+N = 1%

T_C= 75°C

R_L= 2Ω, 3Ω, 4Ω

THD+N = 10%

T_C= 75°C

Figure 14. Output Power vs Supply Voltage

Figure 15. Output Power vs Case Temperature

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ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

7.11 Typical Characteristics, PBTL Configuration

All Measurements taken at audio frequency = 1kHz, PVDD_X = 36V, GVDD_X = 12V, R_L= 2Ω, f_S= 600 kHz, R_OC= 22kΩ, T_C

= 75°C, Output Filter: L_DEM= 10μH, C_DEM= 1 µF, MODE = 10, AES17 + AUX-0025 measurement filters, unless otherwise

noted.

10

1

10

1

T_C= 75qC

1W

50W

150W

2:

4:

8:

0.1

0.01

0.1

0.01

0.001

T_C= 75qC

0.001

0.0004

10m

100m

1

10

100

400

20

100

1k

10k 20k

Po - Output Power - W

f - Frequency - Hz

D016

D017

R_L= 2Ω, 4Ω, 8Ω

T_C= 75°C

R_L= 2Ω

P = 1W, 50W, 1.50W

T_C= 75°C

Figure 16. Total Harmonic Distortion+Noise vs Output

Power

Figure 17. Total Harmonic Distortion+Noise vs Frequency

400

10

2:

T_C= 75qC

1W

50W

150W

360

4:

8:

320

1

0.1

280

240

200

160

120

80

0.01

THD+N = 10%

T_C= 75qC

40

0

0.001

10

15

20

25

30

35

40

20

100

1k

10k

40k

PVDD - Supply Voltage - V

f - Frequency - Hz

D019

D018

R_L= 2Ω, 4Ω, 8Ω

THD+N = 10%

T_C= 75°C

R_L= 2Ω

P = 1W, 50W, 150W

T_C= 75°C

AUX-0025 filter, 80 kHz analyzer BW

Figure 19. Output Power vs Supply Voltage

Figure 18. Total Harmonic Distortion+Noise vs Frequency

350

400

375

350

325

300

275

250

225

200

175

150

125

100

75

2:

4:

300

8:

250

200

150

100

2:

4:

8:

50

THD+N = 1%

T_C= 75qC

25

0

THD+N = 10%

75 100

0

10

15

20

25

30

35

40

0

25

50

PVDD - Supply Voltage - V

T_C- Case Temperature - qC

D020

D021

R_L= 2Ω, 4Ω, 8Ω

THD+N = 1%

T_C= 75°C

R_L= 2Ω, 4Ω, 8Ω

THD+N = 10%

T_C= 75°C

Figure 20. Output Power vs Supply Voltage

Figure 21. Output Power vs Case Temperature

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8 Parameter Measurement Information

All parameters are measured according to the conditions described in the Recommended Operating Conditions,

Typical Characteristics, BTL Configuration, Typical Characteristics, SE Configuration and Typical Characteristics,

PBTL Configuration sections.

Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to

out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to

use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can

be used to reduce the out of band noise remaining on the amplifier outputs.

9 Detailed Description

9.1 Overview

To facilitate system design, the TPA3251D2 needs only a 12-V supply in addition to the (typical) 36-V power-

stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog

circuitry, AVDD and DVDD. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate

drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.

The audio signal path including gate drive and output stage is designed as identical, independent half-bridges.

For this reason, each half-bridge has separate bootstrap pins (BST_X). Power-stage supply pins (PVDD_X) and

gate drive supply pins (GVDD_X) are separate for each full bridge. Although supplied from the same 12-V

source, separating to GVDD_AB, GVDD_CD, and VDD on the printed-circuit board (PCB) by RC filters (see

application diagram for details) is recommended. These RC filters provide the recommended high-frequency

isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as

possible. In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to

the device pins must be kept as short as possible and with as little area as possible to minimize induction (see

reference board documentation for additional information).

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is

charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the

bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output

potential and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33-

nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient

energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully

turned on during the remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB

placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For

optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X node is

decoupled with 1-μF ceramic capacitor placed as close as possible to the supply pins. It is recommended to

follow the PCB layout of the TPA3251D2 reference design. For additional information on recommended power

supply and required components, see the application diagrams in this data sheet.

The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36-V power-

stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical

as facilitated by the internal power-on-reset circuit, but it is recommended to release RESET after the power

supply is settled for minimum turn on audible artefacts. Moreover, the TPA3251D2 is fully protected against

erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-

critical within the specified range (see the Recommended Operating Conditions table of this data sheet).

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9.2 Functional Block Diagrams

/CLIP_OTW

VDD

VBG

VREG

AVDD

DVDD

GND

POWER-UP

RESET

/FAULT

UVP

M1

M2

TEMP

SENSE

GVDD_A

GVDD_B

GVDD_C

GND

GVDD_D

/RESET

DIFFOC

CB3C

STARTUP

CONTROL

C_START

OVER-LOAD

PROTECTION

CURRENT

SENSE

OC_ADJ

OSC_IOM

OSC_IOP

PVDD_X

OUT_X

GND

OSCILLATOR

PPSC

FREQ_ADJ

GVDD_AB

BST_A

PWM

ACTIVITY

DETECTOR

PVDD_AB

OUT_A

GND

-

PWM

RECEIVER

TIMING

CONTROL

GATE-DRIVE

INPUT_A

ANALOG

+

LOOP FILTER

GVDD_AB

BST_B

PVDD_AB

OUT_B

GND

-

PWM

RECEIVER

TIMING

CONTROL

INPUT_B

ANALOG

CONTROL

+

LOOP FILTER

GVDD_CD

BST_C

PVDD_CD

OUT_C

GND

-

PWM

RECEIVER

TIMING

CONTROL

INPUT_C

ANALOG

+

LOOP FILTER

GVDD_CD

BST_D

PVDD_CD

OUT_D

GND

-

PWM

RECEIVER

TIMING

CONTROL

INPUT_D

ANALOG

+

LOOP FILTER

FunctionalBlockDiagram.vsd

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Functional Block Diagrams (continued)

Capacitor for

External

Filtering

&

System

microcontroller or

Analog circuitry

Startup/Stop

BST_A

BST_B

OSC_IOP

OSC_IOM

Oscillator

Synchronization

Bootstrap

Capacitors

2^ndOrder

L-C Output

Filter for

each

OUT_A

OUT_B

Output

H-Bridge 1

INPUT_A

Input DC

Blocking

Caps

ANALOG_IN_A

ANALOG_IN_B

Input

H-Bridge 1

INPUT_B

H-Bridge

2-CHANNEL

H-BRIDGE

BTL MODE

Hardwire PWM

Frame Adjust

& Master/Slave

Mode

FREQ_ADJ

2^ndOrder

L-C Output

Filter for

each

OUT_C

OUT_D

INPUT_C

INPUT_D

Input DC

Blocking

Caps

ANALOG_IN_C

ANALOG_IN_D

Input

H-Bridge 2

Output

H-Bridge 2

H-Bridge

BST_C

BST_D

M1

M2

Hardwire

Mode

Control

Bootstrap

Capacitors

GVDD, VDD,

DVDD &

AVDD

Power Supply

Decoupling

Hardwire

PVDD

GND

PVDD

Power Supply

Decoupling

36V

Over-

Current

Limit

SYSTEM

Power

Supplies

GND

12V

GVDD (12V)/VDD (12V)

VAC

*NOTE1: Logic AND in or outside microcontroller

Figure 22. System Block Diagram

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ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

9.3 Feature Description

9.3.1 Error Reporting

The FAULT, and CLIP_OTW, pins are active-low, open-drain outputs. The function is for protection-mode

signaling to a system-control device.

Any fault resulting in device shutdown is signaled by the FAULT pin going low. Also, CLIP_OTW goes low when

the device junction temperature exceeds 125°C (see Table 2).

Table 2. Error Reporting

FAULT

CLIP_OTW

DESCRIPTION

Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Junction

temperature higher than 125°C (overtemperature warning)

0

Overload (OLP) or undervoltage (UVP). Junction temperature higher than 125°C

(overtemperature warning)

0

1

0

1

Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C

Junction temperature higher than 125°C (overtemperature warning)

Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)

Note that asserting either RESET low forces the FAULT signal high, independent of faults being present. TI

recommends monitoring the CLIP_OTW signal using the system microcontroller and responding to an

overtemperature warning signal by, that is, turning down the volume to prevent further heating of the device

resulting in device shutdown (OTE).

To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and

CLIP_OTW outputs.

9.4 Device Protection System

The TPA3251D2 contains advanced protection circuitry carefully designed to facilitate system integration and

ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions

such as short circuits, overload, overtemperature, and undervoltage. The TPA3251D2 responds to a fault by

immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In

situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault

condition has been removed, that is, the supply voltage has increased.

The device will function on errors, as shown in Table 3.

Table 3. Device Protection

BTL

MODE

PBTL

MODE

SE

MODE

LOCAL

ERROR IN

LOCAL

ERROR IN

LOCAL

ERROR IN

TURNS OFF

A

B

C

D

A

B

C

D

A

B

C

D

A+B

C+D

A+B

C+D

A+B+C+D

Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching,

does not assert FAULT).

9.4.1 Overload and Short Circuit Current Protection

TPA3251D2 has fast reacting current sensors with a programmable trip threshold (OC threshold) on all high-side

and low-side FETs. To prevent output current to increase beyond the programmed threshold, TPA3251D2 has

the option of either limiting the output current for each switching cycle (Cycle By Cycle Current Control, CB3C) or

to perform an immediate shutdown of the output in case of excess output current (Latching Shutdown). CB3C

prevents premature shutdown due to high output current transients caused by high level music transients and a

drop of real speaker’s load impedance, and allows the output current to be limited to a maximum programmed

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level. If the maximum output current persists, i.e. the power stage being overloaded with too low load impedance,

the device will shut down the affected output channel and the affected output is put in a high-impedance (Hi- Z)

state until a RESET cycle is initiated. CB3C works individually for each half bridge output. If an over current

event is triggered, CB3C performs a state flip of the half bridge output that is cleared upon beginning of next

PWM frame.

PWM_X

RISING EDGE PWM

SETS CB3C LATCH

HS PWM

LS PWM

OC EVENT RESETS

CB3C LATCH

OC THRESHOLD

OUTPUT CURRENT

OCH

HS GATE-DRIVE

LS GATE-DRIVE

Figure 23. CB3C Timing Example

During CB3C an over load counter increments for each over current event and decrease for each non-over

current PWM cycle. This allows full amplitude transients into a low speaker impedance without a shutdown

protection action. In the event of a short circuit condition, the over current protection limits the output current by

the CB3C operation and eventually shut down the affected output if the overload counter reaches its maximum

value. If a latched OC operation is required such that the device shuts down the affected output immediately

upon first detected over current event, this protection mode should be selected. The over current threshold and

mode (CB3C or Latched OC) is programmed by the OC_ADJ resistor value. The OC_ADJ resistor needs to be

within its intentional value range for either CB3C operation or Latched OC operation.

I_OC

IOC_max

IOC_min

Not Defined

ROC_ADJ

Figure 24. OC Threshold versus OC_ADJ Resistor Value Example

OC_ADJ values outside specified value range for either CB3C or latched OC operation will result in minimum OC

threshold.

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ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

Table 4. Device Protection

OC_ADJ Resistor Value

Protection Mode

CB3C

OC Threshold

16.3A

22kΩ

24kΩ

27kΩ

30kΩ

47kΩ

51kΩ

56kΩ

64kΩ

CB3C

15.1A

CB3C

13.5A

CB3C

12.3A

Latched OC

16.3A

15.1A

13.5A

12.3A

9.4.2 DC Speaker Protection

The output DC protection scheme protects a connected speaker from excess DC current caused by a speaker

wire accidentally shorted to chassis ground. Such a short circuit results in a DC voltage of PVDD/2 across the

speaker, which potentially can result in destructive current levels. The output DC protection detects any

unbalance of the output and input current of a BTL output, and in the event of the unbalance exceeding a

programmed threshold, the overload counter increments until its maximum value and the affected output channel

is shut down. DC Speaker Protection is disabled in PBTL and SE mode operation.

9.4.3 Pin-to-Pin Short Circuit Protection (PPSC)

The PPSC detection system protects the device from permanent damage in the case that a power output pin

(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent

after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is

performed at startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system

startup does not activate the PPSC detection system. When PPSC detection is activated by a short on the

output, all half bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup

sequence and starts switching. The detection is controlled globally by a two step sequence. The first step

ensures that there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from

OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC

filter. The typical duration is < 15ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the

device will not react to changes applied to the RESET pin. If no shorts are present the PPSC detection passes,

and FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL

and PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC

detection system it is recommended not to insert a resistive load to GND_X or PVDD_X.

9.4.4 Overtemperature Protection OTW and OTE

TPA3251D2 has a two-level temperature-protection system that asserts an active-low warning signal

(CLIP_OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction

temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs

being set in the high-impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To

clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.

9.4.5 Undervoltage Protection (UVP) and Power-on Reset (POR)

The UVP and POR circuits of the TPA3251D2 fully protect the device in any power-up/down and brownout

situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are

fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.

Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on

any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)

state and FAULT being asserted low. The device automatically resumes operation when all supply voltages have

increased above the UVP threshold.

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9.4.6 Fault Handling

If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel

fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and

will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires

resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system

temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET

(RESET high) if the OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity of the

affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being

present. TI recommends monitoring the OTW signal using the system micro controller and responding to an over

temperature warning signal by, that is, turning down the volume to prevent further heating of the device resulting

in device shutdown (OTE).

Table 5. Error Reporting

Fault/Event

Description

Global or

Channel

Reporting

Method

Latched/Self

Clearing

Action needed

to Clear

Fault/Event

Output FETs

HI-Z

PVDD_X UVP

VDD UVP

Increase affected

supply voltage

Voltage Fault

Global

FAULT pin

Self Clearing

AVDD UVP

Allow DVDD to

rise

POR (DVDD UVP)

Power On Reset Global

FAULT pin

None

Self Clearing

HI-Z

Allow BST cap to

recharge (lowside HighSide off

ON, VDD 12V)

Channel (Half

Bridge)

BST_X UVP

Voltage Fault

Cool below OTW

threshold

OTW

OTE

Thermal Warning Global

OTW pin

Normal operation

Thermal

Global

FAULT pin

Latched

Toggle RESET

HI-Z

Shutdown

OLP (CB3C>1.7ms) OC Shutdown

Channel

Latched OC

(47kΩ<ROC_ADJ<68 OC Shutdown

kΩ)

FAULT pin

None

Latched

Toggle RESET

HI-Z

CB3C

Reduce signal

level or remove

short

Flip state, cycle

by cycle at fs/3

(22kΩ<ROC_ADJ<30 OC Limiting

kΩ)

Channel

Global

Self Clearing

No OSC_IO

activity in Slave

Mode

Resume OSC_IO

activity

Stuck at Fault⁽¹⁾

None

HI-Z

(1) Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical Characteristics

table of this data sheet.

9.4.7 Device Reset

Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down

is complete. Output pull downs are active both in SE mode and BTL mode with RESET low.

In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables

weak pulldown of the half-bridge outputs.

Asserting reset input low removes any fault information to be signaled on the FAULT output, that is, FAULT is

forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault.

To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of

FAULT.

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

TPA3251D2 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1

mixed 1x BTL + 2x SE mode depending on output power conditions and system design.

10.2 Typical Applications

10.2.1 Stereo BTL Application

3R3

+12V

470uF

100nF

33nF

1

2

3

4

5

6

7

8

9

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

GVDD_AB

VDD

BST_A

BST_B

GND

10µH

10nF

33nF

M1

1nF

1µF

M2

GND

3R3

10µF

INPUT_A

INPUT_B

INPUT_A

INPUT_B

OC_ADJ

FREQ_ADJ

OSC_IOM

OSC_IOP

DVDD

OUT_A

PVDD_AB

OUT_B

GND

3R3

22k

10nF

1µF

10µH

10k

470uF

PVDD

GND

10

11

12

13

14

15

16

17

18

19

1µF

TPA3251D2

GND

OUT_C

PVDD_CD

OUT_D

GND

1µF

AVDD

10µH

10nF

C_START

INPUT_C

INPUT_D

/RESET

/FAULT

VBG

1µF 470uF

10nF

10µF

INPUT_C

INPUT_D

/RESET

/FAULT

1nF

1µF

3R3

26

25

24

23

3R3

100nF

20

21

22

10nF

GND

33nF

10µH

/CLIP_OTW

GVDD_CD

BST_C

BST_D

3R3

100nF

33nF

Figure 25. Typical Differential Input BTL Application

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Typical Applications (continued)

10.2.1.1 Design Requirements

For this design example, use the parameters in Table 6.

Table 6. Design Requirements, BTL Application

DESIGN PARAMETER

Low Power (Pull-up) Supply

Mid Power Supply 12 V

High Power Supply

EXAMPLE

3.3 V

12 V

12 - 36 V

M2 = L

Mode Selection

M1 = L

INPUT_A = ±3.9 V (peak, max)

INPUT_B = ± 3.9V (peak, max)

INPUT_C = ±3.9 V (peak, max)

INPUT_D = ±3.9 V (peak, max)

Analog Inputs

Output Filters

Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)

Speaker Impedance

3-8 Ω

10.2.1.2 Detailed Design Procedures

A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.

The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio

volume decrease or intelligent power supply nominally operating at a low rail adjusting to a higher supply rail.

The device is inverting the audio signal from input to output.

The DVDD and AVDD pins are not recommended to be used as a voltage sources for external circuitry.

10.2.1.2.1 Decoupling Capacitor Recommendations

In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good

audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this

application.

The voltage of the decoupling capacitors should be selected in accordance with good design practices.

Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the

selection of the 1μF that is placed on the power supply to each full-bridge. It must withstand the voltage

overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple

current created by high power output. A minimum voltage rating of 50 V is required for use with a 36V power

supply.

10.2.1.2.2 PVDD Capacitor Recommendation

The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These

capacitors should be selected for proper voltage margin and adequate capacitance to support the power

requirements. In practice, with a well designed system power supply, 1000 μF, 50 V supports most applications.

The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed

switching.

10.2.1.2.3 PCB Material Recommendation

FR-4 Glass Epoxy material with 2 oz. (70 μm) copper is recommended for use with the TPA3251D2. The use of

this material can provide for higher power output, improved thermal performance, and better EMI margin (due to

lower PCB trace inductance.

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10.2.1.2.4 Oscillator

The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.

To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency

can be changed from nominal to lower values. These values should be chosen such that the nominal and the

lower value switching frequencies together results in the fewest cases of interference throughout the AM band.

The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in master

mode according to the description in the Recommended Operating Conditions table.

For slave mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to DVDD. This configures the

OSC_I/O pins as inputs to be slaved from an external differential clock. In a master/slave system inter channel

delay is automatically setup between the switching of the audio channels, which can be illustrated by no idle

channels switching at the same time. This will not influence the audio output, but only the switch timing to

minimize noise coupling between audio channels through the power supply to optimize audio performance and to

get better operating conditions for the power supply. The inter channel delay will be setup for a slave device

depending on the polarity of the OSC_I/O connection such that a slave mode 1 is selected by connecting the

master device OSC_I/O to the slave 1 device OSC_I/O with same polarity (+ to + and - to -), and slave mode 2 is

selected with the inverse polarity (+ to - and - to +).

10.2.2 Application Curves

Relevant performance plots for TPA3251D2 in BTL configuration are shown in Typical Characteristics, BTL

Configuration

Table 7. Relevant Performance Plots, BTL Configuration

PLOT TITLE

Total Harmonic Distortion+Noise vs Frequency

Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW

Total Harmonic Distortion + Noise vs Output Power

Output Power vs Supply Voltage, 10% THD+N

System Efficiency vs Output Power

FIGURE NUMBER

Figure 1

Figure 2

Figure 3

Figure 4

Figure 6

System Power Loss vs Output Power

Figure 7

Output Power vs Case Temperature

Figure 8

Noise Amplitude vs Frequency

Figure 9

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10.2.3 Typical Application, Single Ended (1N) SE

TPA3251D2 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1

mixed 1x BTL + 2x SE mode depending on output power conditions and system design.

470uF

15µH

3R3

+12V

470uF

100nF

33nF

1

2

3

4

5

6

7

8

9

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

10nF

GVDD_AB

VDD

BST_A

BST_B

GND

1nF

1µF

3R3

33nF

M1

M2

GND

3R3

10µF

INPUT_A

INPUT_B

INPUT_A

INPUT_B

OC_ADJ

FREQ_ADJ

OSC_IOM

OSC_IOP

DVDD

OUT_A

PVDD_AB

OUT_B

GND

10nF

22k

1µF

470uF

15µH

10k

470uF

PVDD

GND

10

11

12

13

14

15

16

17

18

19

1µF

TPA3251D2

GND

OUT_C

PVDD_CD

OUT_D

GND

1µF

AVDD

470uF

15µH

470nF

C_START

INPUT_C

INPUT_D

/RESET

/FAULT

VBG

1µF 470uF

10µF

INPUT_C

INPUT_D

/RESET

/FAULT

10nF

1nF

1µF

26

25

24

23

3R3

100nF

20

21

22

GND

33nF

3R3

/CLIP_OTW

GVDD_CD

BST_C

BST_D

10nF

3R3

100nF

33nF

470uF

15µH

Figure 26. Typical Single Ended (1N) SE Application

10.2.3.1 Design Requirements

Refer to Stereo BTL Application for the Design Requirements.

Table 8. Design Requirements, SE Application

DESIGN PARAMETER

Low Power (Pull-up) Supply

Mid Power Supply 1 2V

High Power Supply

EXAMPLE

3.3 V

12 V

12 - 36 V

M2 = H

M1 = H

Mode Selection

INPUT_A = ±3.9 V (peak, max)

INPUT_B = ±3.9 V (peak, max)

INPUT_C = ±3.9 V (peak, max)

INPUT_D = ±3.9 V (peak, max)

Analog Inputs

Output Filters

Inductor-Capacitor Low Pass FIlter (15 µH + 680 nF)

Speaker Impedance

2 - 8 Ω

10.2.3.2 Detailed Design Procedures

Refer to Stereo BTL Application for the Detailed Design Procedures.

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ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

10.2.3.3 Application Curves

Relevant performance plots for TPA3251D2 in PBTL configuration are shown in Typical Characteristics, SE

Configuration

Table 9. Relevant Performance Plots, SE Configuration

PLOT TITLE

FIGURE NUMBER

Figure 10

Total Harmonic Distortion+Noise vs Output Power

Total Harmonic Distortion+Noise vs Frequency

Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW

Output Power vs Supply Voltage, 10% THD+N

Output Power vs Supply Voltage, 1% THD+N

Output Power vs Case Temperature

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

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10.2.4 Typical Application, Differential (2N) PBTL

TPA3251D2 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1

mixed 1x BTL + 2x SE mode depending on output power conditions and system design.

3R3

+12V

470uF

100nF

33nF

1

2

3

4

5

6

7

8

9

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

GVDD_AB

VDD

BST_A

BST_B

GND

10µH

33nF

M1

M2

GND

10µF

INPUT_A

INPUT_B

INPUT_A

INPUT_B

OC_ADJ

FREQ_ADJ

OSC_IOM

OSC_IOP

DVDD

OUT_A

PVDD_AB

OUT_B

GND

22k

PVDD

1µF

10µH

10k

470uF

10nF

1nF

10

11

12

13

14

15

16

17

18

19

680nF

1µF

3R3

TPA3251D2

GND

3R3

GND

OUT_C

PVDD_CD

OUT_D

GND

10nF

1µF

AVDD

10µH

10nF

C_START

INPUT_C

INPUT_D

/RESET

/FAULT

VBG

1µF 470uF

GND

/RESET

/FAULT

26

25

24

23

100nF

20

21

22

GND

33nF

10µH

/CLIP_OTW

GVDD_CD

BST_C

BST_D

3R3

100nF

33nF

Figure 27. Typical Differential (2N) PBTL Application

10.2.4.1 Design Requirements

Refer to Stereo BTL Application for the Design Requirements.

Table 10. Design Requirements, PBTL Application

DESIGN PARAMETER

Low Power (Pull-up) Supply

Mid Power Supply 12 V

High Power Supply

EXAMPLE

3.3 V

12 V

12 - 36 V

M2 = H

M1 = L

Mode Selection

INPUT_A = ±3.9V (peak, max)

INPUT_B = ±3.9V (peak, max)

INPUT_C = Grounded

Analog Inputs

INPUT_D = Grounded

Output Filters

Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)

Speaker Impedance

2 - 4 Ω

10.2.4.2 Detailed Design Procedures

Refer to Stereo BTL Application for the Detailed Design Procedures.

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ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

10.2.4.3 Application Curves

Relevant performance plots for TPA3251D2 in PBTL configuration are shown in Typical Characteristics, PBTL

Configuration

Table 11. Relevant Performance Plots, PBTL Configuration

PLOT TITLE

FIGURE NUMBER

Figure 16

Total Harmonic Distortion+Noise vs Output Power

Total Harmonic Distortion+Noise vs Frequency

Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW

Output Power vs Supply Voltage, 10% THD+N

Output Power vs Supply Voltage, 1% THD+N

Output Power vs Case Temperature

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

11 Power Supply Recommendations

11.1 Power Supplies

The TPA3251D2 device requires two external power supplies for proper operation. A high-voltage supply called

PVDD is required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one

mid-voltage power supply for GVDD_X and VDD is required to power the gate-drive and other internal digital and

analog portions of the device. The allowable voltage range for both the PVDD and the GVDD_X/VDD supplies

are listed in the Recommended Operating Conditions table. Ensure both the PVDD and the GVDD_X/VDD

supplies can deliver more current than listed in the Electrical Characteristics table.

11.1.1 VDD Supply

The VDD supply required from the system is used to power several portions of the device. It provides power to

internal regulators DVDD and AVDD that are used to power digital and analog sections of the device,

respectively. Proper connection, routing, and decoupling techniques are highlighted in the TPA3251D2 device

EVM User's Guide SLVUAG8 (as well as the Application Information section and Layout Examples section) and

must be followed as closely as possible for proper operation and performance. Deviation from the guidance

offered in the TPA3251D2 device EVM User's Guide, which followed the same techniques as those shown in the

Application Information section, may result in reduced performance, errant functionality, or even damage to the

TPA3251D2 device. Some portions of the device also require a separate power supply which is a lower voltage

than the VDD supply. To simplify the power supply requirements for the system, the TPA3251D2 device includes

integrated low-dropout (LDO) linear regulators to create these supplies. These linear regulators are internally

connected to the VDD supply and their outputs are presented on AVDD and DVDD pins, providing a connection

point for an external bypass capacitors. It is important to note that the linear regulators integrated in the device

have only been designed to support the current requirements of the internal circuitry, and should not be used to

power any additional external circuitry. Additional loading on these pins could cause the voltage to sag and

increase noise injection, which negatively affects the performance and operation of the device.

11.1.2 GVDD_X Supply

The GVDD_X supply required from the system is used to power the gate-drives for the output H-bridges. Proper

connection, routing, and decoupling techniques are highlighted in the TPA3251D2 device EVM User's Guide

SLVUAG8 (as well as the Application Information section and Layout Examples section) and must be followed as

closely as possible for proper operation and performance. Deviation from the guidance offered in the

TPA3251D2 device EVM User's Guide, which followed the same techniques as those shown in the Application

Information section, may result in reduced performance, errant functionality, or even damage to the TPA3251D2

device.

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Power Supplies (continued)

11.1.3 PVDD Supply

The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which

provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are

highlighted in the TPA3251D2 device EVM User's Guide SLVUAG8 (as well as the Application Information

section and Layout Examples section) and must be followed as closely as possible for proper operation and

performance. Due the high-voltage switching of the output stage, it is particularly important to properly decouple

the output power stages in the manner described in the TPA3251D2 device EVM User's Guide SLVUAG8. The

lack of proper decoupling, like that shown in the EVM User's Guide, can results in voltage spikes which can

damage the device, or cause poor audio performance and device shutdown faults.

11.2 Powering Up

The TPA3251D2 does not require a power-up sequence, but it is recommended to hold RESET low minimum

400ms after PVDD supply voltage is turned ON. The outputs of the H-bridges remain in a high-impedance state

until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP)

voltage threshold (see the Electrical Characteristics table of this data sheet). This allows an internal circuit to

charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output as well as

initiating a controlled ramp up sequence of the output voltage.

PVDD

VDD

GVDD

DVDD

t

> 400ms

RESET delay

/RESET

AVDD

t

C 100µs

C 220ms

AVDD ramp

/FAULT

VIN_X

t

Precharge

OUT_X

VOUT_X

t

Startup ramp

Figure 28. Startup Timing

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Powering Up (continued)

When RESET is released to turn on TPA3251D2, FAULT signal will turn low and AVDD voltage regulator will be

enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the

Electrical Characteristics table of this data sheet). After a precharge time to stabilize the DC voltage across the

input AC coupling capacitors, before the ramp up sequence starts.

11.3 Powering Down

The TPA3251D2 does not require a power-down sequence. The device remains fully operational as long as the

gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage

threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a

good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks by

initiating a controlled ramp down sequence of the output voltage.

12 Layout

12.1 Layout Guidelines

•

Use an unbroken ground plane to have good low impedance and inductance return path to the power supply

for power and audio signals.

•

Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as

many of the ground pins as possible, since the ground pins are the best conductors of heat in the package.

•

PCB layout, audio performance and EMI are linked closely together.

Routing the audio input should be kept short and together with the accompanied audio source ground.

The small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins as possible.

A local ground area underneath the device is important to keep solid to minimize ground bounce.

Orient the passive component so that the narrow end of the passive component is facing the TPA3251D2

device, unless the area between two pads of a passive component is large enough to allow copper to flow in

between the two pads.

•

Avoid placing other heat producing components or structures near the TPA3251D2 device.

Avoid cutting off the flow of heat from the TPA3251D2 device to the surrounding ground areas with traces or

via strings, especially on output side of device.

Netlist for this printed circuit board is generated from the schematic in Figure 29.

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12.2 Layout Examples

12.2.1 BTL Application Printed Circuit Board Layout Example

T3

T1

1

2

44

43

42

41

40

39

38

37

3

4

5

6

7

8

T2

9

36

35

34

33

32

31

30

29

28

27

26

25

24

23

10

11

12

13

14

15

16

17

18

19

20

21

22

T1

T3

System Processor

Bottom to top layer connection via

Bottom Layer Signal Traces

Pad to top layer ground pour

Top Layer Signal Traces

A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer

copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)

B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat

sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without

going through vias. No vias or traces should be blocking the current path.

C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and

close to the pins.

D. Note T3: Heat sink needs to have a good connection to PCB ground.

Figure 29. BTL Application Printed Circuit Board - Composite

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Layout Examples (continued)

12.2.2 SE Application Printed Circuit Board Layout Example

T3

T1

1

2

44

43

42

41

40

39

38

37

3

4

5

6

7

8

T2

9

36

35

34

33

32

31

30

29

28

27

26

25

24

23

10

11

12

13

14

15

16

17

18

19

20

21

22

T1

T3

System Processor

Bottom to top layer connection via

Bottom Layer Signal Traces

Pad to top layer ground pour

Top Layer Signal Traces

A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer

copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)

B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat

sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without

going through vias. No vias or traces should be blocking the current path.

C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and

close to the pins.

D. Note T3: Heat sink needs to have a good connection to PCB ground.

Figure 30. SE Application Printed Circuit Board - Composite

31

TPA3251D2

ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

Layout Examples (continued)

12.2.3 PBTL Application Printed Circuit Board Layout Example

T3

T1

1

2

44

43

42

41

40

39

38

37

3

4

5

6

7

8

T2

9

36

35

34

33

32

31

30

29

28

27

26

25

24

23

10

11

12

13

14

15

16

17

18

19

20

21

22

Grounded for PBTL

T1

T3

System Processor

Bottom to top layer connection via

Bottom Layer Signal Traces

Pad to top layer ground pour

Top Layer Signal Traces

A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer

copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)

B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat

sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without

going through vias. No vias or traces should be blocking the current path.

C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and

close to the pins.

D. ote T3: Heat sink needs to have a good connection to PCB ground.

Figure 31. PBTL Application Printed Circuit Board - Composite

32

TPA3251D2

www.ti.com.cn

ZHCSDT9C –JUNE 2015–REVISED JUNE 2015

13 器件和文档支持

13.1 文档支持

《TPA3251D2EVM 用户指南》，SLVUAG8

13.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.3 商标

PurePath, E2E are trademarks of Texas Instruments.

蓝光碟磁盘 is a trademark of Blu-ray Disc Association.

All other trademarks are the property of their respective owners.

13.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

33

PACKAGE OUTLINE

DDV0044D

PowerPAD^TMTSSOP - 1.2 mm max height

S

C

A

L

E

1

.

2

5

0

PLASTIC SMALL OUTLINE

C

8.3

7.9

TYP

SEATING PLANE

PIN 1 ID

AREA

A

0.1 C

42X 0.635

44

1

2X (0.3)

NOTE 6

14.1

13.9

NOTE 3

2X

13.335

7.30

6.72

EXPOSED

THERMAL

PAD

(0.15) TYP

NOTE 6

2X (0.6)

NOTE 6

23

22

0.27

0.17

44X

4.43

3.85

0.08

C A B

6.2

6.0

B

(0.15) TYP

0.25

1.2

1.0

GAGE PLANE

SEE DETAIL A

0.75

0.50

0.15

0.05

0 - 8

DETAIL A

TYPICAL

4218830/A 08/2016

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. The exposed thermal pad is designed to be attached to an external heatsink.

6. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DDV0044D

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

SEE DETAILS

SYMM

44X (1.45)

44X (0.4)

1

44

42X (0.635)

SYMM

(R0.05) TYP

23

22

(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

0.05 MIN

AROUND

0.05 MAX

AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4218830/A 08/2016

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDV0044D

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

44X (1.45)

44X (0.4)

SYMM

1

44

42X (0.635)

SYMM

23

22

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE :6X

4218830/A 08/2016

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

10. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPA3251D2DDV
厂家：	TEXAS INSTRUMENTS
描述：	175W 立体声、350W 单声道、12V 至 38V 电源电压、模拟输入 D 类智能音频放大器 \| DDV \| 44 \| 0 to 70 放大器音频放大器
文件：	总43页 (文件大小：1258K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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