TMUX8212_V01 [TI]
TMUX821x 100-V, Flat Ron, 1:1 (SPST), 4-Channel Switches with Latch-Up Immunity and 1.8-V Logic;型号: | TMUX8212_V01 |
厂家: | TEXAS INSTRUMENTS |
描述: | TMUX821x 100-V, Flat Ron, 1:1 (SPST), 4-Channel Switches with Latch-Up Immunity and 1.8-V Logic |
文件: | 总32页 (文件大小:1266K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TMUX8212
SCDS434A – OCTOBER 2021 – REVISED DECEMBER 2021
TMUX821x 100-V, Flat Ron, 1:1 (SPST), 4-Channel Switches
with Latch-Up Immunity and 1.8-V Logic
1 Features
3 Description
•
High supply voltage capable:
The TMUX8211, TMUX8212, and TMUX8213 are
modern high voltage capable analog switches
with latch-up immunity. Each device has four
independently controllable 1:1, single-pole single-
throw (SPST) switch channels. The devices work well
with dual supplies, a single supply, or asymmetric
supplies up to a maximum supply voltage of 100 V.
The TMUX821x devices provide consistent analog
parametric performance across the entire supply
voltage range. The TMUX821x family supports
bidirectional analog and digital signals on the source
(Sx) and drain (Dx) pins.
– Dual supply: ±10 V to ±50 V
– Single supply: 10 V to 100 V
– Asymmetric dual supply operation
Consistent parametrics across supply voltages
Latch-up immune
High continuous current: 200 mA
Low crosstalk: –110 dB
Low input leakage: 10 pA
Low on-resistance flatness: 0.05 Ω
Low on-resistance: 5 Ω
Low capacitance: 12 pF
Removes need for additional logic rail (VL)
1.8-V Logic capable
Fail-safe logic: up to 48 V independent of supply
Integrated pull-down resistor on logic pins
Bidirectional signal path
•
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•
•
•
•
•
•
•
•
•
•
•
•
All logic inputs support logic levels of 1.8 V, 3.3 V, and
5 V and can be connected as high as 48 V, allowing
for system flexibility with control signal voltage. Fail-
safe logic circuitry allows voltages on the logic pins to
be applied before the supply pin, protecting the device
from potential damage.
Wide operating temperature TA: –40°C to 125°C
Industry-standard TSSOP and
smaller WQFN packages
The device family provides latch-up immunity,
preventing undesirable high current events between
parasitic structures within the device. A latch-up
condition typically continues until the power supply
rails are turned off and can lead to device failure.
The latch-up immunity feature allows this family of
multiplexers to be used in harsh environments.
2 Applications
•
•
•
•
•
•
•
•
•
•
High voltage bidirectional switching
Analog and digital signal switching
Semiconductor test equipment
LCD test equipment
Battery test equipment
Data acquisition systems (DAQ)
Digital multi-meter (DMM)
Factory automation and control
Programmable logic controllers (PLC)
Analog input modules
Device Information(1)
PART NUMBER
PACKAGE
TSSOP (16)
WQFN (16)(2)
BODY SIZE (NOM)
TMUX8211
TMUX8212
TMUX8213
5.00 mm × 4.40 mm
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Preview package.
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL1
SEL2
SEL3
SEL4
SEL4
TMUX8211
TMUX8212
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
TMUX8213
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX8212
www.ti.com
SCDS434A – OCTOBER 2021 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings: TMUX821x Devices...... 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions:
8.5 Charge Injection........................................................19
8.6 Off Isolation...............................................................19
8.7 Crosstalk...................................................................20
8.8 Bandwidth................................................................. 20
8.9 THD + Noise............................................................. 21
9 Detailed Description......................................................22
9.1 Overview...................................................................22
9.2 Functional Block Diagram.........................................22
9.3 Feature Description...................................................22
9.4 Device Functional Modes..........................................24
10 Application and Implementation................................25
10.1 Application Information........................................... 25
10.2 Typical Application.................................................. 25
11 Power Supply Recommendations..............................27
12 Layout...........................................................................28
12.1 Layout Guidelines................................................... 28
12.2 Layout Example...................................................... 28
13 Device and Documentation Support..........................29
13.1 Documentation Support.......................................... 29
13.2 Receiving Notification of Documentation Updates..29
13.3 Support Resources................................................. 29
13.4 Trademarks.............................................................29
13.5 Electrostatic Discharge Caution..............................29
13.6 Glossary..................................................................29
14 Mechanical, Packaging, and Orderable
TMUX821x Devices.......................................................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics (Global): TMUX821x
Devices..........................................................................6
7.6 Electrical Characteristics (±15-V Dual Supply)........... 6
7.7 Electrical Characteristics (±36-V Dual Supply)........... 7
7.8 Electrical Characteristics (±50-V Dual Supply)........... 8
7.9 Electrical Characteristics (72-V Single Supply)...........9
7.10 Electrical Characteristics (100-V Single Supply).....10
7.11 Switching Characteristics: TMUX821x Devices.......11
7.12 Typical Characteristics............................................12
8 Parameter Measurement Information..........................17
8.1 On-Resistance.......................................................... 17
8.2 Off-Leakage Current................................................. 17
8.3 On-Leakage Current................................................. 18
8.4 Device Turn-On and Turn-Off Time...........................18
Information.................................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2021) to Revision A (December 2021)
Page
•
Changed the status of the data sheet from: Advanced Information to: Production Data ...................................1
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SCDS434A – OCTOBER 2021 – REVISED DECEMBER 2021
5 Device Comparison Table
PRODUCT
TMUX8211
TMUX8212
TMUX8213
DESCRIPTION
High Voltage, 4-channel, 1:1 (SPST) switches, (Logic Low)
High Voltage, 4-channel, 1:1 (SPST) switches, (Logic High)
High Voltage, 4-channel, 1:1 (SPST) switches, (Logic Low + Logic High)
6 Pin Configuration and Functions
S1
D1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S2
D2
SEL1
SEL2
V
1
2
3
4
12
11
10
9
SEL2
SEL3
N.C.
SS
V
V
SS
DD
SEL1
GND
SEL4
Thermal
Pad
GND
SEL4
D4
N.C.
SEL3
D3
V
DD
S4
S3
Not to scale
Not to scale
Figure 6-1. PW Package
16-Pin TSSOP
Figure 6-2. RUM Package (Preview)
16-Pin WQFN
Top View
Top View
Table 6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
S1
TSSOP
WQFN(2)
1
2
3
15
16
2
I/O
I/O
I
Source pin 1. Can be an input or output.
Drain pin 1. Can be an input or output.
Logic control input 1.
D1
SEL1
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 1 µF to 10 µF between VSS and GND.
VSS
4
1
P
GND
SEL4
D4
5
6
3
4
P
I
Ground (0 V) reference
Logic control input 4.
7
5
I/O
I/O
I/O
I/O
I
Drain pin 4. Can be an input or output.
Source pin 4. Can be an input or output.
Source pin 3. Can be an input or output.
Drain pin 3. Can be an input or output.
Logic control input 3.
S4
8
6
S3
9
7
D3
10
11
12
8
SEL3
N.C.
11
10
—
No internal connection.
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 1 µF to 10 µF between VDD and GND.
VDD
13
9
P
SEL2
D2
14
15
16
12
13
14
I
Logic control input 2.
I/O
I/O
Drain pin 2. Can be an input or output.
Source pin 2. Can be an input or output.
S2
The thermal pad is not connected internally. It is recommended that the pad be tied to GND or VSS
for best performance.
Thermal Pad
—
(1) I = input, O = output, I/O = input and output, P = power
(2) Preview package.
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7 Specifications
7.1 Absolute Maximum Ratings: TMUX821x Devices
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
110
110
0.5
UNIT
V
VDD–VSS
VDD
Supply voltage
–0.5
–110
–0.5
–30
V
VSS
V
VSELx
ISELx
VS or VD
IDC
Logic control input pin voltage (SELx)
Logic control input pin current (SELx)
Source or drain voltage (Sx, Dx)
Source or drain continuous current (Sx, Dx)
Diode clamp current at 85°C
Diode clamp current at 125°C
Storage temperature
50
V
30
mA
V
VSS–2
–200
–100
–15
VDD+2
200
100
15
mA
mA
mA
°C
(2)
IIK
Tstg
TA
–65
150
150
150
1680
720
Ambient temperature
–55
°C
TJ
Junction temperature
°C
(3)
Ptot
Total power dissipation (QFN)
Total power dissipation (TSSOP)
mW
mW
(4)
Ptot
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) Signal path pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum
ratings.
(3) For QFN package: Ptot derates linearly above TA = 70°C by 24.0 mW/°C
(4) For TSSOP package: Ptot derates linearly above TA = 70°C by 10.5 mW/°C
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
V(ESD) Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions: TMUX821x Devices
over operating free-air temperature range (unless otherwise noted)
MIN
10
NOM
MAX
100
100
VDD
48
UNIT
V
(1)
VDD – VSS
VDD
Power supply voltage differential
Positive power supply voltage
10
V
(2)
VS or VD
VSEL
Signal path input/output voltage (source or drain pin)
Logic input pin voltage
VSS
0
V
V
TA
Ambient temperature
–40
125
200
200
190
100
185
125
65
°C
mA
IDC 1ch.(3)
Continuous current through switch for TSSOP or QFN on 1 channel
TA = 25°C
Continuous current through switch on all channels at the
same time, QFN package
IDC All ch.(4)
TA = 85°C
TA = 125°C
TA = 25°C
TA = 85°C
TA = 125°C
mA
mA
Continuous current through switch on all channels at the
same time, TSSOP package
IDC All ch.(4)
(1) VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 100 V, and the minimum VDD is met.
(2) VS or VD is the voltage on any Source or Drain pins.
(3) Max continuous current shown for a single channel at a time.
(4) Max continuous current shown for all channels at a time. Refer to max power dissipation (Ptot) to ensure package limitations are not
violated.
7.4 Thermal Information
TMUX821x
PW (TSSOP)
16 PINS
96.0
TMUX821x
RUM (WQFN)
16 PINS
41.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
26.8
25.3
42.7
16.0
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.2
0.3
ΨJB
42.0
16.0
RθJC(bot)
N/A
3.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics (Global): TMUX821x Devices
over operating free-air temperature range (unless otherwise noted)
typical at VDD = +36 V, VSS = –36 V, GND = 0 V and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
LOGIC INPUTS
VIH
VIL
IIH
Logic voltage high
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
1.3
0
48
0.8
3.8
V
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
Logic inputs = 0 V, 5 V, or 48 V
Logic inputs = 0 V, 5 V, or 48 V
0.4
µA
µA
pF
IIL
–0.2 –0.005
3
CIN
POWER SUPPLY
25°C
350
350
800
800
900
800
800
900
µA
µA
µA
µA
µA
µA
IDD
VDD supply current
Logic inputs = 0 V, 5 V, or 48 V
Logic inputs = 0 V, 5 V, or 48 V
–40°C to +85°C
–40°C to +125°C
25°C
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
7.6 Electrical Characteristics (±15-V Dual Supply)
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
5
7
VS = –10 V to +10 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
8
10
Ω
Ω
0.2
0.3
0.4
0.5
On-resistance mismatch between VS = –10 V to +10 V
ΔRON
–40°C to +85°C
–40°C to +125°C
channels
ID = –10 mA
VS = –10 V to +10 V
ID = –10 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
25°C
0.07
Ω
VS = 0 V, IS = –10 mA
–40°C to +125°C
25°C
0.03
0.01
Ω/°C
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
nA
nA
nA
pA
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
IS(OFF)
–40
40
VD = –10 V / +10 V
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
0.01
0.01
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
ID(OFF)
–40
40
VD = –10 V / +10 V
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
25°C
–1
–2
1
2
5
35
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
85°C
125°C
120
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.7 Electrical Characteristics (±36-V Dual Supply)
VDD = +36 V ± 10%, VSS = –36 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
5
7
VS = –25 V to +25 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
8
10
Ω
Ω
0.1
0.3
0.4
0.5
On-resistance mismatch between VS = –25 V to +25 V
ΔRON
–40°C to +85°C
–40°C to +125°C
channels
ID = –10 mA
VS = –25 V to +25 V
ID = –10 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
25°C
0.12
Ω
VS = 0 V, IS = –10 mA
–40°C to +125°C
25°C
0.03
0.01
Ω/°C
VDD = 39.6 V, VSS = –39.6 V
Switch state is off
VS = +25 V / –25 V
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
nA
nA
nA
pA
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
IS(OFF)
–40
40
VD = –25 V / +25 V
VDD = 39.6 V, VSS = –39.6 V
Switch state is off
VS = +25 V / –25 V
0.01
0.01
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
ID(OFF)
–40
40
VD = –25 V / +25 V
VDD = 39.6 V, VSS = –39.6 V
Switch state is on
VS = VD = ±25 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
25°C
–1
–2
1
2
5
35
VDD = 39.6 V, VSS = –39.6 V
Switch state is on
VS = VD = ±25 V
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
85°C
125°C
120
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.8 Electrical Characteristics (±50-V Dual Supply)
VDD = +50 V, VSS = –50 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
5
7
VS = –45 V to 45 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
8
10
Ω
Ω
0.2
0.3
0.4
0.5
On-resistance mismatch between VS = –45 V to 45 V
ΔRON
–40°C to +85°C
–40°C to +125°C
channels
ID = –10 mA
VS = –45 V to 45 V
ID = –10 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
25°C
0.13
Ω
VS = 0 V, IS = –10 mA
–40°C to +125°C
25°C
0.03
0.01
Ω/°C
VDD = 50 V, VSS = –50 V
Switch state is off
VS = +45 V / –45 V
VD = –45 V / +45 V
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
nA
nA
nA
pA
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
IS(OFF)
–40
40
VDD = 50 V, VSS = –50 V
Switch state is off
VS = +45 V / –45 V
VD = –45 V / +45 V
0.01
0.01
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
ID(OFF)
–40
40
VDD = 50 V, VSS = –50 V
Switch state is on
VS = VD = ±45 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
25°C
–2
–5
2
5
10
50
VDD = 50 V, VSS = –50 V
Switch state is on
VS = VD = ±45 V
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
85°C
125°C
220
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.9 Electrical Characteristics (72-V Single Supply)
VDD = +72 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
5
7
VS = 0 V to 60 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
8
10
Ω
Ω
0.2
0.3
0.4
0.5
On-resistance mismatch between VS = 0 V to 60 V
ΔRON
–40°C to +85°C
–40°C to +125°C
channels
ID = –10 mA
VS = 0 V to 60 V
ID = –10 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
25°C
0.05
Ω
VS = 0 V, IS = –10 mA
–40°C to +125°C
25°C
0.03
0.01
Ω/°C
Switch state is off
VS = +60 V / 1 V
VD = 1 V / +60 V
IS(OFF)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
nA
nA
nA
pA
–40
40
0.01
0.01
Switch state is off
VS = +60 V / 1 V
VD = 1 V / +60 V
ID(OFF)
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
–40
40
IS(ON)
ID(ON)
Switch state is on
VS = VD = 1 V / +60 V
–40°C to +85°C
–40°C to +125°C
25°C
–2
–5
2
5
15
75
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
Switch state is on
VS = VD = 1 V / +60 V
85°C
125°C
300
(1) When VS is 60 V, VD is 1 V. Or when VS is 1 V, VD is 60 V.
(2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.10 Electrical Characteristics (100-V Single Supply)
VDD = +100 V, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
5
7
VS = 0 V to +95 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
8
10
Ω
Ω
0.2
0.3
0.4
0.5
On-resistance mismatch between VS = 0 V to +95 V
ΔRON
–40°C to +85°C
–40°C to +125°C
channels
ID = –10 mA
VS = 0 V to +95 V
ID = –10 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
25°C
0.07
Ω
VS = 50 V, IS = –10 mA
–40°C to +125°C
25°C
0.03
0.01
Ω/°C
Switch state is off
VS = +95 V / 1 V
VD = 1 V / +95 V
IS(OFF)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
nA
nA
nA
pA
–40
40
0.01
0.01
Switch state is off
VS = +95 V / 1 V
VD = 1 V / +95 V
ID(OFF)
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
–40
40
IS(ON)
ID(ON)
Switch state is on
VS = VD = 1 V / +95 V
–40°C to +85°C
–40°C to +125°C
25°C
–4
4
–10
10
15
100
450
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
Switch state is on
VS = VD = 1 V / +95 V
85°C
125°C
(1) When VS is 95 V, VD is 1 V. Or when VS is 1 V, VD is 95 V.
(2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.11 Switching Characteristics: TMUX821x Devices
over operating free-air temperature range (unless otherwise noted)
typical at VDD = +36 V, VSS = –36 V, GND = 0 V and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
4
VS = 10 V
RL = 10 kΩ, CL = 15 pF
tON
Turn-on time from enable
–40°C to +85°C
–40°C to +125°C
25°C
10
12
µs
(EN)
(EN)
100
60
VS = 10 V
RL = 10 kΩ, CL = 15 pF
tOFF
Turn-off time from enable
–40°C to +85°C
–40°C to +125°C
600
700
ns
µs
VDD ramp rate = 1 V/µs,
VS = 10 V
RL = 10 kΩ, CL = 15pF
Device turn on time
(VDD to output)
tON (VDD)
25°C
tPD
Propagation delay
Charge injection
RL = 50 Ω , CL = 5 pF
25°C
25°C
190
ps
QINJ
VS = (VDD + VSS) / 2, CL = 1 nF
–1.3
nC
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 100 kHz
OISO
XTALK
BW
IL
Off isolation
25°C
25°C
25°C
25°C
–110
–110
420
dB
dB
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 100 kHz
Inter-channel crosstalk
–3dB bandwidth
Insertion loss
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2
MHz
dB
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 1 MHz
–0.4
Dual supply voltage
VPP = 5 V, VBIAS = (VDD + VSS) / 2
RL = 1 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total harmonic distortion + Noise
25°C
0.0008
%
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = (VDD + VSS) / 2 V, f = 1 MHz 25°C
VS = (VDD + VSS) / 2 V, f = 1 MHz 25°C
12
12
pF
pF
CS(ON),
CD(ON)
On capacitance
VS = (VDD + VSS) / 2 V, f = 1 MHz 25°C
14
pF
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7.12 Typical Characteristics
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
10
9
8
TA = 125C
7
6
TA = 85C
5
TA = 25C
4
3
TA = -40C
2
-40
-30
-20
-10
0
10
20
30
VS or VD - Source or Drain Voltage (V)
VDD = 36 V, VSS = –36 V
Flatest Ron Region
VDD = 36 V, VSS = –36 V
.
Figure 7-1. On-Resistance vs Source or Drain Voltage
Figure 7-2. On-Resistance vs Source or Drain Voltage
160
150
TA = 125C
VDD/VSS = ±39.6 V
VDD/VSS = ±36 V
VDD/VSS = ±32.4 V
VDD/VSS = ±16.5 V
VDD/VSS = ±15 V
VDD/VSS = ±13.5 V
140
130
120
110
100
90
TA = 85C
TA = 25C
TA = -40C
140
120
100
80
80
70
60
50
60
40
30
40
20
20
10
0
0
-36
-28
-20
-12
-4
0
4
12
20
28
36
-40
-30
-20
-10
0
10
20
30
40
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
VDD = 36 V, VSS = –36 V
.
Dual Supply Voltages
.
Figure 7-3. On-Resistance vs Source or Drain Voltage
Figure 7-4. On-Resistance vs Source or Drain Voltage
12
160
TA = 125C
TA = 85C
TA = 25C
TA = -40C
TA = 125C
TA = 85C
TA = 25C
TA = -40C
11
10
9
140
120
100
80
8
7
6
5
60
4
3
40
2
20
1
0
-16
0
-16
-12
-8
-4
0
4
8
12
16
-12
-8
-4
0
4
8
12
16
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
VDD = 15 V, VSS = –15 V
VDD = 15 V, VSS = –15 V
Figure 7-5. On-Resistance vs Source or Drain Voltage
Figure 7-6. On-Resistance vs Source or Drain Voltage
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
12
11
10
9
160
140
120
100
80
TA = 125C
TA = 85C
TA = 25C
TA = −40C
TA = 125C
TA = 85C
TA = 25C
TA = −40C
8
7
6
5
60
4
3
40
2
20
1
0
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
VS or VD - Source or Drain Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
VS or VD - Source or Drain Voltage (V)
VDD = 72 V, VSS = 0 V
VDD = 72 V, VSS = 0 V
Figure 7-7. On-Resistance vs Source or Drain Voltage
Figure 7-8. On-Resistance vs Source or Drain Voltage
160
12
TA = 125C
TA = 125C
TA = 85C
TA = 25C
TA = -40C
11
TA = 85C
140
120
100
80
TA = 25C
TA = -40C
10
9
8
7
6
5
4
3
2
60
40
20
0
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
VDD = 100 V, VSS = 0 V
VDD = 100 V, VSS = 0 V
Figure 7-9. On-Resistance vs Source or Drain Voltage
Figure 7-10. On-Resistance vs Source or Drain Voltage
24
100
ID(OFF) VS/VD: -25V/25V
ID(OFF) VS/VD: 25V-25V
IS(OFF) VS/VD: -25V/25V
IS(OFF) VS/VD: 25V/-25V
I(ON) VS = VD = -25V
I(ON) VS = VD = 25V
ID(OFF) VS/VD: -25V/25V
ID(OFF) VS/VD: 25V-25V
IS(OFF) VS/VD: -25V/25V
IS(OFF) VS/VD: 25V/-25V
I(ON) VS = VD = -25V
I(ON) VS = VD = 25V
22
20
10
18
16
14
12
10
8
1
0.1
0.01
6
4
2
0
-2
0.001
0
20
40
60
80
100
120
0
20
40
60
80
100
120
Temperature (C)
Temperature (C)
VDD = 36 V, VSS = –36 V
Figure 7-11. Leakage Current vs Temperature
VDD = 36 V, VSS = –36 V
Figure 7-12. Leakage Current vs Temperature
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
100
100
10
ID(OFF) VS/VD: 1V/60V
ID(OFF) VS/VD: 60V/1V
IS(OFF) VS/VD: 1V/60V
IS(OFF) VS/VD: 60V/1V
I(ON) VS = VD = 1V
ID(OFF) VS/VD: 1V/95V
ID(OFF) VS/VD: 95V/1V
IS(OFF) VS/VD: 1V/95V
IS(OFF) VS/VD: 95V/1V
I(ON) VS = VD = 1V
10
I(ON) VS = VD = 60V
I(ON) VS = VD = 95V
1
1
0.1
0.1
0.01
0.01
0.001
0.001
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
Temperature (C)
Temperature (C)
VDD = 72 V, VSS = 0 V
VDD = 100 V, VSS = 0 V
Figure 7-13. Leakage Current vs Temperature
Figure 7-14. Leakage Current vs Temperature
30
25
20
15
10
5
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
TA = 125C
TA = 85C
TA = 25C
TA = 125C
TA = 85C
TA = 25C
0
-5
-36
-28
-20
-12
-4
0
4
12
20
28
36
-36
-28
-20
-12
-4
0
4
12
20
28
36
VS or VD - Source or Drain Voltage (V)
VDD = 36 V, VSS = –36 V
IS(OFF) and ID(OFF)
VS or VD - Source or Drain Voltage (V)
VDD = 36 V, VSS = –36 V
ION
Figure 7-15. Off-Leakage Current vs Source or Drain Voltage
Figure 7-16. On-Leakage Current vs Source or Drain Voltage
30
0.7
TA = 125C
TA = 85C
TA = 25C
TA = 125C
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = 85C
25
TA = 25C
20
15
10
5
-0.1
-0.2
-0.3
-0.4
0
-5
-36
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
VS or VD - Source or Drain Voltage (V)
-28
-20
-12
-4
0
4
12
20
28
36
VS or VD - Source or Drain Voltage (V)
VDD = 72 V, VSS = 0 V
VDD = 72 V, VSS = 0 V
Figure 7-18. On-Leakage Current vs Source or Drain Voltage
Figure 7-17. Off-Leakage Current vs Source or Drain Voltage
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
30
TA = 125C
TA = 85C
TA = 25C
25
20
15
10
5
0
-5
0
10
20
30
40
50
60
70
80
90 100
VS or VD - Source or Drain Voltage (V)
VDD = 100 V, VSS = 0 V
IS(OFF) and ID(OFF)
VDD = 100 V, VSS = 0 V
ION
Figure 7-19. Off-Leakage Current vs Source or Drain Voltage
Figure 7-20. On-Leakage Current vs Source or Drain Voltage
0
400
375
350
325
TA = 125C
-0.2
-0.4
-0.6
-0.8
-1
TA = 85C
TA = 25C
TA = −40C
300
VDD/VSS: 72V/0V - All Channels Enabled
VDD/VSS: ±36V - All Channels Enabled
VDD/VSS: 72V/0V - All Channels Disabled
275
250
VDD/VSS: ±36V - All Channels Disabled
225
-1.2
-1.4
-1.6
-1.8
200
175
150
125
20 30 40 50 60 70 80 90 100 110 120 130
-36
-28
-20
-12
-4
0
4
12
20
28
36
Temperature (C)
VS or VD - Source or Drain Voltage (V)
.
VDD = 36 V, VSS = –36 V
Figure 7-22. Supply Current vs Temperature
Figure 7-21. Charge Injection vs Source Voltage
5
4
3
2
1
0
0
T(ON)
T(OFF)
VDD/VSS: ±36V
-10
VDD/VSS: 72V/0V
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
10
100
1k
10k
100k
Frequency (Hz)
1M
10M 100M 1G
-36
-28
-20
-12
-4
0
4
12
20
28
36
VS or VD - Source or Drain Voltage (V)
TA = 25°C
VDD = 36 V, VSS = –36 V
Figure 7-24. Off Isolation vs Frequency
Figure 7-23. Turn-On and Turn-Off Times vs Source Voltage
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
0
VDD/VSS: ±36V - Adjacent
VDD/VSS: ±36V - Non-Adjacent
VDD/VSS: 72V/0V - Adjacent
-10
-20
-30
-40
VDD/VSS: 72V/0V - Non-Adjacent
-50
-60
-70
-80
-90
-100
-110
-120
-130
10
100
1k
10k
100k
1M
10M 100M 1G
Frequency (Hz)
TA = 25°C
Bandwidth
Figure 7-25. Crosstalk vs Frequency
Figure 7-26. Insertion Loss vs Frequency
0.005
VDD/VSS: ±15V
VDD/VSS: ±15V
VPP: 5V
RL = 1k
VDD/VSS: ±36V
VPP: 5V
RL: 1k
VPP: 2V
RL: 50
0.004
0.003
0.002
0.001
0
10
100
1k
10k
Frequency (Hz)
TA = 25°C
Figure 7-27. THD+N vs Frequency
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8 Parameter Measurement Information
8.1 On-Resistance
The on-resistance of the TMUX821x is the ohmic resistance across the source (Sx) and drain (Dx) pins of
the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote
on-resistance. Figure 8-1 shows the measurement setup used to measure RON. ΔRON represents the difference
between the RON of any two channels, while RON_FLAT denotes the flatness that is defined as the difference
between the maximum and minimum value of on-resistance measured over the specified analog signal range.
V
VDD
VSS
8
410
=
+
5
VDD
VSS
IS
SW
Sx
Dx
VS
GND
Figure 8-1. On-Resistance Measurement Setup
8.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current IS(OFF): the leakage current flowing into or out of the source pin when the switch
is off.
2. Drain off-leakage current ID(OFF): the leakage current flowing into or out of the drain pin when the switch is
off.
Figure 8-2 shows the setup used to measure both off-leakage currents.
VDD
VSS
VDD
VSS
Is (OFF)
A
ID (OFF)
A
SW
SW
SW
SW
S1
S4
S1
S4
D1
D4
D1
D4
VD
VD
VS
VS
GND
GND
GND
GND
ID (OFF)
A
Is (OFF)
A
VD
VD
VS
VS
GND
GND
GND
GND
GND
GND
IS(OFF)
ID(OFF)
Figure 8-2. Off-Leakage Measurement Setup
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8.3 On-Leakage Current
Source on-leakage current (IS(ON)) and drain on-leakage current (ID(ON)) denote the channel leakage currents
when the switch is in the on state. IS(ON) is measured with the drain floating, while ID(ON) is measured with the
source floating. Figure 8-3 shows the circuit used for measuring the on-leakage currents.
VDD
VSS
VDD
VSS
Is (OFF)
A
ID (OFF)
A
SW
SW
S1
S1
D1
D4
D1
D4
N.C. N.C.
VS
VS
GND
GND
GND
Is (OFF)
A
ID (OFF)
A
SW
SW
S4
S4
N.C. N.C.
VS
VS
GND
GND
GND
IS(ON)
ID(ON)
Figure 8-3. On-Leakage Measurement Setup
8.4 Device Turn-On and Turn-Off Time
Turn-on time (tON) is defined as the time taken by the output of the TMUX8211, TMUX8212, and TMUX8213
to rise to a 90% final value after the SELx signal has risen (for NC switches) or fallen (for NO switches) to a
50% final value. Turn off time (tOFF) is defined as the time taken by the output of the TMUX8211, TMUX8212,
and TMUX8213 to fall to a 10% initial value after the SELx signal has fallen (for NC switches) or risen (for NO
switches) to a 50% initial value. Figure 8-4 shows the setup used to measure tON and tOFF
.
VDD
VSS
0.1 µF
Output
0.1 µF
3 V
VDD
VSS
GND
GND
tr < 20 ns
tf < 20 ns
50%
50%
VSEL
SW
Sx
Dx
0 V
VS
RL
CL
SELx
0.9
tOFF
0.1
GND
tON
Output
GND
GND
VSEL
GND
GND
Figure 8-4. Enable Delay Measurement Setup
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8.5 Charge Injection
Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during
switching, and is denoted by the symbol QINJ. Figure 8-5 shows the setup used to measure charge injection from
the source to drain.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
Output
D1
D4
3 V
VSELx
0 V
tr < 20 ns
tf < 20 ns
CL
VS
GND
GND
GND
S4
Output
CL
Output
VS
VOUT
QINJ = CL ×
VOUT
VS
SELx
GND
VSELx
GND
Figure 8-5. Charge-Injection Measurement Setup
8.6 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to
the source pin (Sx) of an off-channel. The characteristic impedance, ZO, for the measurement is 50 Ω. Figure 8-6
shows the setup used to measure off isolation.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Network Analyzer
GND
SW
SX
VOUT
RS
Dx
VS
50Ω
SELx
Other
Sx/ Dx
pins
VSELx
GND
50Ω
8176
1BB +OKH=PEKJ = 20 × .KC
8
5
Figure 8-6. Off Isolation Measurement Setup
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8.7 Crosstalk
Crosstalk (XTALK) is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is
applied at the source pin (Sx) of an on-channel. The characteristic impedance, ZO, for the measurement is 50 Ω,
as shown in Figure 8-7.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Network Analyzer
GND
SW
SW
SX
SY
DX
DY
50Ω
RS
VOUT
Other
Sx/ Dx
pins
50Ω
VS
50Ω
50Ω
INx
VINx
GND
8176
+JPAN F ?D=JJAH %NKOOP=HG = 20 × .KC
8
5
Figure 8-7. Inter-channel Crosstalk Measurement Setup
8.8 Bandwidth
Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx). Figure 8-8 shows the
setup used to measure bandwidth of the switch.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Network Analyzer
GND
SW
SX
VOUT
RS
Dx
Other
Sx/ Dx
pins
VS
50Ω
SELx
VSELx
50Ω
GND
8176
$=J@SE@PD = 20 × .KC
8
5
Figure 8-8. Bandwidth Measurement Setup
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8.9 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at
the multiplexer output. The on-resistance of the device varies with the amplitude of the input signal and results
in distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is
denoted as THD+N. Figure 8-9 shows the setup used to measure THD+N of the devices.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Audio Precision
GND
SW
SX
RS
Dx
VOUT
VS
RL
Other
Sx/ Dx
pins
SELx
VSELX
GND
50Ω
Figure 8-9. THD+N Measurement Setup
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9 Detailed Description
9.1 Overview
The TMUX8211, TMUX8212 and TMUX8213 are a modern complementary metal-oxide semiconductor (CMOS)
analog switches in quad single-pole single-throw configuration. The devices work well with dual supplies, a
single supply, or asymmetric supplies.
9.2 Functional Block Diagram
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
S1
S2
S3
S4
D1
D2
D3
D4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
SEL1
SEL2
SEL3
SEL4
TMUX8211
TMUX8212
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
TMUX8213
9.3 Feature Description
9.3.1 Bidirectional Operation
The devices conduct equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each signal
path has similar characteristics in both directions.
9.3.2 Flat On-Resistance
The TMUX821x devices are designed with a special switch architecture to produce ultra-flat on-resistance
(RON) across most of the switch input operating region. The flat RON response allows the device to be used in
precision sensor applications since the RON is controlled regardless of the signals sampled. The architecture
is implemented without a charge pump so no unwanted noise is produced from the device to affect sampling
accuracy.
The flatest on-resistance region extends from VSS to roughly 5 V below VDD. Once the signal is within 5 V of VDD
the on-resistance will expoentially increase and may impact desired signal transmission.
9.3.3 Protection Features
These devices offer a number of protection features to enable robust system implementations.
9.3.3.1 Fail-Safe Logic
Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting
the device from potential damage. Additionaly the fail safe logic feature allows the logic inputs of the mux to be
interfaced with high voltages, allowing for simplified interfacing if only high voltage control signals are present.
The logic inputs are protected against positive faults of up to +48 V in powered-off condition, but do not offer
protection against negative overvoltage condition.
Fail-safe logic also allows the devices to interface with a voltage greater than VDD on the control pins during
normal operation to add maximum flexibility in system design. For example, with a VDD = 15 V, the logic control
pins could be connected to +24 V for a logic high signal which allows different types of signals, such as analog
feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the logic
inputs can be interfaced as high as 48 V.
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9.3.3.2 ESD Protection
All pins support HBM ESD protection level up to ±2 kV, which helps protect the devices from ESD events during
the manufacturing process.
9.3.3.3 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
In the TMUX821x devices, an insulating oxide layer is placed on top of the silicon substrate to prevent any
parasitic junctions from forming. As a result, the devices are latch-up immune under all circumstances by device
construction.
The TMUX821x devices are constructed on silicon on insulator (SOI) based process where an oxide layer is
added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from
forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due
to overvoltage or current injections. The latch-up immunity feature allows the TMUX821x to be used in harsh
environments. For more information on latch-up immunity refer to Using Latch Up Immune Multiplexers to Help
Improve System Reliability.
9.3.4 1.8 V Logic Compatible Inputs
The TMUX821x devices have 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs
allows the TMUX821x to interface with processors that have lower logic I/O rails and eliminates the need for an
external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches.
9.3.5 Integrated Pull-Down Resistor on Logic Pins
The TMUX821x have internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The
value of this pull-down resistor is approximately 4 MΩ, but is clamped to 1 µA at higher voltages. This feature
integrates up to four external components and reduces system size and cost.
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9.4 Device Functional Modes
9.4.1 Normal Mode
In Normal Mode operation, signals of up to VDD and VSS can be passed through the switch from source (Sx)
to drain (Dx) or from drain (Dx) to source (Sx). The select (SELx) pins determine which switch path to turn on,
according to the Truth Table. The following conditions must be satisfied for the switch to stay in the ON condition:
•
The difference between the primary supplies (VDD – VSS) must be greater than or equal to 10 V. With a
minimum VDD of 10 V.
•
•
The input signals on the source (Sx) or the drain (Dx) must be be between VDD and VSS.
The logic control (SELx) must have selected the switch.
9.4.2 Truth Tables
Table 9-1, Table 9-2, and Table 9-3 show the truth tables for the TMUX8211, TMUX8212, and TMUX8213,
respectively.
Table 9-1. TMUX8211 Truth Table
SEL #(1)
CHANNEL #
Channel # ON
Channel # OFF
0
1
(1) "#"designates the channel number controlled by SEL pin: "1, 2,
3, or 4"
Table 9-2. TMUX8212 Truth Table
SEL #(1)
CHANNEL #
Channel # OFF
Channel # ON
0
1
(1) "#"designates the channel number controlled by SEL pin: "1, 2,
3, or 4"
Table 9-3. TMUX8213 Truth Table
SEL1 SEL2 SEL3 SEL4
ON / OFF CHANNELS
CHANNEL 1 ON
CHANNEL 1 OFF
CHANNEL 2 OFF
CHANNEL 2 ON
CHANNEL 3 OFF
CHANNEL 3 ON
CHANNEL 4 ON
CHANNEL 4 OFF
0
1
X(1)
X
X
X
X
0
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
1
X
X
1
X
X
X
X
1
(1) "X" means "do not care."
If unused, SELx pins must be tied to GND or Logic High in order to ensure the device does not consume
additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx
or Dx) should be connected to GND for best performance.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TMUX821x are high voltage switches capable of supporting analog and digital signals. The high voltage
capability of these multiplexers allow them to be used in systems with high voltage signal swings, or in systems
with high common mode voltages.
Additionally, the TMUX821x devices provide consistent analog parametric performance across the entire supply
voltage range allowing the devices to be powered by the most convient supply rails in the system while still
providing excellent performance.
10.2 Typical Application
A common feature of many PMUs (precision measurement units) is the ability to change current ranges. This
allows for a system defined current clamp when testing devices and reduces possible damage to the PMU and
DUT (device under test). In high voltage PMUs, large relays are often used to enable this switching, but this
comes with the trade-off of size. To reduce system size, a multi-channel high voltage switch can be added to
facilitate this switching with minimal impact to system size and performance. The TMUX821x allows for switching
between multiple current ranges, and has the added flexibility to use multiple channels in parallel for high current
applications.
V
DD VSS
Gain / Filter
Network
TMUX8212
10k
VDD
-
DUT
DAC
+
High Voltage
Offset
VSS
+
–
V
DD VSS
Gain / Filter
Network
TMUX8212
10k
VDD
-
DUT
DAC
+
High Voltage
Offset
VSS
+
–
Figure 10-1. TMUX8212 Application Schematic
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10.2.1 Design Requirements
Table 10-1. Design Parameters
PARAMETERS
Positive supply (VDD) mux and Op Amps
Positive supply (VSS) mux and Op Amps
Maximum input or output signals with common mode shift
Control logic thresholds
VALUES
36 V
-36 V
-36 V to 36 V
1.8 V compatible, up to 48 V
-40°C to +125°C
Temperature range
10.2.2 Detailed Design Procedure
Multiplexing PMU systems enables a small, flexible solution that can be used over a wide range of current
ranges. TI’s high voltage multiplexers offer a size advantage over typical relay solutions while still achieving an
extremely low level of distortion, noise, and leakage. This high voltage multiplexer can be use in tandem with
high voltage operational amplifiers and DACs to create an accurate PMU with excellent signal-to-noise ratio.
In this example application, the TMUX8212 is paired with a high voltage amplifier and a DAC. The DAC
generates an arbitrary voltage signal that feeds into the amplifier. An additional high voltage offset is also fed
into the amplifier to add any needed common mode shift. This arbitrary signal is then passed through a current
limiting resistor before reaching the DUT. To change the current range of the system, different current limiting
resistors are added in series with each channel of the multiplexer. In this example, the first channel of the
multiplexer uses a 10 kΩ resistor for the low current clamp. This ensures the maximum output current of the
PMU in this range is 5 mA. During the system operation, the PMU is set to this lower current range in the
beginning of the test routine. After the DUT is initially checked in this range and is operating normally with no
unexpected shorts, the current range can be switched to high current. This ensures that the PMU and DUT will
not be unnecessarily damaged from excess current due to a short. In this example, the remaining three channels
of the TMUX8212 are connected in parallel, increasing the maximum current through the device and reducing
the low on-resistance. Because of the flexibility of the TMUX8212, this could easily be modified to fit any system
need. For example, if less maximum current is needed, then two channels could be connected in parallel instead
of three, and the additional single channel could be used to add a third current range option. The additional input
channels make this multiplexed application increasingly valuable by greatly reducing solution size.
The TMUX821x switches have exceptionally flat on-resistance and low leakage currents across the signal
voltage range. The ultra-flat on-resistance ensures that the current clamp stays constant across the signal
voltage range, and the low leakage current reduces the potential noise/offset when measuring on the lowest
current range. Additionally, excellent crosstalk and off-isolation performance allows the TMUX821x devices
to perform well in multi-channel switching applications without having an unselected channel impact the
measurement on selected channels.
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10.2.3 Application Curves
The example application utilizes the excellent leakage and on-resistance flatness performance of the TMUX821x
devices. Figure 10-2 shows the leakage current for a channel that is ON across a varying source voltage. Figure
10-3 shows the extremely flat on-resistance across source voltage while operating within the flatest RON range of
the TMUX821x devices. These features make the devices an ideal solution for applications that require excellent
linearity and low distortion.
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
10
9
TA = 125C
TA = 85C
TA = 25C
8
TA = 125C
7
6
TA = 85C
TA = 25C
5
4
3
TA = -40C
-20 -10
2
-40
-36
-28
-20
-12
-4
0
4
12
20
28
36
-30
0
10
20
30
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
.
.
Figure 10-2. On-Leakage
Figure 10-3. RON Flatness
11 Power Supply Recommendations
The TMUX821x devices operate across a wide supply range of ±10 V to ±50 V (10 V to 100 V in single-supply
mode). They also perform well with asymmetrical supplies such as VDD = 50 V and VSS= –10 V. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 1 µF to 10 µF at both the VDD and VSS
pins to ground. An additional 0.1 µF capacitor placed closest to the supply pins will provide the best supply
decoupling solution. Always ensure the ground (GND) connection is established before supplies are ramped.
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12 Layout
12.1 Layout Guidelines
The image below illustrates an example of a PCB layout with the TMUX821x device. Some key considerations
are:
•
For reliable operation, connect at least one decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and VSS to GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to
the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
Keep the input lines as short as possible.
Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
•
•
•
12.2 Layout Example
S1
D1
S2
Wide (low inductance)
trace for power
D2
Wide (low inductance)
trace for power
SEL2
VDD
SEL1
VSS
GND
SEL4
D4
TMUX821x
N.C.
SEL3
D3
S3
S4
Via to ground plane
Figure 12-1. TMUX821x TSSOP Layout Example
Via to ground plane
VSS
SEL1
GND
SEL4
SEL2
SEL3
N.C.
Wide (low inductance)
trace for power
Wide (low inductance)
trace for power
VDD
Figure 12-2. TMUX821x QFN Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
•
•
•
Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
Texas Instruments, Multiplexers and Signal Switches Glossary application report
Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application
report
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTMUX8212PWR
TMUX8212PWR
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
2000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
TM8212
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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28-Dec-2021
Addendum-Page 2
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