TMUX7219M [TI]
具有 1.8V 逻辑扩展温度的 44V、低 Ron、2:1、1 通道闩锁效应抑制精密多路复用器;
| 型号： | TMUX7219M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1.8V 逻辑扩展温度的 44V、低 Ron、2:1、1 通道闩锁效应抑制精密多路复用器 复用器 |
| 文件： | 总36页 (文件大小：1822K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX7219M
ZHCSP65 –MAY 2022
TMUX7219M 具有1.8V 逻辑电平和闩锁效应抑制特性的44V 扩展工作温度范围
2:1 (SPDT) 精密开关
1 特性
3 说明
• 双电源电压范围：±4.5V 至±22V
• 单电源电压范围：4.5V 至44V
• -55°C 至+125°C 工作温度
• 低导通电阻：2.1Ω
• 低电荷注入：-10pC
• 高电流支持：330mA（最大值）
• 闩锁效应抑制
TMUX7219M 是一款具有闩锁效应抑制特性的互补金
属氧化物半导体 (CMOS) 开关，采用单通道 2:1
(SPDT) 配置。此器件在单电源（4.5 V 至 44 V）、双
电源（±4.5 V 至 ±22 V）或非对称电源（例如 VDD
=
12 V ， VSS = –5 V ） 供电时均能正常运行。
TMUX7219M 可在源极 (Sx) 和漏极 (D) 引脚上支持从
VSS 到VDD 范围的双向模拟和数字信号。
• 兼容1.8V 逻辑电平
可以通过控制 EN 引脚来启用或禁用 TMUX7219M。
当禁用时，两个信号路径开关都被关闭。当启用时，
SEL 引脚可用于打开信号路径 1（S1 至 D）或信号路
径 2（S2 至 D）。所有逻辑控制输入均支持 1.8V 到
VDD 的逻辑电平，因此，当器件在有效电源电压范围内
运行时，可确保 TTL 和CMOS 逻辑兼容性。失效防护
逻辑电路允许先在控制引脚上施加电压，然后在电源引
脚上施加电压，从而保护器件免受潜在的损害。
• 逻辑引脚具有集成的上拉和下拉电阻器
• 失效防护逻辑
• 轨到轨运行
• 双向信号路径
• 先断后合开关
2 应用
• 航空电子设备飞行控制单元
• 飞行器驾驶舱显示屏
• 独立航空电子设备精密飞行控制
• 互连和配电盒
TMUX72xx 系列具有闩锁效应抑制特性，可防止器件
内寄生结构之间通常由过压事件引起的大电流不良事
件。闩锁状态通常会一直持续到电源轨关闭为止，并可
能导致器件故障。抗闩锁特性使得 TMUX72xx 系列开
关和多路复用器能够在恶劣的环境中使用。此外，
TMUX7219M 的额定工作温度可低至 –55°C，非常适
合用于环境恶劣的工业和航空应用。
• 航天和国防
VSS
VDD
S1
S2
D
器件信息(1)
封装尺寸（标称值）
器件型号
封装
TMUX7219M
VSSOP (8)
3.00mm × 3.00mm
Decoder
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
EN SEL
功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS455
TMUX7219M
ZHCSP65 –MAY 2022
www.ti.com.cn
Table of Contents
7.9 Charge Injection........................................................23
7.10 Off Isolation.............................................................23
7.11 Crosstalk................................................................. 24
7.12 Bandwidth............................................................... 24
7.13 THD + Noise........................................................... 25
7.14 Power Supply Rejection Ratio (PSRR)...................25
8 Detailed Description......................................................26
8.1 Overview...................................................................26
8.2 Functional Block Diagram.........................................26
8.3 Feature Description...................................................26
8.4 Device Functional Modes..........................................28
8.5 Truth Tables.............................................................. 28
9 Application and Implementation..................................29
9.1 Application Information............................................. 29
9.2 Typical Applications.................................................. 29
10 Power Supply Recommendations..............................30
11 Layout...........................................................................31
11.1 Layout Guidelines................................................... 31
11.2 Layout Example...................................................... 31
12 Device and Documentation Support..........................32
12.1 Documentation Support.......................................... 32
12.2 Receiving Notification of Documentation Updates..32
12.3 支持资源..................................................................32
12.4 Trademarks.............................................................32
12.5 静电放电警告.......................................................... 32
12.6 术语表..................................................................... 32
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Thermal Information....................................................4
6.4 Recommended Operating Conditions.........................5
6.5 Source or Drain Continuous Current...........................5
6.6 ±15 V Dual Supply: Electrical Characteristics ............6
6.7 ±15 V Dual Supply: Switching Characteristics ...........7
6.8 ±20 V Dual Supply: Electrical Characteristics.............8
6.9 ±20 V Dual Supply: Switching Characteristics............9
6.10 44 V Single Supply: Electrical Characteristics ....... 10
6.11 44 V Single Supply: Switching Characteristics .......11
6.12 12 V Single Supply: Electrical Characteristics ....... 12
6.13 12 V Single Supply: Switching Characteristics ...... 13
6.14 Typical Characteristics............................................14
7 Parameter Measurement Information..........................19
7.1 On-Resistance.......................................................... 19
7.2 Off-Leakage Current................................................. 19
7.3 On-Leakage Current................................................. 20
7.4 Transition Time......................................................... 20
7.5 tON(EN) and tOFF(EN) .................................................. 21
7.6 Break-Before-Make...................................................21
7.7 tON (VDD) Time............................................................22
7.8 Propagation Delay.................................................... 22
Information.................................................................... 32
4 Revision History
DATE
REVISION
NOTES
May 2022
*
Initial Release
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5 Pin Configuration and Functions
D
S1
1
2
3
4
8
7
6
5
S2
VSS
SEL
EN
GND
VDD
Not to scale
图5-1. DGK Package
8-Pin VSSOP
(Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION(2)
NAME
D
NO.
1
I/O
I/O
P
Drain pin. Can be an input or output.
Source pin 1. Can be an input or output.
Ground (0 V) reference
S1
2
GND
3
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
4
P
Active high logic enable, has internal pull-up resistor. When this pin is low, all switches are turned off.
When this pin is high, the SEL logic input determine which switch is turned on.
EN
5
6
I
I
SEL
Logic control input, has internal pull-down resistor. Controls the switch connection as shown in 节8.5.
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
S2
7
8
P
I/O
Source pin 2. Can be an input or output.
(1) I = input, O = output, I/O = input and output, P = power.
(2) Refer to 节8.4 for what to do with unused pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
V
48
VDD –VSS
VDD
Supply voltage
48
V
–0.5
–48
VSS
0.5
V
VSEL or VEN
ISEL or IEN
VS or VD
IIK
Logic control input pin voltage (SEL, EN)(3)
Logic control input pin current (SEL, EN)(3)
Source or drain voltage (Sx, D)(3)
Diode clamp current(3)
48
V
–0.5
30
VDD+0.5
30
mA
V
–30
VSS–0.5
–30
mA
mA
°C
°C
°C
IS or ID (CONT)
TA
Source or drain continuous current (Sx, D)
Ambient temperature
IDC + 10 %(4)
150
–55
–65
Tstg
Storage temperature
150
TJ
Junction temperature
150
Total power dissipation(5)
Ptot
460
mW
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
(4) Refer to Source or Drain Continuous Current table for IDC specifications.
(5) For DGK package: Ptot derates linearily above TA = 70°C by 6.7mW/°C.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TMUX7219M
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
152.1
48.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
73.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.1
ΨJT
71.8
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
4.5
VSS
0
NOM
MAX
44
UNIT
V
(1)
Power supply voltage differential
VDD –VSS
VDD
Positive power supply voltage
44
V
VS or VD
VSEL or VEN
IS or ID (CONT)
TA
Signal path input/output voltage (source or drain pin) (Sx, D)
Address or enable pin voltage
VDD
44
V
V
(2)
Source or drain continuous current (Sx, D)
Ambient temperature
IDC
mA
°C
125
–55
(1) VDD and VSS can be any value as long as 4.5 V ≤(VDD –VSS) ≤44 V, and the minimum VDD is met.
(2) Refer to Source or Drain Continuous Current table for IDC specifications.
6.5 Source or Drain Continuous Current
at supply voltage of VDD ± 10%, VSS ± 10 % (unless otherwise noted)
CONTINUOUS CURRENT PER CHANNEL (IDC
PACKAGE TEST CONDITIONS
+44 V Single Supply(1)
)
TA = 25°C
TA = 85°C
210
TA = 125°C
UNIT
330
120
mA
mA
mA
mA
mA
±15 V Dual Supply
+12 V Single Supply
±5 V Dual Supply
+5 V Single Supply
330
240
240
180
210
160
160
120
120
100
100
80
DGK (VSSOP)
(1) Specified for nominal supply voltage only.
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6.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
2.1
2.9
3.8
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = –10 V to +10 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–55°C to +125°C
25°C
4.5
0.05
0.5
0.25
0.3
VS = –10 V to +10 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
–40°C to +85°C
–55°C to +125°C
25°C
ΔRON
0.35
0.6
VS = –10 V to +10 V
IS = –10 mA
Refer to On-Resistance
0.7
RON FLAT
On-resistance flatness
–40°C to +85°C
–55°C to +125°C
0.85
VS = 0 V, IS = –10 mA
Refer to On-Resistance
RON DRIFT On-resistance drift
0.01
0.05
–55°C to +125°C
Ω/°C
25°C
0.15
1.6
nA
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
–0.15
–1.6
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = –10 V / + 10 V
Refer to Off-Leakage Current
15
nA
–55°C to +125°C
–15
25°C
0.05
0.04
1
3
nA
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
Refer to Off-Leakage Current
–1
–3
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
26
nA
–55°C to +125°C
–26
25°C
1
1.8
18
nA
nA
nA
–1
–1.8
–18
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–55°C to +125°C
Refer to On-Leakage Current
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
44
0.8
2
V
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.005
µA
µA
pF
IIL
–1 –0.005
CIN
3
POWER SUPPLY
25°C
30
3
40
48
62
10
15
25
µA
µA
µA
µA
µA
µA
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–55°C to +125°C
25°C
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
ISS
VSS supply current
–40°C to +85°C
–55°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.7 ±15 V Dual Supply: Switching Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
120
100
100
50
175
190
210
170
185
200
180
195
210
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–55°C to +125°C
25°C
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off Time
tON
Turn-on time from enable
Turn-off time from enable
Break-before-make time delay
–40°C to +85°C
–55°C to +125°C
25°C
(EN)
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off Time
tOFF
–40°C to +85°C
–55°C to +125°C
25°C
(EN)
VS = 10 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
1
1
tBBM
–40°C to +85°C
–55°C to +125°C
25°C
0.19
0.2
VDD rise time = 100ns
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
TON (VDD)
–40°C to +85°C
–55°C to +125°C
0.22
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
700
ps
VD = 0 V, CL = 1 nF
Refer to Charge Injection
QINJ
pC
–10
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Off Isolation
OISO
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
dB
dB
dB
dB
–75
–55
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
XTALK
–117
–106
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
VS = 0 V
Refer to Bandwidth
BW
IL
25°C
25°C
40
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Insertion loss
–0.18
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–64
Refer to ACPSRR
VPP = 15 V, VBIAS = 0 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0005
Refer to THD + Noise
CS(OFF)
CD(OFF)
CS(ON)
Source off capacitance
Drain off capacitance
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
25°C
25°C
33
48
pF
pF
,
On capacitance
VS = 0 V, f = 1 MHz
25°C
148
pF
CD(ON)
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6.8 ±20 V Dual Supply: Electrical Characteristics
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
1.9
2.7
3.5
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = –15 V to +15 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–55°C to +125°C
25°C
4.2
0.04
0.3
0.22
0.28
0.3
VS = –15 V to +15 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
–40°C to +85°C
–55°C to +125°C
25°C
ΔRON
0.75
0.9
VS = –15 V to +15 V
IS = –10 mA
Refer to On-Resistance
RON FLAT
On-resistance flatness
–40°C to +85°C
–55°C to +125°C
1.2
VS = 0 V, IS = –10 mA
Refer to On-Resistance
RON DRIFT On-resistance drift
0.009
0.05
–55°C to +125°C
Ω/°C
25°C
1.5
4
nA
nA
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
–1.5
–4
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = –15 V / + 15 V
Refer to Off-Leakage Current
24
nA
–55°C to +125°C
–24
25°C
0.1
0.1
2
8
nA
nA
VDD = 22 V, VSS = –22 V
Switch state is off
VS = +15 V / –15 V
VD = –15 V / + 15 V
Refer to Off-Leakage Current
–2
–8
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
44
nA
–55°C to +125°C
–44
25°C
2
5
nA
nA
nA
–2
–5
VDD = 22 V, VSS = –22 V
Switch state is on
VS = VD = ±15 V
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–55°C to +125°C
Refer to On-Leakage Current
29
–29
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
44
0.8
2
V
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.005
µA
µA
pF
IIL
–1 –0.005
CIN
3
POWER SUPPLY
25°C
34
4
44
50
65
9
µA
µA
µA
µA
µA
µA
VDD = 22 V, VSS = –22 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–55°C to +125°C
25°C
VDD = 22 V, VSS = –22 V
Logic inputs = 0 V, 5 V, or VDD
12
25
ISS
VSS supply current
–40°C to +85°C
–55°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.9 ±20 V Dual Supply: Switching Characteristics
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
110
110
90
175
190
205
170
185
200
180
190
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–55°C to +125°C
25°C
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off Time
tON
Turn-on time from enable
Turn-off time from enable
Break-before-make time delay
–40°C to +85°C
–55°C to +125°C
25°C
(EN)
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off Time
tOFF
–40°C to +85°C
–55°C to +125°C
25°C
(EN)
55
VS = 10 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
1
1
tBBM
–40°C to +85°C
–55°C to +125°C
25°C
0.18
0.2
VDD rise time = 100ns
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
TON (VDD)
–40°C to +85°C
–55°C to +125°C
0.22
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
715
ps
VD = 0 V, CL = 1 nF
Refer to Charge Injection
QINJ
pC
–15
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Off Isolation
OISO
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
dB
dB
dB
dB
–75
–55
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
XTALK
–117
–106
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
VS = 0 V,
Refer to Bandwidth
BW
IL
25°C
25°C
38
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Insertion loss
–0.16
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–63
Refer to ACPSRR
VPP = 20 V, VBIAS = 0 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0005
Refer to THD + Noise
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
25°C
25°C
32
45
pF
pF
CS(ON),
CD(ON)
On capacitance
VS = 0 V, f = 1 MHz
25°C
146
pF
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MAX UNIT
6.10 44 V Single Supply: Electrical Characteristics
VDD = +44 V, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +44 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
ANALOG SWITCH
25°C
2.2
2.8
3.6
4.2
0.2
0.3
0.35
1
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = 0 V to 40 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–55°C to +125°C
25°C
0.1
0.2
VS = 0 V to 40 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
–40°C to +85°C
–55°C to +125°C
25°C
ΔRON
VS = 0 V to 40 V
ID = –10 mA
Refer to On-Resistance
1.3
1.5
RON FLAT
On-resistance flatness
–40°C to +85°C
–55°C to +125°C
VS = 22 V, IS = –10 mA
Refer to On-Resistance
RON DRIFT On-resistance drift
0.008
0.05
–55°C to +125°C
Ω/°C
VDD = 44 V, VSS = 0 V
Switch state is off
VS = 40 V / 1 V
25°C
5
nA
nA
–5
10
–40°C to +85°C
–10
IS(OFF)
Source off leakage current(1)
VD = 1 V / 40 V
Refer to Off-Leakage Current
35
nA
–55°C to +125°C
–35
VDD = 44 V, VSS = 0 V
Switch state is off
VS = 40 V / 1 V
VD = 1 V / 40 V
Refer to Off-Leakage Current
25°C
0.05
0.05
8
nA
nA
–8
12
–40°C to +85°C
–12
ID(OFF)
Drain off leakage current(1)
70
nA
–55°C to +125°C
–70
25°C
8
10
45
nA
nA
nA
–8
–10
–45
VDD = 44 V, VSS = 0 V
Switch state is on
VS = VD = 40 V or 1 V
Refer to On-Leakage Current
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–55°C to +125°C
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
44
0.8
2
V
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.005
µA
µA
pF
IIL
–1 –0.005
CIN
3
POWER SUPPLY
25°C
17
50
60
75
µA
µA
µA
VDD = 44 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–55°C to +125°C
(1) When VS is 40 V, VD is 1 V, or when VS is 1 V, VD is 40 V.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.11 44 V Single Supply: Switching Characteristics
VDD = +44 V, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +44 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
120
120
120
45
175
190
205
168
185
195
180
200
205
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–55°C to +125°C
25°C
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off Time
tON
Turn-on time from enable
Turn-off time from enable
Break-before-make time delay
–40°C to +85°C
–55°C to +125°C
25°C
(EN)
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off Time
tOFF
–40°C to +85°C
–55°C to +125°C
25°C
(EN)
VS = 18 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
1
1
tBBM
–40°C to +85°C
–55°C to +125°C
25°C
0.15
0.17
0.19
VDD rise time = 1µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
TON (VDD)
–40°C to +85°C
–55°C to +125°C
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
930
ps
VD = 22 V, CL = 1 nF
Refer to Charge Injection
QINJ
pC
–16
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Off Isolation
OISO
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
dB
dB
dB
dB
–75
–55
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
XTALK
–117
–106
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
VS = 6 V
Refer to Bandwidth
BW
IL
25°C
25°C
37
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Insertion loss
–0.18
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–60
Refer to ACPSRR
VPP = 22 V, VBIAS = 22 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0004
Refer to THD + Noise
CS(OFF)
CD(OFF)
CS(ON)
Source off capacitance
Drain off capacitance
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
25°C
25°C
34
48
pF
pF
,
On capacitance
VS = 6 V, f = 1 MHz
25°C
146
pF
CD(ON)
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MAX UNIT
6.12 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
ANALOG SWITCH
25°C
4.6
6
7.5
8.4
0.2
0.32
0.35
2
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = 0 V to 10 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–55°C to +125°C
25°C
0.08
1.2
VS = 0 V to 10 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
–40°C to +85°C
–55°C to +125°C
25°C
ΔRON
VS = 0 V to 10 V
IS = –10 mA
Refer to On-Resistance
2.2
2.4
RON FLAT
On-resistance flatness
–40°C to +85°C
–55°C to +125°C
VS = 6 V, IS = –10 mA
Refer to On-Resistance
RON DRIFT On-resistance drift
0.017
0.05
–55°C to +125°C
Ω/°C
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
25°C
0.5
2
nA
nA
–0.5
–2
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = 1 V / 10 V
Refer to Off-Leakage Current
12
nA
–55°C to +125°C
–12
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
VD = 1 V / 10 V
Refer to Off-Leakage Current
25°C
0.05
0.05
0.5
3
nA
nA
–0.5
–3
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
23
nA
–55°C to +125°C
–23
25°C
1.5
3
nA
nA
nA
–1.5
–3
VDD = 13.2 V, VSS = 0 V
Switch state is on
VS = VD = 10 V or 1 V
Refer to On-Leakage Current
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–55°C to +125°C
15
–15
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
44
0.8
2
V
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.005
µA
µA
pF
IIL
–1 –0.005
CIN
3
POWER SUPPLY
25°C
10
35
45
55
µA
µA
µA
VDD = 13.2 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–55°C to +125°C
(1) When VS is 10 V, VD is 1 V, or when VS is 1 V, VD is 10 V.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.13 12 V Single Supply: Switching Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
180
120
130
40
185
215
235
180
210
230
210
235
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–55°C to +125°C
25°C
VS = 8 V
tON
Turn-on time from enable
Turn-off time from enable
Break-before-make time delay
–40°C to +85°C
–55°C to +125°C
25°C
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off Time
(EN)
VS = 8 V
tOFF
–40°C to +85°C
–55°C to +125°C
25°C
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off Time
(EN)
VS = 8 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
1
1
tBBM
–40°C to +85°C
–55°C to +125°C
25°C
0.19
0.2
VDD rise time = 100ns
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
TON (VDD)
–40°C to +85°C
–55°C to +125°C
0.22
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
740
ps
VD = 6 V, CL = 1 nF
Refer to Charge Injection
QINJ
pC
–6
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Off Isolation
OISO
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
dB
dB
dB
dB
–75
–55
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
XTALK
–117
–106
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
VS = 6 V
Refer to Bandwidth
BW
IL
25°C
25°C
42
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Insertion loss
–0.3
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–65
Refer to ACPSRR
VPP = 6 V, VBIAS = 6 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0009
Refer to THD + Noise
CS(OFF)
CD(OFF)
CS(ON)
Source off capacitance
Drain off capacitance
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
25°C
25°C
38
56
pF
pF
,
On capacitance
VS = 6 V, f = 1 MHz
25°C
150
pF
CD(ON)
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6.14 Typical Characteristics
at TA = 25°C
图6-1. On-Resistance vs Source or Drain Voltage –Dual
图6-2. On-Resistance vs Source or Drain Voltage –Dual
Supply
Supply
图6-3. On-Resistance vs Source or Drain Voltage –Single
图6-4. On-Resistance vs Source or Drain Voltage –Single
Supply
Supply
6
6
TA = 125C
TA = 85C
TA = 125C
TA = 85C
5
5
TA = 25C
TA = 25C
TA = −55C
TA = −55C
4
4
3
2
1
0
3
2
1
0
-15 -12
-9
-6
-3
0
3
6
9
12
15
-20
-15
-10
-5
0
5
10
15
20
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
VDD = 15 V, VSS = -15 V
VDD = 20 V, VSS = -20 V
图6-5. On-Resistance vs Temperature
图6-6. On-Resistance vs Temperature
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6.14 Typical Characteristics (continued)
at TA = 25°C
10
6
5
4
3
2
1
0
TA = 125C
TA = 125C
TA = 85C
TA = 25C
TA = −55C
9
8
7
6
5
4
3
2
1
TA = 85C
TA = 25C
TA = −55C
0
2
4
6
8
10
12
0
4
8
12
16
20
24
28
32
36
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
图6-7. On-Resistance vs Temperature
图6-8. On-Resistance vs Temperature
25
20
15
10
5
ID(OFF) VS/VD = −10 V/10 V
ID(OFF) VS/VD = 10 V/−10 V
I
ON −10 V
ION 10 V
IS(OFF) VS/VD = −10 V/10 V
IS(OFF) VS/VD = 10 V/−10 V
0
-5
-10
-15
-20
-25
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
D011
VDD = 15 V, VSS = -15 V
VDD = 20 V, VSS = -20 V
图6-10. Leakage Current vs Temperature
图6-9. Leakage Current vs Temperature
40
30
ID(OFF) VS/VD = 1 V/30 V
ID(OFF) VS/VD = 30 V/1 V
I(ON) 1 V
I(ON) 30 V
20
IS(OFF) VS/VD = 1 V/30 V
IS(OFF) VS/VD = 30 V/1 V
10
0
-10
-20
-30
-40
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
D013
VDD = 36 V, VSS = 0 V
图6-11. Leakage Current vs Temperature
VDD = 12 V, VSS = 0 V
图6-12. Leakage Current vs Temperature
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6.14 Typical Characteristics (continued)
at TA = 25°C
100
80
60
40
20
0
VDD = 20 V, VSS = -20 V
VDD = 15 V, VSS = œ15 V
VDD = 5 V, VSS = œ5 V
-20
-40
-60
-20
-15
-10
-5
0
5
Source Voltage (V)
10
15
20
D016
图6-13. Supply Current vs Logic Voltage
图6-14. Charge Injection vs Source Voltage –Dual Supply
图6-15. Charge Injection vs Drain Voltage –Dual Supply
图6-16. Charge Injection vs Source Voltage –Single Supply
140
Transition Falling
Transition Rising
135
130
125
120
115
110
105
100
95
90
85
80
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature(C)
D020
VDD = 15 V, VSS = -15 V
图6-18. TTRANSITION vs Temperature
图6-17. Charge Injection vs Drian Voltage –Single Supply
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6.14 Typical Characteristics (continued)
at TA = 25°C
140
140
135
130
125
120
115
110
105
100
95
Transiton_Falling
Transiton_Rising
T(OFF)
T(ON)
135
130
125
120
115
110
105
100
95
90
85
80
90
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
-55
-30
-5
20
45
70
95
120
Temperature(C)
Temperature (C)
VDD = 44 V, VSS = 0 V
VDD = 15 V, VSS = -15 V
图6-20. TON and TOFF vs Temperature
图6-19. TTRANSITION vs Temperature
160
155
150
145
140
135
130
125
120
115
110
105
100
95
T(OFF)
T(ON)
90
85
80
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
VDD = 44 V, VSS = 0 V
图6-21. TON and TOFF vs Temperature
图6-22. Off-Isolation vs Frequency
Switch ON (EN = 1)
Switch OFF (EN = 0)
图6-23. Crosstalk vs Frequency
图6-24. Crosstalk vs Frequency
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6.14 Typical Characteristics (continued)
at TA = 25°C
图6-25. THD+N vs Frequency (Dual Supply)
图6-26. THD+N vs Frequency (Single Supply)
VDD = 15 V, VSS = -15 V
VDD = +15 V, VSS = -15 V
图6-27. On Response vs Frequency
图6-28. ACPSRR vs Frequency
VDD = +15 V, VSS = -15 V
VDD = 12 V, VSS = 0 V
图6-29. Capacitance vs Source Voltage or Drain Voltage
图6-30. Capacitance vs Source Voltage or Drain Voltage
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. 图 7-1 shows the measurement setup used to measure RON. Voltage (V) and current (ISD) are
measured using the following setup, where RON is computed as RON = V / ISD
:
V
ISD
Sx
Dx
VS
图7-1. On-Resistance
7.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current.
2. Drain off-leakage current.
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
图7-2 shows the setup used to measure both off-leakage currents.
.
.
VDD
VSS
VDD
VSS
Is (OFF)
ID (OFF)
S1
S2
S1
S2
A
D
D
A
VS
VS
VD
VD
GND
GND
IS(OFF)
ID(OFF)
图7-2. Off-Leakage Measurement Setup
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VSS
VDD
VSS
Is (ON)
ID (ON)
S1
S2
S1
S2
N.C.
A
D
D
A
N.C.
VS
VS
VS
GND
GND
IS(ON)
ID(ON)
图7-3. On-Leakage Measurement Setup
7.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 90% after the address signal
has risen or fallen past the logic threshold. The 90% transition measurement is utilized to provide the timing of
the device. System level timing can then account for the time constant added from the load resistance and load
capacitance. 图7-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION
.
VDD
VSS
0.1 µF
0.1 µF
VS
3 V
0 V
VDD
VSS
VSEL
tr < 20 ns
tf < 20 ns
50%
50%
S1
S2
D
Output
CL
tTRANSITION
tTRANSITION
90%
RL
SEL
Output
10%
GND
VSEL
0 V
图7-4. Transition-Time Measurement Setup
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7.5 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 7-5
shows the setup used to measure turn-on time, denoted by the symbol tON(EN)
.
Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 7-5
shows the setup used to measure turn-off time, denoted by the symbol tOFF(EN)
.
VDD
VSS
0.1 µF
0.1 µF
3 V
VDD
VSS
VEN
tr < 20 ns
tf < 20 ns
50%
50%
S1
S2
VS
0 V
D
Output
CL
tON
tOFF
90%
RL
EN
Output
10%
GND
VEN
0 V
图7-5. Turn-On and Turn-Off Time Measurement Setup
7.6 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图7-6 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
VSS
0.1 µF
0.1 µF
3 V
VDD
VSS
VSEL
tr < 20 ns
tf < 20 ns
S1
S2
VS
0 V
D
Output
CL
RL
80%
SEL
Output
0 V
tBBM
1
tBBM 2
VSEL
GND
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
图7-6. Break-Before-Make Delay Measurement Setup
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7.7 tON (VDD) Time
The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has
risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in
the system. 图7-7 shows the setup used to measure turn on time, denoted by the symbol tON (VDD)
.
VSS
0.1 µF
0.1 µF
VDD
Supply
Ramp
VDD
VDD
VSS
tr = 10 µs
4.5 V
VS
S2
S1
0 V
D
Output
CL
tON
90%
RL
EN
Output
3 V
SEL
GND
0 V
图7-7. tON (VDD) Time Measurement Setup
7.8 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. 图 7-8 shows the setup used to measure propagation delay, denoted
by the symbol tPD
.
VDD
VSS
0.1 µF
0.1 µF
250 mV
Input
VDD
S1
S2
VSS
50%
50%
tr < 40 ps
(VS)
tf < 40 ps
50 Ω
VS
0 V
D
Output
CL
tPD
1
tPD 2
RL
Output
0 V
50%
50%
GND
tProp Delay = max ( tPD 1, tPD 2)
图7-8. Propagation Delay Measurement Setup
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7.9 Charge Injection
The TMUX7219M has a transmission-gate topology. Any mismatch in capacitance between the NMOS and
PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate
signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QC. 图 7-9 shows the setup used to measure charge injection from source (Sx) to drain
(D).
VDD
VSS
0.1 µF
0.1 µF
3 V
VEN
VDD
VSS
tr < 20 ns
tf < 20 ns
Output
S1
S2
D
0 V
VD
CL
N.C.
Output
VD
EN
VOUT
QINJ = CL ×
VOUT
VEN
GND
图7-9. Charge-Injection Measurement Setup
7.10 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. 图 7-10 shows the setup used to measure, and the equation used to calculate
off isolation.
VDD
VSS
0.1 µF
0.1 µF
Network Analyzer
VDD
VSS
VS
S1
D
50
VOUT
VSIG
50
S2
50
GND
图7-10. Off Isolation Measurement Setup
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7.11 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. 图 7-11 shows the setup used to measure, and the equation used to
calculate crosstalk.
VDD
VSS
0.1 µF
0.1 µF
Network Analyzer
VDD
VSS
VS
S1
S2
D
50
VOUT
50
50
VSIG
GND
图7-11. Crosstalk Measurement Setup
7.12 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 7-12
shows the setup used to measure bandwidth.
VDD
VSS
0.1 µF
0.1 µF
Network Analyzer
VDD
VSS
VS
S1
D
50
VOUT
VSIG
50
S2
50
GND
图7-12. Bandwidth Measurement Setup
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7.13 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
mux output.
The on-resistance of the device varies with the amplitude of the input signal and results in distortion when the
drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as THD + N.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Audio Precision
S1
D
40
VOUT
VS
RL
Other
Sx pins
50
GND
图7-13. THD + N Measurement Setup
7.14 Power Supply Rejection Ratio (PSRR)
PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage
pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave
of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the
ACPSRR. A high ratio represents a high degree of tolerance to supply rail variation.
This helps stabilize the supply and immediately filter as much of the supply noise as possible.
VDD
Network Analyzer
VSS
DC Bias
Injector
With and Without
Capacitor
50 Ω
0.1 µF
0.1 µF
VDD
S1
VSS
620 mVPP
VIN
VBIAS
50 Ω
S2
50 Ω
VOUT
D
CL
RL
GND
图7-14. ACPSRR Measurement Setup
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8 Detailed Description
8.1 Overview
The TMUX7219M is a 2:1, 1-channel switch. Each input is turned on or turned off based on the state of the
select line and enable pin.
8.2 Functional Block Diagram
The following figure shows the functional block diagram of the TMUX7219M.
VSS
VDD
S1
S2
D
Decoder
EN SEL
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX7219M conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
8.3.2 Rail-to-Rail Operation
The valid signal path input and output voltage for TMUX7219M ranges from VSS to VDD
.
8.3.3 1.8 V Logic Compatible Inputs
The TMUX7219M has 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs allows the
device to interface with processors that have lower logic I/O rails and eliminates the need for an external
translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations refer to
Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.4 Integrated Pull-Up and Pull-Down Resistor on Logic Pins
The TMUX7219M has internal weak pull-up and pull-down resistors to GND to ensure the logic pins are not left
floating. The value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1 µA at higher
voltages. The EN pin integrates a pull-up resistor to VDD and the SEL pin integrates a pull-down resistor. This
feature integrates up to two external components and reduces system size and cost.
8.3.5 Fail-Safe Logic
The TMUX7219M supports Fail-Safe Logic on the control input pins (EN and SEL) allowing for operation up to
44 V above ground, regardless of the state of the supply pins. This feature allows voltages on the control pins to
be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system
complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-
Safe Logic feature allows the logic input pins of the TMUX7219M to be ramped to +44 V while VDD and VSS = 0
V. The logic control inputs are protected against positive faults of up to +44 V in powered-off condition, but do not
offer protection against negative overvoltage conditions.
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8.3.6 Latch-Up Immune
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
The TMUX72xx family of devices are constructed on Silicon on Insulator (SOI) based process where an oxide
layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures
from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events
due to overvoltage or current injections. The latch-up immunity feature allows the TMUX72xx family of switches
and multiplexers to be used in harsh environments. For more information on latch-up immunity refer to Using
Latch Up Immune Multiplexers to Help Improve System Reliability.
8.3.7 Ultra-Low Charge Injection
图 8-1 shows how the TMUX7219M has a transmission gate topology. Any mismatch in the stray capacitance
associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
OFF ON
CGDN
CGSN
D
S
CGSP
CGDP
OFF ON
图8-1. Transmission Gate Topology
The TMUX7219M contains specialized architecture to reduce charge injection on the source (Sx). To further
reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the drain (D).
This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on
the drain (D) instead of the source (Sx). As a general rule, Cp should be 20× larger than the equivalent load
capacitance on the source (Sx). 图 8-2 shows charge injection variation with source voltage with different
compensation capacitors on the drain side.
图8-2. Charge Injection Compensation
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8.4 Device Functional Modes
When the EN pin of the TMUX7219M is pulled high, one of the switches is closed based on the state of the SEL
pin. When the EN pin is pulled low, both of the switches are in an open state regardless of the state of the SEL
pin. The control pins can be as high as 44 V.
The TMUX7219M can operate without any external components except for the supply decoupling capacitors.
The EN pin has an internal pull-up resistor of 4 MΩ, and SEL pin has internal pull-down resistor of 4 MΩ. If
unused, EN pin must be tied to VDD and SEL pin must be tied to GND to ensure the device does not consume
additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (S1,
S2, or D) should be connected to GND.
8.5 Truth Tables
表8-1 show the truth tables for the TMUX7219M.
表8-1. TMUX7219M Truth Table
EN SEL
Selected Source Connected To Drain (D) Pin
0
1
1
X(1)
All sources are off (HI-Z)
0
S1
S2
1
(1) X denotes do not care.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
TMUX7219M is part of the precision switches and multiplexers family of devices. TMUX7219M offers low RON,
low on and off leakage currents, and ultra-low charge injection performance. These properties make
TMUX7219M ideal for implementing high precision industrial systems requiring selection of one of two inputs or
outputs.
9.2 Typical Applications
9.2.1 Data Acquisition Calibration
One application of the TMUX7219M is in Data Acquisition systems (DAQ). To account for system loss and
ensure the lowest possible noise floor, a calibration path is needed. To minimize board space and automate this
procedure, many applications utilize a 2:1 (SPDT) switch. 图 9-1 shows the TMUX7219M configured for
switching a calibration path on a precision measurement module.
VDD
VSS
0.1 µF
0.1 µF
Inputs
Module
Voltage Input
S1
S2
D
+
Calibra on Path
To µC
SEL
OPA228
-
Precision
ADC
Precision
DAC
图9-1. Calibration Path Switching for Data Acquisition
9.2.1.1 Design Requirements
For the design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
PARAMETERS
Supply (VDD
Supply (VSS
VALUES
15 V
)
)
-15 V
MUX I/O signal range
Control logic thresholds
EN
-15 V to 15 V (Rail-to-Rail)
1.8 V compatiable (up to 44V)
EN pulled high to enable the switch
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9.2.1.2 Detailed Design Procedure
The TMUX7219M can be operated without any external components except for the supply decoupling
capacitors. All inputs passing through the switch must fall within the recommended operating conditions,
including signal range and continuous current. For this design, with a dual supply of ±15 V, the signal range can
range from -15 V to +15 V. Industrial applications such as factory automation and control and test and
measurement benefit from using a 2:1 switch, because it allows additional flexibility in the design. A single 2:1
switch has numerous applications such as switching between an analog signal path and a calibration path, and
allowing a single channel to be configured as either an analog input or analog output.
10 Power Supply Recommendations
The TMUX7219M operates across a wide supply range of ±4.5 V to ±22 V (4.5 V to 44 V in single-supply mode).
The device also performs well with asymmetrical supplies such as VDD = 12 V and VSS = –5 V.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the
VDD and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as
possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs)
that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply
decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use
of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple
vias in parallel lowers the overall inductance and is beneficial for connections to ground and power planes.
Always ensure the ground (GND) connection is established before supplies are ramped.
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11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
2W
1W min.
W
图11-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
Figure 11-2 illustrates an example of a PCB layout with the TMUX7219M. Some key considerations are:
• For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD/VSS and
GND. TI recommends placing the lowest value capacitor as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the supply voltage.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground
planes.
11.2 Layout Example
S2
VSS
SEL
EN
D
TMUX7219M
S1
GND
VDD
Wide (low inductance)
trace for power
C
C
Wide (low inductance)
trace for power
Via to ground plane
图11-2. TMUX7219MDGK Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief
• Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment application brief
• Texas Instruments, Multiplexers and Signal Switches Glossary application report
• Texas Instruments, QFN/SON PCB Attachment application report
• Texas Instruments, Quad Flatpack No-Lead Logic Packages application report
• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief
• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
32
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Product Folder Links: TMUX7219M
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX7219MDGKR
ACTIVE
VSSOP
DGK
8
2500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
X219
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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