TMUX6208 [TI]
TMUX620x 36 V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers with 1.8 V Logic;
| 型号： | TMUX6208 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMUX620x 36 V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers with 1.8 V Logic |
| 文件： | 总51页 (文件大小：3601K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX6208, TMUX6209
SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021
TMUX620x 36 V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers
with 1.8 V Logic
1 Features
3 Description
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•
•
•
•
•
Single supply range: 4.5 V to 36 V
Dual supply range: ±4.5 V to ±18 V
Low on-resistance: 4 Ω
The TMUX6208 is a precision 8:1, single channel
multiplexer while the TMUX6209 is a 4:1, 2 channel
multiplexer featuring low on resistance and charge
injection. The devices work with a single supply (4.5 V
to 36 V), dual supply (±4.5 V to ±18 V), or asymmetric
supply (such as VDD = 12 V, VSS = –5 V). The
TMUX620x supports bidirectional analog and digital
signals onthe source (Sx) and drain (D) pins ranging
Low charge injection: 3 pC
High current support: 400 mA (maximum) (WQFN)
High current support: 300 mA (maximum)
(TSSOP)
–40°C to +125°C operating temperature
1.8 V logic compatible inputs
Integrated pull-down resistor on logic pins
Fail-safe logic
Rail-to-rail operation
Bidirectional signal path
Break-before-make switching
•
•
•
•
•
•
•
from VSS to VDD
.
All logic control inputs support logic high levels
from 1.8 V to VDD, ensuring both TTL and CMOS
logic compatibility when operating in the valid
supply voltage range. Fail-Safe Logic circuitry allows
voltages on the control pins to be applied before
the supply pin, protecting the device from potential
damage.
2 Applications
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•
•
•
•
•
•
•
•
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•
Factory automation and control
Programmable logic controllers (PLC)
Analog input modules
Semiconductor test equipment
Battery test equipment
Ultrasound scanners
Patient monitoring and diagnostics
Optical networking
The TMUX620x are part of the precision switches and
multiplexers family of devices. These devices have
very low on and off leakage currents and low charge
injection, allowing them to be used in high precision
measurement applications.
Device Information(1)
PART NUMBER
PACKAGE
TSSOP (16) (PW)
WQFN (16) (RUM)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
4.00 mm × 4.00 mm
Optical test equipment
Wired networking
Data acquisition systems (DAQ)
TMUX6208
TMUX6209
(1) For all available packages, see the package option
addendum at the end of the data sheet.
VDD
VSS
VDD
VSS
SW
SW
S1
S2
S1A
SW
DA
DB
SW
SW
S4A
S1B
D
SW
SW
S4B
S8
A0
A1
A2
A0
A1
EN
Logic Decoder
EN
Logic Decoder
TMUX6208
TMUX6209
TMUX6208 and TMUX6209 Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX6208, TMUX6209
SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Thermal Information ...................................................6
7.4 Recommended Operating Conditions ........................6
7.5 Source or Drain Continuous Current ..........................6
7.6 ±15 V Dual Supply: Electrical Characteristics ...........7
7.7 ±15 V Dual Supply: Switching Characteristics ..........8
7.8 36 V Single Supply: Electrical Characteristics ........ 10
7.9 36 V Single Supply: Switching Characteristics ........11
7.10 12 V Single Supply: Electrical Characteristics ...... 13
7.11 12 V Single Supply: Switching Characteristics ......14
7.12 ±5 V Dual Supply: Electrical Characteristics .........16
7.13 ±5 V Dual Supply: Switching Characteristics ........17
7.14 Typical Characteristics............................................19
8 Parameter Measurement Information..........................24
8.1 On-Resistance.......................................................... 24
8.2 Off-Leakage Current................................................. 24
8.3 On-Leakage Current................................................. 25
8.4 Transition Time......................................................... 25
8.5 tON(EN) and tOFF(EN) .................................................. 26
8.6 Break-Before-Make...................................................26
8.7 tON (VDD) Time............................................................27
8.8 Propagation Delay.................................................... 27
8.9 Charge Injection........................................................28
8.10 Off Isolation.............................................................28
8.11 Crosstalk................................................................. 29
8.12 Bandwidth............................................................... 29
8.13 THD + Noise........................................................... 30
8.14 Power Supply Rejection Ratio (PSRR)...................30
9 Detailed Description......................................................31
9.1 Overview...................................................................31
9.2 Functional Block Diagram.........................................31
9.3 Feature Description...................................................31
9.4 Device Functional Modes..........................................33
9.5 Truth Tables.............................................................. 33
10 Application and Implementation................................34
10.1 Application Information........................................... 34
10.2 Typical Application.................................................. 34
10.3 Design Requirements............................................. 35
10.4 Detailed Design Procedure.....................................35
10.5 Application Curve....................................................36
11 Power Supply Recommendations..............................36
12 Layout...........................................................................37
12.1 Layout Guidelines................................................... 37
12.2 Layout Example...................................................... 38
13 Device and Documentation Support..........................39
13.1 Documentation Support.......................................... 39
13.2 Receiving Notification of Documentation Updates..39
13.3 Support Resources................................................. 39
13.4 Trademarks.............................................................39
13.5 Electrostatic Discharge Caution..............................39
13.6 Glossary..................................................................39
14 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2021) to Revision C (August 2021)
Page
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Changed the status of the QFN package for the TMUX6208 and TMUX6209 from: preview to: active ............1
Added ESD detail for RUM package.................................................................................................................. 5
Added the Integrated Pull-Down Resistor on Logic Pins section......................................................................31
Updated the Ultra-Low Charge Injection section.............................................................................................. 32
Updated the TMUX620x Layout Example figures in the Layout Example section............................................38
Changes from Revision A (January 2021) to Revision B (April 2021)
Page
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Added thermal information for QFN package..................................................................................................... 6
Added IDC specs for QFN package in Source or Drain Continuous Current table .............................................6
Updated VDD rise time value from 100ns to 1µs in TON(VDD) test condition........................................................ 8
Updated CL value from 1nF to 100pF in Charge Injection test condition............................................................8
Changes from Revision * (November 2020) to Revision A (January 2021)
Page
•
Changed the document status From: Advanced Information To: Production Data ............................................1
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SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021
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5 Device Comparison Table
PRODUCT
TMUX6208
TMUX6209
DESCRIPTION
Low-Leakage-Current, Precision, 8:1, 1-Ch. multiplexer
Low-Leakage-Current, Precision, 4:1, 2-Ch. multiplexer
6 Pin Configuration and Functions
A0
EN
VSS
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
A2
GND
VDD
S5
VSS
S1
1
2
3
4
12
11
10
9
GND
VDD
S5
Thermal
Pad
S2
S2
S3
S6
S3
S6
S4
S7
D
S8
Not to scale
Not to scale
Figure 6-2. TMUX6208: RUM Package 16-Pin WQFN
Top View
Figure 6-1. TMUX6208: PW Package 16-Pin TSSOP
Top View
Table 6-1. TMUX6208 Pin Functions
NAME
PW NO.
RUM NO.
TYPE(1)
DESCRIPTION(2)
Logic control input, has internal 4 MΩ pull-down resistor. Controls the switch configuration
as shown in Section 9.5.
A0
1
15
I
Logic control input, has internal 4 MΩ pull-down resistor. Controls the switch configuration
as shown in Section 9.5.
A1
16
14
I
Logic control input, has internal 4 MΩ pull-down resistor. Controls the switch configuration
as shown in Section 9.5.
A2
D
15
8
13
6
I
I/O
Drain pin. Can be an input or output.
Active high logic enable, has internal 4 MΩ pull-down resistor. When this pin is low, all
switches are turned off. When this pin is high, the Ax logic input determines which switch
is turned on.
EN
2
16
I
GND
S1
S2
S3
S4
S5
S6
S7
S8
14
4
12
2
P
Ground (0 V) reference.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Source pin 1. Can be an input or output.
Source pin 2. Can be an input or output.
Source pin 3. Can be an input or output.
Source pin 4. Can be an input or output.
Source pin 5. Can be an input or output.
Source pin 6. Can be an input or output.
Source pin 7. Can be an input or output.
Source pin 8. Can be an input or output.
5
3
6
4
7
5
12
11
10
9
10
9
8
7
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VDD and
GND.
VDD
13
3
11
1
P
P
Negative power supply. This pin is the most negative power-supply potential. In single-
supply applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 μF to 10 μF between VSS and GND.
VSS
The thermal pad is not connected internally. No requirement to solder this pad, if
connected it is recommended that the pad be left floating or tied to GND.
Thermal Pad
—
(1) I = input, O = output, I/O = input and output, P = power.
(2) Refer to Section 9.4 for what to do with unused pins.
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A0
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
GND
VDD
S1B
S2B
S3B
S4B
DB
VSS
S1A
S2A
S3A
S4A
DA
VSS
S1A
S2A
S3A
1
2
3
4
12
11
10
9
VDD
S1B
S2B
S3B
Thermal
Pad
Not to scale
Not to scale
Figure 6-4. TMUX6209: RUM Package 16-Pin WQFN
Top View
Figure 6-3. TMUX6209: PW Package 16-Pin TSSOP
Top View
Table 6-2. TMUX6209 Pin Functions
NAME
PW NO.
RUM NO.
TYPE(1)
DESCRIPTION(2)
Logic control input, has internal pull-down resistor. Controls the switch configuration as
shown in Section 9.5.
A0
1
15
I
Logic control input, has internal pull-down resistor. Controls the switch configuration as
shown in Section 9.5.
A1
16
14
I
DA
DB
8
9
6
7
I/O
I/O
Drain Terminal A. Can be an input or an output.
Drain Terminal B. Can be an input or an output.
Active high logic enable, has internal pull-up resistor. When this pin is low, all switches are
turned off. When this pin is high, the Ax logic input determines which switch is turned on.
EN
2
16
I
GND
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
15
4
13
2
P
Ground (0 V) reference.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Source pin 1A. Can be an input or output.
Source pin 1B. Can be an input or output.
Source pin 2A. Can be an input or output.
Source pin 2B. Can be an input or output.
Source pin 3A. Can be an input or output.
Source pin 3B. Can be an input or output.
Source pin 4A. Can be an input or output.
Source pin 4B. Can be an input or output.
13
5
11
3
12
6
10
4
11
7
9
5
10
8
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VDD and
GND.
VDD
14
3
12
1
P
Negative power supply. This pin is the most negative power-supply potential. In single-
supply applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 μF to 10 μF between VSS and GND.
VSS
P
The thermal pad is not connected internally. No requirement to solder this pad, if
connected it is recommended that the pad be left floating or tied to GND.
Thermal Pad
__
(1) I = input, O = output, I/O = input and output, P = power.
(2) Refer to Section 9.4 for what to do with unused pins.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
38
UNIT
VDD – VSS
V
V
V
VDD
VSS
Supply voltage
–0.5
–38
38
0.5
VADDRESS or
VEN
Logic control input pin voltage (EN, A0, A1, A2)
–0.5
38
V
IADDRESS or IEN Logic control input pin current (EN, A0, A1, A2)
–30
VSS–0.5
–30
30
VDD+0.5
30
mA
V
VS or VD
Source or drain voltage (Sx, D)
Diode clamp current(3)
IIK
mA
mA
°C
IS or ID (CONT)
Source or drain continuous current (Sx, D)
Ambient temperature
IDC + 10 %(4)
TA
–55
–65
150
Tstg
TJ
Storage temperature
150
°C
Junction temperature
150
°C
Total power dissipation (QFN package)(5)
Total power dissipation (TSSOP package)(5)
1650
mW
mW
Ptot
700
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
(4) Refer to Source or Drain Continuous Current table for IDC specifications.
(5) For QFN package: Ptot derates linearily above TA = 70°C by 24.4mW/°C.
For TSSOP package: Ptot derates linearily above TA = 70°C by 10.8mW/°C.
7.2 ESD Ratings
VALUE
UNIT
TMUX6208 in PW package
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
±500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
TMUX6209 in PW package
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1500
±500
V(ESD)
Electrostatic discharge
V
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
TMUX6208 and TMUX6209 in RUM package
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1000
±500
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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UNIT
SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021
7.3 Thermal Information
TMUX620x
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
93.5
RUM (WQFN)
16 PINS
41.2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
24.9
24.5
40.0
16.1
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.0
0.2
ΨJB
39.4
16.1
RθJC(bot)
N/A
2.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
(1)
VDD – VSS
VDD
Power supply voltage differential
V
V
V
Positive power supply voltage
4.5
36
VS or VD
Signal path input/output voltage (source or drain pin) (Sx, D)
VSS
VDD
VADDRESS or
VEN
Address or enable pin voltage
0
36
V
(2)
IS or ID (CONT) Source or drain continuous current (Sx, D)
TA Ambient temperature
IDC
mA
°C
–40
125
(1) VDD and VSS can be any value as long as 4.5 V ≤ (VDD – VSS) ≤ 36 V, and the minimum VDD is met.
(2) Refer to Source or Drain Continuous Current table for IDC specifications.
7.5 Source or Drain Continuous Current
at supply voltage of VDD ± 10%, VSS ± 10 % (unless otherwise noted)
CONTINUOUS CURRENT PER CHANNEL (IDC
PACKAGE TEST CONDITIONS
±15 V Dual Supply
)
TA = 25°C
TA = 85°C
190
TA = 125°C
UNIT
300
110
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
+36 V Single Supply(1)
+12 V Single Supply
±5 V Dual Supply
280
220
210
170
400
380
310
300
230
170
150
140
110
230
220
190
190
150
100
90
PW (TSSOP)
RUM (WQFN)
90
+5 V Single Supply
±15 V Dual Supply
+36 V Single Supply(1)
+12 V Single Supply
±5 V Dual Supply
70
120
110
100
100
90
+5 V Single Supply
(1) Specified for nominal supply voltage only.
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7.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
4
5.9
7.4
8.7
0.7
0.8
0.9
1.5
1.7
1.8
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = –10 V to +10 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
0.2
0.4
VS = –10 V to +10 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
VS = –10 V to +10 V
IS = –10 mA
Refer to On-Resistance
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
VS = 0 V, IS = –10 mA
Refer to On-Resistance
–40°C to +125°C
0.02
0.04
Ω/°C
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
25°C
–0.4
–1
0.4
1
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = –10 V / + 10 V
Refer to Off-Leakage Current
–40°C to +125°C
–5
5
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
Refer to Off-Leakage Current
25°C
–0.4
–6
0.04
0.04
0.4
6
nA
nA
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
–40°C to +125°C
–42
42
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
25°C
–0.4
–5
0.4
5
nA
nA
nA
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
–40
40
Refer to On-Leakage Current
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
IIH
Logic voltage high
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
1.3
0
36
0.8
1.2
V
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.4
µA
µA
pF
IIL
–0.1 –0.005
3.5
CIN
POWER SUPPLY
25°C
35
3
57
60
75
14
15
22
µA
µA
µA
µA
µA
µA
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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7.7 ±15 V Dual Supply: Switching Characteristics
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
140
195
220
240
195
220
240
268
285
298
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 10 V
tTRAN
Transition time from control input RL = 300 Ω, CL = 35 pF
Refer to Transition Time
–40°C to +85°C
–40°C to +125°C
25°C
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
140
200
60
–40°C to +85°C
–40°C to +125°C
25°C
tON
Turn-on time from enable
(EN)
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
–40°C to +85°C
–40°C to +125°C
25°C
tOFF
Turn-off time from enable
(EN)
VS = 10 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
tBBM
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
1
1
0.16
0.17
0.17
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
TON (VDD)
–40°C to +85°C
–40°C to +125°C
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
1.8
3
ns
VS = 0 V, CL = 100 pF
Refer to Charge Injection
QINJ
pC
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Off Isolation
OISO
OISO
XTALK
XTALK
BW
Off-isolation
25°C
25°C
25°C
25°C
25°C
–82
–62
–85
–65
30
dB
dB
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
Crosstalk
dB
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1MHz
Refer to Crosstalk
Crosstalk
dB
RL = 50 Ω , CL = 5 pF
VS = 0 V
–3dB Bandwidth (TMUX6208)
MHz
Refer to Bandwidth
RL = 50 Ω , CL = 5 pF
VS = 0 V
Refer to Bandwidth
BW
IL
–3dB Bandwidth (TMUX6209)
Insertion loss
25°C
25°C
52
MHz
dB
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
–0.35
VPP = 0.62 V on VDD and VSS
RL = 50 Ω , CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
–74
dB
%
Refer to ACPSRR
VPP = 15 V, VBIAS = 0 V
RL = 10 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
Source off capacitance
0.0003
Refer to THD + Noise
CS(OFF)
CD(OFF)
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
25°C
25°C
15
pF
pF
Drain off capacitance
(TMUX6208)
135
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7.7 ±15 V Dual Supply: Switching Characteristics (continued)
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
Drain off
capacitance (TMUX6209)
CD(OFF)
VS = 0 V, f = 1 MHz
25°C
25°C
25°C
68
pF
CS(ON),
CD(ON)
On capacitance (TMUX6208)
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
185
115
pF
pF
CS(ON),
CD(ON)
On capacitance (TMUX6209)
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7.8 36 V Single Supply: Electrical Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
4
6.2
7.9
9.4
0.7
0.8
0.9
1.8
2.5
3.1
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = 0 V to 30 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
0.2
0.4
VS = 0 V to 30 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
VS = 0 V to 30 V
IS = –10 mA
Refer to On-Resistance
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
VS = 18 V, IS = –10 mA
Refer to On-Resistance
–40°C to +125°C
0.015
0.04
Ω/°C
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
25°C
–0.4
–2
0.4
2
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = 1 V / 30 V
Refer to Off-Leakage Current
–40°C to +125°C
–10
10
nA
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
VD = 1 V / 30 V
Refer to Off-Leakage Current
25°C
–0.5
–12
0.05
0.05
0.5
12
nA
nA
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
–40°C to +125°C
–85
85
nA
VDD = 39.6 V, VSS = 0 V
Switch state is on
VS = VD = 30 V or 1 V
Refer to On-Leakage Current
25°C
–0.5
–11
–78
0.5
11
nA
nA
nA
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
78
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
IIH
Logic voltage high
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
1.3
0
36
0.8
1.2
V
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.4
µA
µA
pF
IIL
–0.1 –0.005
3.5
CIN
POWER SUPPLY
25°C
55
86
90
µA
µA
µA
VDD = 39.6 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
105
(1) When VS is positive, VD is negative, and vice versa.
(2) When VS is at a voltage potential, VD is floating, and vice versa.
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7.9 36 V Single Supply: Switching Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
105
200
225
240
200
220
240
290
305
315
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 18 V
tTRAN
Transition time from control input RL = 300 Ω, CL = 35 pF
Refer to Transition Time
–40°C to +85°C
–40°C to +125°C
25°C
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
115
90
–40°C to +85°C
–40°C to +125°C
25°C
tON
Turn-on time from enable
(EN)
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
–40°C to +85°C
–40°C to +125°C
25°C
tOFF
Turn-off time from enable
(EN)
40
VS = 18 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
tBBM
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
1
1
0.14
0.15
0.15
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
TON (VDD)
–40°C to +85°C
–40°C to +125°C
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
2.5
2
ns
VS = 18 V, CL = 100 pF
Refer to Charge Injection
QINJ
pC
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
OISO
XTALK
XTALK
BW
Off-isolation
25°C
25°C
25°C
25°C
–62
–85
–65
30
dB
dB
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1MHz
Refer to Crosstalk
Crosstalk
dB
RL = 50 Ω , CL = 5 pF
VS = 6 V
–3dB Bandwidth (TMUX6208)
MHz
Refer to Bandwidth
RL = 50 Ω , CL = 5 pF
VS = 6 V
BW
IL
–3dB Bandwidth (TMUX6209)
Insertion loss
25°C
25°C
50
MHz
dB
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
–0.35
VPP = 0.62 V on VDD and VSS
RL = 50 Ω , CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
–70
dB
%
Refer to ACPSRR
VPP =18 V, VBIAS = 18 V
RL = 10 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
Source off capacitance
0.0003
Refer to THD + Noise
CS(OFF)
CD(OFF)
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
25°C
25°C
15
pF
pF
Drain off capacitance
(TMUX6208)
138
Drain off
capacitance (TMUX6209)
CD(OFF)
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
25°C
25°C
68
pF
pF
CS(ON),
CD(ON)
On capacitance (TMUX6208)
185
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7.9 36 V Single Supply: Switching Characteristics (continued)
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CS(ON),
CD(ON)
On capacitance (TMUX6209)
VS = 18 V, f = 1 MHz
25°C
115
pF
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7.10 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
7
11.8
14.2
16.5
0.7
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = 0 V to 10 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
0.2
1.7
VS = 0 V to 10 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
0.8
0.9
3.4
VS = 0 V to 10 V
IS = –10 mA
Refer to On-Resistance
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
3.8
4.6
VS = 6 V, IS = –10 mA
Refer to On-Resistance
–40°C to +125°C
0.03
0.04
Ω/°C
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
25°C
–0.4
–1
0.4
1
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = 1 V / 10 V
Refer to Off-Leakage Current
–40°C to +125°C
–8
8
nA
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
VD = 1 V / 10 V
Refer to Off-Leakage Current
25°C
–0.4
–5
0.05
0.05
0.4
5
nA
nA
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
–40°C to +125°C
–30
30
nA
VDD = 13.2 V, VSS = 0 V
Switch state is on
VS = VD = 10 V or 1 V
Refer to On-Leakage Current
25°C
–0.4
–4
0.4
4
nA
nA
nA
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
–28
28
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
IIH
Logic voltage high
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
1.3
0
36
0.8
1.2
V
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.4
µA
µA
pF
IIL
–0.1 –0.005
3.5
CIN
POWER SUPPLY
25°C
30
48
54
65
µA
µA
µA
VDD = 13.2 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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7.11 12 V Single Supply: Switching Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
180
210
245
276
202
235
265
318
350
370
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 8 V
tTRAN
Transition time from control input RL = 300 Ω, CL = 35 pF
Refer to Transition Time
–40°C to +85°C
–40°C to +125°C
25°C
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
115
290
50
–40°C to +85°C
–40°C to +125°C
25°C
tON
Turn-on time from enable
(EN)
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
–40°C to +85°C
–40°C to +125°C
25°C
tOFF
Turn-off time from enable
(EN)
VS = 8 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
tBBM
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
1
1
0.16
0.17
0.17
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
TON (VDD)
–40°C to +85°C
–40°C to +125°C
1
1
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
Off-isolation
25°C
25°C
25°C
2.5
2
ns
pC
dB
VS = 6 V, CL = 100 pF
Refer to Charge Injection
QINJ
OISO
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 100 kHz
–82
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
OISO
Off-isolation
Crosstalk
Crosstalk
25°C
25°C
25°C
–62
–85
–65
dB
dB
dB
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
XTALK
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1MHz
Refer to Crosstalk
XTALK
RL = 50 Ω , CL = 5 pF
VS = 6 V
Refer to Bandwidth
BW
IL
–3dB Bandwidth (TMUX6208)
Insertion loss
25°C
25°C
28
MHz
dB
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
–0.6
VPP = 0.62 V on VDD and VSS
RL = 50 Ω , CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
–74
dB
%
Refer to ACPSRR
VPP = 6 V, VBIAS = 6 V
RL = 10 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
Source off capacitance
0.0007
Refer to THD + Noise
CS(OFF)
CD(OFF)
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
25°C
25°C
17
pF
pF
Drain off capacitance
(TMUX6208)
155
Drain off
capacitance (TMUX6209)
CD(OFF)
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
25°C
25°C
78
pF
pF
CS(ON),
CD(ON)
On capacitance (TMUX6208)
200
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7.11 12 V Single Supply: Switching Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CS(ON),
CD(ON)
On capacitance (TMUX6209)
VS = 6 V, f = 1 MHz
25°C
122
pF
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7.12 ±5 V Dual Supply: Electrical Characteristics
VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
7
13.5
16.2
18.5
0.7
Ω
Ω
VDD = +4.5 V, VSS = –4.5 V
VS = –4.5 V to +4.5 V
ID = –10 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.2
2
Ω
On-resistance mismatch between VS = –4.5 V to +4.5 V
ΔRON
–40°C to +85°C
–40°C to +125°C
25°C
0.8
Ω
channels
ID = –10 mA
0.9
Ω
3.8
Ω
VS = –4.5 V to +4.5 V
ID = –10 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
4.2
Ω
4.9
Ω
VS = 0 V, IS = –10 mA
0.03
0.02
Ω/°C
nA
nA
nA
nA
nA
nA
nA
nA
nA
VDD = +5.5 V, VSS = –5.5 V
Switch state is off
VS = +4.5 V / –4.5 V
VD = –4.5 V / + 4.5 V
–0.5
–1.5
–8
0.5
1.5
8
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
IS(OFF)
VDD = +5.5 V, VSS = –5.5 V
Switch state is off
VS = +4.5 V / –4.5 V
VD = –4.5 V / + 4.5 V
–0.5
–3.5
–28
–0.5
–3
0.04
0.04
0.5
3.5
28
0.5
3
–40°C to +85°C
–40°C to +125°C
25°C
ID(OFF)
VDD = +5.5 V, VSS = –5.5 V
Switch state is on
VS = VD = ±4.5 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
–26
26
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
IIH
Logic voltage high
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
1.3
0
36
0.8
1.2
V
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.4
µA
µA
pF
IIL
–0.1 –0.005
3.5
CIN
POWER SUPPLY
25°C
25
2
38
44
55
6.2
7
µA
µA
µA
µA
µA
µA
VDD = +5.5 V, VSS = –5.5 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
VDD = +5.5 V, VSS = –5.5 V
Logic inputs = 0 V, 5 V, or VDD
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
15
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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7.13 ±5 V Dual Supply: Switching Characteristics
VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
125
250
280
305
245
278
305
372
400
420
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 3 V
tTRAN
Transition time from control input RL = 300 Ω, CL = 35 pF
Refer to Transition Time
–40°C to +85°C
–40°C to +125°C
25°C
VS = 3 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
128
300
50
–40°C to +85°C
–40°C to +125°C
25°C
tON
Turn-on time from enable
(EN)
VS = 3 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
–40°C to +85°C
–40°C to +125°C
25°C
tOFF
Turn-off time from enable
(EN)
VS = 3 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
tBBM
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
1
1
0.16
0.17
0.17
VDD rise time = 1 µs
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
TON (VDD)
–40°C to +85°C
–40°C to +125°C
1
1
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
2
ns
VS = 0 V, CL = 100 pF
Refer to Charge Injection
QINJ
1.2
pC
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Off Isolation
OISO
OISO
XTALK
XTALK
BW
Off-isolation
25°C
25°C
25°C
25°C
25°C
–82
–62
–85
–65
28
dB
dB
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
Crosstalk
dB
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1MHz
Refer to Crosstalk
Crosstalk
dB
RL = 50 Ω , CL = 5 pF
VS = 0 V
–3dB Bandwidth (TMUX6208)
MHz
Refer to Bandwidth
RL = 50 Ω , CL = 5 pF
VS = 0 V
BW
IL
–3dB Bandwidth (TMUX6209)
Insertion loss
25°C
25°C
54
MHz
dB
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
–0.7
VPP = 0.62 V on VDD and VSS
RL = 50 Ω , CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
–76
dB
%
Refer to ACPSRR
VPP = 5 V, VBIAS = 0 V
RL = 10 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
Source off capacitance
0.0017
Refer to THD + Noise
CS(OFF)
CD(OFF)
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
25°C
25°C
18
pF
pF
Drain off capacitance
(TMUX6208)
160
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7.13 ±5 V Dual Supply: Switching Characteristics (continued)
VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
Drain off
capacitance (TMUX6209)
CD(OFF)
VS = 0 V, f = 1 MHz
25°C
25°C
25°C
80
pF
CS(ON),
CD(ON)
On capacitance (TMUX6208)
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
205
124
pF
pF
CS(ON),
CD(ON)
On capacitance (TMUX6209)
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7.14 Typical Characteristics
at TA = 25°C (unless otherwise noted)
8
VDD = 18 V, VSS –18 V
VDD = 15 V, VSS –15 V
7
6
5
4
3
2
-25 -20 -15 -10
-5
0
5
10
15
20
25
VS or VD - Source or Drain Voltage (V)
.
.
Figure 7-2. On-Resistance vs Source or Drain Voltage – Dual
Supply
Figure 7-1. On-Resistance vs Source or Drain Voltage – Dual
Supply
12
VDD = 36 V, VSS = 0 V
VDD = 24 V, VSS = 0 V
VDD = 18 V, VSS = 0 V
10
8
6
4
2
0
4
8
12
16
20
24
28
32
36
VS or VD - Source or Drain Voltage (V)
D003
.
.
Figure 7-3. On-Resistance vs Source or Drain Voltage – Single
Supply
Figure 7-4. On-Resistance vs Source or Drain Voltage – Single
Supply
VDD = 15 V, VSS = -15 V
VDD = 36 V, VSS = 0 V
Figure 7-5. On-Resistance vs Temperature
Figure 7-6. On-Resistance vs Temperature
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7.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
VDD = 12 V, VSS = 0 V
VDD = 5 V, VSS = -5 V
Figure 7-7. On-Resistance vs Temperature
Figure 7-8. On-Resistance vs Temperature
VDD = 15 V, VSS = -15 V
VDD = 36 V, VSS = 0 V
Figure 7-9. Leakage Current vs Temperature
Figure 7-10. Leakage Current vs Temperature
30
ID(OFF) VS/VD = 4.5V/–4.5V
ID(OFF) VS/VD = –4.5V/4.5V
I(ON) –4.5V
I(ON) 4.5V
IS(OFF) VS/VD = 4.5V/–4.5V
IS(OFF) VS/VD = –4.5V/4.5V
20
10
0
-10
-20
-30
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D012
VDD = 12 V, VSS = 0 V
VDD = 5 V, VSS = -5 V
Figure 7-12. Leakage Current vs Temperature
Figure 7-11. Leakage Current vs Temperature
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7.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
60
40
30
20
10
0
VDD = 15 V, VSS –15 V
VDD = 15 V, VSS = –15 V
VDD = 5 V, VSS = –5 V
55
50
45
40
35
30
25
20
15
VDD = 5 V, VSS –5 V
VDD = 12 V, VSS = 0 V
VDD = 5 V, VSS = 0 V
-10
-20
-30
0
4
8
12
16
20
24
28
32
36
-20
-15
-10
-5
0
5
10
15
20
Logic Voltage (V)
Source Voltage (V)
.
.
Figure 7-13. Supply Current vs Logic Voltage
Figure 7-14. Charge Injection vs Source Voltage – Dual Supply
50
70
VDD = 15 V, VSS = –15 V
VDD = 5 V, VSS = –5 V
VDD = 36 V, VSS = 0 V
VDD = 20 V, VSS = 0 V
40
60
VDD = 15 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
VDD = 5 V, VSS = 0 V
30
20
50
40
30
20
10
0
10
0
-10
-20
-30
-40
-50
-10
-20
-30
-20
-15
-10
-5
0
5
10
15
20
0
4
8
12
16
20
24
28
32
36
Drain Voltage (V)
Source Voltage (V)
.
.
Figure 7-15. Charge Injection vs Drain Voltage – Dual Supply
Figure 7-16. Charge Injection vs Source Voltage – Single Supply
90
145
VDD = 36 V, VSS = 0 V
VDD = 20 V, VSS = 0 V
VDD = 15 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
VDD = 5 V, VSS = 0 V
VDD = 15V, VSS = –15V
VDD = 36V, VSS = 0V
VDD = 12V, VSS = 0V
80
140
70
135
130
125
120
115
110
105
100
95
60
50
40
30
20
10
0
-10
-20
-30
-40
90
0
4
8
12
16
20
24
28
32
36
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Drain Voltage (V)
.
.
Figure 7-17. Charge Injection vs Drain Voltage – Single Supply
Figure 7-18. TTRANSITION vs Temperature
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7.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
400
360
320
280
240
200
160
120
80
T(OFF)
T(ON)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD = 36 V, VSS = 0 V
VDD = 15 V, VSS = -15 V
Figure 7-20. TON and TOFF vs Temperature
Figure 7-19. TON and TOFF vs Temperature
0
VDD = 15V, VSS = –15V
VDD = 36V, VSS = 0V
VDD = 12V, VSS = 0V
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
1
10
100
1k
10k 100k
1M
10M 100M
Frequency (Hz)
.
VDD = 15 V, VSS = -15 V .
Figure 7-21. Off-Isolation vs Frequency
Figure 7-22. Crosstalk vs Frequency
0.006
0.005
VDD = 15V, VSS = –15V
VDD = 5V, VSS = –5V
0.004
0.003
0.002
0.001
0.0007
0.0005
0.0004
0.0003
10
100
1k
10k
Frequency (Hz)
D028
.
.
Figure 7-24. THD+N vs Frequency (Single Supply)
Figure 7-23. THD+N vs Frequency (Dual Supply)
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7.14 Typical Characteristics (continued)
at TA = 25°C (unless otherwise noted)
VDD = +15 V, VSS = -15 V
VDD = +15 V, VSS = -15 V
Figure 7-25. On Response vs Frequency
Figure 7-26. ACPSRR vs Frequency
VDD = +15 V, VSS = -15 V
VDD = 12 V, VSS = 0 V
Figure 7-27. Capacitance vs Source Voltage or Drain Voltage
Figure 7-28. Capacitance vs Source Voltage or Drain Voltage
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8 Parameter Measurement Information
8.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the
device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote
on-resistance. Figure 8-1 shows the measurement setup used to measure RON. Voltage (V) and current (ISD) are
measured using this setup, and RON is computed with RON = V / ISD
:
V
ISD
Sx
D
VS
Figure 8-1. On-Resistance Measurement Setup
8.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
•
•
Source off-leakage current
Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
Figure 8-2 shows the setup used to measure both off-leakage currents.
VDD
VSS
VDD
VSS
Is (OFF)
S1
S2
S1
S2
A
ID (OFF)
D
D
A
VS
S8
S8
VS
VD
VD
GND
GND
IS(OFF)
ID(OFF)
Figure 8-2. Off-Leakage Measurement Setup
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8.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. Figure 8-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VSS
VDD
VSS
Is (ON)
ID (ON)
S1
S2
S1
S2
N.C.
A
D
D
N.C.
A
VS
S8
S8
VD
VS
VS
GND
GND
IS(ON)
ID(ON)
Figure 8-3. On-Leakage Measurement Setup
8.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 90% after the address signal
has risen or fallen past the logic threshold. The 90% transition measurement is utilized to provide the timing of
the device. System level timing can then account for the time constant added from the load resistance and load
capacitance. Figure 8-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION
.
VDD
VSS
0.1 µF
0.1 µF
VS
3 V
VADDRESS
0 V
VDD
VSS
tr < 20 ns
tf < 20 ns
50%
50%
S1
D
Output
CL
tTRANSITION
tTRANSITION
S2
S8
90%
RL
Output
0 V
10%
A0
A1
A2
VADDRESS
GND
Figure 8-4. Transition-Time Measurement Setup
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8.5 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. Figure 8-7
shows the setup used to measure turn-on time, denoted by the symbol tON(EN)
.
Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. Figure 8-7
shows the setup used to measure turn-off time, denoted by the symbol tOFF(EN)
.
VDD
VSS
0.1 µF
0.1 µF
3 V
VDD
VSS
VEN
tr < 20 ns
tf < 20 ns
50%
50%
S1
VS
0 V
D
Output
CL
tON
tOFF
S2
S8
90%
RL
Output
10%
0 V
EN
A0
A1
VEN
A2
GND
Figure 8-5. Turn-On and Turn-Off Time Measurement Setup
8.6 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 8-6 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
VSS
0.1 µF
0.1 µF
3 V
VADDRESS
0 V
VDD
VSS
tr < 20ns
tf < 20ns
S1
VS
D
Output
CL
S2-S7
RL
80%
S8
Output
0 V
tBBM
1
tBBM 2
A0
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
A1
A2
VADDRESS
GND
Figure 8-6. Break-Before-Make Delay Measurement Setup
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8.7 tON (VDD) Time
The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has
risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in
the system. Figure 8-7 shows the setup used to measure turn on time, denoted by the symbol tON (VDD)
.
VSS
0.1 µF
0.1 µF
VDD
VDD
VSS
VS
S1
VDD
Supply
Ramp
D
Output
CL
tr = 10 µs
4.5 V
S2
S8
RL
0 V
tON
90%
A0
A1
A2
Output
0 V
EN
3 V
GND
Figure 8-7. tON (VDD) Time Measurement Setup
8.8 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. Figure 8-8 shows the setup used to measure propagation delay,
denoted by the symbol tPD
.
VDD
VSS
0.1 µF
0.1 µF
250 mV
Input
(VS)
VDD
S1
VSS
50%
50%
tr < 40ps
tf < 40ps
50 ꢀ
VS
0 V
D
Output
CL
tPD
1
tPD 2
S2
S8
RL
Output
0 V
50%
50%
GND
tProp Delay = max ( tPD 1, tPD 2)
Figure 8-8. Propagation Delay Measurement Setup
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8.9 Charge Injection
The TMUX6208 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted
by the symbol QINJ. Figure 8-9 shows the setup used to measure charge injection from source (Sx) to drain (D).
VDD
VSS
0.1 µF
0.1 µF
3 V
VEN
VDD
VSS
tr < 20 ns
tf < 20 ns
Output
S1
D
0 V
VD
S2
S8
CL
N.C.
N.C.
Output
VD
EN
VOUT
QINJ = CL ×
VOUT
VEN
A0
A1
A2
GND
Figure 8-9. Charge-Injection Measurement Setup
8.10 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to
the source pin (Sx) of an off-channel. Figure 8-10 shows the setup used to measure, and the equation used to
calculate off isolation.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
S1
D
50Ω
VOUT
VSIG
50Ω
Sx
50Ω
GND
8176
1BB +OKH=PEKJ = 20 × .KC
8
5
Figure 8-10. Off Isolation Measurement Setup
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8.11 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. Figure 8-11 shows the setup used to measure, and the equation used to
calculate crosstalk.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
S1
D
50Ω
VOUT
S2
Sx
50Ω
VSIG
50Ω
50Q
GND
8176
%NKOOP=HG = 20 × .KC
8
5
Figure 8-11. Crosstalk Measurement Setup
8.12 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure
8-12 shows the setup used to measure bandwidth.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
S1
D
50Ω
VOUT
VSIG
50Ω
Sx
50Ω
GND
8176
$=J@SE@PD = 20 × .KC
8
5
Figure 8-12. Bandwidth Measurement Setup
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8.13 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
mux output. The on-resistance of the device varies with the amplitude of the input signal and results in distortion
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD+N.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Audio Precision
S1
D
40 Ω
VOUT
VS
RL
Other
Sx pins
50Ω
GND
Figure 8-13. THD+N Measurement Setup
8.14 Power Supply Rejection Ratio (PSRR)
PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage
pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave
of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the
ACPSRR. A high ratio represents a high degree of tolerance to supply rail variation.
Figure 8-14 shows how the decoupling capacitors reduce high frequency noise on the supply pins. This helps
stabilize the supply and immediately filter as much of the supply noise as possible.
VDD
Network Analyzer
VSS
DC Bias
Injector
With & Without
Capacitor
50 Ω
0.1 µF
0.1 µF
VDD
S1
VSS
620 mVPP
VIN
VBIAS
50 Ω
Sx
50 Ω
VOUT
D
RL
GND
CL
8176
2544 = 20 × .KC
8
+0
Figure 8-14. ACPSRR Measurement Setup
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9 Detailed Description
9.1 Overview
The TMUX6208 is an 8:1, 1-channel multiplexer and the TMUX6209 is a 4:1, 2 channel multiplexer. Each input is
turned on or turned off based on the state of the address lines and enable pin.
9.2 Functional Block Diagram
VDD
VSS
VDD
VSS
SW
SW
SW
S1
S2
S1A
DA
DB
SW
SW
S4A
S1B
D
SW
SW
S4B
S8
A0
A1
A2
A0
A1
EN
Logic Decoder
EN
Logic Decoder
TMUX6208
TMUX6209
9.3 Feature Description
9.3.1 Bidirectional Operation
The TMUX6208 and TMUX6209 conduct equally well from source (Sx) to drain (D) or from drain (D) to source
(Sx). Each channel has very similar characteristics in both directions and supports both analog and digital
signals.
9.3.2 Rail-to-Rail Operation
The valid signal path input or output voltage for TMUX6208 and TMUX6209 ranges from VSS to VDD
.
9.3.3 1.8 V Logic Compatible Inputs
TMUX6208 and TMUX6209 support 1.8-V logic compatible control for all logic control inputs. 1.8-V logic level
inputs allows the to interface with processors that have lower logic I/O rails and eliminates the need for an
external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches.
9.3.4 Integrated Pull-Down Resistor on Logic Pins
The TMUX620x has internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The
value of this pull-down resistor is approximatly 4 MΩ, but is clamped to about 1 µA at higher voltages. This
feature integrates up to four external components and reduces system size and cost.
9.3.5 Fail-Safe Logic
TMUX6208 and TMUX6209 support Fail-Safe Logic on the control input pins (EN and Ax) allowing it to operate
up to 36 V, regardless of the state of the supply pins. This feature allows voltages on the control pins to be
applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system
complexity by removing the need for power supply sequencing on the logic control pins. For example, the
Fail-Safe Logic feature allows the TMUX6208 and TMUX6209 logic input pins to ramp up to +36 V while VDD
and VSS = 0 V. The logic control inputs are protected against positive faults of up to +36 V in powered-off
condition, but do not offer protection against negative overvoltage conditions.
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9.3.6 Latch-Up Immune
Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The Latch-Up condition typically requires a power cycle to eliminate the
low impedance path.
The TMUX62xx family of devices are constructed on Silicon on Insulator (SOI) based process where an oxide
layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures
from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events
due to overvoltage or current injections. The latch-up immunity feature allows the TMUX62xx family of switches
and multiplexers to be used in harsh environments. For more information on latch-up immunity refer to Using
Latch Up Immune Multiplexers to Help Improve System Reliability.
9.3.7 Ultra-Low Charge Injection
Figure 9-1 shows that the TMUX620x have a transmission gate topology. Any mismatch in the stray capacitance
associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
OFF ON
CGDN
CGSN
D
S
CGSP
CGDP
OFF ON
Figure 9-1. Transmission Gate Topology
The TMUX620x contain specialized architecture to reduce charge injection on the Drain (D). To further reduce
charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (Sx). This
will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the
Source (Sx) instead of the Drain (D). As a general rule of thumb, Cp should be 20x larger than the equivalent
load capacitance on the Drain (D). Figure 9-2 shows charge injection variation with different compensation
capacitors on the Source side. This plot was captured on the TMUX6219 as part of the TMUX62xx family with a
100pF load capacitance.
Figure 9-2. Charge Injection Compesation
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9.4 Device Functional Modes
When the EN pin of the TMUX6208 is pulled high, one of the switches is closed based on the state of the Ax pin.
Similarly, when the EN pin of the TMUX6209 is pulled high, two of the switches are closed based on the state of
the address lines. When the EN pin is pulled low, all of the switches are in an open state regardless of the state
of the Ax pin. The control pins can be as high as 36 V.
The TMUX6208 and TMUX6209 can be operated without any external components except for the supply
decoupling capacitors. The EN and Ax pins have internal pull-down resistors of 4 MΩ. If unused, Ax and EN
pins must be tied to GND in order to ensure the device does not consume additional current as highlighted in
Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx or D) should be connected to GND.
9.5 Truth Tables
Table 9-1 shows the truth tables for the TMUX6208.
Table 9-1. TMUX6208 Truth Table
Selected Source Connected
EN
A2
A1
A0
To Drain (D) Pin
0
1
1
1
1
1
1
1
1
X(1)
0
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
All sources are off (HI-Z)
S1
S2
S3
S4
S5
S6
S7
S8
0
0
0
1
1
1
1
(1) X denotes do not care.
Table 9-2 show the truth tables for the TMUX6209.
Table 9-2. TMUX6209 Truth Table
Selected Source Connected To
Drain (D) Pin
EN
A0
A1
0
1
1
1
1
X(1)
0
X
0
1
0
1
All sources are off (HI-Z)
S1x
S2x
S3x
S4x
0
1
1
(1) X denotes do not care.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TMUX6208 and TMUX6209 are part of the precision switches and multiplexers family of devices. These
devices operate with dual supplies (±4.5 V to ±18 V), a single supply (4.5 V to 36 V), or asymmetric supplies
(such as VDD = 12 V, VSS = –5 V), and offer true rail-to-rail input and output. The TMUX6208 and TMUX6209
offer low RON, low on and off leakage currents and ultra-low charge injection performance. These features make
the TMUX62xx a family of precision, robust, high-performance analog multiplexers for high-voltage, industrial
applications.
10.2 Typical Application
One example to take advantage of TMUX6208 performance is the implementation of multiplexed data
aquisition front end for multiple input sensors. Applications such as analog input modules for programmable
logic controllers (PLCs), data aquisition (DAQ), and seminconducter test systems commonly need to monitor
multiple signals into a single ADC channel. The multiple inputs can come from different system voltages being
montitored, or environemental sensors such as temperature or humidity. Figure 9-1 shows a simplified example
of monitoring multiple inputs into a single ADC using a multiplexer.
Figure 10-1. Multiplexed Data Aqcuisition Front End
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10.3 Design Requirements
Table 10-1. Design Parameters
PARAMETER
VALUE
Positive supply (VDD)
Negative supply (VSS
+15 V
-15 V
)
Input / output signal range
Control logic thresholds
Temperature range
-12 V to 12 V (limit of ADC)
1.8 V compatible
-40°C to +125°C
10.4 Detailed Design Procedure
The application shown in Figure 9-1 demonstrates how a multiplexer can be used to simplfy the signal chain
and monitor multiple input signals to a single ADC channel. In this example the ADC (ADS8661) has software
programmable input ranges up to ±12.288 V. The ADC also has overvotlage protection up to ±20 V which
allows for the multiplexer to be powered with wider supply voltages than the input signal range to maximize
on-resistance performance of the multiplxer, while still maintaining system level overvotlage protection beyond
the usuable signal range. Both the multiplexer and the ADC are capable of operation in extended industrial
temperature range of -40°C to +125°C allowing for use in a wider array of industrial systems.
Many SAR ADCs have an analog input structure that consists of a sampling switch and a sampling capacitor.
Many signal chains will have a driver amplifier to help charge the input of the ADC to meet a fast system
aquisition time. However a driver amplifier is not always needed to drive SAR ADCs. Figure 9-2 shows a typical
diagram of a sensor driving the SAR ADC input directly after being passed through the multiplxer. A filter
capacitor (CFLT) is connected to the input of the ADC to reduce the sampling charge injection and provides a
charge bucket to quickly charge the internal sample-and-hold capacitor of the ADC.
The sensor block simplifies the device into a Thevenin equivalant voltage source (VTH) and resistance (RTH
)
which can be extracted from the device datasheets. Similarly the multixplexer can be thought of as a series
resistance (RON(MUX)) and capacitance (CON(MUX)). To ensure maximum precison of the signal chain the system
should be able to settle within 1/2 of an LSB within the acquisition time of the ADC. Figure 9-2 shows the
time constant can be calculated. This equation highlights the importance of selecting a multiplexer with low
on-resistance to further reduce the system time constant. Additionaly low charge injection performance of the
multiplexer is helpful to reduce conversion errors and improve accuracy of the measurements.
Figure 10-2. Driving SAR ADC
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10.5 Application Curve
The low on and off leakage currents of TMUX620x and ultra-low charge injection performance make this device
ideal for implementing high precision industrial systems. Figure 10-3 shows the plot for the charge injection
versus source voltage for the TMUX6208.
50
VDD = 15 V, VSS = –15 V
VDD = 5 V, VSS = –5 V
40
30
20
10
0
-10
-20
-30
-40
-50
-20
-15
-10
-5
0
5
10
15
20
Drain Voltage (V)
TA = 25°C
Figure 10-3. Charge Injection vs Drain Voltage
11 Power Supply Recommendations
The TMUX6208 and TMUX6209 operate across a wide supply range of of ±4.5 V to ±18 V (4.5 V to 36 V in
single-supply mode). The device also perform well with asymmetrical supplies such as VDD = 12 V and VSS = –5
V.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply
rails to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the VDD
and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as possible
using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that
offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling
purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias
for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias
in parallel lowers the overall inductance and is beneficial for connections to ground and power planes. Always
ensure the ground (GND) connection is established before supplies are ramped.
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12 Layout
12.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 12-1 shows progressively better techniques of rounding corners. Only the last example
(BEST) maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
2W
1W min.
W
Figure 12-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance.
Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up
interference from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
Figure 12-2 and Figure 12-3 illustrate an example of a PCB layout with the TMUX6208. Some key
considerations are:
•
For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD/VSS and
GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as
possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
•
•
•
•
Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground
planes.
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12.2 Layout Example
Wide (low inductance)
trace for power
VDD
S1B
S2B
S3B
VSS
S1A
S2A
S3A
Wide (low inductance)
trace for power
Via to ground plane
Figure 12-2. TMUX6208 Layout Example
Via to
ground plane
Via to
ground plane
Wide (low inductance)
trace for power
A0
EN
VSS
A1
C
C
C
C
Wide (low inductance)
trace for power
GND
VDD
S1B
S2B
S3B
S4B
DB
S1A
S2A
S3A
S4A
DA
TMUX6209
Wide (low inductance)
trace for power
GND
VDD
S5
VSS
S1
S2
S3
Wide (low inductance)
trace for power
S6
Via to ground plane
Figure 12-3. TMUX6209 Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
•
•
•
•
•
•
Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief.
Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment application brief
Texas Instruments, Sample & Hold Glitch Reduction for Precision Outputs Reference Design reference guide.
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief.
Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application reports.
Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit
application reports.
•
•
•
Texas Instruments, QFN/SON PCB Attachment application reports.
Texas Instruments, Quad Flatpack No-Lead Logic Packages application reports.
Texas Instruments, Using Latch Up Immune Multiplexers to Help Improve System Reliability application
reports.
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX6208PWR
TMUX6208RUMR
ACTIVE
ACTIVE
TSSOP
WQFN
PW
16
16
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
X208
RUM
NIPDAU
TMUX
X208
TMUX6209PWR
TMUX6209RUMR
ACTIVE
ACTIVE
TSSOP
WQFN
PW
16
16
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
X209
RUM
TMUX
X209
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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7-Oct-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX6208PWR
TMUX6209PWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX6208PWR
TMUX6209PWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
853.0
853.0
449.0
449.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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GENERIC PACKAGE VIEW
RUM 16
4 x 4, 0.65 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224843/A
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PACKAGE OUTLINE
RUM0016E
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.95
SYMM
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
4
9
2X 1.95
SYMM
17
2.5 0.1
12X 0.65
1
12
0.35
16X
PIN 1 ID
0.25
13
16
0.1
C A B
0.5
0.3
0.05
16X
4224815/A 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RUM0016E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.5)
SYMM
SEE SOLDER MASK
DETAIL
13
16
16X (0.6)
1
12
16X (0.3)
17
SYMM
12X (0.65)
(3.8)
(1)
4
9
(R0.05) TYP
(
0.2) TYP
VIA
5
8
(1)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224815/A 02/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RUM0016E
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.65) TYP
13
16
16X (0.6)
1
12
16X (0.3)
(0.65) TYP
(3.8)
17
SYMM
12X (0.65)
4X ( 1.1)
9
4
(R0.05) TYP
8
5
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224815/A 02/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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