TMUX1248 [TI]
具有 3157 引脚排列的 3Ω 低 RON、5V、2:1 (SPDT) 通用开关;型号: | TMUX1248 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 3157 引脚排列的 3Ω 低 RON、5V、2:1 (SPDT) 通用开关 开关 通用开关 光电二极管 |
文件: | 总29页 (文件大小:1438K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TMUX1248
ZHCSNX2 –JULY 2021
TMUX1248 采用1.8V 逻辑的3Ω 低RON、5V、2:1 (SPDT) 通用开关
1 特性
3 说明
• 轨至轨运行
• 双向信号路径
• 兼容1.8V 逻辑电平
• 失效防护逻辑
• 控制输入过压容差: 5.5V
• 低导通电阻:3Ω
• 宽电源电压范围:1.08V 至5.5V
• 工作温度范围:-40°C 至+125°C
• 低电源电流:7nA
TMUX1248 是一种通用 2:1 单极双投 (SPDT) 开关,
支持1.08V 至5.5V 的宽工作范围。此器件在源极 (Sx)
和漏极(D) 引脚上支持从GND 到VDD 的双向模拟和数
字信号。选择引脚 (SEL) 的状态决定连接到漏极引脚
的源极引脚。此外,TMUX1248 具有 7nA 的低电源电
流,这使器件能够在许多手持设备或低功耗应用中使
用。
先断后合开关操作可防止同时启用两个源极引脚。此功
能通过防止源极信号在开关事件期间短路,增加了系统
的稳健性。
• 先断后合开关
2 应用
所有逻辑输入都具有兼容 1.8V 逻辑的阈值,允许使用
低压逻辑信号进行操作。失效防护逻辑电路允许先在控
制引脚上施加电压,然后在电源引脚上施加电压,或在
电压高于电源引脚(最高为 5.5V)时施加电压,从而
保护器件免受潜在的损害。
• 模拟和数字开关
• I2C 和SPI 总线多路复用
• 机架式服务器
• 网络接口卡(NIC)
• 条形码扫描仪
• 楼宇自动化
• 模拟输入模块
• 电机驱动器
• 视频监控
器件信息(1)
封装尺寸(标称值)
器件型号
TMUX1248
封装
SC70 (6)
2.00mm × 1.25mm
(1) 如需了解所有可用封装,请参阅数据表末尾的封装选项附录。
• 电子销售终端
• 台式机
• 电器
空白
空白
TMUX1248
Input
R
R
S1
S2
Output
S1
S2
Unity Gain
Inverting
D
D
TLV9001
1.8 V
SEL
SEL
TMUX1248
应用示例
TMUX1248 方框图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SCDS447
TMUX1248
ZHCSNX2 –JULY 2021
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Table of Contents
7.5 Break-Before-Make...................................................17
7.6 Charge Injection........................................................17
7.7 Off Isolation...............................................................18
7.8 Crosstalk...................................................................18
7.9 Bandwidth................................................................. 19
8 Detailed Description......................................................19
8.1 Overview...................................................................19
8.2 Functional Block Diagram.........................................19
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................20
8.5 Truth Tables.............................................................. 20
9 Power Supply Recommendations................................22
10 Layout...........................................................................23
10.1 Layout Guidelines................................................... 23
10.2 Layout Example...................................................... 23
11 Device and Documentation Support..........................24
11.1 Documentation Support.......................................... 24
11.2 接收文档更新通知................................................... 24
11.3 支持资源..................................................................24
11.4 Trademarks............................................................. 24
11.5 Electrostatic Discharge Caution..............................24
11.6 术语表..................................................................... 24
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics (VDD = 5 V ±10 %),
GND = 0 V unless otherwise specified. ........................6
6.6 Electrical Characteristics (VDD = 3.3 V ±10 %),
GND = 0 V unless otherwise specified. ........................8
6.7 Electrical Characteristics (VDD = 1.8 V ±10 %),
GND = 0 V unless otherwise specified. ......................10
6.8 Electrical Characteristics (VDD = 1.2 V ±10 %),
GND = 0 V unless otherwise specified. ......................12
6.9 Typical Characteristics..............................................14
7 Parameter Measurement Information..........................15
7.1 On-Resistance.......................................................... 15
7.2 Off-Leakage Current................................................. 15
7.3 On-Leakage Current................................................. 16
7.4 Transition Time......................................................... 16
Information.................................................................... 24
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
July 2021
*
Initial Release
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5 Pin Configuration and Functions
S2
GND
S1
1
2
3
6
5
4
SEL
VDD
D
Not to scale
图5-1. DCK Package 6-Pin SC70 Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION(2)
NAME
D
NO.
4
I/O
P
Drain pin. Can be an input or output.
Ground (0 V) reference.
GND
S1
2
3
I/O
I/O
I
Source pin 1. Can be an input or output.
Source pin 2. Can be an input or output.
Select pin: controls state of the switch according to 表8-1.
S2
1
SEL
6
Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect
a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
5
P
(1) I = input, O = output, I/O = input and output, P = power.
(2) Refer to 节8.4 for what to do with unused pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
–0.5
–0.5
–30
–0.5
–50
–30
–65
MAX
UNIT
V
VDD
Supply voltage
6
6
VSEL or VEN
ISEL or IEN
VS or VD
IS or ID (CONT)
IK
Logic control input pin voltage (SEL)
Logic control input pin current (SEL)
Source or drain voltage (Sx, D)
Source or drain continuous current (Sx, D)
Diode clamp current(4)
V
30
mA
V
VDD+0.5
50
mA
mA
°C
°C
30
Tstg
Storage temperature
150
150
TJ
Junction temperature
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
(4) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.08
0
NOM
MAX
5.5
UNIT
V
VDD
Supply voltage
VS or VD
VSEL
TA
Signal path input/output voltage (source or drain pin) (Sx, D)
Logic control input pin voltage (SEL)
Ambient temperature
VDD
5.5
V
0
V
125
70
°C
–40
tr,tf
Logic input pin rise and fall time
ns/V
6.4 Thermal Information
TMUX1248
THERMAL METRIC(1)
DCK (SC70)
6 PINS
243.6
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
180.9
106.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
89.1
106.0
ΨJB
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6.4 Thermal Information (continued)
TMUX1248
DCK (SC70)
6 PINS
THERMAL METRIC(1)
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics (VDD = 5 V ±10 %), GND = 0 V unless otherwise specified.
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
3
Ω
VS = 0 V to VDD
ISD = 10 mA
5
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
6
Ω
0.15
Ω
On-resistance matching between
channels
VS = 0 V to VDD
ISD = 10 mA
1
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
1
Ω
1.5
2
Ω
Ω
RON
VS = 0 V to VDD
ISD = 10 mA
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
FLAT
3
Ω
±75
nA
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
IS(OFF) Source off leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
–150
–175
150
175
nA
nA
nA
nA
nA
±200
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1 V
ID(ON)
500
750
Channel on leakage current
IS(ON)
–40°C to +85°C
–40°C to +125°C
–500
–750
LOGIC INPUTS
VIH
VIL
Input logic high
Input logic low
-40°C to 125°C
-40°C to 125°C
1.42
0
5.5
V
V
0.87
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
1
µA
µA
IIH
IIL
±0.05
2
–40°C to +125°C
CIN
CIN
Digital input capacitance
Digital input capacitance
25°C
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.007
µA
µA
IDD VDD supply current
Digital Inputs = 0 V or 5.5 V
1.5
–40°C to +125°C
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6.5 Electrical Characteristics (VDD = 5 V ±10 %), GND = 0 V unless otherwise specified.
(continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
12
ns
VS = 3 V
RL = 200 Ω, CL = 15 pF
18
19
ns
ns
ns
ns
ns
tTRAN
Switching time between channels
–40°C to +85°C
–40°C to +125°C
25°C
8
VS = 3 V
RL = 200 Ω, CL = 15 pF
tOPEN
1
1
Break before make time
Charge Injection
–40°C to +85°C
–40°C to +125°C
(BBM)
VS = VDD /2
RS = 0 Ω, CL = 1 nF
QC
25°C
25°C
25°C
25°C
25°C
pC
dB
dB
dB
dB
–10
–65
–45
–65
–45
RL = 50 Ω, CL = 5 pF
f = 1 MHz
OISO
Off Isolation
RL = 50 Ω, CL = 5 pF
f = 10 MHz
RL = 50 Ω, CL = 5 pF
f = 1 MHz
XTALK
BW
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Bandwidth
25°C
25°C
250
7
MHz
pF
RL = 50 Ω, CL = 5 pF
CSOFF Source off capacitance
f = 1 MHz
CSON
On capacitance
CDON
f = 1 MHz
25°C
23
pF
(1) When VS is 4.5 V, VD is 1.5 V or when VS is 1.5 V, VD is 4.5 V.
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6.6 Electrical Characteristics (VDD = 3.3 V ±10 %), GND = 0 V unless otherwise specified.
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
4.5
Ω
VS = 0 V to VDD
ISD = 10 mA
12.5
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
13
Ω
0.15
Ω
On-resistance matching between
channels
VS = 0 V to VDD
ISD = 10 mA
1
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
1
Ω
3.5
4
Ω
Ω
RON
VS = 0 V to VDD
ISD = 10 mA
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
FLAT
5
Ω
±75
nA
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
IS(OFF) Source off leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
–150
–175
150
175
nA
nA
nA
nA
nA
±200
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
ID(ON)
500
750
Channel on leakage current
IS(ON)
–40°C to +85°C
–40°C to +125°C
–500
–750
LOGIC INPUTS
VIH
VIL
Input logic high
Input logic low
-40°C to 125°C
-40°C to 125°C
1.3
0
5.5
0.8
V
V
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
1
µA
µA
IIH
IIL
±0.05
2
–40°C to +125°C
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.004
µA
µA
IDD VDD supply current
Digital Inputs = 0 V or 5.5 V
0.8
–40°C to +125°C
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6.6 Electrical Characteristics (VDD = 3.3 V ±10 %), GND = 0 V unless otherwise specified.
(continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
14
ns
VS = 2 V
RL = 200 Ω, CL = 15 pF
20
22
ns
ns
ns
ns
ns
tTRAN
Switching time between channels
–40°C to +85°C
–40°C to +125°C
25°C
8
VS = 2 V
RL = 200 Ω, CL = 15 pF
tOPEN
1
1
Break before make time
Charge Injection
–40°C to +85°C
–40°C to +125°C
(BBM)
VS = VDD/2
RS = 0 Ω, CL = 1 nF
QC
25°C
25°C
25°C
25°C
25°C
pC
dB
dB
dB
dB
–6
–65
–45
–65
–45
RL = 50 Ω, CL = 5 pF
f = 1 MHz
OISO
Off Isolation
RL = 50 Ω, CL = 5 pF
f = 10 MHz
RL = 50 Ω, CL = 5 pF
f = 1 MHz
XTALK
BW
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Bandwidth
25°C
25°C
250
7
MHz
pF
RL = 50 Ω, CL = 5 pF
CSOFF Source off capacitance
f = 1 MHz
CSON
On capacitance
CDON
f = 1 MHz
25°C
23
pF
(1) When VS is 3 V, VD is 1 V or when VS is 1 V, VD is 3 V.
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6.7 Electrical Characteristics (VDD = 1.8 V ±10 %), GND = 0 V unless otherwise specified.
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
40
Ω
VS = 0 V to VDD
ISD = 10 mA
80
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
80
Ω
0.4
Ω
On-resistance matching between
channels
VS = 0 V to VDD
ISD = 10 mA
1.5
–40°C to +85°C
–40°C to +125°C
ΔRON
Ω
1.5
Ω
RON
VS = 0 V to VDD
ISD = 10 mA
On-resistance flatness
25°C
35
Ω
FLAT
25°C
±75
nA
VDD = 1.98 V
Switch Off
VD = 1.8 V / 1 V
VS = 1 V / 1.8 V
IS(OFF) Source off leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
–150
–175
150
175
nA
nA
nA
nA
nA
±200
VDD = 1.98 V
Switch On
VD = VS = 1.62 V / 1 V
ID(ON)
500
750
Channel on leakage current
IS(ON)
–40°C to +85°C
–40°C to +125°C
–500
–750
DIGITAL INPUTS
VIH
VIL
Input logic high
Input logic low
1.07
0
5.5
V
V
–40°C to +125°C
–40°C to +125°C
0.68
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
1
µA
µA
IIH
IIL
±0.05
2
–40°C to +125°C
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.002
µA
µA
IDD VDD supply current
Logic Inputs = 0 V or 5.5 V
0.52
–40°C to +125°C
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6.7 Electrical Characteristics (VDD = 1.8 V ±10 %), GND = 0 V unless otherwise specified.
(continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
24
ns
VS = 1 V
RL = 200 Ω, CL = 15 pF
44
45
ns
ns
ns
ns
ns
tTRAN
Switching time between channels
–40°C to +85°C
–40°C to +125°C
25°C
16
VS = 1 V
RL = 200 Ω, CL = 15 pF
tOPEN
1
1
Break before make time
Charge Injection
–40°C to +85°C
–40°C to +125°C
(BBM)
VS = VDD/2
RS = 0 Ω, CL = 1 nF
QC
25°C
25°C
25°C
25°C
25°C
pC
dB
dB
dB
dB
–3
–65
–45
–65
–45
RL = 50 Ω, CL = 5 pF
f = 1 MHz
OISO
Off Isolation
RL = 50 Ω, CL = 5 pF
f = 10 MHz
RL = 50 Ω, CL = 5 pF
f = 1 MHz
XTALK
BW
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Bandwidth
25°C
25°C
250
7
MHz
pF
RL = 50 Ω, CL = 5 pF
CSOFF Source off capacitance
f = 1 MHz
CSON
On capacitance
CDON
f = 1 MHz
25°C
23
pF
(1) When VS is 1.8 V, VD is 1 V or when VS is 1 V, VD is 1.8 V.
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6.8 Electrical Characteristics (VDD = 1.2 V ±10 %), GND = 0 V unless otherwise specified.
at TA = 25°C, VDD = 1.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
70
Ω
VS = 0 V to VDD
IDS = 10 mA
105
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
105
Ω
0.4
Ω
On-resistance matching between
channels
VS = 0 V to VDD
IDS = 10 mA
1.5
–40°C to +85°C
–40°C to +125°C
ΔRON
Ω
1.5
Ω
RON
VS = 0 V to VDD
IDS = 10 mA
On-resistance flatness
25°C
65
Ω
FLAT
25°C
±75
nA
VDD = 1.32 V
Switch Off
VD = 1.2 V / 1 V
VS = 1 V / 1.2 V
IS(OFF) Source off leakage current(1)
–40°C to +85°C
–40°C to +125°C
25°C
–150
–175
150
175
nA
nA
nA
nA
nA
±200
VDD = 1.32 V
Switch On
VD = VS = 1 V / 0.8 V
ID(ON)
500
750
Channel on leakage current
IS(ON)
–40°C to +85°C
–40°C to +125°C
–500
–750
DIGITAL INPUTS
VIH
VIL
Input logic high
Input logic low
0.96
V
V
–40°C to +125°C
–40°C to +125°C
0.36
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
1
µA
µA
IIH
IIL
±0.10
2
–40°C to +125°C
CIN
CIN
Digital input capacitance
Digital input capacitance
25°C
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.0015
µA
µA
IDD VDD supply current
Digital Inputs = 0 V or 5.5 V
0.45
–40°C to +125°C
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6.8 Electrical Characteristics (VDD = 1.2 V ±10 %), GND = 0 V unless otherwise specified.
(continued)
at TA = 25°C, VDD = 1.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
40
ns
VIN = VDD
VS = 1 V
RL = 200 Ω, CL = 15 pF
175
175
ns
ns
ns
ns
ns
tTRAN
Switching time between channels
–40°C to +85°C
–40°C to +125°C
25°C
27
VS = 1 V
RL = 200 Ω, CL = 15 pF
tOPEN
1
1
Break before make time
Charge Injection
–40°C to +85°C
–40°C to +125°C
(BBM)
VS = (VDD + VSS)/2
RS = 0 Ω, CL = 1 nF
QC
25°C
25°C
25°C
25°C
25°C
±5
–64
–44
–64
–44
pC
dB
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
OISO
Off Isolation
RL = 50 Ω, CL = 5 pF
f = 10 MHz
RL = 50 Ω, CL = 5 pF
f = 1 MHz
XTALK
BW
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Bandwidth
25°C
25°C
250
7
MHz
pF
RL = 50 Ω, CL = 5 pF
CSOFF Source off capacitance
f = 1 MHz
CSON
On capacitance
CDON
f = 1 MHz
25°C
23
pF
(1) When VS is 1 V, VD is 1.2 V or when VS is 1.2 V, VD is 1 V.
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6.9 Typical Characteristics
At TA = 25°C, VDD = 5 V (unless otherwise noted).
80
10
8
VDD = 1.08V
60
TA = 125èC
TA = 85èC
6
40
VDD = 1.62 V
4
20
2
VDD = 3 V
VDD = 4.5 V
TA = 25èC
TA = -40èC
0
0
0
0.5
1
1.5
Source or Drain Voltage (V)
2
2.5
3
3.5
4
4.5
5
0
0.5
1
Source or Drain Voltage (V)
1.5
2
2.5
3
D001
D002
TA = 25°C
VDD = 3 V
图6-1. On-Resistance vs Source or Drain Voltage
图6-2. On-Resistance vs Source or Drain Voltage
500
30
25
400
300
200
20
Rising
15
Falling
10
VDD = 3.3 V
VDD = 5 V
100
0
5
0
0
0.5
1
1.5
2
2.5
3
Logic Voltage (V)
3.5
4
4.5
5
0.5
1.5
2.5 3.5
VDD - Supply Voltage (V)
4.5
5.5
D003
D004
TA = 25°C
TA = 25°C
图6-3. Supply Current vs Logic Voltage
图6-4. Ttransition vs Supply Voltage
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-10
-20
-30
-40
-50
-60
-70
-80
-90
100k
1M
10M
Frequency (Hz)
100M
D005
1M
10M
Frequency (Hz)
100M
D006
TA = 25°C
TA = 25°C
图6-5. Crosstalk and Off-Isolation vs Frequency
图6-6. Frequency Response
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. The measurement setup used to measure RON is shown in 图 7-1. Voltage (V) and current (ISD) are
measured using this setup, and RON is computed with RON = V / ISD
:
V
ISD
Sx
D
VS
图7-1. On-Resistance Measurement Setup
7.2 Off-Leakage Current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
The setup used to measure off-leakage current is shown in 图7-2.
VDD
VDD
Is (OFF)
S1
A
D
S2
VS
VD
GND
图7-2. Off-Leakage Measurement Setup
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VDD
VDD
VDD
IS (ON)
S1
S2
S1
S2
ID (ON)
N.C.
A
D
D
A
N.C.
Vs
VS
VS
VD
GND
GND
图7-3. On-Leakage Measurement Setup
7.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the logic control
signal has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the
timing of the device. System level timing can then account for the time constant added from the load resistance
and load capacitance. 图 7-4 shows the setup used to measure transition time, denoted by the symbol
tTRANSITION
.
VDD
0.1…F
VDD
VDD
Logic
Control
tf < 5ns
tr < 5ns
VIH
(VSEL
)
VIL
S1
S2
VS
OUTPUT
0 V
D
RL
CL
tTRANSITION
tTRANSITION
SEL
90%
OUTPUT
VSEL
10%
GND
0 V
图7-4. Transition-Time Measurement Setup
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7.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图7-5 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
0.1…F
VDD
VDD
Logic
Control
S1
S2
tr < 5ns
tf < 5ns
VS
OUTPUT
D
(VSEL
)
0 V
RL
CL
90%
Output
SEL
tBBM
1
tBBM 2
0 V
VSEL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
GND
图7-5. Break-Before-Make Delay Measurement Setup
7.6 Charge Injection
The TMUX1248 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QC. 图 7-6 shows the setup used to measure charge injection from Drain (D) to Source
(Sx).
VDD
VSS
0.1…F
0.1…F
VSS
VDD
VDD
VSEL
S2
N.C.
D
VD
OUTPUT
S1
VOUT
0 V
CL
Output
VOUT
SEL
VS
QC = CL
×
VOUT
VSEL
GND
图7-6. Charge-Injection Measurement Setup
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7.7 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. 图 7-7 shows the setup used to measure, and the equation used to calculate
off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
50Q
S
VSIG
D
VOUT
RL
SX
50Q
GND
RL
50Q
图7-7. Off Isolation Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
7.8 Crosstalk
(1)
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. 图 7-8 shows the setup used to measure, and the equation used to
calculate crosstalk.
0.1µF
NETWORK
VDD
ANALYZER
S1
VOUT
RL
D
50Q
VS
RL
S2
50Q
50Q
VSIG
GND
图7-8. Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
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7.9 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 7-9
shows the setup used to measure bandwidth.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
50Q
VSIG
D
VOUT
RL
50Q
SX
GND
RL
50Q
图7-9. Bandwidth Measurement Setup
8 Detailed Description
8.1 Overview
The TMUX1248 is a 2:1 (SPDT), 1-channel switch where the input is controlled with a single select (SEL) control
pin.
8.2 Functional Block Diagram
TMUX1248
S1
D
S2
SEL
图8-1. TMUX1248 Functional Block Diagram
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1248 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). The device
has very similar characteristics in both directions and supports both analog and digital signals.
8.3.2 Rail to Rail Operation
The valid signal path input/output voltage for TMUX1248 ranges from GND to VDD
.
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8.3.3 1.8 V Logic Compatible Inputs
The TMUX1248 has 1.8 V logic compatible control for the logic control input (SEL). The logic input threshold
scales with supply but still provides 1.8 V logic control when operating at 5.5 V supply voltage. 1.8 V logic level
inputs allow the TMUX1248 to interface with processors that have lower logic I/O rails and eliminates the need
for an external translator, which saves both space and BOM cost. For more information on 1.8 V logic
implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.4 Fail-Safe Logic
The TMUX1248 supports Fail-Safe Logic on the control input pin (SEL) allowing for operation up to 5.5 V,
regardless of the state of the supply pin. This feature allows voltages on the control pin to be applied before the
supply pin, or allows higher voltages on the SEL pin up to 5.5 V, protecting the device from potential damage.
Fail-Safe Logic minimizes system complexity by removing the need for power supply sequencing on the logic
control pin. For example, the Fail-Safe Logic feature allows the select pin of the TMUX1248 to be ramped to 5.5
V while VDD = 0 V. Additionally, the feature enables operation of the TMUX1248 with VDD = 1.2 V while allowing
the select pin to interface with a logic level of another device up to 5.5 V.
8.4 Device Functional Modes
The select (SEL) pin of the TMUX1248 controls which switch is connected to the drain of the device. When a
given input is not selected, that source pin is in high impedance mode (HI-Z). The control pins can be as high as
5.5 V.
The TMUX1248 can be operated without any external components except for the supply decoupling capacitors.
Unused logic control pins should be tied to GND or VDD in order to ensure the device does not consume
additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx
or D) should be connected to GND.
8.5 Truth Tables
表8-1. TMUX1248 Truth Table
CONTROL
Selected Source (Sx) Connected To Drain (D) Pin
LOGIC (SEL)
0
1
S1
S2
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Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TMUX12xx family offers good system performance across a wide operating supply (1.08 V to 5.5 V). These
devices include 1.8 V logic compatible control input pins that enable operation in systems with 1.8 V I/O rails.
Additionally, the control input pin supports Fail-Safe Logic which allows for operation up to 5.5 V, regardless of
the state of the supply pin. This protection stops the logic pins from back-powering the supply rail. These
features of the TMUX12xx, a family of general purpose multiplexers and switches, reduce system complexity,
board size, and overall system cost.
9.2 Typical Application
9.2.1 Switchable Operational Amplifier Gain Setting
Another example application of the TMUX1248 is to change an Op Amp from unity gain setting to an inverting
amplifier configuration. Utilizing a switch allows a system to have a configurable gain and allows the same
architecture to be utilized across the board for various inputs to the system. 图 9-1 shows the TMUX1248
configured for gain setting application.
Input
R
R
Output
S1
S2
Unity Gain
Inverting
D
TLV9001
1.8 V
SEL
TMUX1248
图9-1. Switchable Op Amp Gain Setting
9.2.1.1 Design Requirements
This design example uses the parameters listed in 表9-1.
表9-1. Design Parameters
PARAMETERS
VALUES
0 V to 2.75 V
Input Signal
Mux Supply (VDD
)
2.75 V
Op Amp Supply (V+/ V-)
Mux I/O signal range
Control logic thresholds
±2.75 V
0 V to VDD (Rail to Rail)
1.8 V compatible (up to 5.5 V)
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9.2.1.2 Detailed Design Procedure
The application shown in 图9-1 demonstrates how to use a single control input and toggle between gain settings
of -1 and +1. If switching between inverting and unity gain is not required, the TMUX1248 can be utilized in the
feedback path to select different feedback resistors and provide scalable gain settings for configurable signal
conditioning.
The TMUX1248 can be operated without any external components except for the supply decoupling capacitors.
The select pin is recommended to have a pull-down or pull-up resistor to ensure the input is in a known state if
the control signal becomes disconnected. All inputs to the switch must fall within the recommend operating
conditions of the TMUX1248 including signal range and continuous current. For this design with a supply of 2.75
V the signal range can be 0 V to 2.75 V and the max continuous current can be 50 mA.
9.2.1.3 Application Curve
80
VDD = 1.08V
60
40
VDD = 1.62 V
20
VDD = 3 V
VDD = 4.5 V
0
0
0.5
1
1.5
2
2.5
3
3.5
Source or Drain Voltage (V)
4
4.5
5
D001
TA = 25°C
图9-2. On-Resistance vs Source or Drain Voltage
9 Power Supply Recommendations
The TMUX1248 operates across a wide supply range of 1.08 V to 5.5 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to
ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-
impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes.
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10 Layout
10.1 Layout Guidelines
10.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection primarily occurs because the
width of the trace changes. At the apex of the turn, the trace width increases to 1.414 times its width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 10-1 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
2W
1W min.
W
图10-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
图10-2 illustrates an example of a PCB layout with the TMUX1248. Some key considerations are:
• Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
10.2 Layout Example
Via to
GND plane
TMUX1248
Wide (low inductance)
trace for power
C
图10-2. TMUX1248 Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief
• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief
• Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches application
brief
• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application reports
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021,德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX1248DCKR
ACTIVE
SC70
DCK
6
3000 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
248
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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