TMS570LC4357-EP [TI]

增强型产品 16/32 位 RISC 闪存 MCU、Arm Cortex-R5F、EMAC、FlexRay;


型号：	TMS570LC4357-EP
厂家：	TEXAS INSTRUMENTS
描述：	增强型产品 16/32 位 RISC 闪存 MCU、Arm Cortex-R5F、EMAC、FlexRay 闪存
文件：	总229页 (文件大小：10503K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TMS570LC4357-EP

SPNS253A –MAY 2018–REVISED SEPTEMBER 2019

TMS570LC4357-EP Hercules™ Microcontroller Based on the ARM® Cortex®-R Core

1 Device Overview

1.1 Features

• High-Performance Automotive-Grade

• Multiple Communication Interfaces

– 10/100 Mbps Ethernet MAC (EMAC)

– IEEE 802.3 Compliant (3.3-V I/O Only)

– Supports MII, RMII, and MDIO

Microcontroller for Safety-Critical Applications

– Dual-Core Lockstep CPUs With ECC-Protected

Caches

– ECC on Flash and RAM Interfaces

– Built-In Self-Test (BIST) for CPU, High-End

Timers, and On-Chip RAMs

– FlexRay Controller With 2 Channels

– 8KB of Message RAM With ECC Protection

– Dedicated FlexRay Transfer Unit (FTU)

– Four CAN Controller (DCAN) Modules

– 64 Mailboxes, Each With ECC Protection

– Compliant to CAN Protocol Version 2.0B

– Two Inter-Integrated Circuit (I²C) Modules

– Error Signaling Module (ESM) With Error Pin

– Voltage and Clock Monitoring

• ARM^®Cortex^®- R5F 32-Bit RISC CPU

– 1.66 DMIPS/MHz With 8-Stage Pipeline

– FPU With Single- and Double-Precision

– 16-Region Memory Protection Unit (MPU)

– Five Multibuffered Serial Peripheral Interface

(MibSPI) Modules

– 32KB of Instruction and 32KB of Data Caches

With ECC

– Open Architecture With Third-Party Support

• Operating Conditions

– MibSPI1: 256 Words With ECC Protection

– Other MibSPIs: 128 Words With ECC

Protection

– Four UART (SCI) Interfaces, Two With Local

Interconnect Network (LIN 2.1) Interface

Support

– Up to 300-MHz CPU Clock

– Core Supply Voltage (VCC): 1.14 to 1.32 V

– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V

• Integrated Memory

• Two Next Generation High-End Timer (N2HET)

Modules

– 32 Programmable Channels Each

– 256-Word Instruction RAM With Parity

– Hardware Angle Generator for Each N2HET

– Dedicated High-End Timer Transfer Unit (HTU)

for Each N2HET

– 4MB of Program Flash With ECC

– 512KB of RAM With ECC

– 128KB of Data Flash for Emulated EEPROM

With ECC

• 16-Bit External Memory Interface (EMIF)

• Hercules™ Common Platform Architecture

– Consistent Memory Map Across Family

– Real-Time Interrupt (RTI) Timer (OS Timer)

• Two 12-Bit Multibuffered Analog-to-Digital

Converter (MibADC) Modules

– MibADC1: 32 Channels Plus Control for up to

1024 Off-Chip Channels

– MibADC2: 25 Channels

– Two 128-Channel Vectored Interrupt Modules

(VIMs) With ECC Protection on Vector Table

– VIM1 and VIM2 in Safety Lockstep Mode

– Two 2-Channel Cyclic Redundancy Checker

(CRC) Modules

– 16 Shared Channels

– 64 Result Buffers Each With Parity Protection

• Enhanced Timing Peripherals

– 7 Enhanced Pulse Width Modulator (ePWM)

Modules

– 6 Enhanced Capture (eCAP) Modules

– 2 Enhanced Quadrature Encoder Pulse (eQEP)

Modules

• Direct Memory Access (DMA) Controller

– 32 Channels and 48 Peripheral Requests

– ECC Protection for Control Packet RAM

– DMA Accesses Protected by Dedicated MPU

• Frequency-Modulated Phase-Locked Loop

(FMPLL) With Built-In Slip Detector

• Separate Nonmodulating PLL

• IEEE 1149.1 JTAG, Boundary Scan, and ARM

CoreSight™ Components

• Three On-Die Temperature Sensors

• Up to 145 Pins Available for General-Purpose I/O

(GPIO)

• 16 Dedicated GPIO Pins With External Interrupt

Capability

• Packages

• Advanced JTAG Security Module (AJSM)

• Trace and Calibration Capabilities

– 337-Ball Grid Array (GWT) [Green]

– ETM™, RTP, DMM, POM

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS570LC4357-EP

SPNS253A –MAY 2018–REVISED SEPTEMBER 2019

www.ti.com

• Supports Defense, Aerospace, and Medical

– Available in Extended (–55°C to 125°C)

Applications:

Temperature Range

– Controlled Baseline

– One Assembly/Test Site

– One Fabrication Site

– Extended Product Life Cycle

– Extended Product-Change Notification

– Product Traceability

1.2 Applications

•

Braking Systems (Antilock Brake Systems and

Electronic Stability Control)

•

Active Driver Assistance Systems

Aerospace and Avionics

Railway Communications

Off-road Vehicles

•

Electric Power Steering (EPS)

HEV and EV Inverter Systems

Battery-Management Systems

Device Overview

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SPNS253A –MAY 2018–REVISED SEPTEMBER 2019

1.3 Description

The TMS570LC4357-EP device is part of the Hercules TMS570 series of high-performance automotive-

grade ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available

to assist in the development of ISO 26262 and IEC 61508 functional safety applications. Start evaluating

today with the Hercules TMS570LC43x LaunchPad Development Kit. The TMS570LC4357-EP device has

on-chip diagnostic features including: dual CPUs in lockstep, Built-In Self-Test (BIST) logic for CPU, the

N2HET coprocessors, and for on-chip SRAMs; ECC protection on the L1 caches, L2 flash, and SRAM

memories. The device also supports ECC or parity protection on peripheral memories and loopback

capability on peripheral I/Os.

The TMS570LC4357-EP device integrates two ARM Cortex-R5F floating-point CPUs, operating in

lockstep, which offer an efficient 1.66 DMIPS/MHz, and can run up to 300 MHz providing up to 498

DMIPS. The device supports the big-endian [BE32] format.

The TMS570LC4357-EP device has 4MB of integrated flash and 512KB of data RAM with single-bit error

correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically

erasable and programmable memory, implemented with a 64-bit-wide data bus interface. The flash

operates on a 3.3-V supply input (the same level as the I/O supply) for all read, program, and erase

operations. The SRAM supports read and write accesses in byte, halfword, and word modes.

The TMS570LC4357-EP device features peripherals for real-time control-based applications, including two

Next Generation High-End Timer (N2HET) timing coprocessors with up to 64 total I/O terminals.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, with a specialized timer micromachine and an attached I/O

port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO.

The N2HET is especially well suited for applications requiring multiple sensor information or drive

actuators with complex and accurate time pulses. The High-End Timer Transfer Unit (HTU) can perform

DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU)

is built into the HTU.

The Enhanced Pulse Width Modulator (ePWM) module can generate complex pulse width waveforms with

minimal CPU overhead or intervention. The ePWM is easy to use and supports both high-side and low-

side PWM and deadband generation. With integrated trip zone protection and synchronization with the on-

chip MibADC, the ePWM is ideal for digital motor control applications.

The Enhanced Capture (eCAP) module is essential in systems where the accurately timed capture of

external events is important. The eCAP can also be used to monitor the ePWM outputs or for simple PWM

generation when not needed for capture applications.

The Enhanced Quadrature Encoder Pulse (eQEP) module directly interfaces with a linear or rotary

incremental encoder to get position, direction, and speed information from a rotating machine as used in

high-performance motion and position-control systems.

The device has two 12-bit-resolution MibADCs with 41 total channels and 64 words of parity-protected

buffer RAM. The MibADC channels can be converted individually or by group for special conversion

sequences. Sixteen channels are shared between the two MibADCs. Each MibADC supports three

separate groupings. Each sequence can be converted once when triggered or configured for continuous

conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster

conversion time is desired. One of the channels in MibADC1 and two of the channels in MibADC2 can be

used to convert temperature measurements from the three on-chip temperature sensors.

The device has multiple communication interfaces: Five MibSPIs; four UART (SCI) interfaces, two with LIN

support; four CANs; two I2C modules; one Ethernet Controller; and one FlexRay controller. The SPI

provides a convenient method of serial interaction for high-speed communications between similar shift-

UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the

CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently

supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal

Device Overview

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SPNS253A –MAY 2018–REVISED SEPTEMBER 2019

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for applications operating in noisy and harsh environments (for example, automotive and industrial fields)

that require reliable serial communication or multiplexed wiring. The FlexRay controller uses a dual-

channel serial, fixed time base multimaster communication protocol with communication rates of 10 Mbps

per channel. A FlexRay Transfer Unit (FTU) enables autonomous transfers of FlexRay data to and from

main CPU memory. HTU transfers are protected by a dedicated, built-in MPU. The Ethernet module

supports MII, RMII, and Management Data I/O (MDIO) interfaces. The I2C module is a multimaster

communication module providing an interface between the microcontroller and an I²C-compatible device

through the I²C serial bus. The I2C module supports speeds of 100 and 400 kbps.

The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module multiplies the external frequency

reference to a higher frequency for internal use. The Global Clock Module (GCM) manages the mapping

between the available clock sources and the internal device clock domains.

The device also has two External Clock Prescaler (ECP) modules. When enabled, the ECPs output a

continuous external clock on the ECLK1 and ECLK2 balls. The ECLK frequency is a user-programmable

ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored

externally as an indicator of the device operating frequency.

The Direct Memory Access (DMA) controller has 32 channels, 48 peripheral requests, and ECC protection

on its memory. An MPU is built into the DMA to protect memory against erroneous transfers.

The Error Signaling Module (ESM) monitors on-chip device errors and determines whether an interrupt or

external Error pin/ball (nERROR) is triggered when a fault is detected. The nERROR signal can be

monitored externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous

memories or other slave devices.

A Parameter Overlay Module (POM) is included to enhance the debugging capabilities of application code.

The POM can reroute flash accesses to internal RAM or to the EMIF, thus avoiding the reprogramming

steps necessary for parameter updates in flash. This capability is particularly helpful during real-time

system calibration cycles.

Several interfaces are implemented to enhance the debugging capabilities of application code. In addition

to the built-in ARM Cortex-R5F CoreSight debug features, the Embedded Cross Trigger (ECT) supports

the interaction and synchronization of multiple triggering events within the SoC. An External Trace

Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes,

a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral

accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write

external data into the device memory. Both the RTP and DMM have no or minimal impact on the program

execution time of the application code.

With integrated safety features and a wide choice of communication and control peripherals, the

TMS570LC4357-EP device is an ideal solution for high-performance real-time control applications with

safety-critical requirements.

Table 1-1. Device Information⁽¹⁾

PART NUMBER

TMS570LC4357-EP

PACKAGE

BODY SIZE

NFBGA (337)

16.00 mm × 16.00 mm

(1) For more information on these devices, see Section 9, Mechanical Packaging and Orderable

Information.

Device Overview

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SPNS253A –MAY 2018–REVISED SEPTEMBER 2019

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

32KB Icache

& Dcache w/

ECC

RTP

TPIU

FTU

EMAC

NMPU

Dual Cortex -R5F

CPUs in lockstep

NMPU

HTU1

HTU2

DMM

DMA

DAP

CPU Interconnect Subsystem

Peripheral Interconnect Subsystem

PCR2

PCR3

CRC

1,2

PCR1

IOMM

CAN1_RX

EMIF_nWAIT

EMIF_CLK

EMIF_CKE

EMIF_nCS[4:2]

EMIF_ADDR[21:0]

EMIF_nCS[0]

EMIF_DATA[15:0]

EMIF_BA[1:0]

EMIF_nDQM[1:0]

EMIF_nOE

EMIF

Slave

POM

512KB

SRAM

DCAN1

DCAN2

DCAN3

DCAN4

CAN1_TX

CAN2_RX

CAN2_TX

CAN3_RX

CAN3_TX

4MB Flash

128KB

PMM

EPC

SCM

SYS

EMAC Slaves

ECC

MDCLK

MDIO

Flash for

EEPROM

Emulation

w/ ECC

EMIF

MDIO

CAN4_RX

CAN4_TX

MII_RXD[3:0]

MII_RXER

MII_TXD[3:0]

MII_TXEN

MII_TXCLK

MII_RXCLK

MII_CRS

MII_RXDV

EMIF_nWE

MIBSPI1_CLK

MIBSPI1_SIMO[1:0]

MIBSPI1_SOMI[1:0]

EMIF_nRAS

EMIF_nCAS

EMIF_nRW

MII

CCM-

R5F

MibSPI1

MibSPI2

MibSPI3

MibSPI4

MibSPI5

MIBSPI1_nCS[5:0]

MIBSPI1_nENA

Lockstep

VIMs

MIBSPI2_CLK

MIBSPI2_SIMO

MIBSPI2_SOMI

MII_COL

Color Legend for

Power Domains

eQEPxA

RTI

eQEP

1,2

eQEPxB

eQEPxS

eQEPxI

MIBSPI2_nCS[1:0]

MIBSPI2_nENA

Core/RAM

Core

DCC1

STC1

DCC2

STC2

always on

# 2

MIBSPI3_CLK

# 3

# 4

MIBSPI3_SIMO

MIBSPI3_SOMI

MIBSPI3_nCS[5:0]

MIBSPI3_nENA

eCAP

1..6

eCAP[6:1]

nTZ[3:1]

SYNCO

SYNCI

MIBSPI4_CLK

ePWM

1..7

nPORRST

nRST

MIBSPI4_SIMO

MIBSPI4_SOMI

MIBSPI4_nCS[5:0]

MIBSPI4_nENA

MIBSPI5_CLK

SYS

ECLK[2:1]

ePWMxA

ePWMxB

ESM

nERROR

MIBSPI5_SIMO[3:0]

MIBSPI5_SOMI[3:0]

MIBSPI5_nCS[5:0]

MIBSPI5_nENA

LIN1/

SCI1

LIN2/

SCI2

LIN1_RX

LIN1_TX

FlexRay

MibADC1

MibADC2

N2HET1 N2HET2

GIO

LIN2_RX

LIN2_TX

SCI3_RX

SCI3_TX

SCI3

SCI4

I2C1

I2C2

SCI4_RX

SCI4_TX

I2C1_SDA

I2C1_SCL

I2C2_SDA

I2C2_SCL

Figure 1-1. Functional Block Diagram

Device Overview

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Table of Contents

Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 2

1.3 Description............................................ 3

1.4 Functional Block Diagram ............................ 5

Revision History ......................................... 7

Terminal Configuration and Functions.............. 8

5.13 On-Chip SRAM Initialization and Testing .......... 104

5.14 External Memory Interface (EMIF)................. 108

5.15 Vectored Interrupt Manager........................ 116

5.16 ECC Error Event Monitoring and Profiling ......... 120

5.17 DMA Controller..................................... 122

5.18 Real-Time Interrupt Module........................ 126

5.19 Error Signaling Module............................. 128

5.20 Reset / Abort / Error Sources...................... 133

5.21 Digital Windowed Watchdog....................... 137

5.22 Debug Subsystem ................................. 138

3.1

GWT BGA Package Ball-Map (337 Terminal Grid

Array) ................................................. 8

3.2 Terminal Functions ................................... 9

Specifications ........................................... 54

4.1 Absolute Maximum Ratings......................... 54

4.2 ESD Ratings ........................................ 54

4.3 Power-On Hours (POH)............................. 54

4.4 Recommended Operating Conditions............... 55

Peripheral Information and Electrical

Specifications ......................................... 155

6.1

Enhanced Translator PWM Modules (ePWM)..... 155

6.2 Enhanced Capture Modules (eCAP)............... 160

6.3

Enhanced Quadrature Encoder (eQEP) ........... 163

12-bit Multibuffered Analog-to-Digital Converter

4.5

Switching Characteristics Over Recommended

6.4

Operating Conditions for Clock Domains ........... 56

(MibADC)........................................... 165

4.6 Wait States Required - L2 Memories ............... 56

4.7 Power Consumption Summary...................... 58

6.5 General-Purpose Input/Output..................... 178

6.6 Enhanced High-End Timer (N2HET) .............. 179

6.7 FlexRay Interface .................................. 184

6.8 Controller Area Network (DCAN) .................. 186

4.8

Input/Output Electrical Characteristics Over

Recommended Operating Conditions............... 59

Thermal Resistance Characteristics for the BGA

4.9

6.9

Local Interconnect Network Interface (LIN)........ 187

Package (GWT) ..................................... 60

6.10 Serial Communication Interface (SCI) ............. 188

4.10 Timing and Switching Characteristics............... 60

6.11 Inter-Integrated Circuit (I2C) ....................... 189

System Information and Electrical

6.12 Multibuffered / Standard Serial Peripheral

Specifications ........................................... 63

Interface............................................ 192

5.1 Device Power Domains ............................. 63

5.2 Voltage Monitor Characteristics ..................... 64

6.13 Ethernet Media Access Controller ................. 206

Applications, Implementation, and Layout ...... 210

7.1 TI Design or Reference Design.................... 210

Device and Documentation Support.............. 211

8.1 Device Support..................................... 211

8.2 Documentation Support............................ 213

8.3 Trademarks ........................................ 213

8.4 Electrostatic Discharge Caution ................... 213

8.5 Glossary............................................ 213

8.6 Device Identification................................ 214

8.7 Module Certifications............................... 216

Mechanical Data....................................... 222

9.1 Packaging Information ............................. 222

5.3

Power Sequencing and Power-On Reset ........... 65

5.4 Warm Reset (nRST)................................. 67

5.5 ARM Cortex-R5F CPU Information ................. 68

5.6 Clocks ............................................... 75

5.7 Clock Monitoring .................................... 86

5.8 Glitch Filters......................................... 88

5.9 Device Memory Map ................................ 89

5.10 Flash Memory...................................... 100

5.11 L2RAMW (Level 2 RAM Interface Module) ........ 103

5.12 ECC / Parity Protection for Accesses to Peripheral

RAMs .............................................. 103

Table of Contents

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SPNS253A –MAY 2018–REVISED SEPTEMBER 2019

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (May 2018) to Revision A

Page

•

Deleted extraneous row for MIBSPI1NCS[1]/N2HET1[17] in the GWT Enhanced High-End Timer Modules

(N2HET) table ....................................................................................................................... 14

Added missing section for ethernet controller to the GWT Package section................................................ 32

Added missing section for external memory interface (EMIF) to the GWT Package section ............................. 35

Changed operating free-air temperature minimum from –40°C to –55°C in Absolute Maximum Ratings .............. 54

Changed operating free-air temperature minimum from –40°C to –55°C in Recommended Operating Conditions .. 55

Changed operating junction temperature maximum from 125°C to 150°C in Recommended Operating Conditions.. 55

•

Revision History

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3 Terminal Configuration and Functions

3.1 GWT BGA Package Ball-Map (337 Terminal Grid Array)

AD1IN[15] AD1IN[22]

/ /

AD2IN[15] AD2IN[06]

AD1IN[11]

AD2IN[11]

N2HET1

[10]

MIBSPI5

NCS[0]

MIBSPI1

SIMO[0]

MIBSPI1

NENA

MIBSPI5

CLK

MIBSPI5

SIMO[0]

N2HET1

[28]

DMM_

DATA[0]

AD1IN

[06]

VSS

TMS

DCAN3RX AD1EVT

DCAN3TX AD1IN[24]

AD2IN[24]

VSSAD

AD1IN[08] AD1IN[14] AD1IN[13]

N2HET1

[08]

MIBSPI1

CLK

MIBSPI1

SOMI[0]

MIBSPI5

NENA

MIBSPI5

SOMI[0]

N2HET1

[0]

DMM_

DATA[1]

AD1IN

[04]

AD1IN

[02]

VSS

TDI

TCK

TDO

nTRST

AD2IN[08] AD2IN[14] AD2IN[13]

AD2IN[24]

AD1IN[10]

AD2IN[10]

AD1IN[09]

AD2IN[09]

EMIF_

ADDR[21]

EMIF_

nWE

MIBSPI5

SOMI[1]

DMM_

CLK

MIBSPI5

SIMO[3]

MIBSPI5

SIMO[2]

N2HET1

[31]

EMIF_

nCS[3]

EMIF_

nCS[2]

EMIF_

nCS[4]

EMIF_

nCS[0]

AD1IN

[05]

AD1IN

[03]

AD1IN

[01]

nRST

AD1IN[25]

AD1IN[26]

AD1IN[23] AD1IN[12] AD1IN[19]

AD2IN[07] AD2IN[12] AD2IN[03]

FRAY

TXEN1

EMIF_

ADDR[20]

EMIF_

BA[1]

MIBSPI5

SIMO[1]

DMM_

nENA

MIBSPI5

SOMI[3]

MIBSPI5

SOMI[2]

DMM_

SYNC

N2HET2

[08]

N2HET2

[09]

N2HET2

[10]

N2HET2

[11]

RTCK

ADREFLO

ADREFHI

VSSAD

VCCAD

ETM

AD1IN[21] AD1IN[20]

AD2IN[05] AD2IN[04]

EMIF_ ETM

ADDR[19] ADDR[18] DATA[06] DATA[05] DATA[04] DATA[03] DATA[02]

EMIF_

ETM

DATA[16] / DATA[17] / DATA[18] / DATA[19] /

AD1IN[27] AD1IN[28]

FRAYRX1 FRAYTX1

EMIF_

DATA[0]

EMIF_

DATA[1]

EMIF_

DATA[2]

EMIF_

DATA[3]

AD1IN[18]

AD2IN[02]

N2HET1

nERROR

[26]

EMIF_ ETM

ADDR[17] ADDR[16] DATA[07]

EMIF_

AD1IN

[07]

AD1IN

[0]

VCCIO

VCC

VCCIO

VCC

VCCIO

VCCPLL

VCC

AD1IN[29] AD1IN[30]

ETM

N2HET2 DATA[12] /

[04]

AD1IN[17] AD1IN[16]

AD2IN[01] AD2IN[0]

N2HET1

[17]

N2HET1

[19]

EMIF_

ADDR[15]

ETM

DATA[01]

AD1IN[31]

AD2IN[16]

EMIF_BA[

ETM

DATA[13] /

EMIF_nOE

N2HET1

[04]

EMIF_

ADDR[14]

N2HET2

[05]

ETM

DATA[0]

MIBSPI5

NCS[3]

ECLK

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

AD2IN[19] AD2IN[18] AD2IN[17]

ETM

N2HET2 DATA[14] /

[06]

ETM

TRACE

CTL

N2HET1

[14]

N2HET1

[30]

EMIF_

ADDR[13]

AD2IN[20] AD2IN[21] AD2IN[22] AD2IN[23]

EMIF_

nDQM[1]

ETM

TRACE

CLKOUT

EMIF_

ADDR[12]

DATA[15] /

EMIF_

nDQM[0]

MIBSPI1

NCS[4]

MIBSPI3

NCS[0]

DCAN1TX DCAN1RX

ePWM1B

AD2EVT

MDCLK

GIOB[3]

ETM

DATA[08] /

EMIF_

ETM

TRACE

CLKIN

N2HET1

[27]

FRAY

TXEN2

EMIF_

ADDR[11]

MIBSPI1

NCS[5]

MIBSPI3

CLK

MIBSPI3

NENA

ePWM1A

VCC

VCCIO

ADDR[5]

ETM

DATA[09] /

EMIF_

ETM

DATA[31] / N2HET2

EMIF_

DATA[15]

EMIF_

ADDR[10]

MII_TXD

[0]

MIBSPI3

SOMI

MIBSPI3

SIMO

FRAYRX2 FRAYTX2

N2HET2[1]

VCCP

VCCIO

[23]

ADDR[4]

ETM

N2HET2 DATA[10] /

[2]

ETM

DATA[30] / N2HET2

EMIF_

DATA[14]

EMIF_

ADDR[9]

MII_TX_

CLK

N2HET1

[09]

LIN1RX

GIOA[4]

GIOA[0]

LIN1TX

nPORRST

EMIF_

ADDR[3]

[22]

ETM

N2HET2 DATA[11] /

[0]

ETM

DATA[29] / N2HET2

EMIF_

DATA[13]

MIBSPI5

NCS[1]

EMIF_

ADDR[8]

MII_RX_

N2HET1

[05]

MIBSPI5

NCS[2]

VCCIO

ETM

VCCIO

ETM

VCCIO

FLTP2

VCCIO

FLTP1

VCC

ETM

VCC

ETM

VCCIO

ETM

VCCIO

ETM

VCCIO

ETM

EMIF_

ADDR[2]

[21]

ETM

EMIF_

ADDR[7]

EMIF_

ADDR[1]

DATA[20] / DATA[21] / DATA[22] /

EMIF_

DATA[5]

DATA[23] / DATA[24] / DATA[25] / DATA[26] / DATA[27] / DATA[28] / N2HET2

[20]

MII_RX_

MIBSPI3

NCS[1]

N2HET1

[02]

GIOA[5]

EMIF_

DATA[4]

EMIF_

DATA[6]

EMIF_

DATA[7]

EMIF_

DATA[8]

EMIF_

DATA[9]

EMIF_

DATA[10] DATA[11] DATA[12]

EMIF_

N2HET1

[16]

N2HET1

[12]

EMIF_

ADDR[6]

EMIF_

ADDR[0]

MII_TXD

[3]

N2HET1

[21]

N2HET1

[23]

N2HET2

[15]

N2HET2

[16]

N2HET2

[17]

N2HET2

[18]

N2HET2

[19]

EMIF_

nCAS

MII_

RXCLK

MII_RXD

[0]

MII_TXEN

MDIO

MII_CRS

MII_COL

N2HET1

[29]

N2HET1

[22]

MIBSPI3

NCS[3]

N2HET2

[12]

N2HET1

[11]

MIBSPI1

NCS[1]

MIBSPI1

NCS[2]

MIBSPI1

NCS[3]

EMIF_

CLK

EMIF_

CKE

N2HET1

[25]

N2HET2

[7]

EMIF_

nWAIT

EMIF_

nRAS

MII_RXD

[1]

MII_RXD

[2]

MII_RXD

[3]

N2HET1

[06]

GIOA[6]

MIBSPI3

NCS[2]

N2HET2

[13]

N2HET2

[3]

KELVIN_

GND

N2HET1

[13]

N2HET1

[20]

MIBSPI1

NCS[0]

MII_TXD

[2]

N2HET1

[1]

VSS

GIOA[1]

GIOB[2]

GIOB[5]

DCAN2TX

GIOB[6]

GIOB[1]

GIOB[0]

TEST

VSS

N2HET2

[14]

N2HET1

[18]

N2HET1

[15]

N2HET1

[24]

MII_TXD

[1]

N2HET1

[7]

NHET1

[03]

VSS

GIOA[2]

GIOA[3]

GIOB[7]

GIOB[4]

DCAN2RX

OSCIN

OSCOUT

GIOA[7]

VSS

Figure 3-1. GWT Package Pinout - Top View

Note: Balls can have multiplexed functions. See Section 3.2.2 for detailed information.

Terminal Configuration and Functions

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SPNS253A –MAY 2018–REVISED SEPTEMBER 2019

3.2 Terminal Functions

Table 3-1 through Table 3-27 identify the external signal names, the associated terminal numbers along

with the mechanical package designator, the terminal type (Input, Output, I/O, Power, or Ground), whether

the terminal has any internal pullup/pulldown, whether the terminal can be configured as a GIO, and a

functional terminal description. The first signal name listed is the primary function for that terminal. The

signal name in Bold is the function being described. For information on how to select between different

multiplexed functions, see the Section 3.2.2, Multiplexing of this data manual along with the I/O

Multiplexing Module (IOMM) chapter in the Technical Reference Manual (TRM) (SPNU563).

NOTE

In the Terminal Functions tables below, the "Default Pull State" is the state of the pull applied

to the terminal while nPORRST is low and immediately after nPORRST goes High. The

default pull direction may change when software configures the pin for an alternate function.

The "Pull Type" is the type of pull asserted when the signal name in bold is enabled for the

given terminal by the IOMM control registers.

All I/O signals except nRST are configured as inputs while nPORRST is low and immediately

after nPORRST goes High. While nPORRST is low, the input buffers are disabled, and the

output buffers are disabled with the default pulls enabled.

All output-only signals have the output buffer disabled and the default pull enabled while

nPORRST is low, and are configured as outputs with the pulls disabled immediately after

nPORRST goes High.

Terminal Configuration and Functions

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3.2.1 GWT Package

3.2.1.1 Multibuffered Analog-to-Digital Converters (MibADC)

Table 3-1. GWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)

TERMINAL

OUTPUT

BUFFER

DRIVE

SIGNAL

TYPE

DEFAULT

PULL STATE

PULL TYPE

DESCRIPTION

337

GWT

SIGNAL NAME

STRENGTH

AD1EVT/MII_RX_ER/RMII_RX_ER/nTZ1_1

AD1IN[0]

N19

W14

V17

V18

T17

U18

R17

T19

V14

P18

W17

U17

U19

T16

T18

R18

P19

V13

U13

U14

U16

U15

T15

R19

R16

N18

I/O

Pulldown

Programmable, 20 µA

2-mA ZD

ADC1 event trigger input, or GIO

ADC1 Input

Input

AD1IN[1]

ADC1 Input

AD1IN[2]

ADC1 Input

AD1IN[3]

ADC1 Input

AD1IN[4]

ADC1 Input

AD1IN[5]

ADC1 Input

AD1IN[6]

ADC1 Input

AD1IN[7]

ADC1 Input

AD1IN[8]/AD2IN[8]

AD1IN[9]/AD2IN[9]

AD1IN[10]/AD2IN[10]

AD1IN[11]/AD2IN[11]

AD1IN[12]/AD2IN[12]

AD1IN[13]/AD2IN[13]

AD1IN[14]/AD2IN[14]

AD1IN[15]/AD2IN[15]

AD1IN[16]/AD2IN[0]

AD1IN[17]/AD2IN[1]

AD1IN[18]/AD2IN[2]

AD1IN[19]/AD2IN[3]

AD1IN[20]/AD2IN[4]

AD1IN[21]/AD2IN[5]

AD1IN[22]/AD2IN[6]

AD1IN[23]/AD2IN[7]

AD1IN[24]

ADC1/ADC2 shared Input

ADC1 Input

Terminal Configuration and Functions

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SPNS253A –MAY 2018–REVISED SEPTEMBER 2019

Table 3-1. GWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) (continued)

TERMINAL

OUTPUT

BUFFER

DRIVE

SIGNAL

TYPE

DEFAULT

PULL STATE

PULL TYPE

DESCRIPTION

337

GWT

SIGNAL NAME

STRENGTH

AD1IN[25]

P17

P16

P15

R15

R14

T14

Input

ADC1 Input

ADC1 Input(1)

AD1IN[26]

AD1IN[27]

AD1IN[28]

AD1IN[29]

AD1IN[30]

AD1IN[31]

T13

AD2EVT

T10

I/O

Pulldown

Programmable, 20 µA

2-mA ZD

ADC2 event trigger input, or GIO

MIBSPI3NCS[0]/AD2EVT/eQEP1I

AD2IN[16]

V10(2)

W13

W12

V12

U12

T11

Input

ADC2 Input

AD2IN[17]

AD2IN[18]

AD2IN[19]

AD2IN[20]

AD2IN[21]

U11

V11

W11

V19

W18

V15(3)

V16(3)

AD2IN[22]

AD2IN[23]

AD2IN[24]

Input

ADC2 Input

AD2IN[24]

ADREFHI

Input

ADC high reference supply

ADC low reference supply

ADREFLO

MIBSPI3SOMI/AD1EXT_ENA/ECAP2

Output

Pullup

20 µA

2-mA ZD

External Mux ENA

MIBSPI5SOMI[3]/DMM_DATA[15]/I2C2_SCL/AD1EXT_ENA

MIBSPI3SIMO/AD1EXT_SEL[0]/ECAP3

G16

External Mux Select 0

External Mux Select 1

MIBSPI5SIMO[1]/DMM_DATA[9]/AD1EXT_SEL[0]

MIBSPI3CLK/AD1EXT_SEL[1]/eQEP1A

E16

MIBSPI5SIMO[2]/DMM_DATA[10]/AD1EXT_SEL[1]

MIBSPI5SIMO[3]/DMM_DATA[11]/I2C2_SDA/AD1EXT_SEL[2]

MIBSPI5SOMI[1]/DMM_DATA[13]/AD1EXT_SEL[3]

MIBSPI5SOMI[2]/DMM_DATA[14]/AD1EXT_SEL[4]

H17

G17

E17

H16

Output

Pullup

20 µA

2-mA ZD

External Mux Select 2

External Mux Select 3

External Mux Select 4

Terminal Configuration and Functions

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Table 3-1. GWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) (continued)

TERMINAL

OUTPUT

BUFFER

DRIVE

SIGNAL

TYPE

DEFAULT

PULL STATE

PULL TYPE

DESCRIPTION

337

GWT

SIGNAL NAME

STRENGTH

VCCAD

VSSAD

W15(3)

W16(3)

W19(3)

Input

Operating supply for ADC

ADC supply ground

(1) This ADC channel is also multiplexed with an internal temperature sensor.

(2) This is the secondary terminal at which the signal is also available. See Section 3.2.2.2 for more detail on how to select between the available terminals for input functionality.

(3) The ADREFHI, ADREFLO, VCCAD, and VSSAD connections are common for both ADC cores.

Terminal Configuration and Functions

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3.2.1.2 Enhanced High-End Timer Modules (N2HET)

Table 3-2. GWT Enhanced High-End Timer Modules (N2HET)

Terminal

Output

Signal

Type

Default Pull

State

Buffer

Pull Type

Description

Drive

337

GWT

Signal Name

Strength

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

N2HET1[0]/MIBSPI4CLK/ePWM2B

K18

I/O

Pulldown

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

N2HET1[1]/MIBSPI4NENA/N2HET2[8]/eQEP2A

N2HET1[2]/MIBSPI4SIMO/ePWM3A

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

N2HET1[3]/MIBSPI4NCS[0]/N2HET2[10]/eQEP2B

N2HET1[4]/MIBSPI4NCS[1]/ePWM4B

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

B12

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

N2HET1[5]/MIBSPI4SOMI/N2HET2[12]/ePWM3B

N2HET1[6]/SCI3RX/ePWM5A

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

N2HET1[7]/MIBSPI4NCS[2]/N2HET2[14]/ePWM7B

N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]

N2HET1[9]/MIBSPI4NCS[3]/N2HET2[16]/ePWM7A

N2HET1[10]/MIBSPI4NCS[4]/MII_TX_CLK/nTZ1_3

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ePWM1SYNCO

N2HET1[12]/MIBSPI4NCS[5]/MII_CRS/RMII_CRS_DV

N2HET1[13]/SCI3TX/N2HET2[20]/ePWM5B

N2HET1[14]

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

8 mA

E18

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

D19

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

A11

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

N2HET1[15]/MIBSPI1NCS[4]/N2HET2[22]/ECAP1

N2HET1[16]/ePWM1SYNCI/ePWM1SYNCO

output compare, or GIO

Programmable,

20 µA

N2HET1 time input capture or

2-mA ZD

output compare, or GIO

Terminal Configuration and Functions

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Table 3-2. GWT Enhanced High-End Timer Modules (N2HET) (continued)

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

Strength

N2HET1[17]/EMIF_nOE/SCI4RX

A13

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

I/O

Pulldown

2-mA ZD

2m A ZD

2-mA ZD

MIBSPI1NCS[1]/MII_COL/N2HET1[17]/eQEP1S

F3(1)

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

N2HET1[18]/EMIF_RNW/ePWM6A

N2HET1[19]/EMIF_nDQM[0]/SCI4TX

MIBSPI1NCS[2]/MDIO/N2HET1[19]

B13

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

G3(1)

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

N2HET1[20]/EMIF_nDQM[1]/ePWM6B

N2HET1[21]/EMIF_nDQM[2

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

MIBSPI1NCS[3]/N2HET1[21]/nTZ1_3

J3(1)

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

N2HET1[22]/EMIF_nDQM[3]

N2HET1[23]/EMIF_BA[0]

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

MIBSPI1NENA/MII_RXD[2]/N2HET1[23]/ECAP4

G19(1)

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]

N2HET1[25]

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

MIBSPI3NCS[1]/MDCLK/N2HET1[25]

V5(1)

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

N2HET1[26]/MII_RXD[1]/RMII_RXD[1]

A14

N2HET1[27]

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

MIBSPI3NCS[2]/I2C1_SDA/N2HET1[27]/nTZ1_2

B2(1)

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

N2HET1[28]/MII_RXCLK/RMII_REFCLK

K19

N2HET1[29]

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

MIBSPI3NCS[3]/I2C1_SCL/N2HET1[29]/nTZ1_1

C3(1)

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

N2HET1[30]/MII_RX_DV/eQEP2S

B11

N2HET1[31]

J17

W9(1)

Programmable,

20 µA

N2HET1 time input capture or

output compare, or GIO

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/eQEP1B

N2HET2[0]

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

I/O

Pulldown

2-mA ZD

GIOA[2]/N2HET2[0]/eQEP2I

N2HET2[1]/N2HET1_NDIS

EMIF_ADDR[0]/N2HET2[1]

C1(1)

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

D4(1)

Terminal Configuration and Functions

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Table 3-2. GWT Enhanced High-End Timer Modules (N2HET) (continued)

Terminal

Output

Signal

Type

Default Pull

State

Buffer

Pull Type

Description

Drive

337

GWT

Signal Name

Strength

N2HET2[2]/N2HET2_NDIS

GIOA[3]/N2HET2[2]

E1(1)

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

I/O

Pulldown

output compare, or GIO

N2HET2[3]/MIBSPI2CLK

EMIF_ADDR[1]/N2HET2[3]

N2HET2[4]

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

D5(1)

D13

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

GIOA[6]/N2HET2[4]/ePWM1B

N2HET2[5]

H3(1)

D12

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

EMIF_BA[1]/N2HET2[5]

N2HET2[6]

D16(1)

D11

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

GIOA[7]/N2HET2[6]/ePWM2A

N2HET2[7]/MIBSPI2NCS[0]

M1(1)

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]

N2HET2[8]

N17(1)

K16

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

N2HET1[1]/MIBSPI4NENA/N2HET2[8]/eQEP2A

N2HET2[9]

V2(1)

L16

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]

N2HET2[10]

K17(1)

M16

U1(1)

N16

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

N2HET1[3]/MIBSPI4NCS[0]/N2HET2[10]/eQEP2B

N2HET2[11]

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11]

N2HET2[12]/MIBSPI2NENA/MIBSPI2NCS[1]

N2HET1[5]/MIBSPI4SOMI/N2HET2[12]/ePWM3B

N2HET2[13]/MIBSPI2SOMI

C4(1)

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

V6(1)

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13]

N2HET2[14]/MIBSPI2SIMO

C5(1)

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

N2HET1[7]/MIBSPI4NCS[2]/N2HET2[14]/ePWM7B

N2HET2[15]

T1(1)

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

output compare, or GIO

EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15]

N2HET2[16]

C6(1)

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

I/O

Pulldown

output compare, or GIO

N2HET1[9]/MIBSPI4NCS[3]/N2HET2[16]/ePWM7A

V7(1)

Programmable,

20 µA

N2HET2 time input capture or

2-mA ZD

N2HET2[17]

output compare, or GIO

Terminal Configuration and Functions

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Table 3-2. GWT Enhanced High-End Timer Modules (N2HET) (continued)

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

Strength

N2HET2[18]

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

I/O

Pulldown

2-mA ZD

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ePWM1SYNCO

E3(1)

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

N2HET2[19]/LIN2RX

N2HET2[20]/LIN2TX

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

N2HET1[13]/SCI3TX/N2HET2[20]/ePWM5B

N2(1)

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

N2HET2[21]

N2HET2[22]

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

N2HET1[15]/MIBSPI1NCS[4]/N2HET2[22]/ECAP1

N1(1)

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

N2HET2[23]

I/O

Pulldown

2-mA ZD

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

ETMDATA[24]/EMIF_DATA[8]/N2HET2[24]/MIBSPI5NCS[4]

ETMDATA[25]/EMIF_DATA[9]/N2HET2[25]/MIBSPI5NCS[5]

ETMDATA[26]/EMIF_DATA[10]/N2HET2[26]

ETMDATA[27]/EMIF_DATA[11]/N2HET2[27]

ETMDATA[28]/EMIF_DATA[12]/N2HET2[28]/GIOA[0]

ETMDATA[29]/EMIF_DATA[13]/N2HET2[29]/GIOA[1]

ETMDATA[30]/EMIF_DATA[14]/N2HET2[30]/GIOA[3]

ETMDATA[31]/EMIF_DATA[15]/N2HET2[31]/GIOA[4]

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

Programmable,

20 µA

N2HET2 time input capture or

output compare, or GIO

N2HET2[1]/N2HET1_NDIS

N2HET2[2]/N2HET2_NDIS

Input

Pulldown

Fixed, 20 µA

2-mA ZD

N2HET1 Disable

N2HET2 Disable

(1) This is the secondary terminal at which the signal is also available. See Section 3.2.2.2 for more detail on how to select between the available terminals for input functionality.

Terminal Configuration and Functions

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3.2.1.3 RAM Trace Port (RTP)

Table 3-3. GWT RAM Trace Port (RTP)

Terminal

Default Pull

Output Buffer

Description

Signal Type

Pull Type

337

GWT

State

Drive Strength

Signal Name

EMIF_ADDR[21]/RTP_CLK

C17

D15

C14

D14

C13

C12

C11

C10

M17

I/O

Pulldown

Pullup

Programmable, 20 µA

8 mA

RTP packet clock, or GIO

RTP packet data, or GIO

RTP packet handshake, or GIO

RTP synchronization, or GIO

EMIF_ADDR[18]/RTP_DATA[0]

EMIF_ADDR[17]/RTP_DATA[1]

EMIF_ADDR[16]/RTP_DATA[2]

EMIF_ADDR[15]/RTP_DATA[3]

EMIF_ADDR[14]/RTP_DATA[4]

EMIF_ADDR[13]/RTP_DATA[5]

EMIF_ADDR[12]/RTP_DATA[6]

EMIF_nCS[4]/RTP_DATA[7]/GIOB[5]

EMIF_ADDR[11]/RTP_DATA[8]

EMIF_ADDR[10]/RTP_DATA[9]

EMIF_ADDR[9]/RTP_DATA[10]

EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15]

EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13]

EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11]

EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]

EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]

EMIF_ADDR[19]/RTP_nENA

K17

N17

C15

C16

EMIF_ADDR[20]/RTP_nSYNC

Pullup

(1) This is the secondary terminal at which the signal is also available. See Section 3.2.2.2 for more detail on how to select between the available terminals for input functionality.

Terminal Configuration and Functions

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3.2.1.4 Enhanced Capture Modules (eCAP)

Table 3-4. GWT Enhanced Capture Modules (eCAP)

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

Strength

N2HET1[15]/MIBSPI1NCS[4]/N2HET2[22]/ECAP1

MIBSPI3SOMI/AD1EXT_ENA/ECAP2

I/O

Pullup

Fixed, 20 µA

8 mA

Enhanced Capture Module 1 I/O

Enhanced Capture Module 2 I/O

Enhanced Capture Module 3 I/O

Enhanced Capture Module 4 I/O

Enhanced Capture Module 5 I/O

Enhanced Capture Module 6 I/O

MIBSPI3SIMO/AD1EXT_SEL[0]/ECAP3

G19

H18

MIBSPI1NENA/MII_RXD[2]/N2HET1[23]/ECAP4

MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]/ECAP5

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6

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3.2.1.5 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 3-5. GWT Enhanced Quadrature Encoder Pulse Modules (eQEP)(1)

Terminal

Output

Signal

Type

Default Pull

State

Buffer

Pull Type

Description

Drive

337

GWT

Signal Name

Strength

MIBSPI3CLK/AD1EXT_SEL[1]/eQEP1A

V10

Input

I/O

Pullup

Fixed, 20 µA

Enhanced QEP1 Input A

Enhanced QEP1 Input B

Enhanced QEP1 Index

Enhanced QEP1 Strobe

Enhanced QEP2 Input A

Enhanced QEP2 Input B

Enhanced QEP2 Index

Enhanced QEP2 Strobe

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/eQEP1B

MIBSPI3NCS[0]/AD2EVT/eQEP1I

8 mA

MIBSPI1NCS[1]/MII_COL/N2HET1[17]/eQEP1S

N2HET1[1]/MIBSPI4NENA/N2HET2[8]/eQEP2A

N2HET1[3]/MIBSPI4NCS[0]/N2HET2[10]/eQEP2B

GIOA[2]/N2HET2[0]/eQEP2I

I/O

Input

I/O

8 mA

N2HET1[30]/MII_RX_DV/eQEP2S

B11

I/O

(1) These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

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3.2.1.6 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 3-6. GWT Enhanced Pulse-Width Modulator Modules (ePWM)

TERMINAL

OUTPUT

BUFFER

DRIVE

DEFAULT

PULL

STATE

SIGNAL

TYPE

PULL

TYPE

DESCRIPTION

337

GWT

SIGNAL NAME

ePWM1A

STRENGTH

Output

–

8 mA

Enhanced PWM1 Output A

Enhanced PWM1 Output B

GIOA[5]/EXTCLKIN1/ePWM1A

ePWM1B

B5⁽¹⁾

D10

H3⁽¹⁾

Output

Input

–

8 mA

–

GIOA[6]/N2HET2[4]/ePWM1B

Fixed,

20 µA

External ePWM Sync Pulse

Input

N2HET1[16]/ePWM1SYNCI/ePWM1SYNCO

Pulldown

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/

ePWM1SYNCO

External ePWM Sync Pulse

Output

Pulldown

20 µA

2-mA ZD

N2HET1[16]/ePWM1SYNCI/ePWM1SYNCO

GIOA[7]/N2HET2[6]/ePWM2A

A4⁽¹⁾

Output

Pulldown

–

20 µA

–

8 mA

Enhanced PWM2 Output A

Enhanced PWM2 Output B

Enhanced PWM3 Output A

Enhanced PWM3 Output B

Enhanced PWM4 Output A

Enhanced PWM4 Output B

Enhanced PWM5 Output A

Enhanced PWM5 Output B

Enhanced PWM6 Output A

Enhanced PWM6 Output B

Enhanced PWM7 Output A

Enhanced PWM7 Output B

N2HET1[0]/MIBSPI4CLK/ePWM2B

K18

N2HET1[2]/MIBSPI4SIMO/ePWM3A

N2HET1[5]/MIBSPI4SOMI/N2HET2[12]/ePWM3B

MIBSPI5NCS[0]/DMM_DATA[5]/ePWM4A

N2HET1[4]/MIBSPI4NCS[1]/ePWM4B

N2HET1[6]/SCI3RX/ePWM5A

E19

B12

N2HET1[13]/SCI3TX/N2HET2[20]/ePWM5B

N2HET1[18]/EMIF_RNW/ePWM6A

N2HET1[20]/EMIF_nDQM[1]/ePWM6B

N2HET1[9]/MIBSPI4NCS[3]/N2HET2[16]/ePWM7A

N2HET1[7]/MIBSPI4NCS[2]/N2HET2[14]/ePWM7B

AD1EVT/MII_RX_ER/RMII_RX_ER/nTZ1_1

MIBSPI3NCS[3]/I2C1_SCL/N2HET1[29]/nTZ1_1

GIOB[7]/nTZ1_2

–

N19

C3⁽¹⁾

Fixed,

20 µA

Input

Pulldown

Pullup

–

Trip Zone 1 Input 1

Trip Zone 1 Input 2

Trip Zone 1 Input 3

Fixed,

20 µA

MIBSPI3NCS[2]/I2C1_SDA/N2HET1[27]/nTZ1_2

MIBSPI1NCS[3]/N2HET1[21]/nTZ1_3

N2HET1[10]/MIBSPI4NCS[4]/MII_TX_CLK/nTZ1_3

B2⁽¹⁾

D19⁽¹⁾

Fixed,

20 µA

(1) This is the secondary terminal at which the signal is also available. See Section 3.2.2.2 for more detail on how to select between the

available terminals for input functionality.

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3.2.1.7 Data Modification Module (DMM)

Terminal Configuration and Functions

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Table 3-7. GWT Data Modification Module (DMM)

Terminal

Output Buffer

Drive

Strength

Default Pull

Signal Type

Pull Type

Description

337

GWT

State

Signal Name

DMM_CLK

F17

L19

L18

I/O

Pullup

Programmable, 20 µA

2-mA ZD

DMM clock, or GIO

DMM data, or GIO

DMM handshake, or GIO

DMM_DATA[0]

DMM_DATA[1]

MIBSPI5NCS[2]/DMM_DATA[2]

MIBSPI5NCS[3]/DMM_DATA[3]

T12

H19

E19

MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN

MIBSPI5NCS[0]/DMM_DATA[5]/ePWM4A

MIBSPI5NCS[1]/DMM_DATA[6]

MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]/ECAP5

MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1]

MIBSPI5SIMO[1]/DMM_DATA[9]/AD1EXT_SEL[0]

MIBSPI5SIMO[2]/DMM_DATA[10]/AD1EXT_SEL[1]

MIBSPI5SIMO[3]/DMM_DATA[11]/I2C2_SDA/AD1EXT_SEL[2]

MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0]

MIBSPI5SOMI[1]/DMM_DATA[13]/AD1EXT_SEL[3]

MIBSPI5SOMI[2]/DMM_DATA[14]/AD1EXT_SEL[4]

MIBSPI5SOMI[3]/DMM_DATA[15]/I2C2_SCL/AD1EXT_ENA

DMM_nENA

H18

J19

E16

H17

G17

J18

E17

H16

G16

F16

J16

DMM_SYNC

DMM synchronization, or GIO

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3.2.1.8 General-Purpose Input / Output (GIO)

Table 3-8. GWT General-Purpose Input / Output (GIO)

Terminal

Output Buffer

Drive

Strength

Default Pull

Signal Type

Pull Type

Description

337

GWT

State

Signal Name

GIOA[0]

I/O

Pulldown

Programmable, 20 µA

2-mA ZD

General-purpose I/O, external interrupt capable

ETMDATA[28]/EMIF_DATA[12]/N2HET2[28]/GIOA[0]

GIOA[1]

R5(1)

I/O

Pulldown

Programmable, 20 µA

General-purpose I/O, external interrupt capable

ETMDATA[29]/EMIF_DATA[13]/N2HET2[29]/GIOA[1]

GIOA[2]/N2HET2[0]/eQEP2I

FRAYTX1/GIOA[2]

R6(1)

B15(1)

GIOA[3]/N2HET2[2]

ETMDATA[30]/EMIF_DATA[14]/N2HET2[30]/GIOA[3]

GIOA[4]

R7(1)

ETMDATA[31]/EMIF_DATA[15]/N2HET2[31]/GIOA[4]

GIOA[5]/EXTCLKIN1/ePWM1A

ETMTRACECLKIN/EXTCLKIN2/GIOA[5]

GIOA[6]/N2HET2[4]/ePWM1B

ETMTRACECLKOUT/GIOA[6]

GIOA[7]/N2HET2[6]/ePWM2A

ETMTRACECTL/GIOA[7]

GIOB[0]

R8(1)

R9(1)

R10(1)

R11(1)

FRAYTX2/GIOB[0]

B8(1)

GIOB[1]

FRAYTXEN1/GIOB[1]

B16(1)

GIOB[2]/DCAN4TX

FRAYTXEN2/GIOB[2]

B9(1)

W10

R4(1)

GIOB[3]/DCAN4RX

EMIF_nCAS/GIOB[3]

GIOB[4]

EMIF_nCS[2]/GIOB[4]

L17(1)

GIOB[5]

EMIF_nCS[4]/RTP_DATA[7]/GIOB[5]

M17(1)

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Table 3-8. GWT General-Purpose Input / Output (GIO) (continued)

Terminal

Output Buffer

Drive

Strength

Default Pull

State

Signal Type

Pull Type

Description

337

GWT

Signal Name

GIOB[6]/nERROR

EMIF_nRAS/GIOB[6]

GIOB[7]/nTZ1_2

I/O

Pulldown

Programmable, 20 µA

2-mA ZD

General-purpose I/O, external interrupt capable

R3(1)

I/O

Programmable, 20 µA

EMIF_nWAIT/GIOB[7]

P3(1)

(1) This is the secondary terminal at which the signal is also available. See Section 3.2.2.2 for more detail on how to select between the available terminals for input functionality.

Terminal Configuration and Functions

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3.2.1.9 FlexRay Interface Controller (FlexRay)

Table 3-9. FlexRay Interface Controller (FlexRay)

Terminal

Output

Signal

Type

Default Pull

State

Buffer

Drive

Strength

Pull Type

Description

337

GWT

Signal Name

FRAYRX1

A15

Input

Pullup

Fixed, 100 µA

20 µA

–

FlexRay data receive (channel 1)

FlexRay data receive (channel 2)

FlexRay data transmit (channel 1)

FlexRay data transmit (channel 2)

FlexRay transmit enable (channel 1)

FlexRay transmit enable (channel 2)

FRAYRX2

–

FRAYTX1/GIOA[2]

FRAYTX2/GIOB[0]

FRAYTXEN1/GIOB[1]

FRAYTXEN2/GIOB[2]

B15

Output

Pulldown

8 mA

20 µA

B16

20 µA

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3.2.1.10 Controller Area Network Controllers (DCAN)

Table 3-10. GWT Controller Area Network Controllers (DCAN)

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

DCAN1RX

Strength

B10

A10

I/O

Pullup

Programmable,

20 µA

2-mA ZD

CAN1 receive, or GIO

DCAN1TX

Programmable,

20 µA

CAN1 transmit, or GIO

CAN2 receive, or GIO

CAN2 transmit, or GIO

CAN3 receive, or GIO

CAN3 transmit, or GIO

CAN4 receive, or GIO

CAN4 transmit, or GIO

DCAN2RX

Pullup

Programmable,

20 µA

DCAN2TX

Pullup

Programmable,

20 µA

DCAN3RX

M19

M18

W10

Pullup

Programmable,

20 µA

DCAN3TX

Pullup

Programmable,

20 µA

GIOB[3]/DCAN4RX

GIOB[2]/DCAN4TX

Pulldown

Programmable,

20 µA

Programmable,

20 µA

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3.2.1.11 Local Interconnect Network Interface Module (LIN)

Table 3-11. GWT Local Interconnect Network Interface Module (LIN)

Terminal

Output

Signal

Type

Default Pull

State

Buffer

Pull Type

Description

Drive

337

GWT

Signal Name

LIN1RX

Strength

I/O

Pullup

Programmable,

20 µA

2-mA ZD

LIN receive, or GIO

LIN transmit, or GIO

LIN receive, or GIO

LIN transmit, or GIO

LIN1TX

Programmable,

20 µA

N2HET2[19]/LIN2RX

N2HET2[20]/LIN2TX

Pulldown

Programmable,

20 µA

Programmable,

20 µA

Terminal Configuration and Functions

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3.2.1.12 Standard Serial Communication Interface (SCI)

Table 3-12. GWT Standard Serial Communication Interface (SCI)

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

Strength

N2HET1[6]/SCI3RX/ePWM5A

I/O

Pulldown

Programmable,

20 µA

2-mA ZD

SCI receive, or GIO

SCI transmit, or GIO

SCI receive, or GIO

SCI transmit, or GIO

N2HET1[13]/SCI3TX/N2HET2[20]/ePWM5B

N2HET1[17]/EMIF_nOE/SCI4RX

Programmable,

20 µA

A13

B13

Programmable,

20 µA

N2HET1[19]/EMIF_nDQM[0]/SCI4TX

Programmable,

20 µA

Terminal Configuration and Functions

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3.2.1.13 Inter-Integrated Circuit Interface Module (I2C)

Table 3-13. GWT Inter-Integrated Circuit Interface Module (I2C)

Terminal

Output

Signal

Type

Default Pull

State

Buffer

Pull Type

Description

Drive

337

GWT

Signal Name

Strength

MIBSPI3NCS[3]/I2C1_SCL/N2HET1[29]/nTZ1_1

I/O

Pullup

Programmable,

20 µA

2-mA ZD

I2C serial clock, or GIO

MIBSPI3NCS[2]/I2C1_SDA/N2HET1[27]/nTZ1_2

I/O

Pullup

Programmable, 20uA

2-mA ZD

I2C serial data, or GIO

I2C serial clock, or GIO

I2C serial data, or GIO

MIBSPI5SOMI[3]/DMM_DATA[15]/I2C2_SCL/AD1EXT_ENA

MIBSPI5SIMO[3]/DMM_DATA[11]/I2C2_SDA/AD1EXT_SEL[2]

G16

G17

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3.2.1.14 Multibuffered Serial Peripheral Interface Modules (MibSPI)

Table 3-14. GWT Multibuffered Serial Peripheral Interface Modules (MibSPI)

Terminal

Default Pull

State

Output Buffer

Drive Strength

Signal Type

Pull Type

Description

337

GWT

Signal Name

MIBSPI1CLK

F18

I/O

Pullup

Programmable, 20 µA

Programmable, 20 >µA

Programmable, 20 µA

8 mA

MibSPI1 clock, or GIO

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6

MIBSPI1NCS[1]/MII_COL/N2HET1[17]/eQEP1S

MIBSPI1NCS[2]/MDIO /N2HET1[19]

MIBSPI1NCS[3]/N2HET1[21]/nTZ1_3

MIBSPI1NCS[4]

8 mA

MibSPI1 chip select, or GIO

2-mA ZD

U10

N1(1)

N2HET1[15]/MIBSPI1NCS[4]/N2HET2[22]/ECAP1

MIBSPI1NCS[5]

I/O

Pullup

Programmable, 20 µA

2-mA ZD

MibSPI1 chip select, or GIO

N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]

MIBSPI1NENA/MII_RXD[2]/N2HET1[23]/ECAP4

MIBSPI1SIMO[0]

P1(1)

G19

F19

E18

G18

I/O

Pullup

Programmable, 20 µA

2-mA ZD

8 mA

MibSPI1 enable, or GIO

MibSPI1 slave-in master-out, or GIO

MibSPI1 slave-out master-in, or GIO

MibSPI2 clock, or GIO

N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]

MIBSPI1SOMI[0]

Pulldown

Pullup

8 mA

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6

N2HET2[3]/MIBSPI2CLK

Pullup

8 mA

Pulldown

Pullup

8 mA

N2HET2[7]/MIBSPI2NCS[0]

2-mA ZD

8 mA

MibSPI2 chip select, or GIO

MibSPI2 enable, or GIO

N2HET2[12]/MIBSPI2NENA/MIBSPI2NCS[1]

N2HET2[14]/MIBSPI2SIMO

MibSPI2 slave-in master-out, or GIO

MibSPI2 slave-out master-in, or GIO

MibSPI3 clock, or GIO

N2HET2[13]/MIBSPI2SOMI

8 mA

MIBSPI3CLK/AD1EXT_SEL[1]/eQEP1A

MIBSPI3NCS[0]/AD2EVT/eQEP1I

8 mA

V10

Pullup

2-mA ZD

8 mA

MibSPI3 chip select, or GIO

MibSPI3 enable, or GIO

MIBSPI3NCS[1]/MDCLK/N2HET1[25]

MIBSPI3NCS[2]/I2C1_SDA/N2HET1[27] /nTZ1_2

MIBSPI3NCS[3]/I2C1_SCL/N2HET1[29] /nTZ1_1

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ePWM1SYNCO

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/eQEP1B

MIBSPI3SIMO/AD1EXT_SEL[0]/ECAP3

MIBSPI3SOMI/AD1EXT_ENA/ECAP2

N2HET1[0]/MIBSPI4CLK/ePWM2B

Pullup

Pulldown

Pullup

MibSPI3 slave-in master-out, or GIO

MibSPI3 slave-out master-in, or GIO

MibSPI4 clock, or GIO

Pullup

8 mA

K18

Pulldown

8 mA

N2HET1[3]/MIBSPI4NCS[0]/N2HET2[10]/eQEP2B

2-mA ZD

MibSPI4 chip select, or GIO

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Table 3-14. GWT Multibuffered Serial Peripheral Interface Modules (MibSPI) (continued)

Terminal

Default Pull

State

Output Buffer

Drive Strength

Signal Type

Pull Type

Description

337

GWT

Signal Name

N2HET1[4]/MIBSPI4NCS[1]/ePWM4B

B12

I/O

Pulldown

Pullup

Programmable, 20 µA

2-mA ZD

4 mA

MibSPI4 chip select, or GIO

N2HET1[7]/MIBSPI4NCS[2]/N2HET2[14]/ePWM7B

N2HET1[9]/MIBSPI4NCS[3]/N2HET2[16]/ePWM7A

N2HET1[10]/MIBSPI4NCS[4]/MII_TX_CLK/nTZ1_3

N2HET1[12]/MIBSPI4NCS[5]/MII_CRS/RMII_CRS_DV

N2HET1[1]/MIBSPI4NENA/N2HET2[8]/eQEP2A

N2HET1[2]/MIBSPI4SIMO/ePWM3A

MibSPI4 chip select, or GIO

D19

MibSPI4 chip select, or GIO

8 mA

MibSPI4 enable, or GIO

8 mA

MibSPI4 slave-in master-out, or GIO

MibSPI4 slave-out master-in, or GIO

MibSPI5 clock, or GIO

N2HET1[5]/MIBSPI4SOMI/N2HET2[12]/ePWM3B

MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN

MIBSPI5NCS[0]/DMM_DATA[5]/ePWM4A

8 mA

H19

E19

8 mA

Pullup

2-mA ZD

8 mA

MibSPI5 chip select, or GIO

MIBSPI5NCS[1]/DMM_DATA[6]

Pullup

MibSPI5 chip select, or GIO

MIBSPI5NCS[2]/DMM_DATA[2]

T12

Pullup

MibSPI5 chip select, or GIO

MIBSPI5NCS[3]/DMM_DATA[3]

Pullup

MibSPI5 chip select, or GIO

ETMDATA[24]/EMIF_DATA[8]/N2HET2[24]/MIBSPI5NCS[4]

ETMDATA[25]/EMIF_DATA[9]/N2HET2[25]/MIBSPI5NCS[5]

MIBSPI5NENA/DMM_DATA[7] /MII_RXD[3]/ECAP5

MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1]

MIBSPI5SIMO[1]/DMM_DATA[9]/AD1EXT_SEL[0]

MIBSPI5SIMO[2]/DMM_DATA[10]/AD1EXT_SEL[1]

MIBSPI5SIMO[3]/DMM_DATA[11]/I2C2_SDA/AD1EXT_SEL[2]

MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0]

MIBSPI5SOMI[1]/DMM_DATA[13]/AD1EXT_SEL[3]

MIBSPI5SOMI[2]/DMM_DATA[14]/AD1EXT_SEL[4]

MIBSPI5SOMI[3]/DMM_DATA[15]/I2C2_SCL/AD1EXT_ENA

Pullup

MibSPI5 chip select, or GIO

Pullup

MibSPI5 chip select, or GIO

H18

J19

E16

H17

G17

J18

E17

H16

G16

Pullup

MibSPI5 enable, or GIO

Pullup

MibSPI5 slave-in master-out, or GIO

MibSPI5 slave-out master-in, or GIO

Pullup

8 mA

Pullup

8 mA

Pullup

8 mA

Pullup

8 mA

Pullup

8 mA

Pullup

8 mA

Pullup

8 mA

(1) This is the secondary terminal at which the signal is also available. See Section 3.2.2.2 for more detail on how to select between the available terminals for input functionality.

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3.2.1.15 Ethernet Controller

Table 3-15. GWT Ethernet Controller: MDIO Interface

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

Strength

MDCLK

V5(1)

Output

I/O

8 mA

Serial clock output

MIBSPI3NCS[1]/MDCLK/N2HET1[25]

MDIO

Pulldown

Fixed, 20 µA

Serial data input/output

MIBSPI1NCS[2]/MDIO/N2HET1[19]

G3(1)

(1) This is the secondary terminal at which the signal is also available. See Section 3.2.2.2 for more detail on how to select between the available terminals for input functionality.

Table 3-16. GWT Ethernet Controller: Reduced Media Independent Interface (RMII)

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

Strength

N2HET1[12]/MIBSPI4NCS[5]/MII_CRS/RMII_CRS_DV

N2HET1[28]/MII_RXCLK/RMII_REFCLK

RMII carrier sense and data

valid

Input

Pulldown

Fixed, 20 µA

EMII synchronous reference

clock for receive, transmit and

control interface

K19

8 mA

AD1EVT/MII_RX_ER/RMII_RX_ER/nTZ1_1

N19

Input

Pulldown

Pullup

Fixed, 20 µA

20 µA

RMII receive error

RMII receive data

RMII transmit data

RMII transmit enable

N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]

N2HET1[26]/MII_RXD[1]/RMII_RXD[1]

A14

J18

J19

H19

Input

MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0]

MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1]

MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN

Output

8 mA

Pullup

20 µA

Pullup

20 µA

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Table 3-17. GWT Ethernet Controller: Media Independent Interface (MII)

Terminal

Output

Signal

Type

Default Pull

State

Buffer

Pull Type

Description

Drive

337

GWT

Signal Name

MII_COL

Strength

F3(1)

Input

Pullup

Pulldown

Fixed, 20 µA

Collision detect

Carrier sense and receive valid

Received data valid

Receive error

MIBSPI1NCS[1]/MII_COL/N2HET1[17]/eQEP1S

MII_CRS

N2HET1[12]/MIBSPI4NCS[5]/MII_CRS/RMII_CRS_DV

MII_RX_DV

B4(1)

Input

N2HET1[30]/MII_RX_DV/eQEP2S

MII_RX_ER

B11(1)

Input

AD1EVT/MII_RX_ER/RMII_RX_ER/nTZ1_1

MII_RXCLK

N19(1)

Input

Receive clock

N2HET1[28]/MII_RXCLK/RMII_REFCLK

MII_RXD[0]

K19(1)

Input

Receive data

N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]

MII_RXD[1]

P1(1)

Input

Receive data

N2HET1[26]/MII_RXD[1]/RMII_RXD[1]

MII_RXD[2]

A14(1)

Input

Receive data

MIBSPI1NENA/MII_RXD[2]/N2HET1[23]/ECAP4

MII_RXD[3]

G19(1)

Input

Receive data

MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]/ECAP5

MII_TX_CLK

H18(1)

Input

Transmit clock

Transmit data

N2HET1[10]/MIBSPI4NCS[4]/MII_TX_CLK/nTZ1_3

MII_TXD[0]

D19(1)

Output

8 mA

MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0]

MII_TXD[1]

J18(1)

Transmit data

MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1]

MII_TXD[2]

J19(1)

Transmit data

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6

MII_TXD[3]

R2(1)

Transmit data

N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]

E18(1)

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Table 3-17. GWT Ethernet Controller: Media Independent Interface (MII) (continued)

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

MII_TXEN

Strength

Output

8 mA

Transmit enable

MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN

H19(1)

(1) This is the secondary terminal at which the signal is also available. See Section 3.2.2.2 for more detail on how to select between the available terminals for input functionality.

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3.2.1.16 External Memory Interface (EMIF)

Table 3-18. External Memory Interface (EMIF)(2)

Terminal

Output

Signal

Type

Default Pull

State

Buffer

Pull Type

Description

Drive

337

GWT

Signal Name

Strength

EMIF_ADDR[0]/N2HET2[1]

Output

Pulldown

20 µA

8 mA

EMIF address

EMIF_ADDR[1]/N2HET2[3]

ETMDATA[11]/EMIF_ADDR[2]

ETMDATA[10]/EMIF_ADDR[3]

ETMDATA[9]/EMIF_ADDR[4]

ETMDATA[8]/EMIF_ADDR[5]

EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11]

EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13]

EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15]

EMIF_ADDR[9]/RTP_DATA[10]

EMIF_ADDR[10]/RTP_DATA[9]

EMIF_ADDR[11]/RTP_DATA[8]

EMIF_ADDR[12]/RTP_DATA[6]

EMIF_ADDR[13]/RTP_DATA[5]

EMIF_ADDR[14]/RTP_DATA[4]

EMIF_ADDR[15]/RTP_DATA[3]

EMIF_ADDR[16]/RTP_DATA[2]

EMIF_ADDR[17]/RTP_DATA[1]

EMIF_ADDR[18]/RTP_DATA[0]

EMIF_ADDR[19]/RTP_nENA

EMIF_ADDR[20]/RTP_nSYNC

EMIF_ADDR[21]/RTP_CLK

Pulldown

Pullup

20 µA

C10

C11

C12

C13

D14

C14

D15

C15

C16

C17

E13

J4(1)

Pullup

Pulldown

ETMDATA[12]/EMIF_BA[0]

EMIF bank address or address

line

Output

Pulldown

20 µA

8 mA

N2HET1[23]/EMIF_BA[0]

EMIF bank address or address

line

EMIF_BA[1]/N2HET2[5]

D16

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Table 3-18. External Memory Interface (EMIF)(2) (continued)

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

Strength

EMIF_CKE

Output

I/O

8 mA

EMIF clock enable

EMIF clock

EMIF data

EMIF_CLK/ECLK2

Pulldown

20 µA

ETMDATA[16]/EMIF_DATA[0]

K15

L15

M15

N15

Fixed, 20 µA

20 µA

ETMDATA[17]/EMIF_DATA[1]

I/O

ETMDATA[18]/EMIF_DATA[2]

I/O

ETMDATA[19]/EMIF_DATA[3]

I/O

ETMDATA[20]/EMIF_DATA[4]

I/O

ETMDATA[21]/EMIF_DATA[5]

I/O

ETMDATA[22]/EMIF_DATA[6]

I/O

ETMDATA[23]/EMIF_DATA[7]

I/O

ETMDATA[24]/EMIF_DATA[8]/N2HET2[24]/MIBSPI5NCS[4]

ETMDATA[25]/EMIF_DATA[9]/N2HET2[25]/MIBSPI5NCS[5]

ETMDATA[26]/EMIF_DATA[10]/N2HET2[26]

ETMDATA[27]/EMIF_DATA[11]/N2HET2[27]

ETMDATA[28]/EMIF_DATA[12]/N2HET2[28]/GIOA[0]

ETMDATA[29]/EMIF_DATA[13]/N2HET2[29]/GIOA[1]

ETMDATA[30]/EMIF_DATA[14]/N2HET2[30]/GIOA[3]

ETMDATA[31]/EMIF_DATA[15]/N2HET2[31]/GIOA[4]

EMIF_nCAS/GIOB[3]

I/O

Output

EMIF column address strobe

EMIF chip select, synchronous

EMIF chip select, asynchronous

EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]

EMIF_nCS[2]/GIOB[4]

N17

L17

K17

M17

E10

B13(1)

E11

P2(1)

20 µA

EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]

EMIF_nCS[4]/RTP_DATA[7]/GIOB[5]

ETMDATA[15]/EMIF_nDQM[0]

20 µA

Output

Pulldown

20 µA

8 mA

EMIF byte enable

N2HET1[19]/EMIF_nDQM[0]/SCI4TX

ETMDATA[14]/EMIF_nDQM[1]

N2HET1[20]/EMIF_nDQM[1]/ePWM6B

N2HET1[21]/EMIF_nDQM[2]

Output

Pulldown

20 µA

8 mA

EMIF byte enable

N2HET1[22]/EMIF_nDQM[3]

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Table 3-18. External Memory Interface (EMIF)(2) (continued)

Terminal

Output

Signal

Type

Default Pull

State

Buffer

Pull Type

Description

Drive

337

GWT

Signal Name

Strength

ETMDATA[13]/EMIF_nOE

N2HET1[17]/EMIF_nOE/SCI4RX

EMIF_nRAS/GIOB[6]

E12

A13(1)

Output

Pulldown

20 µA

8 mA

EMIF output enable

Output

Input

Pulldown

Pullup

20 µA

8 mA

EMIF row address strobe

EMIF wait

EMIF_nWAIT/GIOB[7]

Fixed, 20 µA

EMIF_nWE/EMIF_RNW

D17

J1(1)

Output

8 mA

EMIF write enable

EMIF_nWE/EMIF_RNW

Output

8 mA

EMIF read-not-write

N2HET1[18]/EMIF_RNW/ePWM6A

(1) This is the secondary terminal at which the signal is also available. See Section 3.2.2.2 for more detail on how to select between the available terminals for input functionality.

(2) By default, the EMIF interface pins are the primary pins before configurating the IOMM (IO Muxing Module). The output buffers of these pins are forced to tri-state until enabled by setting

PINMMR174[8] = 0 and PINMMR174[9] = 1.”

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3.2.1.17 Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5)

Table 3-19. GWT Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5)

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

Strength

ETMDATA[0]

R12

R13

J15

H15

G15

F15

E15

E14

Output

Pulldown

20 µA

8 mA

ETM data

ETMDATA[1]

ETMDATA[2]

ETMDATA[3]

ETMDATA[4]

ETMDATA[5]

ETMDATA[6]

ETMDATA[7]

ETMDATA[8]/EMIF_ADDR[5]

ETMDATA[9]/EMIF_ADDR[4]

ETMDATA[10]/EMIF_ADDR[3]

ETMDATA[11]/EMIF_ADDR[2]

ETMDATA[12]/EMIF_BA[0]

ETMDATA[13]/EMIF_nOE

ETMDATA[14]/EMIF_nDQM[1]

ETMDATA[15]/EMIF_nDQM[0]

ETMDATA[16]/EMIF_DATA[0]

ETMDATA[17]/EMIF_DATA[1]

ETMDATA[18]/EMIF_DATA[2]

ETMDATA[19]/EMIF_DATA[3]

ETMDATA[20]/EMIF_DATA[4]

ETMDATA[21]/EMIF_DATA[5]

ETMDATA[22]/EMIF_DATA[6]

ETMDATA[23]/EMIF_DATA[7]

E13

E12

E11

E10

K15

L15

M15

N15

ETMDATA[24]/EMIF_DATA[8]/N2HET2[24]/MIBSPI5NCS[4]

ETMDATA[25]/EMIF_DATA[9]/N2HET2[25]/MIBSPI5NCS[5]

ETMDATA[26]/EMIF_DATA[10]/N2HET2[26]

ETMDATA[27]/EMIF_DATA[11]/N2HET2[27]

ETMDATA[28]/EMIF_DATA[12]/N2HET2[28]/GIOA[0]

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Table 3-19. GWT Embedded Trace Macrocell Interface for Cortex-R5F (ETM-R5) (continued)

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

Strength

ETMDATA[29]/EMIF_DATA[13]/N2HET2[29]/GIOA[1]

ETMDATA[30]/EMIF_DATA[14]/N2HET2[30]/GIOA[3]

ETMDATA[31]/EMIF_DATA[15]/N2HET2[31]/GIOA[4]

ETMTRACECLKIN/EXTCLKIN2/GIOA[5]

ETMTRACECLKOUT/GIOA[6]

Output

Input

Pulldown

Pullup

20 µA

8 mA

ETM data

20 µA

ETM data

Fixed, 20 µA

20 µA

ETM trace clock input

ETM trace clock output

ETM trace control

R10

R11

Output

Pulldown

8 mA

ETMTRACECTL/GIOA[7]

20 µA

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3.2.1.18 System Module Interface

Table 3-20. GWT System Module Interface

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

Strength

nERROR

B14

Output

Input

I/O

Pulldown

Pullup

20 µA

8 mA

ESM error

GIOB[6]/nERROR

nPORRST

nRST

ESM error 1

B17

100 µA

Power-on reset, cold reset

System reset, warm reset

4 mA

3.2.1.19 Clock Inputs and Outputs

Table 3-21. GWT Clock Inputs and Outputs

Terminal

Default Pull

Signal Type

Output Buffer

Drive Strength

Pull Type

Description

337

GWT

State

Signal Name

ECLK1

A12

I/O

Pulldown

Pullup

Programmable, 20 µA

2-mA ZD/8 mA External clock output, or GIO

EMIF_CLK/ECLK2

GIOA[5]/EXTCLKIN1/ePWM1A

ETMTRACECLKIN/EXTCLKIN2/GIOA[5]

KELVIN_GND

I/O

Programmable, 20 µA

Input

Fixed, 20 µA

External clock input

Fixed, 20 µA

External clock input # 2

Kelvin ground for oscillator

OSCIN

From external crystal/resonator, or

external clock input

OSCOUT

Output

To external crystal/resonator

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3.2.1.20 Test and Debug Modules Interface

Table 3-22. GWT Test and Debug Modules Interface

TERMINAL

OUTPUT

SIGNAL

TYPE

DEFAULT

PULL STATE

BUFFER

PULL TYPE

DESCRIPTION

DRIVE

337

GWT

SIGNAL NAME

STRENGTH

nTRST

TCK

TDI

D18

B18

A17

C18

Input

Pulldown

Pullup

100 µA

JTAG test hardware reset

JTAG test clock

Fixed, 100 µA

Input

JTAG test data in

TDO

Output

Pulldown

8 mA

JTAG test data out

Test mode enable. This terminal

must be connected to ground directly

or through a pulldown resistor.

TEST

Input

Pulldown

Fixed, 100 µA

TMS

C19

A16

Input

Pullup

Fixed, 100 µA

JTAG test mode select

JTAG return test clock

RTCK

Output

8 mA

3.2.1.21 Flash Supply and Test Pads

Table 3-23. GWT Flash Supply and Test Pads

TERMINAL

OUTPUT

BUFFER

DRIVE

SIGNAL

TYPE

DEFAULT

PULL STATE

PULL TYPE

DESCRIPTION

337

GWT

SIGNAL NAME

STRENGTH

VCCP

FLTP1

3.3-V Power

Input

–

Flash pump supply

Flash test pads. These terminals are

reserved for TI use only. For proper

operation these terminals must

connect only to a test pad or not be

connected at all [no connect (NC)].

FLTP2

Input

–

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3.2.1.22 Supply for Core Logic: 1.2-V Nominal

Table 3-24. GWT Supply for Core Logic: 1.2-V Nominal

Terminal

Output

Buffer

Drive

Signal

Type

Default Pull

State

Pull Type

Description

337

GWT

Signal Name

Strength

VCC

P10

1.2-V

Power

Core supply

F10

J14

K14

M10

H10

K12

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3.2.1.23 Supply for I/O Cells: 3.3-V Nominal

Table 3-25. GWT Supply for I/O Cells: 3.3-V Nominal

Terminal

Output

Signal

Type

Default Pull

State

Buffer

Pull Type

Description

Drive

337

GWT

Signal Name

Strength

VCCIO

F11

F12

F13

F14

G14

H14

L14

M14

N14

P14

P13

P12

3.3-V

Power

–

Operating supply for I/Os

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3.2.1.24 Ground Reference for All Supplies Except VCCAD

Table 3-26. GWT Ground Reference for All Supplies Except VCCAD

TERMINAL

SIGNAL NAME

DEFAULT

PULL

STATE

SIGNAL

TYPE

OUTPUT BUFFER

DRIVE STRENGTH

PULL TYPE

DESCRIPTION

Ground reference

337 GWT

VSS

–

Ground reference

A18

A19

B19

M11

M12

Ground

L10

L11

L12

K10

K11

J10

J11

J12

H11

H12

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3.2.1.25 Other Supplies

Table 3-27. Other Supplies

TERMINAL

OUTPUT

DEFAULT

PULL

STATE

SIGNAL

TYPE

BUFFER

PULL TYPE

DESCRIPTION

DRIVE

337

GWT

SIGNAL NAME

STRENGTH

Supply for PLL: 1.2-V nominal

1.2-V

Power

VCCPLL

P11

–

Core supply for PLL's

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3.2.2 Multiplexing

This microcontroller has several interfaces and uses extensive multiplexing to bring out the functions as required by the target application. The

multiplexing is mostly on the output signals. A few inputs are also multiplexed to allow the same input signal to be driven in from an alternative

terminal. For more information on multiplexing, refer to the IOMM chapter of the device specific technical reference manual.

3.2.2.1 Output Multiplexing

Table 3-28. Output Multiplexing

Address

Offset

337

GWT

BALL

DEFAULT

FUNCTION

Select

Bit

Alternate

Function 1

Select

Bit

Alternate

Function 2

Select

Bit

Alternate

Function 3

Select

Bit

Alternate

Function 4

Select

Bit

Alternate

Function 5

Select

Bit

0x110

0x114

0x118

0x11C

0x120

N19

AD1EVT

0[0]

0[8]

MII_RX_ER

N2HET2[1]

N2HET2[3]

N2HET2[11]

N2HET2[13]

N2HET2[15]

0[2]

0[10]

0[18]

0[26]

1[2]

RMII_RX_ER

0[3]

nTZ1_1

0[5]

EMIF_ADDR[0]

EMIF_ADDR[1]

EMIF_ADDR[6]

EMIF_ADDR[7]

EMIF_ADDR[8]

EMIF_ADDR[9]

EMIF_ADDR[10]

EMIF_ADDR[11]

EMIF_ADDR[12]

EMIF_ADDR[13]

EMIF_ADDR[14]

EMIF_ADDR[15]

EMIF_ADDR[16]

EMIF_ADDR[17]

EMIF_ADDR[18]

EMIF_ADDR[19]

EMIF_ADDR[20]

EMIF_ADDR[21]

0[16]

0[24]

1[0]

RTP_DATA[13]

RTP_DATA[12]

RTP_DATA[11]

RTP_DATA[10]

RTP_DATA[9]

RTP_DATA[8]

RTP_DATA[6]

RTP_DATA[5]

RTP_DATA[4]

RTP_DATA[3]

RTP_DATA[2]

RTP_DATA[1]

RTP_DATA[0]

RTP_nENA

0[25]

1[1]

1[8]

1[9]

1[10]

1[16]

1[24]

2[0]

1[17]

1[25]

2[1]

C10

C11

C12

C13

D14

C14

D15

C15

C16

C17

2[8]

2[9]

2[16]

2[24]

3[0]

2[17]

2[25]

3[1]

3[8]

3[9]

3[16]

3[24]

4[0]

3[17]

3[25]

4[1]

4[8]

RTP_nSYNC

RTP_CLK

4[9]

4[16]

4[17]

0x124

Reserved

0x12C

0x130

0x134

PINMMR8[23:0] are reserved

D16

EMIF_BA[1]

RESERVED

EMIF_nCAS

EMIF_nCS[0]

EMIF_nCS[2]

8[24]

9[0]

8[25]

9[1]

N2HET2[5]

8[26]

9[2]

EMIF_CLK

ECLK2

GIOB[3]

9[8]

9[10]

9[18]

9[26]

N17

L17

9[16]

9[24]

RTP_DATA[15]

9[17]

N2HET2[7]

GIOB[4]

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Table 3-28. Output Multiplexing (continued)

Address

Offset

337

GWT

BALL

DEFAULT

FUNCTION

Select

Bit

Alternate

Function 1

Select

Bit

Alternate

Function 2

Select

Bit

Alternate

Function 3

Select

Bit

Alternate

Function 4

Select

Bit

Alternate

Function 5

Select

Bit

0x138

0x13C

0x140

0x144

0x148

0x14C

0x150

0x154

K17

M17

EMIF_nCS[3]

EMIF_nCSl[4]

EMIF_nRAS

10[0]

10[8]

RTP_DATA[14]

RTP_DATA[7]

10[1]

10[9]

N2HET2[9]

GIOB[5]

GIOB[6]

GIOB[7]

10[2]

10[10]

10[18]

10[26]

10[16]

10[24]

11[0]

EMIF_nWAIT

EMIF_nWE

D17

EMIF_RNW

EMIF_ADDR[5]

EMIF_ADDR[4]

EMIF_ADDR[3]

EMIF_ADDR[2]

EMIF_BA[0]

11[1]

11[9]

ETMDATA[8]

11[8]

ETMDATA[9]

11[16]

11[24]

12[0]

11[17]

11[25]

12[1]

ETMDATA[10]

ETMDATA[11]

ETMDATA[12]

ETMDATA[13]

ETMDATA[14]

ETMDATA[15]

ETMDATA[16]

ETMDATA[17]

ETMDATA[18]

ETMDATA[19]

ETMDATA[20]

ETMDATA[21]

ETMDATA[22]

ETMDATA[23]

ETMDATA[24]

ETMDATA[25]

ETMDATA[26]

ETMDATA[27]

ETMDATA[28]

ETMDATA[29]

ETMDATA[30]

ETMDATA[31]

ETMTRACECLKIN

ETMTRACECLKOUT

ETMTRACECTL

E13

E12

E11

E10

K15

L15

M15

N15

12[8]

12[9]

12[16]

12[24]

13[0]

EMIF_nOE

12[17]

12[25]

13[1]

EMIF_nDQM[1]

EMIF_nDQM[0]

EMIF_DATA[0]

EMIF_DATA[1]

EMIF_DATA[2]

EMIF_DATA[3]

EMIF_DATA[4]

EMIF_DATA[5]

EMIF_DATA[6]

EMIF_DATA[7]

EMIF_DATA[8]

EMIF_DATA[9]

EMIF_DATA[10]

EMIF_DATA[11]

EMIF_DATA[12]

EMIF_DATA[13]

EMIF_DATA[14]

EMIF_DATA[15]

EXTCLKIN2

13[8]

13[9]

13[16]

13[24]

14[0]

13[17]

13[25]

14[1]

14[8]

14[9]

14[16]

14[24]

15[0]

14[17]

14[25]

15[1]

15[8]

15[9]

N2HET2[24]

N2HET2[25]

N2HET2[26]

N2HET2[27]

N2HET2[28]

N2HET2[29]

N2HET2[30]

N2HET2[31]

15[10]

15[18]

15[26]

16[2]

MIBSPI5NCS[4]

MIBSPI5NCS[5]

15[11]

15[19]

15[16]

15[24]

16[0]

15[17]

15[25]

16[1]

16[8]

16[9]

16[10]

16[18]

16[26]

17[2]

GIOA[0]

GIOA[1]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

16[11]

16[19]

16[27]

17[3]

16[16]

16[24]

17[0]

16[17]

16[25]

17[1]

17[8]

17[9]

17[11]

17[19]

17[27]

R10

R11

17[16]

17[24]

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Table 3-28. Output Multiplexing (continued)

Address

Offset

337

GWT

BALL

DEFAULT

FUNCTION

Select

Bit

Alternate

Function 1

Select

Bit

Alternate

Function 2

Select

Bit

Alternate

Function 3

Select

Bit

Alternate

Function 4

Select

Bit

Alternate

Function 5

Select

Bit

0x158

0x15C

0x160

0x164

0x168

0x16C

0x170

0x174

B15

FRAYTX1

FRAYTX2

18[0]

18[8]

GIOA[2]

GIOB[0]

GIOB[1]

GIOB[2]

18[3]

18[11]

18[19]

18[27]

B16

FRAYTXEN1

FRAYTXEN2

GIOA[2]

18[16]

18[24]

19[0]

N2HET2[0]

N2HET2[2]

19[2]

eQEP2I

19[5]

GIOA[3]

19[8]

19[10]

GIOA[5]

19[16]

19[24]

20[0]

EXTCLKIN1

19[19]

ePWM1A

ePWM1B

ePWM2A

19[21]

19[29]

20[5]

GIOA[6]

N2HET2[4]

N2HET2[6]

19[26]

20[2]

GIOA[7]

GIOB[2]

20[8]

DCAN4TX

DCAN4RX

20[11]

20[19]

W10

GIOB[3]

20[16]

20[24]

21[0]

GIOB[6]

nERROR

RESERVED

20[25]

21[1]

21[9]

GIOB[7]

nTZ1_2

ECAP6

21[5]

21[13]

21[21]

MIBSPI1NCS[0]

MIBSPI1NCS[1]

MIBSPI1NCS[2]

MIBSPI1NCS[3]

MIBSPI1NENA

MIBSPI3CLK

MIBSPI3NCS[0]

MIBSPI3NCS[1]

MIBSPI3NCS[2]

MIBSPI3NCS[3]

MIBSPI3NENA

MIBSPI3SIMO

MIBSPI3SOMI

MIBSPI5CLK

MIBSPI5NCS[0]

MIBSPI5NCS[1]

MIBSPI5NCS[2]

MIBSPI5NCS[3]

MIBSPI5NENA

21[8]

MIBSPI1SOMI[1]

MII_TXD[2]

MII_COL

MDIO

21[10]

21[18]

21[26]

21[16]

21[24]

22[0]

N2HET1[17]

N2HET1[19]

N2HET1[21]

N2HET1[23]

21[19]

21[27]

22[3]

eQEP1S

nTZ1_3

ECAP4

eQEP1A

eQEP1I

22[5]

22[13]

22[21]

22[29]

G19

22[8]

MII_RXD[2]

MDCLK

22[10]

23[2]

22[11]

22[16]

22[24]

23[0]

AD1EXT_SEL[1]

AD2EVT

22[17]

22[25]

V10

N2HET1[25]

N2HET1[27]

N2HET1[29]

N2HET1[31]

23[3]

23[11]

23[19]

23[27]

23[8]

I2C1_SDA

I2C1_SCL

23[9]

23[17]

23[25]

24[1]

nTZ1_2

nTZ1_1

eQEP1B

ECAP3

ECAP2

23[13]

23[21]

23[29]

24[5]

23[16]

23[24]

24[0]

MIBSPI3NCS[5]

AD1EXT_SEL[0]

AD1EXT_ENA

DMM_DATA[4]

DMM_DATA[5]

DMM_DATA[6]

DMM_DATA[2]

DMM_DATA[3]

DMM_DATA[7]

24[8]

24[9]

24[13]

H19

E19

24[16]

24[24]

25[0]

24[17]

24[25]

25[1]

MII_TXEN

24[18]

25[26]

RMII_TXEN

24[19]

ePWM4A

24[29]

25[29]

T12

H18

25[8]

25[9]

25[16]

25[24]

25[17]

25[25]

MII_RXD[3]

ECAP5

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Table 3-28. Output Multiplexing (continued)

Address

Offset

337

GWT

BALL

DEFAULT

FUNCTION

Select

Bit

Alternate

Function 1

Select

Bit

Alternate

Function 2

Select

Bit

Alternate

Function 3

Select

Bit

Alternate

Function 4

Select

Bit

Alternate

Function 5

Select

Bit

0x178

0x17C

0x180

0x184

0x188

0x18C

0x190

0x194

J19

E16

H17

G17

J18

E17

H16

G16

K18

MIBSPI5SIMO[0]

MIBSPI5SIMO[1]

MIBSPI5SIMO[2]

MIBSPI5SIMO[3]

MIBSPI5SOMI[0]

MIBSPI5SOMI[1]

MIBSPI5SOMI[2]

MIBSPI5SOMI[3]

N2HET1[0]

26[0]

26[8]

DMM_DATA[8]

DMM_DATA[9]

DMM_DATA[10]

DMM_DATA[11]

DMM_DATA[12]

DMM_DATA[13]

DMM_DATA[14]

DMM_DATA[15]

MIBSPI4CLK

26[1]

26[9]

MII_TXD[1]

26[2]

RMII_TXD[1]

26[3]

AD1EXT_SEL[0]

AD1EXT_SEL[1]

AD1EXT_SEL[2]

26[12]

26[20]

26[28]

26[16]

26[24]

27[0]

26[17]

26[25]

27[1]

I2C2_SDA

MII_TXD[0]

26[26]

27[2]

RMII_TXD[0]

27[3]

27[8]

27[9]

AD1EXT_SEL[3]

AD1EXT_SEL[4]

AD1EXT_ENA

27[12]

27[20]

27[28]

27[16]

27[24]

28[0]

27[17]

27[25]

28[1]

I2C2_SCL

27[26]

ePWM2B

eQEP2A

ePWM3A

eQEP2B

ePWM4B

ePWM3B

ePWM5A

ePWM7B

28[5]

28[13]

28[21]

28[29]

29[5]

N2HET1[1]

28[8]

MIBSPI4NENA

MIBSPI4SIMO

MIBSPI4NCS[0]

MIBSPI4NCS[1]

MIBSPI4SOMI

SCI3RX

28[9]

N2HET2[8]

N2HET2[10]

N2HET2[12]

N2HET2[14]

28[11]

28[27]

29[11]

29[27]

N2HET1[2]

28[16]

28[24]

29[0]

28[17]

28[25]

29[1]

N2HET1[3]

B12

N2HET1[4]

N2HET1[5]

29[8]

29[9]

29[13]

29[21]

29[29]

N2HET1[6]

29[16]

29[24]

30[0]

29[17]

29[25]

30[1]

N2HET1[7]

MIBSPI4NCS[2]

MIBSPI1SIMO[1]

MIBSPI4NCS[3]

MIBSPI4NCS[4]

MIBSPI3NCS[4]

MIBSPI4NCS[5]

SCI3TX

E18

N2HET1[8]

MII_TXD[3]

MII_TX_CLK

MII_CRS

30[2]

30[18]

31[2]

N2HET1[9]

30[8]

30[9]

N2HET2[16]

RESERVED

N2HET2[18]

RMII_CRS_DV

N2HET2[20]

N2HET2[22]

ePWM1SYNCI

30[11]

30[19]

30[27]

31[3]

ePWM7A

nTZ1_3

30[13]

30[21]

30[29]

D19

N2HET1[10]

N2HET1[11]

N2HET1[12]

N2HET1[13]

N2HET1[15]

N2HET1[16]

N2HET1[17]

N2HET1[18]

N2HET1[19]

N2HET1[20]

N2HET1[21]

N2HET1[22]

N2HET1[23]

N2HET1[24]

30[16]

30[24]

31[0]

30[17]

30[25]

31[1]

ePWM1SYNCO

31[8]

31[9]

31[11]

31[19]

31[27]

ePWM5B

ECAP1

31[13]

31[21]

31[29]

31[16]

31[24]

32[0]

MIBSPI1NCS[4]

31[17]

ePWM1SYNCO

A13

EMIF_nOE

EMIF_RNW

32[1]

32[9]

SCI4RX

SCI4TX

32[2]

32[8]

ePWM6A

ePWM6B

32[13]

32[29]

B13

32[16]

32[24]

33[0]

EMIF_nDQM[0]

EMIF_nDQM[1]

EMIF_nDQM[2]

EMIF_nDQM[3]

EMIF_BA[0]

32[17]

32[25]

33[1]

32[18]

33[8]

33[9]

33[16]

33[24]

33[17]

33[25]

MIBSPI1NCS[5]

MII_RXD[0]

33[26]

RMII_RXD[0]

33[27]

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Table 3-28. Output Multiplexing (continued)

Address

Offset

337

GWT

BALL

DEFAULT

FUNCTION

Select

Bit

Alternate

Function 1

Select

Bit

Alternate

Function 2

Select

Bit

Alternate

Function 3

Select

Bit

Alternate

Function 4

Select

Bit

Alternate

Function 5

Select

Bit

0x198

0x19C

0x1A0

0x1A4

A14

K19

B11

N2HET1[26]

N2HET1[28]

N2HET1[30]

N2HET2[1]

N2HET2[2]

N2HET2[12]

N2HET2[13]

N2HET2[14]

N2HET2[19]

N2HET2[20]

MII_RXCLK

MII_TX_CLK

N2HET2[3]

N2HET2[7]

34[0]

34[8]

MII_RXD[1]

MII_RXCLK

MII_RX_DV

34[2]

34[10]

34[18]

RMII_RXD[1]

34[3]

RMII_REFCLK

34[11]

RESERVED

34[12]

34[16]

34[24]

35[0]

eQEP2S

34[21]

35[13]

N2HET1_NDIS

N2HET2_NDIS

34[25]

35[1]

35[8]

MIBSPI2NENA

MIBSPI2SOMI

MIBSPI2SIMO

35[12]

35[20]

35[28]

MIBSPI2NCS[1]

35[16]

35[24]

36[0]

LIN2RX

LIN2TX

36[1]

36[9]

36[8]

36[16]

36[24]

37[0]

RESERVED

36[20]

36[28]

37[4]

MIBSPI2CLK

MIBSPI2NCS[0]

37[8]

37[12]

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3.2.2.1.1 Notes on Output Multiplexing

Table 3-28 lists the output signal multiplexing and control signals for selecting the desired functionality for

each pad.

•

The pads default to the signal defined by the "Default Function" in Table 3-28.

The CTRL x columns in Table 3-28 contain a value of type x[y] which indicates the control register

PINMMRx, bit y. It indicates the multiplexing control register and the bit that must be set in order to

select the corresponding functionality to be output on any particular pad.

–

For example, consider the multiplexing on pin H3 for the 337-GWT package:

337

GWT

BALL

DEFAULT

FUNCTION

CTRL1

OPTION 2

CTRL2

OPTION 3

CTRL3

OPTION 4

CTRL4

OPTION 5

CTRL5

OPTION 6

CTRL6

GIOA[6]

19[24]

N2HET2[4] 19[26]

ePWM1B

19[29]

–

When GIOA[6] is configured as an output pin in the GIO module control register, then the

programmed output level appears on pin H3 by default. The PINMMR19[24] is set by default to

indicate that the GIOA[6] signal is selected to be output.

–

If the application must output the N2HET2[4] signal on pin H3, it must clear PINMMR19[24] and set

PINMMR19[26].

Note that the pin is connected as input to both the GIO and N2HET2 modules. That is, there is no

input multiplexing on this pin.

•

The base address of the IOMM module starts at 0xFFFF_1C00. The Output mux control registers with

the first register PINMMR0 starts at the offset address 0x110 within the IOMM module.

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3.2.2.2 Input Multiplexing

Some signals are connected to more than one terminals, so that the inputs for these signals can come

from either of these terminals. A multiplexor is implemented to let the application choose the terminal that

will be used for providing the input signal from among the available options. The input path selection is

done based on two bits in the PINMMR control registers as listed in Table 3-29.

Table 3-29. Input Multiplexing

Address

Offset

Signal Name

Default Terminal

Terminal 1 Input

Multiplex Control

Alternate Terminal

Terminal 2 Input

Multiplex Control

250h

25Ch

260h

AD2EVT

GIOA[0]

T10

PINMMR80[0]

PINMMR83[24]

PINMMR84[0]

PINMMR84[8]

PINMMR84[16]

PINMMR84[24]

PINMMR85[0]

PINMMR85[8]

PINMMR85[16]

PINMMR85[24]

PINMMR86[0]

PINMMR86[8]

PINMMR86[16]

PINMMR86[24]

PINMMR87[0]

PINMMR87[8]

PINMMR87[16]

PINMMR87[24]

PINMMR88[0]

PINMMR88[8]

PINMMR89[16]

PINMMR89[24]

PINMMR90[0]

PINMMR90[8]

PINMMR90[16]

PINMMR90[24]

PINMMR91[0]

PINMMR91[8]

PINMMR91[16]

PINMMR91[24]

PINMMR92[0]

PINMMR92[8]

PINMMR92[16]

PINMMR92[24]

PINMMR93[0]

PINMMR93[8]

PINMMR93[16]

PINMMR93[24]

V10

PINMMR80[1]

PINMMR83[25]

PINMMR84[1]

PINMMR84[9]

PINMMR84[17]

PINMMR84[25]

PINMMR85[1]

PINMMR85[9]

PINMMR85[17]

PINMMR85[25]

PINMMR86[1]

PINMMR86[9]

PINMMR86[17]

PINMMR86[25]

PINMMR87[1]

PINMMR87[9]

PINMMR87[17]

PINMMR87[25]

PINMMR88[1]

PINMMR88[9]

PINMMR89[17]

PINMMR89[25]

PINMMR90[1]

PINMMR90[9]

PINMMR90[17]

PINMMR90[25]

PINMMR91[1]

PINMMR91[9]

PINMMR91[17]

PINMMR91[25]

PINMMR92[1]

PINMMR92[9]

PINMMR92[17]

PINMMR92[25]

PINMMR93[1]

PINMMR93[9]

PINMMR93[17]

PINMMR93[25]

GIOA[1]

GIOA[2]

B15

GIOA[3]

GIOA[4]

264h

268h

26Ch

GIOA[5]

GIOA[6]

R10

R11

GIOA[7]

GIOB[0]

GIOB[1]

B16

GIOB[2]

GIOB[3]

W10

GIOB[4]

L17

M17

GIOB[5]

GIOB[6]

GIOB[7]

MDIO

270h

274h

278h

MIBSPI1NCS[4]

MIBSPI1NCS[5]

MII_COL

U10

MII_CRS

MII_RX_DV

MII_RX_ER

MII_RXCLK

MII_RXD[0]

MII_RXD[1]

MII_RXD[2]

MII_RXD[3]

MII_TX_CLK

N2HET1[17]

N2HET1[19]

N2HET1[21]

N2HET1[23]

N2HET1[25]

N2HET1[27]

N2HET1[29]

N2HET1[31]

B11

N19

K19

27Ch

280h

284h

A14

G19

H18

D19

A13

B13

G19

J17

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Table 3-29. Input Multiplexing (continued)

Address

Offset

Signal Name

Default Terminal

Terminal 1 Input

Multiplex Control

Alternate Terminal

Terminal 2 Input

Multiplex Control

288h

28Ch

290h

294h

298h

29Ch

N2HET2[0]

N2HET2[1]

N2HET2[2]

N2HET2[3]

N2HET2[4]

N2HET2[5]

N2HET2[6]

N2HET2[7]

N2HET2[8]

N2HET2[9]

N2HET2[10]

N2HET2[11]

N2HET2[12]

N2HET2[13]

N2HET2[14]

N2HET2[15]

N2HET2[16]

N2HET2[18]

N2HET2[20]

N2HET2[22]

nTZ1_1

PINMMR94[0]

PINMMR94[8]

PINMMR94[16]

PINMMR94[24]

PINMMR95[0]

PINMMR95[8]

PINMMR95[16]

PINMMR95[24]

PINMMR96[0]

PINMMR96[8]

PINMMR96[16]

PINMMR96[24]

PINMMR97[0]

PINMMR97[8]

PINMMR97[16]

PINMMR97[24]

PINMMR98[0]

PINMMR98[8]

PINMMR98[16]

PINMMR98[24]

PINMMR99[0]

PINMMR99[8]

PINMMR99[16]

PINMMR94[1]

PINMMR94[9]

PINMMR94[17]

PINMMR94[25]

PINMMR95[1]

PINMMR95[9]

PINMMR95[17]

PINMMR95[25]

PINMMR96[1]

PINMMR96[9]

PINMMR96[17]

PINMMR96[25]

PINMMR97[1]

PINMMR97[9]

PINMMR97[17]

PINMMR97[25]

PINMMR98[1]

PINMMR98[9]

PINMMR98[17]

PINMMR98[25]

PINMMR99[1]

PINMMR99[9]

PINMMR99[17]

D16

N17

D13

D12

D11

K16

L16

M16

N16

K17

N19

nTZ1_2

nTZ1_3

D19

3.2.2.2.1 Notes on Input Multiplexing

•

The Terminal x Input Multiplex Control column in Table 3-29 lists the multiplexing control register and

the bit that must be set in order to select the terminal for providing the input signal to the system. For

example, N2HET2[22] can appears on two different terminals at terminal number T7 and N1. By

default PINMMR98[24] is set and PINMMR98[25] is cleared to select T7 for providing N2HET2[22] to

the system. If the application chooses to use N1 for providing N2HET2[22] then PINMMR98[24] must

be cleared and PINMMR98[25] must be set.

•

Base address of the IOMM module starts at 0xFFFF_1C00. Input mux control registers with the first

3.2.2.2.2 General Rules for Multiplexing Control Registers

•

The PINMMR control registers can only be written in privileged mode. A write in a nonprivileged mode

will generate an error response.

If the application writes all 9’s to any PINMMR control register, then the default functions are selected

for the affected pads.

Each byte in a PINMMR control register is used to select the functionality for a given pad. If the

application sets more than one bit within a byte for any pad, then the default function is selected for

this pad.

•

Several bits in the PINMMR control registers are reserved and are not used to enable any functions. If

the application sets only these bits and clears the other bits, then the default functions are selected for

the affected pads.

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4 Specifications

4.1 Absolute Maximum Ratings⁽¹⁾

Over Operating Free-Air Temperature Range

MIN

–0.3

MAX

1.43

4.6

UNIT

(2)

V_CC

(2)

Supply voltage

Input voltage

V_CCIO, V_CCP

V_CCAD

6.25

4.6

All input pins, with exception of ADC pins

ADC input pins

6.25

I_IK(V_I< 0 or V_I> V_CCIO

All pins, except AD1IN[31:0] and AD2IN[24:0]

)

–20

–10

Input clamp current:

I_IK(V_I< 0 or V_I> V_CCAD

AD1IN[31:0] and AD2IN[24:0]

)

Total

–40

–55

–65

125

150

Operating free-air temperature (T_A)

Operating junction temperature (T_J)

°C

Storage temperature (T_stg

)

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated

grounds.

4.2 ESD Ratings

MIN

MAX UNIT

Human Body Model (HBM), per AEC Q100-002D⁽¹⁾

–2

500

750

Electrostatic discharge (ESD)

performance:

All pins except corner

V_ESD

–500

–750

Charged Device Model (CDM), per AEC

Q100-011

balls

Corner balls

(1) AEC Q100-002D indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001-2011 specification.

4.3 Power-On Hours (POH)

POH is a function of voltage and temperature. Usage at higher voltages and temperatures will result in a

reduction in POH to achieve the same reliability performance. The POH information in Table 4-1 is

provided solely for convenience and does not extend or modify the warranty provided under TI’s standard

terms and conditions for TI Semiconductor Products. To avoid significant device degradation, the device

POH must be limited to those listed in Table 4-1. To convert to equivalent POH for a specific temperature

profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application Report

(SPNA207).

Table 4-1. Power-On Hours Limits

JUNCTION

TEMPERATURE (T_J)

NOMINAL V_CCVOLTAGE (V)

LIFETIME POH⁽¹⁾

105°C

100k

25k

1.2 V

125°C

(1) POH represents device operation under the specified nominal conditions continuously for the duration of the calculated lifetime.

Specifications

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1000000

100000

10000

1000

100

105

110

115

120

125

130

135

140

145

150

155

160

Temperature (èC)

D001

(1) Silicon operating life design goal is 100,000 power-on hours (POH) at 105°C junction temperature (does not include package

interconnect life).

(2) The predicted operating lifetime versus junction temperature is based on reliability modeling using electromigration as the dominant

failure mechanism affecting device wearout for the specific device process and design characteristics.

Figure 4-1. TMS570LC4357-EP Operating Life Derating Chart

4.4 Recommended Operating Conditions⁽¹⁾

MIN

1.14

NOM

1.2

MAX UNIT

V_CC

Digital logic supply voltage (Core)

PLL supply voltage

1.32

3.6

V_CCPLL

V_CCIO

V_CCAD

V_CCP

V_SS

1.2

Digital logic supply voltage (I/O)

MibADC supply voltage

3.3

5.25

3.6

Flash pump supply voltage

3.3

Digital logic supply ground

V_SSAD

V_ADREFHI

V_ADREFLO

T_A

MibADC supply ground

–0.1

V_SSAD

–55

0.1

V_CCAD

125

Analog-to-Digital (A-to-D) high-voltage reference source

A-to-D low-voltage reference source

Operating free-air temperature

Operating junction temperature

°C

T_J

–55

150

(1) All voltages are with respect to V_SS, except V_CCAD, which is with respect to V_SSAD

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4.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains

Table 4-2. Clock Domain Timing Specifications

TEST

CONDITIONS

PARAMETER

MIN

MAX

UNIT

f_OSC

OSC - oscillator clock frequency using an external crystal

GCLK - R5F CPU clock frequency

300

150

110

150

110

f_VCLK

f_HCLK

110

MHz

f_GCLK1

f_GCLK2

f_HCLK

GCLK - R5F CPU clock frequency

HCLK - System clock frequency

f_VCLK

VCLK - Primary peripheral clock frequency

VCLK2 - Secondary peripheral clock frequency

VCLK3 - Secondary peripheral clock frequency

VCLKA1 - Primary asynchronous peripheral clock frequency

VCLKA2 - Secondary asynchronous peripheral clock frequency

VCLKA4 - Secondary asynchronous peripheral clock frequency

RTICLK1 - clock frequency

f_VCLK2

f_VCLK3

f_VCLKA1

f_VCLKA2

f_VCLKA4

f_RTICLK1

f_PROG/ERASESystem clock frequency - flash programming/erase

f_ECLK1

f_ECLK2

External Clock 1

External Clock 2

f_ETMCLKOUTETM trace clock output

f_ETMCLKIN

f_EXTCLKIN1

f_EXTCLKIN2

ETM trace clock input

External input clock 1

External input clock 2

110

Table 4-2 lists the maximum frequency of the CPU (GLKx), the level-2 memory (HCLK) and the peripheral

clocks (VCLKx). It is not always possible to run each clock at its maximum frequency as GCLK must be an

integral multiple of HCLK and HCLK must be an integral multiple of VCLKx. Depending on the system, the

optimum performance may be obtained by maximizing either the CPU frequency, the level-two RAM

interface, the level-two flash interface, or the peripherals.

4.6 Wait States Required - L2 Memories

Wait states are cycles the CPU must wait in order to retrieve data from the memories which have access

times longer than a CPU clock. Memory wrapper, SCR interconnect and the CPU itself may introduce

additional cycles of latency due to logic pipelining and synchronization. Therefore, the total latency cycles

as seen by the CPU can be more than the number of wait states to cover the memory access time.

Figure 4-2 shows only the number of programmable wait states needed for L2 flash memory at different

frequencies. The number of wait states is correlated to HCLK frequency. The clock ratio between CPU

clock (GCLKx) and HCLK can vary. Therefore, the total number of wait states in terms of GCLKx can be

obtained by taking the programmed wait states multiplied by the clock ratio.

There is no user programmable wait state for L2 SRAM access. L2 SRAM is clocked by HCLK and is

limited to maximum 150 MHz.

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RAM

Data Waitstates

150MHz

HCLK = 0MHz

Flash (Main Memory)

RWAIT Setting

HCLK = 0MHz

45MHz

90MHz

75MHz

135MHz

150MHz

EEPROM Flash (BUS2)

EWAIT Setting

HCLK = 0MHz

45MHz

60MHz

90MHz

105MHz

120MHz

135MHz

Figure 4-2. Wait States Scheme

L2 flash is clocked by HCLK and is limited to maximum 150 MHz. The L2 flash can support zero data wait

state up to 45 MHz.

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4.7 Power Consumption Summary

Over Recommended Operating Conditions

PARAMETER

TEST CONDITIONS

f_GCLK= 300 MHz,

MIN TYP⁽¹⁾

MAX UNIT

f_HCLK= 150 MHz,

f_VCLK= 75 MHz,

f_VCLK2= 75 MHz,

f_VCLK3= 150 MHz

V_CCdigital supply and PLL current

(operating mode)

(2)

510

990

I_CC

LBIST clock rate = 75 MHz

V_CCdigital supply and PLL current

(LBIST mode, or PBIST mode)

880 1375⁽³⁾⁽⁴⁾mA

PBIST ROM clock frequency = 75 MHz

No DC load, V_CCmax

I_CCIO

V_CCIOdigital supply current (operating mode)

15 mA

Single ADC operational, V_CCADmax

Single ADC power down, V_CCADmax

Both ADCs operational, V_CCADmax

Single ADC operational, AD_REFHImax

Both ADCs operational, AD_REFHImax

I_CCADV_CCADsupply current (operating mode)

µA

30 mA

I_CCREF

AD_REFHIsupply current (operating mode)

10 mA

Read operation of two banks in parallel,

V_CCPmax

70 mA

I_CCP

V_CCPpump supply current

Read from two banks and program or

erase another bank, V_CCPmax

93 mA

(1) The typical value is the average current for the nominal process corner and junction temperature of 25°C.

(2) The maximum I_CC,value can be derated

•

linearly with voltage

by 1.8 mA/MHz for lower GCLK frequency when f_GCLK= 2 * f_HCLK= 4 * f_VCLK

for lower junction temperature by the equation below where T_JKis the junction temperature in Kelvin and the result is in milliamperes.

405 - 0.2 e^{0.018 T}

(3) The maximum I_CC,value can be derated

•

linearly with voltage

by 3.2 mA/MHz for lower GCLK frequency

for lower junction temperature by the equation below where T_JKis the junction temperature in Kelvin and the result is in milliamperes.

405 - 0.2 e^{0.018 T}

(4) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the

device and the voltage regulator.

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4.8 Input/Output Electrical Characteristics Over Recommended Operating Conditions⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

180

100

–0.3

TYP

MAX UNIT

All inputs (except

FRAYRX1,

FRAYRX2)

V_hys

Input hysteresis

FRAYRX1, FRAYRX2

All inputs⁽²⁾(except

FRAYRX1,

0.8

0.4 * V_CCIO

V_CCIO+ 0.3

V_IL

Low-level input voltage

FRAYRX2)

FRAYRX1, FRAYRX2

All inputs⁽²⁾(except

FRAYRX1,

V_IH

High-level input voltage

Low-level output voltage

FRAYRX2)

FRAYRX1, FRAYRX2

0.6 * V_CCIO

I_OL= I_OLmax

0.2 * V_CCIO

0.2

V_OL

I_OL= 50 µA, standard

output mode

I_OH= I_OHmax

0.8 * V_CCIO

V_CCIO– 0.3

V_OH

High-level output voltage

I_OH= 50 µA, standard

output mode

V_I< V_SSIO– 0.3 or V_I

> V_CCIO+ 0.3

I_IC

Input clamp current (I/O pins)

–3.5

3.5

I_IHPulldown 20 µA

I_IHPulldown 100 µA

I_ILPullup 20 µA

I_ILPullup 100 µA

All other pins

V_I= V_CCIO

V_I= V_SS

195

–5

I_I

Input current (I/O pins)

-40

µA

V_I= V_SS

–195

–1

–40

No pullup or pulldown

V_OLmax

Pins with output

buffers of 8 mA drive

strength

Pins with output

buffers of 4 mA drive

strength

I_OL

Low-level output current

Pins with output

buffers of 2 mA drive

strength

Pins with output

buffers of 8 mA drive

strength

V_OLmin

–8

–4

–2

Pins with output

buffers of 4 mA drive

strength

I_OH

High-level output current

Pins with output

buffers of 2 mA drive

strength

C_I

Input capacitance

Output capacitance

C_O

(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.

(2) This does not apply to the nPORRST pin.

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4.9 Thermal Resistance Characteristics for the BGA Package (GWT)

(1)

Over operating free-air temperature range (unless otherwise noted)

°C / W

14.3

5.49

5.02

0.29

6.41

RΘ_JA

RΘ_JB

RΘ_JC

Ψ_JT

Junction-to-free air thermal resistance, still air (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane)

Junction-to-board thermal resistance (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane)

Junction-to-case thermal resistance (2s0p PCB)

Junction-to-package top, still air (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane)

Junction-to-board, still air (includes 5×5 thermal via cluster in 2s2p PCB connected to 1st ground plane)

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report SPRA953

4.10 Timing and Switching Characteristics

4.10.1 Input Timings

t_pw

V_CCIO

Input

V_IH

V_IL

Figure 4-3. TTL-Level Inputs

Table 4-3. Timing Requirements for Inputs⁽¹⁾

MIN

t_c(VCLK)+ 10⁽²⁾

MAX

UNIT

t_pw

Input minimum pulse width

t_{in_slew}

Time for input signal to go from V_ILto V_IHor from V_IHto V_IL

(1) t_c(VCLK)= peripheral VBUS clock cycle time = 1 / f_(VCLK)

(2) The timing shown above is only valid for pin used in general-purpose input mode.

t_pw

V_CCIO

Input

0.6*V_CCIO

0.4*V_CCIO

Figure 4-4. FlexRay Inputs

Table 4-4. Timing Requirements for FlexRay Inputs⁽¹⁾

MIN

t_c(VCLKA2)

2.5

MAX

UNIT

t_pw

Input minimum pulse width to meet the FlexRay sampling requirement

(1) t_c(VCLKA2)= sample clock cycle time for FlexRay = 1 / f_(VCLKA2)

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4.10.2 Output Timings

Table 4-5. Switching Characteristics for Output Timings versus Load Capacitance (CL)

PARAMETER

MIN

MAX

2.5

UNIT

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL= 50 pF

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

7.2

12.5

2.5

8 mA low EMI pins

4 mA low EMI pins

2 mA-z low EMI pins

7.2

12.5

5.6

10.4

16.8

23.2

5.6

10.4

16.8

23.2

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

2.5

7.2

12.5

2.5

8 mA mode

7.2

12.5

Selectable 8mA / 2mA-z pins

2 mA-z mode

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t_r

V_CCIO

Output

V_OH

V_OL

Figure 4-5. CMOS-Level Outputs

Table 4-6. Timing Requirements for Outputs⁽¹⁾

MIN

MAX

UNIT

Delay between low to high, or high to low transition of general-purpose output signals

that can be configured by an application in parallel, for example, all signals in a

GIOA port, or all N2HET1 signals, and so forth.

t_{d(parallel_out)}

(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check

for output buffer drive strength information on each signal.

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5 System Information and Electrical Specifications

5.1 Device Power Domains

The device core logic is split up into multiple virtual power domains to optimize the power for a given

application use case.

This device has six logic power domains: PD1, PD2, PD3, PD4, PD5, and PD6. PD1 is a domain which

cannot turn off of its clocks at once through the Power-Management Module (PMM). However, individual

clock domain operating in PD1 can be individually enabled or disabled through the SYS.CDDIS register.

Each of the other power domains can be turned ON, IDLE or OFF as per the application requirement

through the PMM module.

In this device, a power domain can operate in one of the three possible power states: ON, IDLE and OFF.

ON state is the normal operating state where clocks are actively running in the power domain. When

clocks are turned off, the dynamic current is removed from the power domain. In this device, both the

IDLE and OFF states have the same power characteristic. When put into either the IDLE or the OFF state,

only clocks are turned off from the power domain. Leakage current from the power domain still remains.

Note that putting a power domain in the OFF state will not remove any leakage current in this device. In

changing the power domain states, the user must poll the system status register to check the completion

of the transition. From a programmer model perspective, all three power states are available from the

PMM module.

The actual management of the power domains and the hand-shaking mechanism is managed by the

PMM. Refer to the Power Management Module (PMM) chapter of the device technical reference manual

for more details.

System Information and Electrical Specifications

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5.2 Voltage Monitor Characteristics

A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the

requirement for a specific sequence when powering up the core and I/O voltage supplies.

5.2.1 Important Considerations

•

The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the

device is held in reset when the voltage supplies are out of range.

•

The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other

supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a

source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and

VCCP supplies.

5.2.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO

signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when

the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and

PGMCU being low isolates the core logic as well as the I/O controls during power up or power down of the

supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When

the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output

pins high impedance, and asserts a power-on reset. The I/O supply must be above the threshold for

monitoring the core supply. The voltage monitor is disabled when the device enters a low power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 5.3.3.1 for the timing

information on this glitch filter.

Table 5-1. Voltage Monitoring Specifications

PARAMETER

MIN

0.75

1.40

1.85

TYP

0.9

1.7

2.4

MAX UNIT

VCC low - VCC level below this threshold is detected as too low.

VCC high - VCC level above this threshold is detected as too high.

VCCIO low - VCCIO level below this threshold is detected as too low.

1.13

Voltage

V_MONmonitoring

thresholds

2.1

2.99

5.2.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.

Table 5-2 lists the characteristics of the supply filtering. Glitches in the supply larger than the maximum

specification cannot be filtered.

Table 5-2. VMON Supply Glitch Filtering Capability

PARAMETER

MIN

250

MAX

1000

UNIT

Width of glitch on VCC that can be filtered

Width of glitch on VCCIO that can be filtered

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5.3 Power Sequencing and Power-On Reset

5.3.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-

up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (for more details,

see Table 5-3), core voltage rising above the minimum core supply threshold and the release of power-on

reset. The high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. The

oscillator start-up time is dependent on the type of oscillator and is provided by the oscillator vendor. The

different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

Table 5-3. Power-Up Phases

Oscillator start-up and validity check

eFuse autoload

1024 oscillator cycles

3650 oscillator cycles

250 oscillator cycles

1460 oscillator cycles

6384 oscillator cycles

Flash pump power-up

Flash bank power-up

Total

The CPU reset is released at the end of the above sequence and fetches the first instruction from address

0x00000000.

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5.3.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

5.3.3 Power-On Reset: nPORRST

This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core

supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an

internal pulldown.

5.3.3.1 nPORRST Electrical and Timing Requirements

Table 5-4. Electrical Requirements for nPORRST

NO.

MIN

MAX

UNIT

V_CCPORL

V_CCPORH

V_CCIOPORL

V_CCIOPORH

V_CClow supply level when nPORRST must be active during power up

0.5

V_CChigh supply level when nPORRST must remain active during

power up and become active during power down

1.14

V_CCIO/ V_CCPlow supply level when nPORRST must be active during

power up

1.1

V_CCIO/ V_CCPhigh supply level when nPORRST must remain active

during power up and become active during power down

3.0

Low-level input voltage of nPORRST V_CCIO> 2.5 V

Low-level input voltage of nPORRST V_CCIO< 2.5 V

0.2 * V_CCIO

0.5

V_IL(PORRST)

Setup time, nPORRST active before V_CCIOand V_CCP> V_CCIOPORL

during power up

t_su(PORRST)

t_h(PORRST)

t_su(PORRST)

µs

Hold time, nPORRST active after V_CC> V_CCPORH

Setup time, nPORRST active before V_CC< V_CCPORHduring power

down

t_h(PORRST)

Hold time, nPORRST active after V_CCIOand V_CCP> V_CCIOPORH

Hold time, nPORRST active after V_CC< V_CCPORL

Filter time nPORRST terminal; pulses less than MIN will be filtered out,

pulses greater than MAX will generate a reset. Pulses greater than

MIN but less than MAX may or may not generate a reset.

t_f(nPORRST)

475

2000

3.3 V

V_CCIOPORH

CCIOPORH

/ V

CCP

CCIO

1.2 V

CCPORH

CCIOPORL

CCPORL

(1.2 V)

/ V

(3.3 V)

CCP

CCIO

IL(PORRST)

nPORRST

A. Figure 5-1 shows that there is no timing dependency between the ramp of the V_CCIOand the V_CCsupply voltages.

Figure 5-1. nPORRST Timing Diagram^(A)

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5.4 Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset

condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the

output buffer is implemented as an open drain (drives low only). To ensure an external reset is not

arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup

5.4.1 Causes of Warm Reset

Table 5-5. Causes of Warm Reset

DEVICE EVENT

SYSTEM STATUS FLAG

Exception Status Register, bit 15

Global Status Register, bit 0

Power-Up Reset

Oscillator fail

PLL slip

Global Status Register, bits 8 and 9

Exception Status Register, bit 13

Exception Status Register, bit 11

Exception Status Register, bit 5

Exception Status Register, bit 4

Exception Status Register, bit 3

Watchdog exception

Debugger reset

CPU Reset (driven by the CPU STC)

Software Reset

External Reset

5.4.2 nRST Timing Requirements

Table 5-6. nRST Timing Requirements⁽¹⁾

MIN

5032t_c(OSC)

32t_c(VCLK)

MAX

UNIT

Valid time, nRST active after nPORRST inactive

t_v(RST)

t_f(nRST)

Valid time, nRST active (all other System reset conditions)

Filter time nRST terminal; pulses less than MIN will be filtered

out, pulses greater than MAX will generate a reset

475

2000

(1) Specified values do not include rise/fall times. For rise and fall timings, see Table 4-5.

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5.5 ARM Cortex-R5F CPU Information

5.5.1 Summary of ARM Cortex-R5F CPU Features

The features of the ARM Cortex-R5F CPU include:

•

An integer unit with integral Embedded ICE-RT logic.

High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)

for Level two (L2) master and slave interfaces.

•

Floating-Point Coprocessor

Dynamic branch prediction with a global history buffer, and a 4-entry return stack

Low interrupt latency.

Nonmaskable interrupt.

Harvard Level one (L1) memory system with:

–

32KB of instruction cache and 32KB of data cache implemented. Both Instruction and data cache

have ECC support.

–

ARMv7-R architecture Memory Protection Unit (MPU) with 16 regions

•

Dual core logic for fault detection in safety-critical applications.

L2 memory interface:

–

Single 64-bit master AXI interface

64-bit slave AXI interface to cache memories

32-bit AXI_Peri ports to support low latency peripheral ports

•

Debug interface to a CoreSight Debug Access Port (DAP).

Performance Monitoring Unit (PMU).

Vectored Interrupt Controller (VIC) port.

AXI accelerator coherency port (ACP) supporting IO coherency with write-through cacheable regions

Ability to generate ECC on L2 data buses and parity of all control channels

Both CPU cores in lock-step

Eight hardware breakpoints

Eight watchpoints

5.5.2 Dual Core Implementation

The device has two Cortex-R5F cores, where the output signals of both CPUs are compared in the CCM-

R5F unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two

clock cycles as shown in Figure 5-2.

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PDx

PDy

cpu1clk

Outputs from CPU2 to

Outputs from CPU1 to

the system

CCM-R5F

2 cycle delay

CPU Bus Compare

PD Inactivity

Monitor

Compare errors

ESM

Checker CPU

Inactivity Monitor

VIM Bus Compare

Safe values (values

that will force the

ꢀZꢁꢀlꢁŒ /tÜ[• }µš‰µš•

to inactive states)

VIM1

VIM2

CPU2

(Checker

CPU)

CPU1

(Main CPU)

2 cycle delay

cpu2clk

Inputs to CPU1

Figure 5-2. Dual Core Implementation

5.5.3 Duplicate Clock Tree After GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the second CPU

running at the same frequency and in phase to the clock of CPU1. See Figure 5-2.

5.5.4 ARM Cortex-R5F CPU Compare Module (CCM) for Safety

CCM-R5F has two major functions. One is to compare the outputs of two Cortex-R5F processor cores and

the VIM modules. The second function is inactivity monitoring, to detect any faulted transaction initiated by

the checker core.

5.5.4.1 Signal Compare Operating Modes

The CCM-R5F module run in one of four operating modes - active compare lockstep, self-test, error

forcing, and self-test error forcing mode. To select an operating mode, a dedicated key must be written to

the key register. CPU compare block and VIM compare block have separate key registers to select their

operating modes. Status registers are also separate for these blocks.

5.5.4.1.1 Active Compare Lockstep Mode

In this mode the output signals of both CPUs and both VIMs are compared, and a difference in the outputs

is indicated by the compare_error terminal. For more details about CPU and VIM lockstep comparison,

refer to the device technical reference manual.

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CCM-R5F also produces a signal to ESM GP1.92 to indicate its current status whether it is out of lockstep

or is in self-test mode. This ensures that any lock step fault is reported to the CPU.

5.5.4.1.2 Self-Test Mode

In self-test mode the CCM-R5F is checked for faults, by applying internally generated, series of test

patterns to look for any hardware faults inside the module. During self-test the compare error signal is

deactivated. If a fault on the CCM-R5F module is detected, an error is shown on the selftest_error pin.

5.5.4.1.3 Error Forcing Mode

In error forcing mode a test pattern is applied to the CPU and VIM related inputs of the compare logic to

force an error at the compare error signal of the compare unit. Error forcing mode is done separately for

VIM signal compare block and CPU signal compare block. For each block, this mode is enabled by writing

the key in corresponding block’s key register.

5.5.4.1.4 Self-Test Error Forcing Mode

In self-test error forcing mode an error is forced at the self-test error signal. The compare block is still

running in lockstep mode and the key is switched to lockstep after one clock cycle.

Table 5-7. CPU Compare Self-Test Cycles

MODE

NUMBER OF GCLK CYCLES

Self-Test Mode

4947

Self-Test Error Forcing Mode

Error Forcing Mode

Table 5-8. VIM Compare Self-Test Cycles

MODE

Self-Test Mode

NUMBER OF VCLK CYCLES

151

Self-Test Error Forcing Mode

Error Forcing Mode

5.5.4.2 Bus Inactivity Monitor

CCM-R5F also monitors the inputs to the interconnect coming from the checker Cortex-R5F core. The

input signals to the interconnect are compared against their default clamped values. The checker core

must not generate any bus transaction to the interconnect system as all bus transactions are carried out

through the main CPU core. If any signal value is different from its clamped value, an error signal is

generated. The error response in case of a detected transaction is sent to ESM.

In addition to bus monitoring the checker CPU core, the CCM-R5F will also monitor several other critical

signals from other masters residing in other power domains. This is to ensure an inadvertent bus

transaction from an unused power domain can be detected. To enable detection of unwanted transaction

from an unused master, the power domain in which the master to be monitored will need to be configured

in OFF power state through the PMM module.

5.5.4.3 CPU Registers Initialization

To avoid an erroneous CCM-R5F compare error, the application software must ensure that the CPU

registers of both CPUs are initialized with the same values before the registers are used, including

function calls where the register values are pushed onto the stack.

Example routine for CPU register initialization:

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.text

.state32

.global __clearRegisters_

.asmfunc

__clearRegisters_:

mov

msr

mov

r0, lr

r1, #0x0000

r2, #0x0000

r3, #0x0000

r4, #0x0000

r5, #0x0000

r6, #0x0000

r7, #0x0000

r8, #0x0000

r9, #0x0000

r10, #0x0000

r11, #0x0000

r12, #0x0000

r1, #0x11

cpsr, r1

; FIQ Mode = 10001

spsr, r1

lr, r0

r8, #0x0000

; Registers R8 to R12 are also

banked in FIQ mode

r9, #0x0000

mov

msr

mov

msr

mov

msr

mov

msr

mov

msr

r10, #0x0000

r11, #0x0000

r12, #0x0000

r1, #0x13

cpsr, r1

spsr, r1

lr, r0

r1, #0x17

cpsr, r13

spsr, r13

lr, r0

r1, #0x12

cpsr, r13

spsr, r13

lr, r0

r1, #0x1B

cpsr, r13

spsr, r13

lr, r0

; SVC Mode = 10011

; ABT Mode = 10111

; IRQ Mode = 10010

; UDEF Mode = 11011

; System Mode = 11011111

r1, #0xDF

cpsr, r13

spsr, r13

; Floating Point Co-Processor Initialization. FPU needs to be enabled first.

mrc

orr

mcr

mov

p15,

r2,

p15,

r2,

#0x00,

r2,

#0x00,

#0x40000000

r2,

#0xF00000

r2,

c1, c0, #0x02

fmxr fpexc,

fmdrr d0, r1,

fmdrr d1, r1,

fmdrr d2, r1,

fmdrr d3, r1,

fmdrr d4, r1,

fmdrr d5, r1,

fmdrr d6, r1,

fmdrr d7, r1,

fmdrr d8, r1,

fmdrr d9, r1,

fmdrr d10, r1,

fmdrr d11, r1,

fmdrr d12, r1,

fmdrr d13, r1,

fmdrr d14, r1,

fmdrr d15, r1,

$+4

.endasmfunc

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5.5.5 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R5F CPU Cores using the

Deterministic Logic BIST Controller as the test engine.

The main features of the self-test controller are:

•

Ability to divide the complete test run into independent test intervals

Capable of running the complete test as well as running few intervals at a time

Ability to continue from the last executed interval (test set) as well as ability to restart from the

beginning (First test set)

•

Complete isolation of the self-tested CPU core from rest of the system during the self-test run

Ability to capture the Failure interval number

Time-out counter for the CPU self-test run as a fail-safe feature

5.5.5.1 Application Sequence for CPU Self-Test

1. Configure clock domain frequencies.

2. Select number of test intervals to be run.

3. Configure the time-out period for the self-test run.

4. Enable self-test.

5. Wait for CPU reset.

6. In the reset handler, read CPU self-test status to identify any failures.

7. Retrieve CPU state if required.

For more information see the device technical reference manual.

5.5.5.2 CPU Self-Test Clock Configuration

The maximum clock rate for the self-test is 110 MHz. The STCCLK is divided down from the CPU clock.

This divider is configured by the STCCLKDIV register at address 0xFFFFE644.

For more information see the device-specific Technical Reference Manual.

5.5.5.3 CPU Self-Test Coverage

The self-test, if enabled, is automatically applied to the entire processor group. Self-test will only start

when nCLKSTOPPEDm is asserted which indicates the CPU cores and the ACP interface are in

quiescent state. While the processor group is in self-test, other masters can still function normally

including accesses to the system memory such as the L2 SRAM. Because uSCU is part of the processor

group under self-test, the cache coherency checking will be bypassed.

When the self-test is completed, reset is asserted to all logic subjected to self-test. After self-test is

complete, software must invalidate the cache accordingly.

The default value of the CPU LBIST clock prescaler is’ divide-by-1’. A prescalar in the STC module can be

used to configure the CPU LBIST frequency with respect to the CPU GCLK frequency.

Table 5-9 lists the CPU test coverage achieved for each self-test interval. It also lists the cumulative test

cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.

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Table 5-9. CPU Self-Test Coverage

INTERVALS

TEST COVERAGE, %

TEST CYCLES

56.85

64.19

68.76

71.99

1629

3258

4887

6516

8145

76.61

78.08

79.2

9774

11403

13032

14661

16290

17919

19548

21177

22806

24435

26064

27693

29322

30951

32580

34209

35838

37467

39096

40725

42354

43983

45612

47241

48870

50499

52128

53757

55386

57015

58644

60273

61902

63531

65160

80.18

81.03

81.9

82.58

83.24

83.73

84.15

84.52

84.9

85.26

85.68

86.05

86.4

86.68

86.94

87.21

87.48

87.74

87.98

88.18

88.38

88.56

88.75

88.93

89.1

89.23

89.41

89.55

89.7

89.83

89.96

90.1

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5.5.6 N2HET STC / LBIST Self-Test Coverage

Logic BIST self-test capability for N2HETs is available in this device. The STC2 can be configured to

perform self-test for both N2HETs at the same time or one at the time. The default value of the N2HET

LBIST clock prescaler is divide-by-1. However, the maximum clock rate for the N2HET STC / LBIST is

VCLK/2. N2HET STC test should not be executed concurrently with CPU STC test.

Table 5-10. N2HET Self-Test Coverage

INTERVALS

TEST COVERAGE, %

TEST CYCLES

70.01

77.89

81.73

84.11

86.05

87.78

88.96

89.95

90.63

1365

2730

4095

5460

6825

8190

9555

10920

12285

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5.6 Clocks

5.6.1 Clock Sources

Table 5-11 lists the available clock sources on the device. Each clock source can be enabled or disabled

using the CSDISx registers in the system module. The clock source number in the table corresponds to

the control bit in the CSDISx register for that clock source.

Table 5-11 also lists the default state of each clock source.

Table 5-11. Available Clock Sources

CLOCK

SOURCE NO.

NAME

DESCRIPTION

DEFAULT STATE

OSCIN

PLL1

Main Oscillator

Output From PLL1

Enabled

Disabled

Enabled

Disabled

Reserved

EXTCLKIN1

CLK80K

CLK10M

PLL2

Reserved

External Clock Input 1

Low-Frequency Output of Internal Reference Oscillator

High-Frequency Output of Internal Reference Oscillator

Output From PLL2

EXTCLKIN2

External Clock Input 2

5.6.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors

across the external OSCIN and OSCOUT pins as shown in Figure 5-3. The oscillator is a single-stage

inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test

measurement and low power modes.

NOTE

TI strongly encourages each customer to submit samples of the device to the

resonator/crystal vendors for validation. The vendors are equipped to determine which load

capacitors will best tune their resonator/crystal to the microcontroller device for optimum

start-up and operation over temperature and voltage extremes.

An external oscillator source can be used by connecting a 3.3-V clock signal to the OSCIN terminal and

leaving the OSCOUT terminal unconnected (open) as shown in Figure 5-3.

(see Note B)

Kelvin_GND

(see Note B)

OSCIN

OSCOUT

OSCIN Kelvin_GND OSCOUT

External

Clock Signal

(toggling 0 V to 3.3 V)

VSS

(see Note A)

Crystal

(a)

(b)

Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor.

Note B: Kelvin_GND should not be connected to any other GND when used with a crystal; however, when used with an

external clock source, Kelvin_GND may be tied to VSS.

Figure 5-3. Recommended Crystal/Clock Connection

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5.6.1.1.1 Timing Requirements for Main Oscillator

Table 5-12. Timing Requirements for Main Oscillator

MIN

NOM

MAX UNIT

t_c(OSC)

Cycle time, OSCIN (when using a sine-wave input)

200

t_{c(OSC_SQR)}

t_w(OSCIL)

t_w(OSCIH)

Cycle time, OSCIN, (when input to the OSCIN is a square wave)

Pulse duration, OSCIN low (when input to the OSCIN is a square wave)

Pulse duration, OSCIN high (when input to the OSCIN is a square wave)

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5.6.1.2 Low-Power Oscillator

The Low-Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single

macro.

5.6.1.2.1 Features

The main features of the LPO are:

•

Supplies a clock at extremely low power to reduce power consumption. This is connected as clock

source 4 of the Global Clock Module (GCM).

Supplies a high-frequency clock for nontiming-critical systems. This is connected as clock source 5 of

the GCM.

Provides a comparison clock for the crystal oscillator failure detection circuit.

BIAS_EN

LFEN

LFLPO

LF_TRIM

Low-Power

Oscillator

HFEN

HFLPO

HF_TRIM

HFLPO_VALID

nPORRST

Figure 5-4. LPO Block Diagram

Figure 5-4 shows a block diagram of the internal reference oscillator. This is a low-power oscillator (LPO)

and provides two clock sources: one nominally 80 kHz and one nominally 10 MHz.

5.6.1.2.2 LPO Electrical and Timing Specifications

Table 5-13. LPO Specifications

PARAMETER

MIN

TYP

MAX

UNIT

Oscillator fail frequency - lower threshold, using untrimmed

LPO output

1.375

2.4

4.875

MHz

Clock detection

Oscillator fail frequency - higher threshold, using untrimmed

LPO output

38.4

MHz

Untrimmed frequency

Trimmed frequency

5.5

8.0

19.5

11.0

MHz

9.6

LPO - HF oscillator

Start-up time from STANDBY (LPO BIAS_EN high for at least

900 µs)

µs

Cold start-up time

900

180

µs

Untrimmed frequency

kHz

Start-up time from STANDBY (LPO BIAS_EN high for at least

900 µs)

LPO - LF oscillator

100

µs

Cold start-up time

2000

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5.6.1.3 Phase-Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

•

Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The

frequency modulation capability of PLL2 is permanently disabled.

Configurable frequency multipliers and dividers

Built-in PLL Slip monitoring circuit

•

Option to reset the device on a PLL slip detection

5.6.1.3.1 Block Diagram

Figure 5-5 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and

PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the

multiplier and dividers for PLL2.

/NR

/OD

PLLCLK

OSCIN

INTCLK

VCOCLK

post_ODCLK

PLL

/1 to /64

/1 to /8

/1 to /32

f_PLLCLK= (f_OSCIN/ NR) * NF / (OD * R)

/NF

/1 to /256

/NR2

/OD2

/R2

PLL2CLK

OSCIN

VCOCLK2

INTCLK2

post_ODCLK2

/1 to /64

PLL#2

/1 to /8

/1 to /32

f_PLL2CLK= (f_OSCIN/ NR2) * NF2 / (OD2 * R2)

/NF2

/1 to /256

Figure 5-5. GWT PLLx Block Diagram

5.6.1.3.2 PLL Timing Specifications

Table 5-14. PLL Timing Specifications

PARAMETER

MIN

MAX

UNIT

MHz

f_INTCLK

PLL1 Reference Clock frequency

f_{post_ODCLK}

f_VCOCLK

Post-ODCLK – PLL1 Post-divider input clock frequency

VCOCLK – PLL1 Output Divider (OD) input clock frequency

PLL2 Reference Clock frequency

400

550

f_INTCLK2

f_{post_ODCLK2}

f_VCOCLK2

Post-ODCLK – PLL2 Post-divider input clock frequency

VCOCLK – PLL2 Output Divider (OD) input clock frequency

400

550

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5.6.1.4 External Clock Inputs

The device supports up to two external clock inputs. This clock input must be a square-wave input.

Table 5-15 specifies the electrical and timing requirements for these clock inputs.

Table 5-15. External Clock Timing and Electrical Specifications

PARAMETER

MIN

MAX

UNIT

MHz

f_EXTCLKx

External clock input frequency

EXTCLK high-pulse duration

EXTCLK low-pulse duration

Low-level input voltage

High-level input voltage

t_w(EXTCLKIN)H

t_w(EXTCLKIN)L

v_iL(EXTCLKIN)

v_iH(EXTCLKIN)

–0.3

0.8

VCCIO + 0.3

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5.6.2 Clock Domains

5.6.2.1 Clock Domain Descriptions

Table 5-16 lists the device clock domains and their default clock sources. Table 5-16 also lists the system

module control register that is used to select an available clock source for each clock domain.

Table 5-16. Clock Domain Descriptions

DEFAULT

SOURCE

SOURCE SELECTION

CLOCK DOMAIN

CLOCK DISABLE BIT

SPECIAL CONSIDERATIONS

•

This the main clock from which HCLK is

divided down

•

In phase with HCLK

Is disabled separately from HCLK through

the CDDISx registers bit 0

GCLK1

SYS.CDDIS.0

OSCIN

SYS.GHVSRC[3:0]

•

Can be divided-by-1 up to 8 when running

CPU self-test (LBIST) using the CLKDIV

field of the STCCLKDIV register at

address 0xFFFFE108

•

Always the same frequency as GCLK1

2 cycles delayed from GCLK1

Is disabled along with GCLK1

GCLK2

HCLK

SYS.CDDIS.0

SYS.CDDIS.1

OSCIN

SYS.GHVSRC[3:0]

Gets divided by the same divider setting

as that for GCLK1 when running CPU self-

test (LBIST)

•

Divided from GCLK1 through

HCLKCNTLregister

•

Allowable clock ratio from 1:1 to 4:1

Is disabled through the CDDISx registers

bit 1

•

Divided down from HCLK through

CLKCNTL register

•

Can be HCLK/1, HCLK/2,... or HCLK/16

VCLK

SYS.CDDIS.2

OSCIN

SYS.GHVSRC[3:0]

Is disabled separately from HCLK through

the CDDISx registers bit 2

•

HCLK:VCLK2:VCLK must be integer ratios

of each other

•

Divided down from HCLK

Can be HCLK/1, HCLK/2,... or HCLK/16

Frequency must be an integer multiple of

VCLK frequency

VCLK2

VCLK3

SYS.CDDIS.3

SYS.CDDIS.8

OSCIN

SYS.GHVSRC[3:0]

•

Is disabled separately from HCLK through

the CDDISx registers bit 3

•

Divided down from HCLK

Can be HCLK/1, HCLK/2,... or HCLK/16

Is disabled separately from HCLK through

the CDDISx registers bit 8

•

Defaults to VCLK as the source

VCLKA1

VCLKA2

VCLKA4

SYS.CDDIS.4

SYS.CDDIS.5

SYS.CDDIS.11

VCLK

SYS.VCLKASRC[3:0]

SYS.VCLKACON1[19:16]

Is disabled through the CDDISx registers

bit 4

•

Defaults to VCLK as the source

Is disabled through the CDDISx registers

bit 5

•

Defaults to VCLK as the source

Is disabled through the CDDISx registers

bit 11

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Table 5-16. Clock Domain Descriptions (continued)

DEFAULT

SOURCE

SOURCE SELECTION

CLOCK DOMAIN

CLOCK DISABLE BIT

SPECIAL CONSIDERATIONS

•

Divided down from VCLKA4 using the

VCLKA4R field of the VCLKACON1

Frequency can be VCLKA4/1,

VCLKA4/2, ..., or VCLKA4/8

VCLKA4_DIVR

SYS.VCLKACON1.20

VCLK

SYS.VCLKACON1[19:16]

•

Default frequency is VCLKA4/2

Is disabled separately through the

VCLKA4_DIV_CDDIS bit in the

VCLKACON1 register, if the VCLKA4 is

not already disabled

•

Defaults to VCLK as the source

If a clock source other than VCLK is

selected for RTICLK1, then the RTICLK1

frequency must be less than or equal to

VCLK/3

RTICLK1

SYS.CDDIS.6

VCLK

SYS.RCLKSRC[3:0]

•

Application can ensure this by

programming the RTI1DIV field of the

RCLKSRC register, if necessary

Is disabled through the CDDISx registers

bit 6

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5.6.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in Figure 5-6.

GCM

GCLK, GCLK2 (to CPU, CCM)

OSCIN

FMzPLL

X1..256

(SSPLL)

/1..8

HCLK1 (to SYSTEM)

/1..4

/1..32

/1..64

VCLK_s (VCLK to system modules)

VCLK (VCLK to peripherals on PCR3)

VCLK2 (to N2HETx and HTUx)

/1..16

80kHz

Low Power

Oscillator

10MHz

/1..16

PLL # 2 (SSPLL)

VCLK3 (to EMIF, eCAPx, ePWMx,

Ethernet and eQEPx)

/1..32

/1..64 X1..256

/1..8

* the frequency at this node must not

exceed the maximum GCLK specification.

CLKSRC(7:0)

VCLK

EXTCLKIN1

EXTCLKIN2

VCLKA1 (to DCANx)

CLKSRC(7:0)

VCLK

VCLK3

VCLKA2 (to FlexRay and FTU)

VCLKA4_DIVR

CLKSRC(7:0)

VCLK

VCLKA4_DIVR_EMAC (to Ethernet,

as alternate for MIIXCLK and/or

MIIRXCLK) VCLKA4 is left open.

Ethernet

CLKSRC(7:0)

VCLK

/1, 2, 4, or 8

RTICLK1 (to RTI1, DWWD)

EMIF

VCLKA1

VCLK

VCLK2

VCLKA2

VCLK2

VCLKA2

HRP

/1..64

/2,3..2²⁴

/1,2..32

/1,2..65536

/1,2..256

/1,2,..4

/1,2,..256

/1,2,..1024

N2HETx

FlexRay

GTUC1,2

FlexRay

Baud

Rate

LRP

/2⁰..2⁵

Prop_seg

Phase_seg2

I2C baud

rate

ECLK

SPI

Baud Rate

ADCLK

LIN / SCI

Baud Rate

Phase_seg1

I2C

Loop

High

Resolution Clock

SPIx,MibSPIx

LIN, SCI

External Clock

MibADCx

FlexRay

EXTCLKIN1

NTU[3]

NTU[2]

NTU[1]

NTU[0]

CAN Baud Rate

DCANx

PLL#2 output

Startof cycle

Macro Tick

N2HETx

RTI

Figure 5-6. Device Clock Domains

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5.6.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC

Some applications may need to use both the FlexRay and the Ethernet interfaces. The FlexRay controller

requires the VCLKA2 frequency to be 80 MHz, while the MII interface requires VCLKA4_DIVR_EMAC to

be 25 MHz and the RMII requires VCLKA4_DIVR_EAMC to be 50 MHz.

These different frequencies are supported by adding special dedicated clock source selection options for

the VCLKA4_DIVR_EMAC clock domain. This logic is shown in Figure 5-7.

VCLKA4 (left open)

VCLK

/DIVR

VCLKA4_DIVR_EMAC

PLL2 post_ODCLK/8

(to EMAC)

PLL2 post_ODCLK/16

VCLKA4_SRC

Figure 5-7. VCLKA4_DIVR Source Selection Options

The PLL2 post_ODCLK is brought out as a separate output from the PLL wrapper module. There are two

additional dividers implemented at the device-level to divide this PLL2 post_ODCLK by 8 and by 16.

As shown in Figure 5-7, the VCLKA4_SRC configured through the system module VCLKACON1 control

multiplexor is implemented to select between the VCLKA4_DIVR and the two additional clock sources –

PLL2 post_ODCLK/8 and post_ODCLK/16.

Table 5-17 lists the VCLKA4_DIVR_EMAC clock source selections.

Table 5-17. VCLKA4_DIVR_EMAC Clock Source Selection

VCLKA4_SRC FROM VCLKACON1[19–16]

CLOCK SOURCE FOR VCLKA4_DIVR_EMAC

OSCIN / VCLKA4R

0x0

0x1

PLL1CLK / VCLKA4R

Reserved

0x2

0x3

EXTCLKIN1 / VCLKA4R

LF LPO / VCLKA4R

HF LPO / VCLKA4R

PLL2CLK / VCLKA4R

EXTCLKIN2 / VCLKA4R

VCLK

0x4

0x5

0x6

0x7

0x8–0xD

0xE

PLL2 post_ODCLK/8

PLL2 post_ODCLK/16

0xF

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5.6.4 Clock Test Mode

The TMS570 platform architecture defines a special mode that allows various clock signals to be selected

and output on the ECLK1 terminal and N2HET1[12] device outputs. This special mode, Clock Test Mode,

is very useful for debugging purposes and can be configured through the CLKTEST register in the system

module. See Table 5-18 and Table 5-19 for the CLKTEST bits value and signal selection.

Table 5-18. Clock Test Mode Options for Signals on ECLK1

SEL_ECP_PIN = CLKTEST[4-0]

00000

SIGNAL ON ECLK1

Oscillator Clock

00001

PLL1 Clock Output

00010

Reserved

00011

EXTCLKIN1

00100

Low-Frequency Low-Power Oscillator (LFLPO) Clock [CLK80K]

00101

High-Frequency Low-Power Oscillator (HFLPO) Clock [CLK10M]

00110

PLL2 Clock Output

EXTCLKIN2

GCLK1

00111

01000

01001

RTI1 Base

Reserved

01010

01011

VCLKA1

01100

VCLKA2

01101

Reserved

01110

VCLKA4_DIVR

Flash HD Pump Oscillator

Reserved

01111

10000

10001

HCLK

10010

VCLK

10011

VCLK2

10100

VCLK3

10101

Reserved

10110

Reserved

10111

EMAC Clock Output

Reserved

11000

11001

Reserved

11010

Reserved

11011

Reserved

11100

Reserved

11101

Reserved

11110

Reserved

11111

Reserved

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Table 5-19. Clock Test Mode Options for Signals on N2HET1[12]

SEL_GIO_PIN = CLKTEST[11-8]

SIGNAL ON N2HET1[12]

Oscillator Valid Status

PLL1 Valid Status

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Reserved

HFLPO Clock Output Valid Status [CLK10M]

PLL2 Valid Status

Reserved

LFLPO Clock Output Valid Status [CLK80K]

Oscillator Valid status

Reserved

VCLKA4

Oscillator Valid status

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5.7 Clock Monitoring

The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal LPO.

The LPO provides two different clock sources – a low frequency (CLK80K) and a high frequency

(CLK10M).

The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN

frequency falls out of a frequency window, the CLKDET flags this condition in the global status register

(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the CLK10M clock (limp

mode clock).

The valid OSCIN frequency range is defined as: f_CLK10M/ 4 < f_OSCIN< f_CLK10M* 4.

5.7.1 Clock Monitor Timings

upper

threshold

lower

threshold

fail

pass

fail

f[MHz]

1.375

4.875

Figure 5-8. LPO and Clock Detection, Untrimmed CLK10M

5.7.2 External Clock (ECLK) Output Functionality

The ECLK1/ECLK2 terminal can be configured to output a prescaled clock signal indicative of an internal

device clock. This output can be externally monitored as a safety diagnostic.

5.7.3 Dual Clock Comparators

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by

counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of

spec, an error signal is generated. For example, the DCC1 can be configured to use CLK10M as the

reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration

allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.

An additional use of this module is to measure the frequency of a selectable clock source. For example,

the reference clock is connected to Counter 0 and the signal to be measured is connected to Counter 1.

Counter 0 is programmed with a start value of known time duration (measurement time) from the

reference clock. Counter 1 is programmed with a maximum start value. Start both counter simultaneously.

When Counter 0 decrements to zero, both counter will stop and an error signal is generated if Counter 1

does not reach zero. The frequency of the input signals can be calculated from the count value of Counter

1 and the measurement time.

5.7.3.1 Features

•

Takes two different clock sources as input to two independent counter blocks.

One of the clock sources is the known-good, or reference clock; the second clock source is the "clock

under test."

•

Each counter block is programmable with initial, or seed values.

The counter blocks start counting down from their seed values at the same time; a mismatch from the

expected frequency for the clock under test generates an error signal which is used to interrupt the

CPU.

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5.7.3.2 Mapping of DCC Clock Source Inputs

Table 5-20. DCC1 Counter 0 Clock Sources

CLOCK SOURCE[3:0]

CLOCK NAME

Oscillator (OSCIN)

High-frequency LPO

Test clock (TCK)

Others

0x5

0xA

Table 5-21. DCC1 Counter 1 Clock Sources

KEY[3:0]

CLOCK SOURCE[3:0]

CLOCK NAME

Others

–

N2HET1[31]

Main PLL free-running clock

output

0x0

0x1

0x2

PLL #2 free-running clock output

Low-frequency LPO

High-frequency LPO

Reserved

0xA

0x3

0x4

0x5

EXTCLKIN1

0x6

EXTCLKIN2

0x7

Reserved

0x8 - 0xF

VCLK

Table 5-22. DCC2 Counter 0 Clock Sources

CLOCK SOURCE[3:0]

CLOCK NAME

Oscillator (OSCIN)

Test clock (TCK)

Others

0xA

Table 5-23. DCC2 Counter 1 Clock Sources

KEY[3:0]

CLOCK SOURCE[3:0]

CLOCK NAME

Others

–

N2HET2[0]

PLL2_post_ODCLK/8

PLL2_post_ODCLK/16

Reserved

0x1

0x2

0xA

0x3 - 0x7

0x8 - 0xF

VCLK

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5.8 Glitch Filters

Table 5-24 lists the signals with glitch filters present .

Table 5-24. Glitch Filter Timing Specifications

TERMINAL

PARAMETER

MIN

MAX UNIT

Filter time nPORRST terminal; pulses less than MIN will be filtered out,

pulses greater than MAX will generate a reset⁽¹⁾

nPORRST

t_f(nPORRST)

t_f(nRST)

475

2000

Filter time nRST terminal; pulses less than MIN will be filtered out, pulses

greater than MAX will generate a reset

nRST

TEST

475

Filter time TEST terminal; pulses less than MIN will be filtered out, pulses

greater than MAX will pass through

t_f(TEST)

(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,

I/O pins, forth) without also generating a valid reset signal to the CPU.

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5.9 Device Memory Map

5.9.1 Memory Map Diagram

Figure 5-9 shows the device memory map.

0xFFFFFFFF

SYSTEM Peripherals - Frame 1

0xFFF80000

0xFFF7FFFF

Peripherals - Frame 3

CRC1

0xFF000000

0xFEFFFFFF

0xFE000000

RESERVED

0xFCFFFFFF

Peripherals - Frame 2

0xFC000000

0xFBFFFFFF

CRC2

0xFB000000

RESERVED

Flash

(Flash ECC, OTP and EEPROM accesses)

0xF047FFFF

0xF0000000

RESERVED

0x87FFFFFF

0x80000000

EMIF (128MB)

SDRAM

CS0

RESERVED

0x6FFFFFFF ^reserved

CS4

^0x6C000000EMIF (16MB * 3)

0x68000000

CS3

0x64000000 Async RAM

CS2

0x60000000

RESERVED

0x37FFFFFF

0x34000000

0x33FFFFFF

R5F Cache

RESERVED

0x30000000

0x0847FFFF

0x08400000

RAM - ECC

RESERVED

0x0807FFFF

0x08000000

RAM (512KB)

RESERVED

0x003FFFFF

0x00000000

Flash (4MB)

Figure 5-9. Memory Map

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5.9.2 Memory Map Table

Table 5-25. Module Registers / Memories Memory Map

ADDRESS RANGE

RESPONSE FOR

ACCESS TO

UNIMPLEMENTED

LOCATIONS IN

FRAME

MEMORY

SELECT

FRAME

SIZE

ACTUAL

SIZE

TARGET NAME

START

END

Level 2 Memories

Level 2 Flash Data Space

Level 2 RAM

0x0000_0000

0x003F_FFFF

0x083F_FFFF

0x087F_FFFF

4MB

Abort

0x0800_0000

0x0840_0000

512KB

Level 2 RAM ECC

Accelerator Coherency Port

0x0800_0000 0x087F_FFFF

Level 1 Cache Memories

Accelerator Coherency Port

8MB

512KB

Abort

Cortex-R5F Data Cache

Memory

0x3000_0000

0x3100_0000

0x30FF_FFFF

0x31FF_FFFF

16MB

32KB

Cortex-R5F Instruction Cache

Memory

External Memory Accesses

EMIF Chip Select 2

(asynchronous)

Access to

"Reserved" space

will generate Abort

0x6000_0000

0x63FF_FFFF

0x67FF_FFFF

0x6BFF_FFFF

0x87FF_FFFF

64MB

128MB

16MB

128MB

EMIF Chip Select 3

(asynchronous)

0x6400_0000

0x6800_0000

0x8000_0000

EMIF Chip Select 4

(asynchronous)

EMIF Chip Select 0

(synchronous)

Flash OTP, ECC, EEPROM Bank

Customer OTP, Bank0

Customer OTP, Bank1

0xF000_0000

0xF000_2000

0xF000_1FFF

0xF000_3FFF

8KB

4KB

Abort

Customer OTP, EEPROM

Bank

0xF000_E000

0xF000_FFFF

8KB

1KB

Customer OTP-ECC, Bank0

Customer OTP-ECC, Bank1

0xF004_0000

0xF004_0400

0xF004_03FF

0xF004_07FF

1KB

512B

Customer OTP-ECC,

EEPROM Bank

0xF004_1C00

0xF004_1FFF

1KB

128B

TI OTP, Bank0

0xF008_0000

0xF008_2000

0xF008_E000

0xF00C_0000

0xF00C_0400

0xF00C_1C00

0xF010_0000

0xF020_0000

0xF040_0000

0xF008_1FFF

0xF008_3FFF

0xF008_FFFF

0xF00C_03FF

0xF00C_07FF

0xF00C_1FFF

0xF01F_FFFF

0xF03F_FFFF

0xF05F_FFFF

8KB

1KB

1MB

2MB

4KB

TI OTP, Bank1

TI OTP, EEPROM Bank

TI OTP-ECC, Bank0

TI OTP-ECC, Bank1

TI OTP-ECC, EEPROM Bank

EEPROM Bank-ECC

EEPROM Bank

1KB

512B

128B

16KB

128KB

512KB

Abort

Flash Data Space ECC

Interconnect SDC MMR

0xFA00_0000

0xFAFF_FFFF

16MB

Registers/Memories under PCR2 (Peripheral Segment 2)

CPPI Memory Slave (Ethernet

RAM)

Abort

PCS[41]

0xFC52_0000

0xFCF7_8000

0xFC52_1FFF

0xFCF7_87FF

8KB

2KB

8KB

2KB

CPGMAC Slave (Ethernet

Slave)

No Error

PS[30]-PS[31]

CPGMACSS Wrapper

(Ethernet Wrapper)

PS[29]

0xFCF7_8800

0xFCF7_8900

0xFCF7_88FF

0xFCF7_89FF

256B

Ethernet MDIO Interface

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Table 5-25. Module Registers / Memories Memory Map (continued)

ADDRESS RANGE

RESPONSE FOR

ACCESS TO

UNIMPLEMENTED

LOCATIONS IN

FRAME

MEMORY

SELECT

FRAME

SIZE

ACTUAL

SIZE

TARGET NAME

START

END

ePWM1

ePWM2

ePWM3

ePWM4

ePWM5

ePWM6

ePWM7

eCAP1

0xFCF7_8C00

0xFCF7_8D00

0xFCF7_8E00

0xFCF7_8F00

0xFCF7_9000

0xFCF7_9100

0xFCF7_9200

0xFCF7_9300

0xFCF7_9400

0xFCF7_9500

0xFCF7_9600

0xFCF7_9700

0xFCF7_9800

0xFCF7_9900

0xFCF7_9A00

0xFCF7_8CFF

0xFCF7_8DFF

0xFCF7_8EFF

0xFCF7_8FFF

0xFCF7_90FF

0xFCF7_91FF

0xFCF7_92FF

0xFCF7_93FF

0xFCF7_94FF

0xFCF7_95FF

0xFCF7_96FF

0xFCF7_97FF

0xFCF7_98FF

0xFCF7_99FF

0xFCF7_9AFF

256B

Abort

PS[28]

PS[27]

PS[26]

eCAP2

eCAP3

eCAP4

eCAP5

eCAP6

eQEP1

PS[25]

eQEP2

PCR2 registers

Reads return zeros,

writes have no effect

PPSE[4]–PPSE[5]

0xFCFF_1000

0xFCFF_17FF

2KB

NMPU (EMAC)

EMIF Registers

PPSE[6]

PPS[2]

0xFCFF_1800

0xFCFF_E800

0xFCFF_18FF

0xFCFF_E8FF

512B

256B

512B

256B

Abort

Cyclic Redundancy Checker (CRC) Module Register Frame

CRC1

CRC2

Accesses above

0xFE000200

generate abort.

0xFE00_0000

0xFB00_0000

0xFEFF_FFFF

0xFBFF_FFFF

16MB

512KB

Accesses above

0xFB000200

generate abort.

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Table 5-25. Module Registers / Memories Memory Map (continued)

ADDRESS RANGE

RESPONSE FOR

ACCESS TO

UNIMPLEMENTED

LOCATIONS IN

FRAME

MEMORY

SELECT

FRAME

SIZE

ACTUAL

SIZE

TARGET NAME

START

END

Memories under User PCR3 (Peripheral Segment 3)

MIBSPI5 RAM

Abort for accesses

above 2KB

PCS[5]

0xFF0A_0000

0xFF06_0000

0xFF0C_0000

0xFF08_0000

0xFF0E_0000

0xFF0B_FFFF

0xFF07_FFFF

0xFF0D_FFFF

0xFF09_FFFF

0xFF0F_FFFF

128KB

2KB

4KB

MIBSPI4 RAM

MIBSPI3 RAM

MIBSPI2 RAM

MIBSPI1 RAM

DCAN4 RAM

Abort for accesses

above 2KB

PCS[3]

PCS[6]

PCS[4]

PCS[7]

Abort for accesses

above 2KB

Abort for accesses

above 2KB

Abort for accesses

above 4KB

Abort generated for

accesses beyond

offset 0x2000

PCS[12]

PCS[13]

PCS[14]

PCS[15]

0xFF18_0000

0xFF1A_0000

0xFF1C_0000

0xFF1E_0000

0xFF19_FFFF

0xFF1B_FFFF

0xFF1D_FFFF

0xFF1F_FFFF

128KB

8KB

DCAN3 RAM

DCAN2 RAM

DCAN1 RAM

MIBADC2 RAM

Abort generated for

accesses beyond

offset 0x2000

Abort generated for

accesses beyond

offset 0x2000

Abort generated for

accesses beyond

offset 0x2000.

Wrap around for

accesses to

PCS[29]

0xFF3A_0000

0xFF3B_FFFF

128KB

8KB

unimplemented

address offsets

lower than 0x1FFF.

MIBADC1 RAM

Wrap around for

accesses to

unimplemented

address offsets

lower than 0x1FFF.

MIBADC1 Look-UP Table

Look-Up Table for

ADC1 wrapper.

Starts at address

offset 0x2000 and

ends at address

PCS[31]

0xFF3E_0000

0xFF3F_FFFF

128KB

offset 0x217F. Wrap

around for accesses

between offsets

384 bytes

0x0180 and 0x3FFF.

Abort generation for

accesses beyond

offset 0x4000.

NHET2 RAM

Wrap around for

accesses to

unimplemented

address offsets

lower than 0x3FFF.

Abort generated for

accesses beyond

0x3FFF.

PCS[34]

PCS[35]

0xFF44_0000

0xFF46_0000

0xFF45_FFFF

0xFF47_FFFF

128KB

16KB

NHET1 RAM

Wrap around for

accesses to

unimplemented

address offsets

lower than 0x3FFF.

Abort generated for

accesses beyond

0x3FFF.

HET TU2 RAM

HET TU1 RAM

FlexRay TU RAM

PCS[38]

PCS[39]

PCS[40]

0xFF4C_0000

0xFF4E_0000

0xFF50_0000

0xFF4D_FFFF

0xFF4F_FFFF

0xFF51_FFFF

128KB

1KB

Abort

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Table 5-25. Module Registers / Memories Memory Map (continued)

ADDRESS RANGE

RESPONSE FOR

ACCESS TO

UNIMPLEMENTED

LOCATIONS IN

FRAME

MEMORY

SELECT

FRAME

SIZE

ACTUAL

SIZE

TARGET NAME

START

END

CoreSight Debug Components

0xFFA0_0000

CoreSight Debug ROM

Reads return zeros,

writes have no effect

CSCS[0]

0xFFA0_0FFF

0xFFA0_1FFF

0xFFA0_2FFF

0xFFA0_3FFF

0xFFA0_4FFF

0xFFA0_7FFF

0xFFA0_9FFF

0xFFA0_AFFF

0xFFA0_BFFF

4KB

Cortex-R5F Debug

ETM-R5

CoreSight TPIU

POM

Reads return zeros,

writes have no effect

CSCS[1]

CSCS[2]

CSCS[3]

CSCS[4]

CSCS[7]

CSCS[9]

CSCS[10]

CSCS[11]

0xFFA0_1000

0xFFA0_2000

0xFFA0_3000

0xFFA0_4000

0xFFA0_7000

0xFFA0_9000

0xFFA0_A000

0xFFA0_B000

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

CTI1

Reads return zeros,

writes have no effect

CTI3

Reads return zeros,

writes have no effect

CTI4

Reads return zeros,

writes have no effect

CSTF

Reads return zeros,

writes have no effect

Registers under PCR3 (Peripheral Segment 3)

PCR3 registers

FTU

Reads return zeros,

writes have no effect

PS[31:30]

PS[23]

0xFFF7_8000

0xFFF7_A000

0xFFF7_87FF

0xFFF7_A1FF

2KB

Reads return zeros,

writes have no effect

512B

HTU1

HTU2

NHET1

PS[22]

0xFFF7_A400

0xFFF7_A500

0xFFF7_A4FF

0xFFF7_A5FF

256B

Abort

Reads return zeros,

writes have no effect

PS[17]

PS[16]

PS[15]

PS[12]+PS[13]

PS[10]

PS[8]

0xFFF7_B800

0xFFF7_B900

0xFFF7_BC00

0xFFF7_C000

0xFFF7_C200

0xFFF7_C800

0xFFF7_D400

0xFFF7_D500

0xFFF7_DC00

0xFFF7_DE00

0xFFF7_E000

0xFFF7_E200

0xFFF7_E400

0xFFF7_E500

0xFFF7_E600

0xFFF7_E700

0xFFF7_B8FF

0xFFF7_B9FF

0xFFF7_BCFF

0xFFF7_C1FF

0xFFF7_C3FF

0xFFF7_CFFF

0xFFF7_D4FF

0xFFF7_D5FF

0xFFF7_DDFF

0xFFF7_DFFF

0xFFF7_E1FF

0xFFF7_E3FF

0xFFF7_E4FF

0xFFF7_E5FF

0xFFF7_E6FF

0xFFF7_E7FF

256B

512B

2KB

256B

512B

2KB

NHET2

GIO

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

MIBADC1

MIBADC2

FlexRay

I2C1

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

256B

512B

256B

512B

256B

I2C2

Reads return zeros,

writes have no effect

DCAN1

DCAN2

DCAN3

DCAN4

LIN1

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

PS[8]

Reads return zeros,

writes have no effect

PS[7]

Reads return zeros,

writes have no effect

PS[7]

Reads return zeros,

writes have no effect

PS[6]

SCI3

Reads return zeros,

writes have no effect

PS[6]

LIN2

Reads return zeros,

writes have no effect

PS[6]

SCI4

Reads return zeros,

writes have no effect

PS[6]

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Table 5-25. Module Registers / Memories Memory Map (continued)

ADDRESS RANGE

RESPONSE FOR

ACCESS TO

UNIMPLEMENTED

LOCATIONS IN

FRAME

MEMORY

SELECT

FRAME

SIZE

ACTUAL

SIZE

TARGET NAME

START

END

MibSPI1

Reads return zeros,

writes have no effect

PS[2]

PS[1]

PS[0]

0xFFF7_F400

0xFFF7_F600

0xFFF7_F800

0xFFF7_FA00

0xFFF7_FC00

0xFFF7_F5FF

0xFFF7_F7FF

0xFFF7_F9FF

0xFFF7_FBFF

0xFFF7_FDFF

512B

MibSPI2

MibSPI3

MibSPI4

MibSPI5

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

System Modules Control Registers and Memories under PCR1 (Peripheral Segment 1)

DMA RAM

VIM RAM

PPCS[0]

0xFFF8_0000

0xFFF8_0FFF

4KB

Abort

Wrap around for

accesses to

unimplemented

address offsets

lower than 0x2FFF.

PPCS[2]

0xFFF8_2000

0xFFF8_2FFF

4KB

RTP RAM

PPCS[3]

PPCS[7]

PPCS[12]

0xFFF8_3000

0xFFF8_7000

0xFFF8_C000

0xFFFF_0000

0xFFF8_3FFF

0xFFF8_7FFF

0xFFF8_CFFF

0xFFFF_01FF

4KB

512B

4KB

512B

Abort

Flash Wrapper

eFuse Farm Controller

Power Domain Control (PMM) PPSE[0]

FMTM

Reads return zeros,

writes have no effect

Note: This module is only used PPSE[1]

by TI during test

0xFFFF_0400

0xFFFF_0800

0xFFFF_05FF

0xFFFF_08FF

512B

256B

512B

256B

STC2 (NHET1/2)

PPSE[2]

Reads return zeros,

writes have no effect

SCM

PPSE[2]

PPSE[3]

0xFFFF_0A00

0xFFFF_0C00

0xFFFF_0AFF

0xFFFF_0FFF

256B

1KB

256B

1KB

Abort

EPC

PCR1 registers

Reads return zeros,

writes have no effect

PPSE[4]–PPSE[5]

0xFFFF_1000

0xFFFF_17FF

2KB

NMPU (PS_SCR_S)

NMPU (DMA Port A)

Pin Mux Control (IOMM)

PPSE[6]

0xFFFF_1800

0xFFFF_1A00

0xFFFF_19FF

0xFFFF_1BFF

512B

Abort

Reads return zeros,

writes have no effect

PPSE[7]

PPS[0]

PPS[1]

0xFFFF_1C00

0xFFFF_E100

0xFFFF_E400

0xFFFF_E600

0xFFFF_1FFF

0xFFFF_E1FF

0xFFFF_E5FF

0xFFFF_E6FF

2KB

256B

512B

256B

1KB

256B

512B

256B

System Module - Frame 2 (see

the TRM SPNU563)

Reads return zeros,

writes have no effect

PBIST

Reads return zeros,

writes have no effect

STC1 (Cortex-R5F)

DCC1

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

PPS[3]

PPS[4]

PPS[5]

0xFFFF_EC00

0xFFFF_F000

0xFFFF_F400

0xFFFF_ECFF

0xFFFF_F3FF

0xFFFF_F4FF

256B

1KB

256B

1KB

DMA

Abort

DCC2

Reads return zeros,

writes have no effect

256B

ESM register

CCM-R5F

DMM

Reads return zeros,

writes have no effect

PPS[5]

0xFFFF_F500

0xFFFF_F600

0xFFFF_F5FF

0xFFFF_F6FF

256B

Reads return zeros,

writes have no effect

Reads return zeros,

writes have no effect

PPS[5]

PPS[6]

0xFFFF_F700

0xFFFF_F900

0xFFFF_FA00

0xFFFF_F7FF

0xFFFF_F9FF

0xFFFF_FAFF

256B

L2RAMW

RTP

Abort

Reads return zeros,

writes have no effect

RTI + DWWD

Reads return zeros,

writes have no effect

PPS[7]

0xFFFF_FC00

0xFFFF_FCFF

256B

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Table 5-25. Module Registers / Memories Memory Map (continued)

ADDRESS RANGE

RESPONSE FOR

ACCESS TO

UNIMPLEMENTED

LOCATIONS IN

FRAME

MEMORY

SELECT

FRAME

SIZE

ACTUAL

SIZE

TARGET NAME

START

END

VIM

Reads return zeros,

writes have no effect

PPS[7]

0xFFFF_FD00

0xFFFF_FF00

0xFFFF_FEFF

0xFFFF_FFFF

512B

256B

512B

256B

System Module - Frame 1 (see

the TRM SPNU563)

Reads return zeros,

writes have no effect

PPS[7]

5.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts

Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an

imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to

handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU program

status register (CPSR).

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5.9.4 Master/Slave Access Privileges

Table 5-26 and Table 5-27 list the access permissions for each bus master on the device. A bus master is

a module that can initiate a read or a write transaction on the device.

Each slave module on either the CPU Interconnect Subsystem or the Peripheral Interconnect Subsystem

is listed in Table 5-27. Allowed indicates that the module listed in the MASTERS column can access that

slave module.

Table 5-26. Bus Master / Slave Access Matrix for CPU Interconnect Subsystem

SLAVES ON CPU INTERCONNECT SUBSYSTEM

MASTERS

L2 Flash OTP, ECC,

Bank 7 (EEPROM)

L2 FLASH

L2 SRAM

CACHE MEMORY

EMIF

CPU Read

CPU Write

DMA PortA

POM

Allowed

Not allowed

Allowed

Not allowed

Allowed

Not allowed

Allowed

Not allowed

Allowed

Not allowed

Allowed

PS_SCR_M

ACP_M

Allowed

Not allowed

Not Allowed

Not allowed

Table 5-27. Bus Master / Slave Access Matrix for Peripheral Interconnect Subsystem

SLAVES ON PERIPHERAL INTERCONNECT SUBSYSTEM

CPU Interconnect

MASTER ID TO

MASTERS

Resources Under

PCR2 and PCR3

Resources Under

PCR1

Subsystem SDC

MMR Port (see

Section 5.9.6 )

PCRx

CRC1/CRC2

CPU Read

CPU Write

Reserved

DMA PortB

HTU1

Allowed

–

Allowed

–

Allowed

Not allowed

Allowed

Not allowed

Allowed

Not allowed

Allowed

Not allowed

Allowed

HTU2

FTU

DMM

DAP

Allowed

EMAC

Not allowed

5.9.4.1 Special Notes on Accesses to Certain Slaves

By design only the CPU and debugger can have privileged write access to peripherals under the PCR1

segment. The other masters can only read from these registers.

The master-id filtering check is implemented inside each PCR module of each peripheral segment and

can be used to block certain masters from write accesses to certain peripherals. An unauthorized master

write access detected by the PCR will result in the transaction being discarded and an error being

generated to the ESM module.

The device contains dedicated logic to generate a bus error response on any access to a module that is in

a power domain that has been turned off.

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5.9.5 MasterID to PCRx

The MasterID associated with each master port on the Peripheral Interconnect Subsystem contains a 4-bit

value. The MasterID is passed along with the address and control signals to three PCR modules. PCR

decodes the address and control signals to select the peripheral. In addition, it decodes this 4-bit MasterID

value to perform memory protection. With 4-bit of MasterID, it allows the PCR to distinguish among 16

different masters to allow or disallow access to a given peripheral. Associated with each peripheral a 16-

bit MasterID access protection register is defined. Each bit grants or denies the permission of the

corresponding binary coded decimal MasterID. For example, if bit 5 of the access permission register is

set, it grants MasterID 5 to access the peripheral. If bit 7 is clear, it denies MasterID 7 to access the

peripheral. Figure 5-10 shows the MasterID filtering scheme. Table 5-27 lists the MasterID of each master,

which can access the PCRx.

MasterID

Address/Control

ID Decode

Addr Decode

Peripheral Select N

PCRx

Figure 5-10. PCR MasterID Filtering

5.9.6 CPU Interconnect Subsystem SDC MMR Port

The CPU Interconnect Subsystem SDC MMR Port is a special slave to the Peripheral Interconnect

Subsystem. It is memory mapped at starting address of 0xFA00_0000. Various status registers pertaining

to the diagnostics of the CPU Interconnect Subsystem can be access through this slave port. The CPU

Interconnect Subsystem contains built-in hardware diagnostic checkers which will constantly watch

transactions flowing through the interconnect. There is a checker for each master and slave attached to

the CPU Interconnect Subsystem. The checker checks the expected behavior against the generated

behavior by the interconnect. For example, if the CPU issues a burst read request to the flash, the

checker will ensure that the expected behavior is indeed a burst read request to the proper slave module.

If the interconnects generates a transaction which is not a read, or not a burst or not to the flash as the

destination, then the checker will flag it one of the registers. The detected error will also be signaled to the

ESM module. Refer to the Interconnect chapter of the TRM SPNU563 for details on the registers.

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Table 5-28. CPU Interconnect Subsystem SDC Register Bit Field Mapping

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

Remark

•

Each bit indicates the

transaction processing block

inside the interconnect

corresponding to the master

that is detected by the

interconnect checker to have

a fault.

ERR_GENERIC_PARITY

PS_SCR_M

POM

DMA_PORTA

Reserved

CPU AXI-M

ACP-M

Reserved

•

error related to parity

mismatch in the incoming

address

error related to unexpected

transaction sent by the

master

ERR_UNEXPECTED_TRANS

PS_SCR_M

POM

DMA_PORTA

Reserved

CPU AXI-M

ACP-M

Reserved

•

error related to mismatch on

the transaction ID

ERR_TRANS_ID

ERR_TRANS_SIGNATURE

ERR_TRANS_TYPE

PS_SCR_M

POM

DMA_PORTA

Reserved

CPU AXI-M

ACP-M

Reserved

error related to mismatch on

the transaction signature

error related to mismatch on

the transaction type

error related to mismatch on

the parity

ERR_USER_PARITY

Each bit indicates the

transaction processing block

inside the interconnect

corresponding to the slave

that is detected by the

interconnect checker to have

a fault.

L2 Flash

Wrapper Port A

L2 Flash Wrapper

Port B

SERR_UNEXPECTED_MID

L2 RAM Wrapper

EMIF

Reserved

CPU AXi-S

ACP-S

•

error related to mismatch on

the master ID

error related to mismatch on

the most significant address

bits

L2 Flash

Wrapper Port A

L2 Flash Wrapper

Port B

SERR_ADDR_DECODE

SERR_USER_PARITY

L2 RAM Wrapper

EMIF

Reserved

CPU AXi-S

ACP-S

•

error related to mismatch on

the parity of the most

significant address bits

L2 Flash

Wrapper Port A

L2 Flash Wrapper

Port B

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5.9.7 Parameter Overlay Module (POM) Considerations

The Parameter Overlay Module (POM) is implemented as part of the L2FMC module. It is used to redirect

flash memory accesses to external memory interfaces or internal SRAM. The POM has an OCP master

port to redirect accesses. The POM MMRs are located in a separate block and read/writes will happen

through the Debug APB port on the L2FMC. The POM master port is capable of read accesses only.

Inside the CPU Subsystem SCR, the POM master port is connected to both the L2RAMW and EMIF

slaves. The primary roles of the POM are:

•

The POM snoops the access on the two flash slave ports to determine if access should be remapped

or not. It supports 32 regions among the two slave ports.

If access is to be remapped, then the POM kills the access to the flash bank, and instead redirects the

access through its own master.

Upon obtaining response, the POM populates the response FIFO of the respective port so that the

response is delivered back to the original requester.

•

The access is unaffected if the request is not mapped to any region, or if the POM is disabled.

The POM does not add any latency to the flash access when it is turned off.

The POM does not add any latency to the remapped access (except the latency, if any, associated

with the getting the response from the an alternate slave)

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5.10 Flash Memory

5.10.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a

customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense

amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical

construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or

erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

Table 5-29. Flash Memory Banks and Sectors

SECTOR

NO.

MEMORY ARRAYS (OR BANKS)

SEGMENT

LOW ADDRESS

HIGH ADDRESS

16KB

0x0000_0000

0x0000_4000

0x0000_8000

0x0000_C000

0x0001_0000

0x0001_4000

0x0001_8000

0x0002_0000

0x0004_0000

0x0006_0000

0x0008_0000

0x000C_0000

0x0010_0000

0x0014_0000

0x0018_0000

0x001C_0000

0x0020_0000

0x0022_0000

0x0024_0000

0x0026_0000

0x0028_0000

0x002A_0000

0x002C_0000

0x002E_0000

0x0030_0000

0x0032_0000

0x0034_0000

0x0036_0000

0x0038_0000

0x003A_0000

0x003C_0000

0x003E_0000

0x0000_3FFF

0x0000_7FFF

0x0000_BFFF

0x0000_FFFF

0x0001_3FFF

0x0001_7FFF

0x0001_FFFF

0x0003_FFFF

0x0005_FFFF

0x0007_FFFF

0x000B_FFFF

0x000F_FFFF

0x0013_FFFF

0x0017_FFFF

0x001B_FFFF

0x001F_FFFF

0x0021_FFFF

0x0023_FFFF

0x0025_FFFF

0x0027_FFFF

0x0029_FFFF

0x002B_FFFF

0x002D_FFFF

0x002F_FFFF

0x0031_FFFF

0x0033_FFFF

0x0035_FFFF

0x0037_FFFF

0x0039_FFFF

0x003B_FFFF

0x003D_FFFF

0x003F_FFFF

16KB

32KB

128KB

256KB

128KB

BANK0 (2.0MB)

BANK1 (2.0MB)

100

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Table 5-30. EEPROM Flash Bank

SECTOR

SEGMENT

NO.

MEMORY ARRAYS (OR BANKS)

LOW ADDRESS

HIGH ADDRESS

4KB

0xF020_0000

0xF020_0FFF

BANK7 (128KB) for EEPROM emulation

4KB

0xF021_F000

0xF021_FFFF

5.10.2 Main Features of Flash Module

•

Support for multiple flash banks for program and/or data storage

Simultaneous read accesses on two banks while performing program or erase operation on any other

bank

•

Integrated state machines to automate flash erase and program operations

Software interface for flash program and erase operations

Pipelined mode operation to improve instruction access interface bandwidth

Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R5F CPU

Support for a rich set of diagnostic features

5.10.3 ECC Protection for Flash Accesses

All accesses to the L2 program flash memory are protected by SECDED logic embedded inside the CPU.

The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash

memory. The CPU calculates the expected ECC code based on the 64 bits data received and compares it

with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU,

while a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling

mechanism is not enabled by default and must be enabled by setting the 'X' bit of the Performance

Monitor Control Register, c9.

MRC p15,#0,r1,c9,c12,#0

ORR r1, r1, #0x00000010

MCR p15,#0,r1,c9,c12,#0

MRC p15,#0,r1,c9,c12,#0

;Enabling Event monitor states

;Set 4th bit (‘X’) of PMNC register

NOTE

ECC is permanently enabled in the CPU L2 interface.

5.10.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, refer to Section 4.6.

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5.10.5 Flash Program and Erase Timings

5.10.5.1 Flash Program and Erase Timings for Program Flash

Table 5-31. Timing Requirements for Program Flash

MIN

NOM

MAX

300

UNIT

µs

t_{prog(288bits)}

t_prog(Total)

Wide Word (288-bits) programming time

4.0MB programming time⁽¹⁾

–40°C to 125°C

21.3

0°C to 60°C, for first

25 cycles

5.3

0.3

10.6

–40°C to 125°C

t_erase

Sector/Bank erase time

0°C to 60°C, for first

25 cycles

100

Write/erase cycles with 15-year Data Retention

requirement

t_wec

–40°C to 125°C

1000

cycles

(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes

programming 288 bits at a time at the maximum specified operating frequency.

5.10.5.2 Flash Program and Erase Timings for Data Flash

Table 5-32. Timing Requirements for Data Flash

MIN

NOM

MAX

300

2.6

UNIT

µs

t_prog(72bits)

t_prog(Total)

Wide Word (72-bits) programming time

–40°C to 125°C

EEPROM Emulation (bank 7) 128KB

programming time⁽¹⁾

0°C to 60°C, for first

25 cycles

775

0.2

1320

–40°C to 125°C

EEPROM Emulation (bank 7) Sector/Bank erase time t_erase(bank7)

0°C to 60°C, for first

25 cycles

100

Write/erase cycles with 15-year Data Retention

requirement

t_wec

–40°C to 125°C

100000

cycles

(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes

programming 72 bits at a time at the maximum specified operating frequency.

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5.11 L2RAMW (Level 2 RAM Interface Module)

L2RAMW is the TMS570 level two RAM wrapper. Major features implemented in this device include:

•

Supports 512KB of L2 SRAMs

One 64-bit OCP interface

Built-in ECC generation and evaluation logic

–

The ECC logic is enabled by default.

When enabled, automatic ECC correction on write data from masters on any write sizes (8-,16-,32-

,or 64-bit)

–

Less than 64-bit write forces built in read-modify-write

When enabled, reads due to read-modify-write go through ECC correction before data merging with

the incoming write data

•

Redundant address decoding. Same address decode logic block is duplicated and compared to each

other

Data Trace

–

Support tracing of both read and write accesses through RTP module

•

Auto initialization of memory banks to known values for both data and their corresponding ECC

checksum

5.11.1 L2 SRAM Initialization

The entire L2 SRAM can be globally initialized by setting the corresponding bit in SYS.MSINENA register.

When initialized, the memory arrays are written with all zeros for the 64-bit data and the corresponding 8-

bit ECC checksum. Hardware memory initialization eliminates ECC error when the CPU reads from an un-

initialized memory location which can cause an ECC error. For more information, see the device-specific

Technical Reference Manual.

5.12 ECC / Parity Protection for Accesses to Peripheral RAMs

Accesses to some peripheral RAMs are protected by either odd/even parity checking or ECC checking.

During a read access the parity or ECC is calculated based on the data read from the peripheral RAM and

compared with the good parity or ECC value stored in the peripheral RAM for that peripheral. If any word

fails the parity or ECC check, the module generates a ECC/parity error signal that is mapped to the Error

Signaling Module. The module also captures the peripheral RAM address that caused the parity error.

The parity or ECC protection for peripheral RAMs is not enabled by default and must be enabled by the

application. Each individual peripheral contains control registers to enable the parity or ECC protection for

accesses to its RAM.

NOTE

For peripherals with parity protection the CPU read access gets the actual data from the

peripheral. The application can choose to generate an interrupt whenever a peripheral RAM

parity error is detected.

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5.13 On-Chip SRAM Initialization and Testing

5.13.1 On-Chip SRAM Self-Test Using PBIST

5.13.1.1 Features

•

Extensive instruction set to support various memory test algorithms

ROM-based algorithms allow application to run TI production-level memory tests

Independent testing of all on-chip SRAM

5.13.1.2 PBIST RAM Groups

Table 5-33. PBIST RAM Grouping

TEST PATTERN

(ALGORITHM)

March 13N⁽¹⁾

SINGLE

PORT

TRIPLE

READ

SLOW READ FAST READ

TRIPLE

READ

March 13N⁽¹⁾

TWO PORT

(cycles)

RAM

GROUP

MEM

TYPE

NO.

BANKS

MEMORY

TEST CLOCK RGS RDS

(cycles)

ALGO MASK ALGO MASK ALGO MASK ALGO MASK

0x1

0x2

0x4

0x8

GCM_PBIST_R

PBIST_ROM

ROM

24578

8194

GCM_PBIST_R

STC1_1_ROM_R5

STC1_2_ROM_R5

STC2_ROM_NHET

49154

46082

16386

15362

GCM_PBIST_R

AWM1

DCAN1

DCAN2

DMA

GCM_VCLKP

GCM_HCLK

GCM_VCLK2

GCM_VCLKP

GCM_VCLK2

GCM_VCLK

4210

25260

37740

6540

1..6

1..4

1..12

1..2

HTU1

MIBSPI1

MIBSPI2

MIBSPI3

NHET1

VIM

66760

33480

50520

16740

Reserved

RTP

GCM_HCLK

GCM_GCLK1

GCM_VCLKP

GCM_VCLK2

GCM_VCLKP

GCM_VCLK2

GCM_VCLKP

1..12

1..16

50520

133920

4210

ATB⁽²⁾

AWM2

DCAN3

DCAN4

HTU2

1..6

1..4

1..12

25260

6540

MIBSPI4

MIBSPI5

NHET2

FTU

33480

50520

8370

FRAY_INBUF_OUTB

GCM_VCLKP

GCM_VCLK3

1..8

1..3

4..6

33680

6390

8730

CPGMAC_STATE_R

XADDR

CPGMAC_STAT_FIF

(1) March13N is the only algorithm recommended for application testing of RAM.

(2) ATB RAM is part of the ETM module. PBIST testing of this RAM is limited to 85ºC or lower.

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Table 5-33. PBIST RAM Grouping (continued)

TEST PATTERN

(ALGORITHM)

March 13N⁽¹⁾

SINGLE

PORT

TRIPLE

READ

SLOW READ FAST READ

TRIPLE

READ

March 13N⁽¹⁾

TWO PORT

(cycles)

RAM

GROUP

MEM

TYPE

NO.

BANKS

MEMORY

TEST CLOCK RGS RDS

(cycles)

ALGO MASK ALGO MASK ALGO MASK ALGO MASK

0x1

0x2

0x4

0x8

L2RAMW

GCM_HCLK

532580

1597740

166600

299820

166600

R5_ICACHE

R5_DCACHE

Reserved

GCM_GCLK1

GCM_GCLK2

Reserved

GCM_GCLK2

GCM_VCLKP

299820

149910

FRAY_TRBUF_MSG

RAM

9..11

CPGMAC_CPPI

R5_DCACHE_Dirty

Reserved

GCM_VCLK3

133170

16690

GCM_GCLK1

Several memory testing algorithms are stored in the PBIST ROM. However, TI only recommends the

March13N algorithm for application testing of RAM.

The PBIST ROM clock frequency is limited to the maximum frequency of 82.5 MHz.

The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV

field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.

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5.13.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware

Initialization mechanism in the system module. This hardware mechanism allows an application to

program the memory arrays with error detection capability to a known state based on their error detection

scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects

the memories that are to be initialized.

For more information on these registers, see the device-specific Technical Reference Manual.

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is provided in

Table 5-34.

Table 5-34. Memory Initialization⁽¹⁾⁽²⁾

ADDRESS RANGE

BASE ADDRESS

SYS.MSINENA Register L2RAMW.MEMINT_ENA

CONNECTING MODULE

Bit #

ENDING ADDRESS

0x0800FFFF

0x0801FFFF

0x0802FFFF

0x0803FFFF

0x0804FFFF

0x0805FFFF

0x0806FFFF

0x0807FFFF

0xFF0BFFFF

0xFF07FFFF

0xFF0DFFFF

0xFF09FFFF

0xFF0FFFFF

0xFF19FFFF

0xFF1BFFFF

0xFF1DFFFF

0xFF1FFFFF

0xFF3BFFFF

0xFF3FFFFF

0xFF45FFFF

0xFF47FFFF

0xFF4DFFFF

0xFF4FFFFF

0xFFF80FFF

0xFFF82FFF

0xFF51FFFF

L2 SRAM

0x08000000

0x08010000

0x08020000

0x08030000

0x08040000

0x08050000

0x08060000

0x08070000

0xFF0A0000

0xFF060000

0xFF0C0000

0xFF080000

0xFF0E0000

0xFF180000

0xFF1A0000

0xFF1C0000

0xFF1E0000

0xFF3A0000

0xFF3E0000

0xFF440000

0xFF460000

0xFF4C0000

0xFF4E0000

0xFFF80000

0xFFF82000

0xFF500000

L2 SRAM

MIBSPI5 RAM⁽⁴⁾

MIBSPI4 RAM⁽⁴⁾

MIBSPI3 RAM⁽⁴⁾

MIBSPI2 RAM⁽⁴⁾

MIBSPI1 RAM⁽⁴⁾

DCAN4 RAM

DCAN3 RAM

DCAN2 RAM

DCAN1 RAM

MIBADC2 RAM

MIBADC1 RAM

NHET2 RAM

NHET1 RAM

HET TU2 RAM

HET TU1 RAM

DMA RAM

n/a

VIM RAM

FlexRay TU RAM

(1) If parity protection is enabled for the peripheral SRAM modules, then the parity bits will also be initialized along with the SRAM modules.

(2) If ECC protection is enabled for the CPU data RAM or peripheral SRAM modules, then the auto-initialization process also initializes the

corresponding ECC space.

(3) The L2 SRAM from range 128KB to 512KB is divided into 8 memory regions. Each region has an associated control bit to enable auto-

initialization.

(4) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the multibuffered mode is enabled. This is

independent of whether the application has already initialized these RAMs using the auto-initialization method or not. The MibSPIx

modules must be released from reset by writing a 1 to the SPIGCR0 registers before starting auto-initialization on the respective RAMs.

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NOTE

Peripheral memories not listed in the table either do not support auto-initialization or have

implemented auto-initialization controlled directly by their respective peripherals.

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5.14 External Memory Interface (EMIF)

5.14.1 Features

The EMIF includes many features to enhance the ease and flexibility of connecting to external

asynchronous memories or SDRAM devices. The EMIF features includes support for:

•

3 addressable chip select for asynchronous memories of up to 16MB each

1 addressable chip select space for SDRAMs up to 128MB

8 or 16-bit data bus width

Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time

Select strobe mode

Extended Wait mode

Data bus parking

NOTE

The EMIF is inherently BE8, or byte invariant big endian. This device is BE32, or word

invariant big endian. There is no difference when interfacing to RAM or using an 8-bit wide

data bus. However, there is an impact when reading from external ROMs or interfacing to

hardware registers with a 16-bit wide data bus. The EMIF can be made BE32 by connecting

EMIF_DATA[7:0] to the ROM or ASIC DATA[15:8] and EMIF_DATA[15:8] to the ROM or

ASIC DATA[7:0].

Alternatively, the code stored in the ROM can be linked as -be8 instead of -be32.

NOTE

For a 32-bit access on the 16-bit EMIF interface, the lower 16-bits (the EMIF_BA[1] will be

low) will be put out first followed by the upper 16-bits (EMIF_BA[1] will be high).

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5.14.2 Electrical and Timing Specifications

5.14.2.1 Read Timing (Asynchronous RAM)

EMIF_nCS[3:2]

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_nDQM[1:0]

EMIF_nOE

EMIF_DATA[15:0]

EMIF_nWE

Figure 5-11. Asynchronous Memory Read Timing

Extended Due to EMIF_WAIT

SETUP

STROBE

STROBE HOLD

EMIF_nCS[3:2]

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_DATA[15:0]

EMIF_nOE

EMIF_WAIT

Asserted

Deasserted

Figure 5-12. EMIFnWAIT Read Timing Requirements

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5.14.2.2 Write Timing (Asynchronous RAM)

EMIF_nCS[3:2]

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_nDQM[1:0]

EMIF_nWE

EMIF_DATA[15:0]

EMIF_nOE

Figure 5-13. Asynchronous Memory Write Timing

Extended Due to EMIF_WAIT

SETUP

STROBE

STROBE HOLD

EMIF_nCS[3:2]

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_DATA[15:0]

EMIF_nWE

EMIF_WAIT

Asserted

Deasserted

Figure 5-14. EMIFnWAIT Write Timing Requirements

5.14.2.3 EMIF Asynchronous Memory Timing

Table 5-35. EMIF Asynchronous Memory Timing Requirements⁽¹⁾

NO.

MIN

NOM

MAX

UNIT

Reads and Writes

(1) E = EMIF_CLK period in ns.

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Table 5-35. EMIF Asynchronous Memory Timing Requirements⁽¹⁾(continued)

NO.

MIN

NOM

MAX

UNIT

t_{w(EM_WAIT)}

Pulse duration, EMIFnWAIT assertion and deassertion

Reads

t_{su(EMDV-EMOEH)}

t_{h(EMOEH-EMDIV)}

t_{su(EMOEL-EMWAIT)}

Setup time, EMIFDATA[15:0] valid before EMIFnOE high

Hold time, EMIFDATA[15:0] valid after EMIFnOE high

Setup Time, EMIFnWAIT asserted before end of Strobe Phase⁽²⁾

Writes

0.5

4E+14

t_{su(EMWEL-EMWAIT)}

Setup Time, EMIFnWAIT asserted before end of Strobe Phase⁽²⁾

4E+14

(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended

wait states. Figure 5-12 and Figure 5-14 describe EMIF transactions that include extended wait states inserted during the STROBE

phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where

the HOLD phase would begin if there were no extended wait cycles.

Table 5-36. EMIF Asynchronous Memory Switching Characteristics^(1)(2)(3)

NO.

PARAMETER

MIN

TYP

MAX UNIT

Reads and Writes

Reads

t_{d(TURNAROUND)}

Turn around time

(TA)*E -3

(TA)*E

(TA)*E + 3

t_c(EMRCYCLE)

EMIF read cycle time (EW = 0)

EMIF read cycle time (EW = 1)

(RS+RST+RH)*E-3

(RS+RST+RH)*E

(RS+RST+RH)*E + 3

(RS+RST+RH+

EWC)*E -3

(RS+RST+RH+

EWC)*E

(RS+RST+RH+

EWC)*E + 3

Output setup time, EMIF_nCS[4:2] low to

EMIF_nOE low (SS = 0)

(RS)*E-3

–3

(RS)*E

(RS)*E+3

t_{su(EMCEL-EMOEL)}

Output setup time, EMIFnCS[4:2] low to

EMIF_nOE low (SS = 1)

Output hold time, EMIF_nOE high to

EMIF_nCS[4:2] high (SS = 0)

(RH)*E -4

–4

(RH)*E

(RH)*E + 3

t_{h(EMOEH-EMCEH)}

Output hold time, EMIF_nOE high to

EMIF_nCS[4:2] high (SS = 1)

Output setup time, EMIF_BA[1:0] valid to

EMIF_nOE low

t_{su(EMBAV-EMOEL)}

t_{h(EMOEH-EMBAIV)}

t_{su(EMBAV-EMOEL)}

t_{h(EMOEH-EMAIV)}

(RS)*E-3

(RH)*E-4

(RS)*E-3

(RH)*E-4

(RS)*E

(RH)*E

(RS)*E

(RH)*E

(RS)*E+3

(RH)*E+3

(RS)*E+3

(RH)*E+3

Output hold time, EMIF_nOE high to

EMIF_BA[1:0] invalid

Output setup time, EMIF_ADDR[21:0] valid to

EMIF_nOE low

Output hold time, EMIF_nOE high to

EMIF_ADDR[21:0] invalid

10 t_w(EMOEL)

EMIF_nOE active low width (EW = 0)

EMIF_nOE active low width (EW = 1)

(RST)*E-3

(RST)*E

(RST)*E+3

(RST+EWC) *E-3

(RST+EWC)*E

(RST+EWC) *E+3

Delay time from EMIF_nWAIT deasserted to

EMIF_nOE high

11 t_{d(EMWAITH-EMOEH)}

29 t_{su(EMDQMV-EMOEL)}

30 t_{h(EMOEH-EMDQMIV)}

3E-3

(RS)*E-5

(RH)*E-4

(RS)*E

(RH)*E

4E+5

(RS)*E+3

(RH)*E+5

Output setup time, EMIF_nDQM[1:0] valid to

EMIF_nOE low

Output hold time, EMIF_nOE high to

EMIF_nDQM[1:0] invalid

Writes

15 t_c(EMWCYCLE)

EMIF write cycle time (EW = 0)

EMIF write cycle time (EW = 1)

(WS+WST+WH)* E-3

(WS+WST+WH)*E

(WS+WST+WH)* E+3

(WS+WST+WH+

EWC)*E -3

(WS+WST+WH+

EWC)*E

(WS+WST+WH+

EWC)*E + 3

(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,

MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait

Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1],

WST[64–1], WH[8–1], and MEWC[1–256]. See the EMIF chapter of the TRM SPNU563 for more information.

(2) E = EMIF_CLK period in ns.

(3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note

that the maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See

the EMIF chapter of the TRM SPNU563 for more information.

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MAX UNIT

Table 5-36. EMIF Asynchronous Memory Switching Characteristics^(1)(2)(3)(continued)

NO.

PARAMETER

MIN

TYP

Output setup time, EMIF_nCS[4:2] low to

EMIF_nWE low (SS = 0)

(WS)*E -3

(WS)*E

(WS)*E + 3

16 t_{su(EMCEL-EMWEL)}

Output setup time, EMIF_nCS[4:2] low to

EMIF_nWE low (SS = 1)

–3

(WH)*E-3

–3

(WH)*E

(WH)*E+3

Output hold time, EMIF_nWE high to

EMIF_nCS[4:2] high (SS = 0)

17 t_{h(EMWEH-EMCEH)}

Output hold time, EMIF_nWE high to

EMIF_CS[4:2] high (SS = 1)

Output setup time, EMIF_nDQM[1:0] valid to

EMIF_nWE low

18 t_{su(EMDQMV-EMWEL)}

19 t_{h(EMWEH-EMDQMIV)}

20 t_{su(EMBAV-EMWEL)}

21 t_{h(EMWEH-EMBAIV)}

22 t_{su(EMAV-EMWEL)}

(WS)*E-3

(WH)*E-3

(WS)*E-3

(WH)*E-3

(WS)*E-3

(WH)*E-3

(WS)*E

(WH)*E

(WS)*E

(WH)*E

(WS)*E

(WH)*E

(WS)*E+3

(WH)*E+3

(WS)*E+3

(WH)*E+3

(WS)*E+3

(WH)*E+3

Output hold time, EMIF_nWE high to

EMIF_nDQM[1:0] invalid

Output setup time, EMIF_BA[1:0] valid to

EMIF_nWE low

Output hold time, EMIF_nWE high to

EMIF_BA[1:0] invalid

Output setup time, EMIF_ADDR[21:0] valid to

EMIF_nWE low

Output hold time, EMIF_nWE high to

EMIF_ADDR[21:0] invalid

23 t_{h(EMWEH-EMAIV)}

24 t_w(EMWEL)

EMIF_nWE active low width (EW = 0)

EMIF_nWE active low width (EW = 1)

(WST)*E-3

(WST)*E

(WST)*E+3

(WST+EWC) *E-3

(WST+EWC)*E

(WST+EWC) *E+3

Delay time from EMIF_nWAIT deasserted to

EMIF_nWE high

25 t_{d(EMWAITH-EMWEH)}

26 t_{su(EMDV-EMWEL)}

27 t_{h(EMWEH-EMDIV)}

3E+3

(WS)*E-3

(WH)*E-3

(WS)*E

(WH)*E

4E+14

(WS)*E+3

(WH)*E+3

Output setup time, EMIF_DATA[15:0] valid to

EMIF_nWE low

Output hold time, EMIF_nWE high to

EMIF_DATA[15:0] invalid

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5.14.2.4 Read Timing (Synchronous RAM)

BASIC SDRAM

READ OPERATION

EMIF_CLK

EMIF_nCS[0]

EMIF_nDQM[1:0]

EMIF_BA[1:0]

EMIF_ADDR[21:0]

2 EM_CLK Delay

EMIF_DATA[15:0]

EMIF_nRAS

EMIF_nCAS

EMIF_nWE

Figure 5-15. Basic SDRAM Read Operation

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5.14.2.5 Write Timing (Synchronous RAM)

BASIC SDRAM

WRITE OPERATION

EMIF_CLK

EMIF_CS[0]

EMIF_DQM[1:0]

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_DATA[15:0]

EMIF_nRAS

EMIF_nCAS

EMIF_nWE

Figure 5-16. Basic SDRAM Write Operation

5.14.2.6 EMIF Synchronous Memory Timing

Table 5-37. EMIF Synchronous Memory Timing Requirements

NO.

MIN

MAX

UNIT

Input setup time, read data valid on

EMIF_DATA[15:0] before EMIF_CLK rising

t_{su(EMIFDV-EM_CLKH)}

t_h(CLKH-DIV)

Input hold time, read data valid on

EMIF_DATA[15:0] after EMIF_CLK rising

2.2

Table 5-38. EMIF Synchronous Memory Switching Characteristics

NO.

PARAMETER

MIN

MAX

UNIT

t_c(CLK)

Cycle time, EMIF clock EMIF_CLK

t_w(CLK)

Pulse width, EMIF clock EMIF_CLK high or low

Delay time, EMIF_CLK rising to EMIF_nCS[0] valid

Output hold time, EMIF_CLK rising to EMIF_nCS[0] invalid

Delay time, EMIF_CLK rising to EMIF_nDQM[1:0] valid

Output hold time, EMIF_CLK rising to EMIF_nDQM[1:0] invalid

t_d(CLKH-CSV)

t_{oh(CLKH-CSIV)}

t_d(CLKH-DQMV)

t_{oh(CLKH-DQMIV)}

Delay time, EMIF_CLK rising to EMIF_ADDR[21:0] and EMIF_BA[1:0]

valid

t_d(CLKH-AV)

Output hold time, EMIF_CLK rising to EMIF_ADDR[21:0] and

EMIF_BA[1:0] invalid

t_oh(CLKH-AIV)

t_d(CLKH-DV)

Delay time, EMIF_CLK rising to EMIF_DATA[15:0] valid

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Table 5-38. EMIF Synchronous Memory Switching Characteristics (continued)

NO.

PARAMETER

MIN

MAX

UNIT

t_oh(CLKH-DIV)

t_d(CLKH-RASV)

t_{oh(CLKH-RASIV)}

t_d(CLKH-CASV)

t_{oh(CLKH-CASIV)}

t_d(CLKH-WEV)

t_{oh(CLKH-WEIV)}

t_{dis(CLKH-DHZ)}

t_{ena(CLKH-DLZ)}

Output hold time, EMIF_CLK rising to EMIF_DATA[15:0] invalid

Delay time, EMIF_CLK rising to EMIF_nRAS valid

Output hold time, EMIF_CLK rising to EMIF_nRAS invalid

Delay time, EMIF_CLK rising to EMIF_nCAS valid

Output hold time, EMIF_CLK rising to EMIF_nCAS invalid

Delay time, EMIF_CLK rising to EMIF_nWE valid

Output hold time, EMIF_CLK rising to EMIF_nWE invalid

Delay time, EMIF_CLK rising to EMIF_DATA[15:0] tri-stated

Output hold time, EMIF_CLK rising to EMIF_DATA[15:0] driving

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5.15 Vectored Interrupt Manager

There are two on-chip Vector Interrupt Manager (VIM) modules. The VIM module provides hardware

assistance for prioritizing and controlling the many interrupt sources present on a device. Interrupts are

caused by events outside of the normal flow of program execution. Normally, these events require a timely

response from the CPU; therefore, when an interrupt occurs, the CPU switches execution from the normal

program flow to an interrupt service routine (ISR).

5.15.1 VIM Features

The VIM module has the following features:

•

Supports 128 interrupt channels

Provides programmable priority for the request lines

Manages interrupt channels through masking

Prioritizes interrupt channels to the CPU

Provides the CPU with the address of the interrupt service routine (ISR) for each interrupt

The two VIM modules are in lockstep. These two VIM modules are memory mapped to the same address

space. From a programmer’s model point of view it is only one VIM module. Writes to VIM1 registers and

memory will be broadcasted to both VIM1 and VIM2. Reads from VIM1 will only read the VIM1 registers

and memory. All interrupt requests which go to the VIM1 module will also go to the VIM2 module.

Because the VIM1 and VIM2 have the identical setup, both will result in the same output behavior

responding to the same interrupt requests. The second VIM module acts as a diagnostic checker module

against the first VIM module. The output signals of the two VIM modules are routed to CCM-R5F module

and are compared constantly. Mis-compare detected will be signaled as an error to the ESM module. The

lockstep VIM pair takes care of the interrupt generation to the lockstep R5F pair.

5.15.2 Interrupt Generation

To avoid common mode failures the input and output signals of the two VIMs are delayed in a different

way as shown in Figure 5-17.

PCR

Cortex-R5 Processor Group

nIRQ/nFIQ/IRQVECADDR

R5F-0

VIM1

Interrupt

Requests

2 cyc

delay

2 cyc

delay

CCM-R5F

ESM

2 cyc

delay

2 cyc

delay

R5F-1

VIM2

Figure 5-17. Interrupt Generation

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5.15.3 Interrupt Request Assignments

Table 5-39. Interrupt Request Assignments

DEFAULT VIM

INTERRUPT CHANNEL

MODULES

VIM INTERRUPT SOURCES

ESM

Reserved

RTI

ESM high-level interrupt (NMI)

Reserved

RTI1 compare interrupt 0

RTI1 compare interrupt 1

RTI1 compare interrupt 2

RTI1 compare interrupt 3

RTI1 overflow interrupt 0

RTI1 overflow interrupt 1

RTI1 time-base

RTI

GIO

GIO high level interrupt

NHET1 high-level interrupt (priority level 1)

HET TU1 level 0 interrupt

MIBSPI1 level 0 interrupt

LIN1 level 0 interrupt

NHET1

HET TU1

MIBSPI1

LIN1

MIBADC1

DCAN1

MIBSPI2

FlexRay

CRC1

ESM

MIBADC1 event group interrupt

MIBADC1 software group 1 interrupt

DCAN1 level 0 interrupt

MIBSPI2 level 0 interrupt

FlexRay level 0 interrupt (CC_int0)

CRC1 Interrupt

ESM low-level interrupt

Software interrupt for Cortex-R5F (SSI)

Cortex-R5F PMU Interrupt

GIO low level interrupt

SYSTEM

CPU

GIO

NHET1

HET TU1

MIBSPI1

LIN1

NHET1 low level interrupt (priority level 2)

HET TU1 level 1 interrupt

MIBSPI1 level 1 interrupt

LIN1 level 1 interrupt

MIBADC1

DCAN1

MIBSPI2

MIBADC1

FlexRay

DMA

MIBADC1 software group 2 interrupt

DCAN1 level 1 interrupt

MIBSPI2 level 1 interrupt

MIBADC1 magnitude compare interrupt

FlexRay level 1 interrupt (CC_int1)

FTCA interrupt

DMA

LFSA interrupt

DCAN2

DMM

DCAN2 level 0 interrupt

DMM level 0 interrupt

MIBSPI3

DMA

MIBSPI3 level 0 interrupt

MIBSPI3 level 1 interrupt

HBCA interrupt

DMA

BTCA interrupt

EMIF

AEMIFINT

DCAN2

DMM

DCAN2 level 1 interrupt

DMM level 1 interrupt

DCAN1

DCAN1 IF3 interrupt

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Table 5-39. Interrupt Request Assignments (continued)

DEFAULT VIM

INTERRUPT CHANNEL

MODULES

VIM INTERRUPT SOURCES

DCAN3

DCAN2

DCAN3 level 0 interrupt

DCAN2 IF3 interrupt

67–72

86–87

FPU

FPU interrupt of Cortex-R5F

FlexRay TU Transfer Status interrupt (TU_Int0)

MIBSPI4 level 0 interrupt

MibADC2 event group interrupt

MibADC2 software group1 interrupt

FlexRay T0C interrupt (CC_tint0)

MIBSPI5 level 0 interrupt

MIBSPI4 level 1 interrupt

DCAN3 level 1 interrupt

MIBSPI5 level 1 interrupt

MibADC2 software group2 interrupt

FlexRay TU Error interrupt (TU_Int1)

MibADC2 magnitude compare interrupt

DCAN3 IF3 interrupt

FlexRay TU

MIBSPI4

MIBADC2

FlexRay

MIBSPI5

MIBSPI4

DCAN3

MIBSPI5

MIBADC2

FlexRay TU

MIBADC2

DCAN3

L2FMC

FSM_DONE interrupt

FlexRay

FlexRay T1C interrupt (CC_tint1)

NHET2 level 0 interrupt

SCI3 level 0 interrupt

NHET2

SCI3

NHET TU2

I2C1

NHET TU2 level 0 interrupt

I2C level 0 interrupt

Reserved

NHET2

Reserved

NHET2 level 1 interrupt

SCI3 level 1 interrupt

SCI3

NHET TU2

Ethernet

NHET TU2 level 1 interrupt

C0_MISC_PULSE

Ethernet

C0_TX_PULSE

Ethernet

C0_THRESH_PULSE

C0_RX_PULSE

Ethernet

HWAG1

HWA_INT_REQ_H

HWAG2

HWA_INT_REQ_H

DCC1

DCC1 done interrupt

DCC2

DCC2 done interrupt

SYSTEM

PBIST

Reserved

PBIST Done

Reserved

HWAG1

Reserved

HWA_INT_REQ_L

HWAG2

HWA_INT_REQ_L

ePWM1INTn

ePWM1TZINTn

ePWM2INTn

ePWM2TZINTn

ePWM3INTn

ePWM3TZINTn

ePWM4INTn

ePWM4TZINTn

ePWM1 Interrupt

ePWM1 Trip Zone Interrupt

ePWM2 Interrupt

ePWM2 Trip Zone Interrupt

ePWM3 Interrupt

ePWM3 Trip Zone Interrupt

ePWM4 Interrupt

ePWM4 Trip Zone Interrupt

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Table 5-39. Interrupt Request Assignments (continued)

DEFAULT VIM

INTERRUPT CHANNEL

MODULES

VIM INTERRUPT SOURCES

ePWM5INTn

ePWM5 Interrupt

ePWM5 Trip Zone Interrupt

ePWM6 Interrupt

ePWM5TZINTn

ePWM6INTn

ePWM6TZINTn

ePWM7INTn

ePWM7TZINTn

eCAP1INTn

eCAP2INTn

eCAP3INTn

eCAP4INTn

eCAP5INTn

eCAP6INTn

eQEP1INTn

eQEP2INTn

Reserved

DCAN4

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125-127

ePWM6 Trip Zone Interrupt

ePWM7 Interrupt

ePWM7 Trip Zone Interrupt

eCAP1 Interrupt

eCAP2 Interrupt

eCAP3 Interrupt

eCAP4 Interrupt

eCAP5 Interrupt

eCAP6 Interrupt

eQEP1 Interrupt

eQEP2 Interrupt

Reserved

DCAN4 Level 0 interrupt

I2C2 interrupt

I2C2

LIN2

LIN2 level 0 interrupt

SCI4 level 0 interrupt

DCAN4 Level 1 interrupt

LIN2 level 1 interrupt

SCI4 level 1 interrupt

DCAN4 IF3 Interrupt

CRC2 Interrupt

SCI4

DCAN4

LIN2

SCI4

DCAN4

CRC2

Reserved

EPC

Reserved

EPC FIFO FULL or CAM FULL interrupt

Reserved

NOTE

Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR

entry; therefore only request channels 0..126 can be used and are offset by one address in

the VIM RAM.

NOTE

The EMIF_nWAIT signal has a pull-up on it. The EMIF module generates a "Wait Rise"

interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt

condition is indicated as soon as the device is powered up. This can be ignored if the

EMIF_nWAIT signal is not used in the application. If the EMIF_nWAIT signal is actually used

in the application, then the external slave memory must always drive the EMIF_nWAIT signal

such that an interrupt is not caused due to the default pull-up on this signal.

NOTE

The lower-order interrupt channels are higher priority channels than the higher-order interrupt

channels.

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NOTE

The application can change the mapping of interrupt sources to the interrupt channels

through the interrupt channel control registers (CHANCTRLx) inside the VIM module.

5.16 ECC Error Event Monitoring and Profiling

This device includes an Error Profiling Controller (EPC) module. The main goal of this module is to enable

the system to tolerate a certain amount of ECC correctable errors on the same address repeatedly in the

memory system with minimal runtime overhead. Main features implemented in this device are described

below.

•

Capture the address of correctable ECC faults from different sources (for example, CPU, L2RAM,

Interconnect) into a 16-entry Content Addressable Memory (CAM).

•

For correctable faults, the error handling depends on the below conditions:

–

if the incoming address is already in the 16-entry CAM, discard the fail. No error generated to ESM

if the address is not in the CAM list, and the CAM has empty entries, add the address into the CAM

list. In addition, raise the error signal to the ESM group 1 if enabled.

–

if the address is not in the CAM list, and the CAM has no empty entries, always raise a signal to the

ESM group 1.

•

A 4-entry FIFO to store correctable error events and addresses for each IP interface.

For uncorrectable faults of non-CPU access, capture the address and raise a signal to the ESM group

•

The CAM is implemented in memory mapped registers. The CPU can read and write to any entry for

diagnostic test as if a real CAM memory macro.

Correctable Error Event Source

CPU0 Correctable Error

FSM

ch0

FIFO

Err Gen

Err Stat

ch2

ch3

ch4

CAM

Lookup

CPU SCR Correctable ECC for DMA I/F

CPU SCR Correctable ECC for PS_SCR_M I/F

L2RAMW RMW Correctable Error

FIFO

Correctable Error Capture Block

ch0

ch1

UERR Addr Reg Err Stat

CPU SCR Uncorrectable ECC for DMA I/F

CPU SCR Uncorrectable ECC for PS_SCR_M I/F

Err Gen

Uncorrectable Error Capture Block

EPC Module

Unorrectable Error Event Source

Figure 5-18. EPC Block Diagram

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5.16.1 EPC Module Operation

5.16.1.1 Correctable Error Handling

When a correctable error is detected in the system by an IP, it sends the error signal along with the error

address to EPC module. The EPC module will scan this error address in the 16-entry CAM. If there is a

match then the address is discard and no error is generated to ESM by the ECP. It takes one cycle to

scan one address at a time through the CAM. The idea is to allow the system to tolerate a correctable

error occurring on the same address because this error has been handled before by the CPU. This error

scenario is particularly frequent when the software is in a for loop fetching the same address. Because

there are multiple IPs which can simultaneously detect correctable errors in the system, the EPC employs

a 4-entry FIFO per IP interface so that error addresses are not lost.

If an address is not matched in the CAM then it depends if there is empty entry in the CAM. If there is an

empty entry then the new address is stored into the empty entry. For each entry there is a 4-bit valid key.

When a new address is stored the 4-bit key is updated with "1010". It is programmable to generate a

correctable error to the ESM if the address is not matched and there is an empty CAM entry. Once CPU is

interrupted, it can choose to evaluate the error address and handle it accordingly. The software can also

invalidate the entry by writing "0101".

If an dress is not matched and there is no empty entry in the CAM then the correctable error is

immediately sent to the ESM. The new error address is lost if there is no empty entry left in the CAM.

5.16.1.2 Uncorrectable Error Handling

Uncorrectable errors reported by the IP (non-CPU access) are immediately captured for their error

addresses and update to the uncorrectable error status register. For more information see the device

specific technical reference guide SPNU563.

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5.17 DMA Controller

The DMA controller is used to transfer data between two locations in the memory map in the background

of CPU operations. Typically, the DMA is used to:

•

Transfer blocks of data between external and internal data memories

Restructure portions of internal data memory

Continually service a peripheral

5.17.1 DMA Features

•

64-bit OCP protocol to perform bus master accesses

INCR-4 64-bit burst accesses

Multithreading architecture allowing data of two different channel transfers to be interleaved during

nonburst accesses

•

2-port configuration for parallel bus master

Channels can be assigned to either high-priority queue or low-priority queue. Within each queue, fixed

or round-robin priorities can be serviced

•

Built-in ECC generation and evaluation logic for internal RAM storing channel transfer information

Supports multiple interrupt outputs for mapping to multiple interrupt controllers in multicore systems

48 requests can be mapped to any 32 channels

Supports LE endianess

External ECC Gen/Eval block of DMA support ECC generation for data transactions, and parity for

address, and control signals (following Cortex-R5F standard)

•

8 MPU regions

Channel chaining capability

Hardware and software DMA requests

8-, 16-, 32-, or 64-bit transactions supported

Multiple addressing modes for source/destination (fixed, increment, offset)

Auto-initiation

5.17.2 DMA Transfer Port Assignment

There are two ports, port A and port B attached to the DMA controller. When configuring a DMA channel

for a transfer, the application must also specify the port associated with the transfer source and

destination. Table 5-40 lists the mapping between each port and the resources. For example, if a transfer

is to be made from the the flash to the SRAM, the application will need configure the desired DMA

channel in the PARx register to select port A as the target for both the source and destination. If a transfer

is to be made from the SRAM to a peripheral or a peripheral memory, the application will need to

configure the desired DMA channel in the PARx register to select port A for read and port B for write.

Likewise, if a transfer is from a peripheral to the SRAM then the PARx will be configured to select port B

for read and port A for write.

Table 5-40. DMA Port Assignment

TARGET NAME

ACCESS PORT OF DMA

Flash

Port A

Port B

SRAM

EMIF

Flash OTP/ECC/EEPROM

All other targets (peripherals, peripheral memories)

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5.17.3 Default DMA Request Map

The DMA module on this microcontroller has 32 channels and up to 48 hardware DMA requests. The

module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By

default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.

Some DMA requests have multiple sources, see Table 5-41. The application must ensure that only one of

these DMA request sources is enabled at any time.

Table 5-41. DMA Request Line Connection

MODULES

DMA REQUEST SOURCES

DMA REQUEST

DMAREQ[0]

DMAREQ[1]

DMAREQ[2]

DMAREQ[3]

DMAREQ[4]

DMAREQ[5]

DMAREQ[6]

DMAREQ[7]

DMAREQ[8]

DMAREQ[9]

DMAREQ[10]

DMAREQ[11]

DMAREQ[12]

DMAREQ[13]

DMAREQ[14]

DMAREQ[15]

DMAREQ[16]

DMAREQ[17]

DMAREQ[18]

DMAREQ[19]

DMAREQ[20]

DMAREQ[21]

DMAREQ[22]

DMAREQ[23]

DMAREQ[24]

DMAREQ[25]

DMAREQ[26]

DMAREQ[27]

DMAREQ[28]

DMAREQ[29]

DMAREQ[30]

DMAREQ[31]

DMAREQ[32]

DMAREQ[33]

DMAREQ[34]

DMAREQ[35]

DMAREQ[36]

DMAREQ[37]

DMAREQ[38]

DMAREQ[39]

DMAREQ[40]

DMAREQ[41]

MIBSPI1

MIBSPI2

MIBSPI1[1]⁽¹⁾

MIBSPI1[0]⁽²⁾

MIBSPI2[1]⁽¹⁾

MIBSPI2[0]⁽²⁾

MIBSPI1 / MIBSPI3 / DCAN2

DCAN1 / MIBSPI5

MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3

MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2

DCAN1 IF2 / MIBSPI5[2]

MIBADC1 / MIBSPI5

MIBADC1 event / MIBSPI5[3]

MIBSPI1 / MIBSPI3 / DCAN1

MIBSPI1 / MIBSPI3 / DCAN2

MIBADC1 / I2C / MIBSPI5

MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1

MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1

MIBADC1 G1 / I2C receive / MIBSPI5[4]

MIBADC1 / I2C / MIBSPI5

MIBADC1 G2 / I2C transmit / MIBSPI5[5]

RTI1 / MIBSPI1 / MIBSPI3

RTI1 DMAREQ0 / MIBSPI1[6] / MIBSPI3[6]

RTI1 DMAREQ1 / MIBSPI1[7] / MIBSPI3[7]

MIBSPI3[1]⁽¹⁾/ MibADC2 event / MIBSPI5[6]

MIBSPI3[0]⁽²⁾/ MIBSPI5[7]

RTI1 / MIBSPI1 / MIBSPI3

MIBSPI3 / MibADC2 / MIBSPI5

MIBSPI3 / MIBSPI5

MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2

MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2

RTI1 / MIBSPI5

MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1

MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2

RTI1 DMAREQ2 / MIBSPI5[8]

RTI1 / MIBSPI5

RTI1 DMAREQ3 / MIBSPI5[9]

NHET1 / NHET2 / DCAN3

NHET1 DMAREQ[4] / NHET2 DMAREQ[4] / DCAN3 IF2

NHET1 DMAREQ[5] / NHET2 DMAREQ[5] / DCAN3 IF3

MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10]

NHET1 / NHET2 / DCAN3

MIBSPI1 / MIBSPI3 / MIBSPI5

NHET1 / NHET2 / MIBSPI4 / MIBSPI5

CRC1 / MIBSPI1 / MIBSPI3

LIN1 / MIBSPI5

MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11]

NHET1 DMAREQ[6] / NHET2 DMAREQ[6] / MIBSPI4[1] ⁽¹⁾/ MIBSPI5[12]

NHET1 DMAREQ[7] / NHET2 DMAREQ[7] / MIBSPI4[0]⁽²⁾/ MIBSPI5[13]

CRC1 DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12]

CRC1 DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13]

LIN1 receive / MIBSPI5[14]

LIN1 / MIBSPI5

LIN1 transmit / MIBSPI5[15]

MIBSPI1 / MIBSPI3 / SCI3 / MIBSPI5

I2C2 / ePWM1 / MIBSPI2 / MIBSPI4 / GIOA

I2C2 / ePWM 1 / MIBSPI2 / MIBSPI4 / GIOA

ePWM2 / MIBSPI2 / MIBSPI4 / GIOA

ePWM3 / MIBSPI2 / MIBSPI4 / GIOA

MIBSPI1[14] / MIBSPI3[14] / SCI3 receive / MIBSPI5[1]⁽¹⁾

MIBSPI1[15] / MIBSPI3[15] / SCI3 transmit / MIBSPI5[0]⁽²⁾

I2C2 receive / ePWM1_SOCA / MIBSPI2[2] / MIBSPI4[2] / GIOA[0]

I2C2 transmit / ePWM1_SOCB / MIBSPI2[3] / MIBSPI4[3] / GIOA[1]

ePWM2_SOCA / MIBSPI2[4] / MIBSPI4[4] / GIOA[2]

ePWM2_SOCB / MIBSPI2[5] / MIBSPI4[5] / GIOA[3]

ePWM3_SOCA / MIBSPI2[6] / MIBSPI4[6] / GIOA[4]

ePWM3_SOCB / MIBSPI2[7] / MIBSPI4[7] / GIOA[5]

CRC2 / ePWM4 / MIBSPI2 / MIBSPI4 / GIOA CRC2 DMAREQ[0] / ePWM4_SOCA / MIBSPI2[8] / MIBSPI4[8] / GIOA[6]

CRC2 / ePWM4 / MIBSPI2 / MIBSPI4 / GIOA CRC2 DMAREQ[1] / ePWM4_SOCB / MIBSPI2[9] / MIBSPI4[9] / GIOA[7]

LIN2 / ePWM5 / MIBSPI2 / MIBSPI4 / GIOB

LIN2 receive / ePWM5_SOCA / MIBSPI2[10] / MIBSPI4[10] / GIOB[0]

LIN2 transmit / ePWM5_SOCB / MIBSPI2[11] / MIBSPI4[11] / GIOB[1]

(1) SPI1, SPI2, SPI3, SPI4, SPI5 receive in compatibility mode

(2) SPI1, SPI2, SPI3, SPI4, SPI5 transmit in compatibility mode

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Table 5-41. DMA Request Line Connection (continued)

MODULES

DMA REQUEST SOURCES

DMA REQUEST

SCI4 / ePWM6 / MIBSPI2 / MIBSPI4 / GIOB

ePWM7 / MIBSPI2 / MIBSPI4 / GIOB

SCI4 receive / ePWM6_SOCA / MIBSPI2[12] / MIBSPI4[12] / GIOB[2]

SCI4 transmit / ePWM6_SOCB / MIBSPI2[13] / MIBSPI4[13] / GIOB[3]

ePWM7_SOCA / MIBSPI2[14] / MIBSPI4[14] / GIOB[4]

DMAREQ[42]

DMAREQ[43]

DMAREQ[44]

ePWM7 / MIBSPI2 / MIBSPI4 / GIOB /

DCAN4

ePWM7_SOCB / MIBSPI2[15] / MIBSPI4[15] / GIOB[5] / DCAN4 IF1

DMAREQ[45]

GIOB / DCAN4

GIOB[6] / DCAN4_IF2

GIOB[7] / DCAN4_IF3

DMAREQ[46]

DMAREQ[47]

124

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5.17.4 Using a GIO terminal as a DMA Request Input

Each GIO terminal can also directly be used as DMA request input as listed in Table 5-41. The polarity of

the GIO terminal to trigger a DMA request can be selected inside the DMA module. To use the GIO

terminal as a DMA request input, the corresponding select bit must be set to low. See Figure 5-19 for an

illustration. For more information see the technical reference guide SPNU563.

I2C2 receive

EPWM1_SOCA

MIBSPI2[2]

MIBSPI4[2]

DMAREQ[32]

DMA

GIOA[0]

PINMMR175[0]

DMAREQ[47]

Figure 5-19. Using a GIO terminal as a DMA Request Input

Table 5-42. GIO DMA Request Disable Mapping

GIO TERMINAL

GIOA[0]

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

GIOB[0]

GIOB[1]

GIOB[2]

GIOB[3]

GIOB[4]

GIOB[5]

GIOB[6]

GIOB[7]

GIO DMA REQUEST SELECT BIT

PINMMR175[0]

PINMMR175[8]

PINMMR175[16]

PINMMR175[24]

PINMMR176[0]

PINMMR176[8]

PINMMR176[16]

PINMMR176[24]

PINMMR177[0]

PINMMR177[8]

PINMMR177[16]

PINMMR177[24]

PINMMR178[0]

PINMMR178[8]

PINMMR178[16]

PINMMR178[24]

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5.18 Real-Time Interrupt Module

The real-time interrupt (RTI) module provides timer functionality for operating systems and for

benchmarking code. The RTI module can incorporate several counters that define the time bases needed

for scheduling an operating system.

The timers also let you benchmark certain areas of code by reading the values of the counters at the

beginning and the end of the desired code range and calculating the difference between the values.

5.18.1 Features

The RTI module has the following features:

•

Two independent 64-bit counter blocks

Four configurable compares for generating operating system ticks or DMA requests. Each event can

be driven by either counter block 0 or counter block 1.

•

Fast enabling/disabling of events

Two timestamp (capture) functions for system or peripheral interrupts, one for each counter block

5.18.2 Block Diagrams

Figure 5-20 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI

module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only

available as time-base inputs for the counter block 0. Figure 5-21 shows the compare unit block diagram

of the RTI module.

Compare

up counter

RTICPUCx

OVLINTx

Up counter

RTIUCx

RTICLK

To Compare

Unit

Free-running counter

RTIFRCx

NTU0

NTU1

NTU2

NTU3

Capture

up counter

RTICAUCx

Capture

free-running counter

RTICAFRCx

CAP event source 0

CAP event source 1

External

control

Figure 5-20. Counter Block Diagram

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Update

compare

RTIUDCPy

DMAREQy

INTy

Compare

RTICOMPy

From counter

block 0

From counter

block 1

Compare

control

Figure 5-21. Compare Block Diagram

5.18.3 Clock Source Options

The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.

The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the

system module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.

For more information on clock sources, see Table 5-11 and Table 5-16.

5.18.4 Network Time Synchronization Inputs

The RTI module supports four Network Time Unit (NTU) inputs that signal internal system events, and

which can be used to synchronize the time base used by the RTI module. On this device, these NTU

inputs are connected as shown in Table 5-43.

Table 5-43. Network Time Synchronization Inputs

NTU INPUT

SOURCE

FlexRay Macrotick

FlexRay Start of Cycle

PLL2 Clock output

EXTCLKIN1 clock input

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5.19 Error Signaling Module

The Error Signaling Module (ESM) manages the various error conditions on the TMS570LCx

microcontroller. The error condition is handled based on a fixed severity level assigned to it. Any severe

error condition can be configured to drive a low level on a dedicated device terminal called nERROR. The

nERROR can be used as an indicator to an external monitor circuit to put the system into a safe state.

5.19.1 ESM Features

The features of the ESM are:

•

160 interrupt/error channels are supported, divided into three groups

–

96 channels with maskable interrupt and configurable error terminal behavior

32 error channels with nonmaskable interrupt and predefined error terminal behavior

32 channels with predefined error terminal behavior only

•

Error terminal to signal severe device failure

Configurable time base for error signal

Error forcing capability

5.19.2 ESM Channel Assignments

The ESM integrates all the device error conditions and groups them in the order of severity. Group1 is

used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device

response to each error is determined by the severity group to which the error is connected. Table 5-45

lists the channel assignment for each group.

Table 5-44. ESM Groups

INFLUENCE ON

ERROR GROUP

INTERRUPT CHARACTERISTICS

ERROR

TERMINAL

Group1

Group2

Group3

Maskable, low or high priority

Nonmaskable, high priority

No interrupt generated

Configurable

Fixed

Table 5-45. ESM Channel Assignments

ESM ERROR SOURCES

Group1

GROUP CHANNELS

Reserved

MibADC2 - parity

Group1

DMA - MPU error for CPU (DMAOCP_MPVINT(0))

DMA - ECC uncorrectable error

EPC - Correctable Error

Reserved

L2FMC - correctable error (implicit OTP read).

NHET1 - parity

HET TU1/HET TU2 - parity

HET TU1/HET TU2 - MPU

PLL1 - slip

LPO Clock Monitor - interrupt

FlexRay RAM - ECC uncorrectable error

Reserved

128

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Table 5-45. ESM Channel Assignments (continued)

ESM ERROR SOURCES

FlexRay TU RAM - ECC uncorrectable error (TU_UCT_err)

VIM RAM - ECC uncorrectable error

FlexRay TU - MPU violation (TU_MPV_err)

MibSPI1 - ECC uncorrectable error

MibSPI3 - ECC uncorrectable error

MibADC1 - parity

GROUP CHANNELS

Group1

DMA - Bus Error

DCAN1 - ECC uncorrectable error

DCAN3 - ECC uncorrectable error

DCAN2 - ECC uncorrectable error

MibSPI5 - ECC uncorrectable error

Reserved

L2RAMW - correctable error

Cortex-R5F CPU - self-test

Reserved

DCC1 - error

CCM-R5F - self-test

Reserved

NHET2 - parity

Reserved

IOMM - Mux configuration error

Power domain compare error

Power domain self-test error

eFuse farm – EFC error

eFuse farm - self-test error

PLL2 - slip

Ethernet Controller master interface

Reserved

Cortex-R5F Core - cache correctable error event

ACP d-cache invalidate

Reserved

MibSPI2 - ECC uncorrectable error

MibSPI4 - ECC uncorrectable error

DCAN4 - ECC uncorrectable error

CPU Interconnect Subsystem - Global error

CPU Interconnect Subsystem - Global Parity Error

NHET1/2 - self-test error

NMPU - EMAC MPU Error

Reserved

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Table 5-45. ESM Channel Assignments (continued)

ESM ERROR SOURCES

NMPU - PS_SCR_S MPU Error

GROUP CHANNELS

Group1

93-95

DCC2 - error

Reserved

NMPU - DMA Port A MPU Error

DMA - Transaction Bus Parity Error

FlexRay TU RAM- ECC single bit error (TU_SBE_err)

FlexRay - ECC single bit error

DCAN1 - ECC single bit error

DCAN2 - ECC single bit error

DCAN3 - ECC single bit error

DCAN4 - ECC single bit error

MIBSPI1 - ECC single bit error

MIBSPI2 - ECC single bit error

MIBSPI3 - ECC single bit error

MIBSPI4 - ECC single bit error

MIBSPI5 - ECC single bit error

DMA - ECC single bit error

VIM - ECC single bit error

EMIF 64-bit Bridge I/F ECC uncorrectable error

EMIF 64-bit Bridge I/F ECC single bit error

Reserved

DMA - Register Soft Error

L2FMC - Register Soft Error

SYS - Register Soft Error

SCM - Time-out Error

CCM-R5F - Operating status

Reserved

Group2

Reserved

Group2

Reserved

CCM-R5F - CPU compare error

Cortex-R5F Core - All fatal bus error events. [Commonly caused by improper

or incomplete ECC values in Flash.]

Group2

Event Reference

0x71

Event Description

Bus ECC

EVNTBUSm bit

Reserved

Group2

L2RAMW - Uncorrectable error type B

Reserved

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Table 5-45. ESM Channel Assignments (continued)

ESM ERROR SOURCES

GROUP CHANNELS

Reserved

Group2

Reserved

L2FMC - parity error

•

Mcmd parity error on Idle command

Group2

POM idle state parity error

Port A/B Idle state parity error

Reserved

Group2

L2FMC - double bit ECC error-error due to implicit OTP reads

Reserved

EPC - Uncorrectable Error

Reserved

RTI_WWD_NMI

CCM-R5F VIM compare error

CPU1 AXIM Bus Monitor failure

Reserved

CCM-R5F - Power Domain monitor error

Reserved

Group3

Reserved

Group3

eFuse Farm - autoload error

Reserved

L2RAMW - double bit ECC uncorrectable error

Reserved

Cortex-R5F Core - All fatal events (OR of:

Event Reference

Event Description

EVNTBUSm Bit

Value

0x60

0x61

Group3

Data Cache

Data Cache tag/dirty

Reserved

Group3

CPU Interconnect Subsystem - Diagnostic Error

L2FMC - uncorrectable error due to:

•

address parity/internal parity error

address tag

Group3

internal switch time-out

L2RAMW - Uncorrectable error Type A

L2RAMW - Address/Control parity error

Group3

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Table 5-45. ESM Channel Assignments (continued)

ESM ERROR SOURCES

GROUP CHANNELS

Reserved

Group3

132

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5.20 Reset / Abort / Error Sources

Table 5-46. Reset/Abort/Error Sources

ESM HOOKUP

GROUP.CHANNE

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

CPU TRANSACTIONS

Precise write error (NCNB/Strongly Ordered)

Precise read error (NCB/Device or Normal)

Imprecise write error (NCB/Device or Normal)

User/Privilege

Precise Abort (CPU)

Imprecise Abort (CPU)

N/A

Undefined Instruction Trap

(CPU)⁽¹⁾

Illegal instruction

User/Privilege

N/A

MPU access violation

Correctable error

User/Privilege

Abort (CPU)

ESM

N/A

1.4

Uncorrectable error

ESM => NMI

2.21

LEVEL 2 SRAM

CPU Write ECC single error (correctable)

User/Privilege

ESM

1.26

3.3

ECC double bit error:

Read-Modify-Write (RMW) ECC double error

CPU Write ECC double error

Bus Error, ESM => nERROR

Uncorrectable error Type A:

Write SECDED malfunction error

Redundant address decode error

Read SECDED malfunction error

User/Privilege

Bus Error, ESM => nERROR

3.14

Uncorrectable error type B:

Memory scrubbing SECDED malfunction error

Memory scrubbing Redundant address decode error

Memory scrubbing address/control parity error

Write data merged mux diagnostic error

Write SECDED malfunction diagnostic error

Read SECDED malfunction diagnostic error

Write ECC correctable and uncorrectable diagnostic error

Read ECC correctable and uncorrectable diagnostic error

Write data merged mux error

User/Privilege

ESM => NMI

2.7

Redundant address decode diagnostic error

Command parity error on idle

Address/Control parity error

User/Privilege

Bus Error, ESM => nERROR

Bus Error

3.15

N/A

Level 2 RAM illegal address error Memory initialization error

FLASH

L2FMC correctable error - single bit ECC error for implicit OTP

read

User/Privilege

ESM

1.6

L2FMC uncorrectable error - double bit ECC error for implicit

OTP read

ESM => NMI

2.19

L2FMC fatal uncorrectable error:

address parity error/internal parity error

address tag error

User/Privilege

Bus Error, ESM => nERROR

ESM => NMI

3.13

2.17

Internal switch time-out

L2FMC parity error:

Mcmd parity error on Idle command

POM idle state parity error

Port A/B Idle state parity error

L2FMC nonfatal uncorrectable error:

Response error on POM

Response parity error on POM

Bank accesses during special operation (program/erase) by the

FSM

User/Privilege

Bus Error

N/A

Bank/Pump in sleep

Unimplemented special/unavailable space

(1) The Undefined Instruction TRAP is not detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of

the CPU.

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Table 5-46. Reset/Abort/Error Sources (continued)

ESM HOOKUP

GROUP.CHANNE

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

L2FMC register soft error.

User/Privilege

ESM

1.89

DMA TRANSACTIONS

Memory access permission violation

Memory ECC uncorrectable error

User/Privilege

ESM

1.2

1.3

Transaction Error:

that is, Bus Parity Error

User/Privilege

ESM

1.70

Memory ECC single bit error

User/Privilege

ESM

1.82

1.88

1.20

DMA register soft error

DMA bus error

EMIF_ECC

64-bit Bridge I/F ECC uncorrectable error

64-bit Bridge I/F ECC single error

HET TU1 (HTU1)

User/Privilege

ESM

1.84

1.85

NCNB (Strongly Ordered) transaction with slave error response

External imprecise error (Illegal transaction with ok response)

Memory access permission violation

Memory parity error

User/Privilege

Interrupt => VIM

ESM

N/A

1.9

1.8

ESM

HET TU2 (HTU2)

NCNB (Strongly Ordered) transaction with slave error response

External imprecise error (Illegal transaction with ok response)

Memory access permission violation

Memory parity error

User/Privilege

Interrupt => VIM

ESM

N/A

1.9

1.8

ESM

N2HET1

Memory parity error

User/Privilege

ESM

1.7

N2HET2

Memory parity error

1.34

MibSPI

MibSPI1 memory ECC uncorrectable error

MibSPI2 memory ECC uncorrectable error

MibSPI3 memory ECC uncorrectable error

MibSPI4 memory ECC uncorrectable error

MibSPI5 memory ECC uncorrectable error

MibSPI1 memory ECC single error

MibSPI2 memory ECC single error

MibSPI3 memory ECC single error

MibSPI4 memory ECC single error

MibSPI5 memory ECC single error

MibADC

User/Privilege

ESM

1.17

1.49

1.18

1.50

1.24

1.77

1.78

1.79

1.80

1.81

MibADC1 Memory parity error

MibADC2 Memory parity error

DCAN

User/Privilege

ESM

1.19

1.1

DCAN1 memory ECC uncorrectable error

DCAN2 memory ECC uncorrectable error

DCAN3 memory ECC uncorrectable error

DCAN4 memory ECC uncorrectable error

DCAN1 memory ECC single error

User/Privilege

ESM

1.21

1.23

1.22

1.51

1.73

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Table 5-46. Reset/Abort/Error Sources (continued)

ESM HOOKUP

GROUP.CHANNE

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

DCAN2 memory ECC single error

DCAN3 memory ECC single error

DCAN4 memory ECC single error

PLL

User/Privilege

ESM

1.74

1.75

1.76

PLL1 slip error

User/Privilege

ESM

1.10

1.42

PLL2 slip error

Clock Monitor

Clock monitor interrupt

DCC

User/Privilege

ESM

1.11

DCC1 error

User/Privilege

ESM

1.30

1.62

DCC2 error

CCM-R5F

Self-test failure

User/Privilege

ESM

1.31

2.2

CPU Bus Compare failure

VIM Bus Compare failure

Power Domain Monitor failure

ESM => NMI

2.25

2.28

CCM-R5F operating status (asserted when not in lockstep or

CCM-R5F is in self-test mode)

User/Privilege

ESM

1.92

EPC (Error Profiling Controller)

Correctable Error

User/Privilege

ESM

1.4

Uncorrectable Error

ESM => NMI

2.21

SCM (SCR Control module)

Time-out Error

User/Privilege

ESM

1.91

FlexRay

Memory ECC uncorrectable error

Memory ECC single error

User/Privilege

ESM

1.12

1.72

FlexRay TU

NCNB (Strongly Ordered) transaction with slave error response

External imprecise error (Illegal transaction with ok response)

Memory access permission violation

Memory ECC uncorrectable error

Memory ECC single bit error

Ethernet master interface

Any error reported by slave being accessed

VIM

User/Privilege

Interrupt => VIM

ESM

N/A

1.16

1.14

1.71

ESM

User/Privilege

ESM

1.43

Memory ECC uncorrectable error

Memory ECC single bit error

Voltage Monitor

User/Privilege

ESM

1.15

1.83

VMON out of voltage range

Self-Test (LBIST)

N/A

Reset

N/A

Cortex-R5F CPU self-test (LBIST) error

NHET Self-test (LBIST) error

IOMM (terminal multiplexing control)

Mux configuration error

User/Privilege

ESM

1.27

1.54

User/Privilege

User

ESM

1.37

N/A

Power Domain Control

Power Domain control access privilege error

Imprecise Abort (CPU)

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Table 5-46. Reset/Abort/Error Sources (continued)

ESM HOOKUP

GROUP.CHANNE

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

PSCON compare error

PSCON self-test error

Efuse farm

User/Privilege

ESM

1.38

1.39

eFuse farm autoload error

eFuse farm error

User/Privilege

ESM

3.1

1.40

1.41

eFuse farm self-test error

WIndowed Watchdog

WWD Nonmaskable Interrupt Exception

Errors Reflected in the SYSESR Register

Power-Up Reset

N/A

ESM

2.24

N/A

Reset

ESM

N/A

1.90

Oscillator fail / PLL slip⁽²⁾

Watchdog exception

N/A

CPUx Reset

N/A

Software Reset

N/A

External Reset

N/A

User/Privilege

CPU Interconnect Subsystem

Diagnostic error

User/Privilege

ESM => Error terminal

3.12

1.52

1.53

Global error

ESM

Global Parity error

NMPU for EMAC

MPU Access violation error

NMPU for PS_SCR_S

MPU Access violation error

NMPU for DMA Port A

MPU Access violation error

PCR1

User/Privilege

ESM

1.55

1.61

1.69

N/A

ESM

MasterID filtering MPU Access violation error

PCR2

Bus Error

MasterID filtering MPU Access violation error

PCR3

MasterID filtering MPU Access violation error

(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.

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5.21 Digital Windowed Watchdog

This device includes a Digital Windowed Watchdog (DWWD) module that protects against runaway code

execution (see Figure 5-22).

The DWWD module allows the application to configure the time window within which the DWWD module

expects the application to service the watchdog. A watchdog violation occurs if the application services the

watchdog outside of this window, or fails to service the watchdog at all. The application can choose to

generate a system reset or a nonmaskable interrupt to the CPU in case of a watchdog violation.

The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog

can only be disabled upon a system reset.

Down

Counter

DWWD Preload

100%

Window Open

Window

Down Counter

50%

Window Open

Window

25%

W Open

Window

RESET

12.5%

Digital

Windowed

Watchdog

Dog

Window

INTERRUPT

ESM

6.25%

WaWtcahtdcohg

Window

3.125%

Window

Figure 5-22. Digital Windowed Watchdog Example

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5.22 Debug Subsystem

5.22.1 Block Diagram

The device contains an ICEPICK module (version C) to allow JTAG access to the scan chains (see

Figure 5-23).

Boundary Scan

Interface

BSR/BSDL

TRST

TMS

TCK

Debug APB

RTCK

DAP

TDI

TDO

Debug Tap 0

APB Mux

AHB-AP

R5F

CPU

R5F

ETM

Debug

ROM

POM

PS_SCR

OCP2_

BVUSP

VBUSP2

APBv3

CTI1

CTI3

CTI4

PCR3

RTP

CTM1

CTM2

Debug Tap 1

DMM

CSTF

TPIU

Debug Tap 2

Test Tap 0

AJSM

eFuse Farm

PSCON

Test Tap 1

Figure 5-23. Debug Subsystem Block Diagram

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5.22.2 Debug Components Memory Map

Table 5-47. Debug Components Memory Map

FRAME ADDRESS RANGE

RESPONSE FOR ACCESS

TO UNIMPLEMENTED LOCATIONS

IN FRAME

MODULE

NAME

FRAME CHIP

SELECT

FRAME

SIZE

ACTUAL

SIZE

START

END

CoreSight Debug ROM

CSCS0

CSCS1

CSCS2

CSCS3

CSCS4

CSCS7

CSCS9

CSCS10

CSCS11

0xFFA0_0000

0xFFA0_1000

0xFFA0_2000

0xFFA0_3000

0xFFA0_4000

0xFFA0_7000

0xFFA0_9000

0xFFA0_A000

0xFFA0_B000

0xFFA0_0FFF

0xFFA0_1FFF

0xFFA0_2FFF

0xFFA0_3FFF

0xFFA0_4FFF

0xFFA0_7FFF

0xFFA0_9FFF

0xFFA0_AFFF

0xFFA0_BFFF

4KB

Reads return zeros, writes have no effect

Cortex-R5F Debug

ETM-R5

CoreSight TPIU

POM

CTI1

CTI3

CTI4

CSTF

5.22.3 Embedded Cross Trigger

The Embedded Cross Trigger (ECT) is a modular component that supports the interaction and

synchronization of multiple triggering events within a SoC.

The ECT consists of two modules:

•

A (Cross Trigger Interface) CTI. The CTI provides the interface between a component or subsystem

and the Cross Trigger Matrix (CTM).

•

A CTM. The CTM combines the trigger requests generated from CTIs and broadcasts them to all CTIs

as channel triggers. This enables subsystems to interact, cross trigger, with one another.

CTI3

ch0

ch2

tieoff

ch0 ch2

CTM1

CTI1

CTM2

Reserved

ch1 ch3

ch1

ch3

CTI4

Figure 5-24. CTI/CTM Integration

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CTI1

CTITRIGIN[3:2]

ETM-R5

EXTOUT[1:0]

TRIGSBYPASS

TRIGGER

CTITRIGIN[6]

TRIGGERACK

EXTIN[1:0]

CTITRIGINACK[6]

TIHSBYPASS[2:1]

CTITRIGOUT[2:1]

CTITRIGOUTACK[2:1]

ETMDBGRQ

CTITRIGIN[7]

R5F

TIHSBYPASS[0]

CTITRIOUT[0]

EDBGRQ

DBTRIGGER

DBGRESTART

DBGRESTARTED

COMMRX

CTITRIGOUTACK[0]

CTITRIGIN[0]

CTITRIGINACK[0]

CTITRIGOUT[7]

TIHSBYPASS[7]

GCLK1

CTITRIGOUTACK[7]

CTITRIGIN[4]

CTITRIGIN[5]

COMMTX

nPMUIRQ

nIRQ

CTITRIGIN[1]

TIHSBYPASS[3]

CTITRIGOUT]3]

CTITRIGOUTACK[3]

nIRQ from VIM

Figure 5-25. CTI1 Mapping

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NOTE

ETM-R5, Cortex-R5F and CTI1 run at same frequency.

Table 5-48. CTI1 Mapping

CTI TRIGGER

Trigger Input 0

Trigger Input 1

Trigger Input 2

Trigger Input 3

Trigger Input 4

Trigger Input 5

Trigger Input 6

Trigger Input 7

Trigger Output 0

Trigger Output 1

Trigger Output 2

Trigger Output 3

Trigger Output 4

Trigger Output 5

Trigger Output 6

Trigger Output 7

Module Signal

From Cortex-R5F DBTRIGGER

From Cortex-R5F nPMUIRQ

From ETM-R5 EXTOUT[0]

From ETM-R5 EXTOUT[1]

From Cortex-R5F COMMRX

From Cortex-R5F COMMTX

From ETM-R5 TRIGGER

From Cortex-R5F DBTRIGGER

To Cortex-R5F EDBGRQ

To ETM-R5 EXTIN[0]

To ETM-R5 EXTIN[1]

To Cortex-R5F nIRQ

Reserved

To Cortex-R5F DBGRESTARTED

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CTI3

TPIU

FLUSHIN

CTITRIGOUT[1]

CTITRIGOUT[0]

TRIGIN

FLUSHINACK

TRIGINACK

CTITRIGOUTACK[1]

CTITRIGOUTACK[0]

TIHSBYPASS[7:2]

CTITRIGOUTACK[7:2]

Figure 5-26. CTI3 Mapping

NOTE

TPIU and CTI3 run at different frequencies.

Table 5-49. CTI3 Mapping

CTI TRIGGER

Trigger Input 0

Trigger Input 1

Trigger Input 2

Trigger Input 3

Trigger Input 4

Trigger Input 5

Trigger Input 6

Trigger Input 7

Trigger Output 0

Trigger Output 1

Trigger Output 2

Trigger Output 3

Trigger Output 4

Trigger Output 5

Trigger Output 6

Trigger Output 7

Module Signal

Reserved

To TPIU TRIGIN

To TPIU FLUSHIN

Reserved

142

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CTI4

CTITRIGIN[0]

CTITRIGINACK[0]

DMA_DBGREQ

Pulse Creator

Sync_Output

NHET1_DBGREQ

CTITRIGIN[1]

CTITRIGINACK[1]

CTITRIGIN[2]

CTITRIGINACK[2]

NHET2_DBGREQ

HTU1_DBGREQ

CTITRIGIN[3]

CTITRIGINACK[3]

HTU2_DBGREQ

CTITRIGIN[4]

CTITRIGINACK[4]

Pulse Creator

Sync_Output

CTITRIGIN[5]

CTITRIGIN[6]

CTITRIGIN[7]

CTITRIGOUT[0]

CTITRIGOUTACK[0]

SYS_MODULE_TRIGGER

Sync_Input

USER_PERIPHERAL_TRIGGER1

USER_PERIPHERAL_TRIGGER2

CTITRIGOUT[1]

CTITRIGOUTACK[1]

CTITRIGOUT[2]

CTITRIGOUTACK[2]

CTITRIGOUT[3]

USER_PERIPHERAL_TRIGGER3

IcePick Debug_Attention

Sync_Input

CTITRIGOUTACK[3]

CTITRIGOUT[4]

CTITRIGOUTACK[4]

CTITRIGOUTACK[7:4]

Figure 5-27. CTI4 Mapping

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Table 5-50. CTI4 Mapping

CTI TRIGGER

Trigger Input 0

Trigger Input 1

Trigger Input 2

Trigger Input 3

Trigger Input 4

Trigger Input 5

Trigger Input 6

Trigger Input 7

Trigger Output 0

Trigger Output 1

Trigger Output 2

Trigger Output 3

Trigger Output 4

Trigger Output 5

Trigger Output 6

Trigger Output 7

Module Signal

From DMA_DBGREQ

From N2HET1_DBGREQ

From N2HET2_DBGREQ

From HTU1_DBGREQ

From HTU2_DBGREQ

From DMA_DBGREQ

From N2HET1_DBGREQ or HTU1_DBGREQ

From N2HET2_DBGREQ or HTU2_DBGREQ

To SYS_MODULE_TRIGGER

To USER_PERIPHERAL_TRIGGER1

To USER_PERIPHERAL_TRIGGER2

To USER_PERIPHERAL_TRIGGER3

To IcePick Debug_Attention

Reserved

Table 5-51. Peripheral Suspend Generation

TRIGGER OUTPUT

SYS_MODULE_TRIGGER

MODULE SIGNAL CONNECTED

DESCRIPTION

L2FMC Wrapper Suspend

L2FMC_CPU_EMUSUSP

CCM_R5_CPU_EMUSUSP

CRC_CPU_EMUSUSP

SYS_CPU_EMUSUSP

DMA_SUSPEND

CCM_R5 module suspend

CRC1 / CRC2 module suspend

SYS module Suspend

DMA Suspend

USER_PERIPHERAL_TRIGGER1

RTI_CPU_SUSPEND

AWM_CPU_SUSPEND

HTU_CPU_EMUSUSP

SCI_CPU_EMUSUSP

LIN_CPU_EMUSUSP

I2C_CPU_EMUSUSP

EMAC_CPU_EMUSUSP

EQEP_CPU_EMUSUSP

ECAP_CPU_EMUSUSP

DMM_CPU_EMUSUSP

DCC_CPU_EMUSUSP

RTI1 / RTI2 Suspend

AWM1 / AWM2 Suspend

HTU1 / HTU2 Suspend

SCI3 / SCI4 Suspend

LIN1 / LIN2 Suspend

I2C1 / I2C2 Suspend

EMAC Suspend

EQEP Suspend

ECAP Suspend

DMM Suspend

DCC1 / DCC2 Suspend

DCAN1 / DCAN2 / DCAN3 / DCAN4

Suspend

USER_PERIPHERAL_TRIGGER2

USER_PERIPHERAL_TRIGGER3

DCAN_CPU_EMUSUSP

ePWM_CPU_EMUSUSP

ePWM1..7 Trip Zone TZ6n and ePWM1..7

Suspend

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5.22.4 JTAG Identification Code

The JTAG ID code for this device is the same as the device ICEPick Identification Code. For the JTAG ID

Code per silicon revision, see Table 5-52.

Table 5-52. JTAG ID Code

SILICON REVISION

Rev A

0x0B95A02F

0x1B95A02F

Rev B

5.22.5 Debug ROM

The Debug ROM stores the location of the components on the Debug APB bus (see Table 5-53).

Table 5-53. Debug ROM Table

ADDRESS

0x000

0x004

0x008

0x00C

0x018

0x020

0x024

0x028

0x02C

DESCRIPTION

Cortex-R5F

ETM-R5

TPIU

VALUE

0x00001003

0x00002003

0x00003003

0x00004003

0x00007003

0x00009003

0x0000A003

0x0000B003

0x00000000

POM

CTI1

CTI3

CTI4

CSTF

end of table

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5.22.6 JTAG Scan Interface Timings

Table 5-54. JTAG Scan Interface Timing⁽¹⁾

NO.

PARAMETER

MIN

MAX

UNIT

MHz

fTCK

TCK frequency (at HCLKmax)

fRTCK

RTCK frequency (at TCKmax and HCLKmax)

Delay time, TCK to RTCK

td(TCK -RTCK)

tsu(TDI/TMS - RTCKr)

th(RTCKr -TDI/TMS)

th(RTCKr -TDO)

td(TCKf -TDO)

Setup time, TDI, TMS before RTCK rise (RTCKr)

Hold time, TDI, TMS after RTCKr

Hold time, TDO after RTCKf

Delay time, TDO valid after RTCK fall (RTCKf)

(1) Timings for TDO are specified for a maximum of 50-pF load on TDO.

TCK

RTCK

TMS

TDI

TDO

Figure 5-28. JTAG Timing

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5.22.7 Advanced JTAG Security Module

This device includes an Advanced JTAG Security Module (AJSM), which lets the user limit JTAG access

to the device after programming.

Flash Module Output

OTP Contents

(example)

. . .

Unlock By Scan

Internal Tie-Offs

(example only)

UNLOCK

128-Bit Comparator

Internal Tie-Offs

(example only)

Figure 5-29. AJSM Unlock

The device is unlocked by default by virtue of a 128-bit visible unlock code programmed in the One-Time

Programmable (OTP) address 0xF000 0000.The OTP contents are XOR-ed with the contents of the

Unlock-By-Scan register. The outputs of these XOR gates are again combined with a set of secret internal

tie-offs. The output of this combinational logic is compared against a secret, hard-wired, 128-bit value. A

match asserts the UNLOCK signal, so that the device is now unlocked.

A user can lock the device by changing bits in the visible unlock code from 1 to 0. Changing a 0 to 1 is not

possible because the visible unlock code is stored in the OTP flash region. Also, changing all the 128 bits

to zeros is not a valid condition and will permanently lock the device.

Once locked, a user can unlock the device by scanning an appropriate value into the Unlock-By-Scan

AJSM TAP. The value to be scanned is such that the XOR of the OTP contents and the contents of the

Unlock-By-Scan register results in the original visible unlock code.

The Unlock-By-Scan register is reset only by asserting power-on reset (nPORRST).

A locked device only permits JTAG accesses to the AJSM scan chain through the Secondary TAP 2 of the

ICEPick module. All other secondary TAPs, test TAPs and the boundary scan interface are not accessible

in this state.

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5.22.8 Embedded Trace Macrocell (ETM-R5)

The device contains a ETM-R5 module with a 32-bit internal data port. The ETM-R5 module is connected

to a Trace Port Interface Unit (TPIU) with a 32-bit data bus. The TPIU provides a 35-bit (32-bit data, 3-bit

control) external interface for trace. The ETM-R5 is CoreSight compliant and follows the ETM v3

specification. For more details, see the ARM CoreSight ETM-R5 TRM specification.

5.22.8.1 ETM TRACECLKIN Selection

The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN terminal. The

selection is chosen by the EXTCTLOUT[1:0] control bits of the TPIU (default is '00'). The address of this

Before the user begins accessing TPIU registers, the TPIU should be unlocked through the CoreSight key

and 1 or 2 written to this register.

Table 5-55. TPIU / TRACECLKIN Selection

EXTCTLOUT[1:0]

TPIU/TRACECLKIN

Tied-zero

VCLK

ETMTRACECLKIN

Tied-zero

5.22.8.2 Timing Specifications

t_l(ETM)

t_h(ETM)

t_r(ETM)

t_f(ETM)

t_cyc(ETM)

Figure 5-30. ETMTRACECLKOUT Timing

Table 5-56. ETMTRACECLK Timing

PARAMETER

MIN

18.18

MAX

UNIT

t_cyc(ETM)

t_l(ETM)

Clock period

Low pulse width

High pulse width

t_h(ETM)

t_r(ETM)

t_f(ETM)

Clock and data rise time

Clock and data fall time

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ETMTRACECLK

ETMDATA

t_su(ETM)

t_h(ETM)

Figure 5-31. ETMDATA Timing

Table 5-57. ETMDATA Timing

PARAMETER

MIN

2.5

MAX

UNIT

t_su(ETM)

t_h(ETM)

Data setup time

Data hold time

1.5

NOTE

The ETMTRACECLK and ETMDATA timing is based on a 15-pF load and for ambient

temperatures lower than 85°C.

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5.22.9 RAM Trace Port (RTP)

The RTP provides the ability to datalog the RAM contents of the TMS570 devices or accesses to

peripherals without program intrusion. It can trace all data write or read accesses to internal RAM. In

addition, it provides the capability to directly transfer data to a FIFO to support a CPU-controlled

transmission of the data. The trace data is transmitted over a dedicated external interface.

5.22.9.1 RTP Features

The RTP offers the following features:

•

Two modes of operation - Trace Mode and Direct Data Mode

–

Trace Mode

•

Nonintrusive data trace on write or read operation

Visibility of RAM content at any time on external capture hardware

Trace of peripheral accesses

2 configurable trace regions for each RAM module to limit amount of data to be traced

FIFO to store data and address of data of multiple read/write operations

Trace of CPU and/or DMA accesses with indication of the master in the transmitted data packet

–

Direct Data Mode

•

Directly write data with the CPU or trace read operations to a FIFO, without transmitting header

and address information

•

Dedicated synchronous interface to transmit data to external devices

Free-running clock generation or clock stop mode between transmissions

Up to 100 Mbps terminal transfer rate for transmitting data

Pins not used in functional mode can be used as GIOs

5.22.9.2 Timing Specifications

t_l(RTP)

t_h(RTP)

t_f

t_r

t_cyc(RTP)

Figure 5-32. RTPCLK Timing

Table 5-58. RTPCLK Timing

PARAMETER

Clock period

MIN

9.09 (= 110 MHz)

MIN

UNIT

t_cyc(RTP)

t_h(RTP)

t_l(RTP)

High pulse width

Low pulse width

((t_cyc(RTP))/2) - ((t_r+t_f)/2)

150

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t_ssu(RTP)

t_sh(RTP)

RTPSYNC

RTPCLK

RTPDATA

t_dsu(RTP)

t_dh(RTP)

Figure 5-33. RTPDATA Timing

Table 5-59. RTPDATA Timing

PARAMETER

MIN

MAX

UNIT

t_dsu(RTP)

t_dh(RTP)

t_ssu(RTP)

t_sh(RTP)

Data setup time

Data hold time

SYNC setup time

SYNC hold time

t_ena(RTP)

t_dis(RTP)

10 11

12 13

15 16

HCLK

RTPCLK

RTPnENA

RTPENA

RTPSYNC

RTPDATA

Divide by 1

Figure 5-34. RTPnENA timing

Table 5-60. RTPnENA timing

PARAMETER

MIN

3t_c(HCLK)+ t_r(RTPSYNC)

+ 12

MAX

UNIT

t_dis(RTP)

Disable time, time RTPnENA must go high before what

would be the next RTPSYNC, to ensure delaying the next

packet

t_ena(RTP)

Enable time, time after RTPnENA goes low before a

packet that has been halted, resumes

4t_c(HCLK)+ t_r(RTPSYNC)5t_c(HCLK)+ t_r(RTPSYNC)

+ 12

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5.22.10 Data Modification Module (DMM)

The Data Modification Module (DMM) provides the capability to modify data in the entire 4GB address

space of the TMS570devices from an external peripheral, with minimal interruption of the application.

5.22.10.1 DMM Features

The DMM module has the following features:

•

Acts as a bus master, enabling direct writes to the 4GB address space without CPU intervention

Writes to memory locations specified in the received packet (leverages packets defined by trace mode

of the RAM Trace Port (RTP) module

•

Writes received data to consecutive addresses, which are specified by the DMM module (leverages

packets defined by direct data mode of the RTP module)

•

Configurable port width (1-, 2-, 4-, 8-, 16-pins)

Up to 100 Mbps terminal data rate

Unused pins configurable as GIO pins

5.22.10.2 Timing Specifications

Table 5-61. DMMCLK Timing (see Figure 5-35)

PARAMETER

MIN

9.09

MAX

UNIT

t_cyc(DMM)

t_h(DMM)

t_l(DMM)

Cycle time, DMMCLK clock period

High-pulse width

((t_cyc(DMM))/2) - ((t_r+t_f)/2)

Low-pulse width

t_l(DMM)

t_h(DMM)

t_f

t_r

t_cyc(DMM)

Figure 5-35. DMMCLK Timing

Table 5-62. DMMDATA Timing (see Figure 5-36)

PARAMETER

MIN

MAX

UNIT

t_ssu(DMM)

t_sh(DMM)

t_dsu(DMM)

t_dh(DMM)

Setup time, SYNC active before clk falling edge

Hold time, clk falling edge after SYNC deactive

Setup time, DATA before clk falling edge

Hold time, clk falling edge after DATA hold time

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t_ssu(DMM)

t_sh(DMM)

DMMSYNC

DMMCLK

DMMDATA

t_dsu(DMM)

t_dh(DMM)

Figure 5-36. DMMDATA Timing

Figure 5-37 shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data

width = 8, portwidth = 4) where none of the packets received by the DMM are sent out, leading to filling up

of the internal buffers. The DMMnENA signal is shown asserted, after the first two packets have been

received and synchronized to the HCLK domain. Here, the DMM has the capacity to accept packets D4x,

D5x, D6x, D7x. Packet D8 would result in an overflow. Once DMMnENA is asserted, the DMM expects to

stop receiving packets after 4 HCLK cycles; once DMMnENA is deasserted, the DMM can handle packets

immediately (after 0 HCLK cycles).

HCLK

DMMCLK

DMMSYNC

D00

D01

D10

D11

D20

D21

D30

D31

D40

D41

D50

DMMDATA

DMMnENA

Figure 5-37. DMMnENA Timing

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5.22.11 Boundary Scan Chain

The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary

scan chain is connected to the Boundary Scan Interface of the ICEPICK module (see Figure 5-38).

Device Pins (conceptual)

TRST

TMS

TCK

TDI

Boundary

Scan

Boundary Scan Interface

TDO

RTCK

TDI

TDO

BSDL

Figure 5-38. Boundary Scan Implementation (Conceptual Diagram)

Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO.

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6 Peripheral Information and Electrical Specifications

6.1 Enhanced Translator PWM Modules (ePWM)

Figure 6-1 shows the connections between the seven ePWM modules (ePWM1–ePWM7) on the device.

NHET1_LOOP_SYNC

EPWMSYNCI

EPWM1A

SYNCI

EPWM1TZINTn

EPWM1INTn

VIM

EPWM1B

see Note A

TZ1/2/3n

Mux

Selector

SOCA1, SOCB1

ADC Wrapper

ePWM1

VBus32

EQEP1ERR / EQEP2ERR /

EQEP1ERR or EQEP2ERR

OSC FAIL or PLL Slip

EQEP1 + EQEP2

System Module

CPU

TZ4n

VCLK3, SYS_nRST

EPWM1ENCLK

TBCLKSYNC

TZ5n

TZ6n

Debug Mode Entry

SYNCO

EPWM2/3/4/5/6A

EPWM2/3/4/5/6TZINTn

EPWM2/3/4/5/6INTn

VIM

EPWM2/3/4/5/6B

TZ1/2/3n

see Note A

VBus32

ADC Wrapper

Mux

Selector

SOCA2/3/4/5/6

SOCB2/3/4/5/6

ePWM

2/3/4/5/6

EQEP1ERR / EQEP2ERR /

EQEP1ERR or EQEP2ERR

OSC FAIL or PLL Slip

EQEP1 + EQEP2

System Module

CPU

TZ4n

VCLK3, SYS_nRST

EPWM2/3/4/5/6ENCLK

TBCLKSYNC

TZ5n

TZ6n

Debug Mode Entry

EPWM7A

EPWM7TZINTn

EPWM7INTn

VIM

EPWM7B

see Note A

TZ1/2/3n

Mux

Selector

SOCA7, SOCB7

ADC Wrapper

ePWM7

VBus32

EQEP1ERR / EQEP2ERR /

EQEP1ERR or EQEP2ERR

OSC FAIL or PLL SLip

EQEP1 + EQEP2

System Module

CPU

TZ4n

TZ5n

TZ6n

VCLK3, SYS_nRST

EPWM7ENCLK

TBCLKSYNC

Debug Mode Entry

Pulse

Stretch,

8 VCLK3

cycles

EPWM1SYNCO

(after stretch)

EPWM1SYNCO (before stretch)

VBus32 / VBus32DP

ECAP1

eCAP1

ECAP1INTn

VIM

A. For more detail on the ePWMx input synchronization selection, see Figure 6-2.

Figure 6-1. ePWMx Module Interconnections

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Figure 6-2 shows the detailed input synchronization selection (asynchronous, double-synchronous, or

double synchronous + filter width) for ePWMx.

TZxn

(x = 1, 2, or 3)

double

sync

ePWMx

(x = 1 through 7)

6 VCLK3

Cycles Filter

Figure 6-2. ePWMx Input Synchronization Selection Detail

6.1.1 ePWM Clocking and Reset

Each ePWM module has a clock enable (ePWMxENCLK) which is controlled by its respective Peripheral

Power Down bit in the PSPWRDWNCLRx register of the PCR2 module. To properly reset the peripherals,

the peripherals must be released from reset by setting the PENA bit of the CLKCNTL register in the

system module. In additional, the peripherals must be released from their power down state by clearing

their respective bit in the PSPWRDWNCLRx register. By default after reset, the peripherals are in

powerdown state.

Table 6-1. ePWMx Clock Enable Control

CONTROL REGISTER TO

ePWM MODULE INSTANCE

DEFAULT VALUE

ENABLE CLOCK

ePWM1

ePWM2

ePWM3

ePWM4

ePWM5

ePWM6

ePWM7

PSPWRDWNCLR3[16]

PSPWRDWNCLR3[17]

PSPWRDWNCLR3[18]

PSPWRDWNCLR3[19]

PSPWRDWNCLR3[12]

PSPWRDWNCLR3[13]

PSPWRDWNCLR3[14]

6.1.2 Synchronization of ePWMx Time-Base Counters

A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM

module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The

input synchronization for the first instance (ePWM1) comes from an external pin. Figure 6-1 shows the

synchronization connections for all the ePWMx modules. Each ePWM module can be configured to use or

ignore the synchronization input. For more information, see the ePWM module chapter of the device-

specific TRM.

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6.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base

The connection between the NHET1_LOOP_SYNC and the SYNCI input of ePWM1 module is

implemented as shown in Figure 6-3.

N2HET1_LOOP_SYNC

EXT_LOOP_SYNC

N2HET1

N2HET2

PINMMR165[24]=0 and PINMMR165[25]=1

2 VCLK3 cycles

Pulse Stretch

SYNCI

ePWM1

EPWM1SYNCI

double

sync

6 VCLK3

Cycles Filter

Figure 6-3. Synchronizing Time Bases Between N2HET1, N2HET2 and ePWMx Modules

6.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules

The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM

modules on a device. This bit is implemented as PINMMR166[1] register bit 1.

When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped. This is the default

condition.

When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned.

For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must

be set identically. The proper procedure for enabling the ePWM clocks is as follows:

•

Each ePWM is individually associated with a power down bit in the PSPWRDWNCLRx register of the

PCR2 module. Enable the individual ePWM module clocks (if disable) using the control registers in the

PCR2.

•

Configure TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.

Configure the prescaler values and desired ePWM modes.

Configure TBCLKSYNC = 1.

6.1.5 ePWM Synchronization with External Devices

The output sync from the ePWM1 module is also exported to the I/O Mux such that multiple devices can

be synchronized together. The signal pulse must be stretched by 8 VCLK3 cycles before being exported

on the IO Mux pin as the ePWMSYNCO signal.

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6.1.6 ePWM Trip Zones

The ePWMx modules have 6 trip zone inputs each. These are active-low signals. The application can

control the ePWMx module response to each of the trip zone input separately. The timing requirements

from the assertion of the trip zone inputs to the actual response are specified in the electrical and timing

section of this document.

6.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n

These 3 trip zone inputs are driven by external circuits and are connected to device-level inputs. These

signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with

VCLK3, or double-synchronized and then filtered with a 6-cycle VCLK3-based counter before connecting

to the ePWMx (see Figure 6-2). By default, the trip zone inputs are asynchronously connected to the

ePWMx modules.

Table 6-2. Connection to ePWMx Modules for Device-Level Trip Zone Inputs

CONTROL FOR

ASYNCHRONOUS

CONNECTION TO ePWMx

CONTROL FOR

DOUBLE-SYNCHRONIZED

CONNECTION TO ePWMx

CONTROL FOR

TRIP ZONE

INPUT

DOUBLE-SYNCHRONIZED AND

FILTERED CONNECTION TO ePWMx⁽¹⁾

TZ1n

TZ2n

TZ3n

PINMMR172[18:16] = 001

PINMMR172[26:24] = 001

PINMMR173[2:0] = 001

PINMMR172[18:16] = 010

PINMMR172[18:16] = 100

PINMMR172[26:24] = 100

PINMMR173[2:0] = 100

PINMMR172[26:24] = 010

PINMMR173[2:0] = 010

(1) The filter width is 6 VCLK3 cycles.

6.1.6.2 Trip Zone TZ4n

This trip zone input is dedicated to eQEPx error indications. There are 2 eQEP modules on this device.

Each eQEP module indicates a phase error by driving its EQEPxERR output high. The following control

registers allow the application to configure the trip zone input (TZ4n) to each ePWMx module based on

the requirements of the applicationapplication's requirements.

Table 6-3. TZ4n Connections for ePWMx Modules

CONTROL FOR TZ4n =

NOT(EQEP1ERR OR EQEP2ERR)

CONTROL FOR TZ4n =

NOT(EQEP1ERR)

CONTROL FOR TZ4n =

NOT(EQEP2ERR)

ePWMx

ePWM1

ePWM2

ePWM3

ePWM4

ePWM5

ePWM6

ePWM7

PINMMR167[2:0] = 001

PINMMR167[10:8] = 001

PINMMR167[18:16] = 001

PINMMR167[26:24] = 001

PINMMR168[2:0] = 001

PINMMR168[10:8] = 001

PINMMR168[18:16] = 001

PINMMR167[2:0] = 010

PINMMR167[2:0] = 100

PINMMR167[10:8] = 010

PINMMR167[18:16] = 010

PINMMR167[26:24] = 010

PINMMR168[2:0] = 010

PINMMR168[10:8] = 010

PINMMR168[18:16] = 010

PINMMR167[10:8] = 100

PINMMR167[18:16] = 100

PINMMR167[26:24] = 100

PINMMR168[2:0] = 100

PINMMR168[10:8] = 100

PINMMR168[18:16] = 100

NOTE

The EQEPxERR signal is an active high signal coming out of EQEPx module. As listed in

Table 6-3, the selected combination of the EQEPxERR signals must be inverted before

connecting to the TZ4n input of the ePWMx modules.

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6.1.6.3 Trip Zone TZ5n

This trip zone input is dedicated to a clock failure on the device. That is, this trip zone input is asserted

whenever an oscillator failure or a PLL slip is detected on the device. The applciation can use this trip

zone input for each ePWMx module to prevent the external system from going out of control when the

device clocks are not within expected range (system running at limp clock).

The oscillator failure and PLL slip signals used for this trip zone input are taken from the status flags in the

system module. These level signals are set until cleared by the application.

6.1.6.4 Trip Zone TZ6n

This trip zone input to the ePWMx modules is dedicated to a debug mode entry of the CPU. If enabled,

the user can force the PWM outputs to a known state when the emulator stops the CPU. This prevents the

external system from going out of control when the CPU is stopped.

NOTE

There is a signal called DBGACK that the CPU drives when it enters debug mode. This

signal must be inverted and used as the Debug Mode Entry signal for the trip zone input.

6.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs

A special scheme is implemented to select the actual signal used for triggering the start of conversion on

the two ADCs on this device. This scheme is defined in Section 6.4.2.3.

6.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Electrical Data/Timing

Table 6-4. ePWMx Timing Requirements

TEST CONDITIONS

Asynchronous

MIN

2 t_c(VCLK3)

MAX UNIT

cycles

t_w(SYNCIN)

Synchronization input pulse width

Synchronous

2 t_c(VCLK3)

cycles

Synchronous with input filter

2 t_c(VCLK3)+ filter width⁽¹⁾

cycles

(1) The filter width is 6 VCLK3 cycles.

Table 6-5. ePWMx Switching Characteristics

TEST

CONDITIONS

PARAMETER

Pulse duration, ePWMx output high or low

MIN

MAX

UNIT

t_w(PWM)

33.33

t_w(SYNCOUT)

Synchronization Output Pulse Width

8 t_c(VCLK3)

cycles

Delay time, trip input active to PWM forced high, OR

Delay time, trip input active to PWM forced low

t_d(PWM)tza

No pin load

t_d(TZ-PWM)HZ

Delay time, trip input active to PWM Hi-Z

Table 6-6. ePWMx Trip-Zone Timing Requirements

TEST CONDITIONS

MIN

MAX UNIT

Asynchronous

2 * TBePWMx

2 t_c(VCLK3)

t_w(TZ)

Pulse duration, TZn input low

Synchronous

cycles

Synchronous with input filter

2 t_c(VCLK3)+ filter width⁽¹⁾

(1) The filter width is 6 VCLK3 cycles.

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6.2 Enhanced Capture Modules (eCAP)

Figure 6-4 shows how the eCAP modules are interconnected on this microcontroller.

EPWM1SYNCO

ECAP1SYNCI

ECAP1

see Note A

ECAP1INTn

eCAP1

VIM

VBus32

VCLK3, SYS_nRST

ECAP1ENCLK

ECAP1SYNCO

ECAP2SYNCI

ECAP2

see Note A

eCAP

ECAP2INTn

VIM

2/3/4/5

VBus32

VCLK3, SYS_nRST

ECAP2ENCLK

ECAP2SYNCO

ECAP6SYNCI

ECAP6

see Note A

eCAP

VBus32

VIM

ECAP6INTn

VCLK3, SYS_nRST

ECAP6ENCLK

ECAP6SYNCO

A. For more detail on the eCAPx input synchronization selection, see Figure 6-5.

Figure 6-4. eCAP Module Connections

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Figure 6-5 shows the detailed input synchronization selection (asynchronous, double-synchronous, or

double synchronous + filter width) for eCAPx.

ECAPx

(x = 1, 2, 3, 4, 5, or 6)

double

sync

eCAPx

6 VCLK3

Cycles Filter

(x = 1 through 6)

Figure 6-5. eCAPx Input Synchronization Selection Detail

6.2.1 Clock Enable Control for eCAPx Modules

Each of the eCAPx modules has a clock enable (ECAPxENCLK) which is controlled by its respective

Peripheral Power Down bit in the PSPWRDWNCLRx register of the PCR2 module. To properly reset the

peripherals, the peripherals must be released from reset by setting the PENA bit of the CLKCNTL register

in the system module. In addition, the peripherals must be released from their power down state by

clearing the respective bit in the PSPWRDWNCLRx register. By default, after reset, the peripherals are in

the power down state.

Table 6-7. eCAPx Clock Enable Control

CONTROL REGISTER TO

eCAP MODULE INSTANCE

DEFAULT VALUE

ENABLE CLOCK

PSPWRDWNCLR3[15]

PSPWRDWNCLR3[8]

PSPWRDWNCLR3[9]

PSPWRDWNCLR3[10]

PSPWRDWNCLR3[11]

PSPWRDWNCLR3[4]

eCAP1

eCAP2

eCAP3

eCAP4

eCAP5

eCAP6

6.2.2 PWM Output Capability of eCAPx

When not used in capture mode, each of the eCAPx modules can be used as a single-channel PWM

output. This is called the Auxiliary PWM (APWM) mode of operation of the eCAPx modules. For more

information, see the eCAP module chapter of the device-specific TRM.

6.2.3 Input Connection to eCAPx Modules

The input connection to each of the eCAPx modules can be selected between a double-VCLK3-

synchronized input or a double-VCLK3-synchronized and filtered input, as listed in Table 6-8.

Table 6-8. Device-Level Input Connection to eCAPx Modules

CONTROL FOR

INPUT SIGNAL

DOUBLE-SYNCHRONIZED

CONNECTION TO eCAPx

DOUBLE-SYNCHRONIZED AND

FILTERED CONNECTION TO eCAPx⁽¹⁾

eCAP1

eCAP2

eCAP3

eCAP4

eCAP5

eCAP6

PINMMR169[2:0] = 001

PINMMR169[2:0] = 010

PINMMR169[10:8] = 001

PINMMR169[18:16] = 001

PINMMR169[26:24] = 001

PINMMR170[2:0] = 001

PINMMR170[10:8] = 001

PINMMR169[10:8] = 010

PINMMR169[18:16] = 010

PINMMR169[26:24] = 010

PINMMR170[2:0] = 010

PINMMR170[10:8] = 010

(1) The filter width is 6 VCLK3 cycles.

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6.2.4 Enhanced Capture Module (eCAP) Electrical Data/Timing

Table 6-9. eCAPx Timing Requirements

TEST CONDITIONS

MIN

2 t_c(VCLK3)

2 t_c(VCLK3)+ filter width⁽¹⁾

MAX

UNIT

cycles

Synchronous

t_w(CAP)

Pulse width, capture input

Synchronous with input filter

(1) The filter width is 6 VCLK3 cycles.

Table 6-10. eCAPx Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

t_w(APWM)

Pulse duration, APWMx output high or low

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6.3 Enhanced Quadrature Encoder (eQEP)

Figure 6-6 shows the eQEP module interconnections on the device.

VBus32

EQEP1A

EQEP1B

EQEP1ENCLK

VCLK3

SYS_nRST

see Note A

EQEP1I

EQEP1IO

EQEP1IOE

EQEP1

Module

EPWM1/../7

EQEP1INTn

EQEP1ERR

VIM

EQEP1S

EQEP1SO

EQEP1SOE

Mux

VBus32

EQEP2A

see Note A EQEP2B

EQEP2ENCLK

VCLK3

SYS_nRST

EQEP2I

EQEP2IO

EQEP2IOE

EQEP2

Module

EQEP2INTn

EQEP2ERR

VIM

Connection

Selection

Mux

EQEP2S

EQEP2SO

EQEP2SOE

A. For more detail on the eQEPx input synchronization selection, see Figure 6-7.

Figure 6-6. eQEP Module Interconnections

Figure 6-7 shows the detailed input synchronization selection (asynchronous, double-synchronous, or

double synchronous + filter width) for eQEPx.

EQEPxA or EQEPxB

(x = 1 or 2)

double

sync

eQEPx

6 VCLK3

Cycles Filter

(x = 1 or 2)

Figure 6-7. eQEPx Input Synchronization Selection Detail

6.3.1 Clock Enable Control for eQEPx Modules

Each of the EQEPx modules has a clock enable (EQEPxENCLK) which is controlled by its respective

Peripheral Power Down bit in the PSPWRDWNCLRx register of the PCR2 module. To properly reset the

peripherals, the peripherals must be released from reset by setting the PENA bit of the CLKCNTL register

in the system module. In addition, the peripherals must be released from their power down state by

clearing the respective bit in the PSPWRDWNCLRx register. By default after reset, the peripherals are in

power down state.

Table 6-11. eQEPx Clock Enable Control

CONTROL REGISTER TO

eQEP MODULE INSTANCE

DEFAULT VALUE

ENABLE CLOCK

PSPWRDWNCLR3[5]

PSPWRDWNCLR3[6]

eQEP1

eQEP2

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6.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs

The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs

EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection

multiplexer. This multiplexer is defined in Table 6-3. As shown in Figure 6-6, the output of this selection

multiplexer is inverted and connected to the TZ4n trip-zone input of all ePWMx modules. This connection

allows the application to define the response of each ePWMx module on a phase error indicated by the

eQEP modules.

6.3.3 Input Connection to eQEPx Modules

The input connection to each of the eQEP modules can be selected between a double-VCLK3-

synchronized input or a double-VCLK3-synchronized and filtered input, as listed in Table 6-12.

Table 6-12. Device-Level Input Connection to eQEPx Modules

CONTROL FOR

CONTROL FOR DOUBLE-SYNCHRONIZED

INPUT SIGNAL

DOUBLE-SYNCHRONIZED AND

CONNECTION TO eQEPx

FILTERED CONNECTION⁽¹⁾TO eQEPx

eQEP1A

eQEP1B

eQEP1I

eQEP1S

eQEP2A

eQEP2B

eQEP2I

eQEP2S

PINMMR170[18:16] = 001

PINMMR170[18:16] = 010

PINMMR170[26:24] = 001

PINMMR171[2:0] = 001

PINMMR171[10:8] = 001

PINMMR171[18:16] = 001

PINMMR171[26:24] = 001

PINMMR172[2:0] = 001

PINMMR172[10:8] = 001

PINMMR170[26:24] = 010

PINMMR171[2:0] = 010

PINMMR171[10:8] = 010

PINMMR171[18:16] = 010

PINMMR171[26:24] = 010

PINMMR172[2:0] = 010

PINMMR172[10:8] = 010

(1) The filter width is 6 VCLK3 cycles.

6.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing

Table 6-13. eQEPx Timing Requirements⁽¹⁾

TEST CONDITIONS

MIN

2 t_c(VCLK3)

MAX UNIT

Synchronous

t_w(QEPP)

QEP input period

cycles

Synchronous with input filter

Synchronous

2 t_c(VCLK3)+ filter width

2 t_c(VCLK3)

t_w(INDEXH)

QEP Index Input High Time

QEP Index Input Low Time

cycles

Synchronous with input filter

Synchronous

2 t_c(VCLK3)+ filter width

2 t_c(VCLK3)

t_w(INDEXL)

Synchronous with input filter

Synchronous

2 t_c(VCLK3)+ filter width

2 t_c(VCLK3)

t_w(STROBH)QEP Strobe Input High Time

Synchronous with input filter

Synchronous

2 t_c(VCLK3)+ filter width

2 t_c(VCLK3)

t_w(STROBL)QEP Strobe Input Low Time

(1) The filter width is 6 VCLK3 cycles.

Synchronous with input filter

2 t_c(VCLK3)+ filter width

Table 6-14. eQEPx Switching Characteristics

PARAMETER

MIN

MAX

4 t_c(VCLK3)

6 t_c(VCLK3)

UNIT

cycles

t_d(CNTR)xin

Delay time, external clock to counter increment

Delay time, QEP input edge to position compare sync output

t_{d(PCS-OUT)QEP}

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6.4 12-bit Multibuffered Analog-to-Digital Converter (MibADC)

The MibADC has a separate power bus for its analog circuitry that enhances the Analog-to-Digital (A-to-D)

performance by preventing digital switching noise on the logic circuitry which could be present on V_SSand

V_CCfrom coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to

AD_REFLO, unless otherwise noted.

Table 6-15. MibADC Overview

DESCRIPTION

Resolution

VALUE

12 bits

Assured

Monotonic

Output conversion code

00h to FFFh [00 for V_AI≤ AD_REFLO; FFF for V_AI≥ AD_REFHI]

6.4.1 MibADC Features

•

10-/12-bit resolution

AD_REFHIand AD_REFLOpins (high and low reference voltages)

Total Sample/Hold/Convert time: 600 ns Typical Minimum at 30 MHz ADCLK

One memory region per conversion group is available (Event Group, Group 1, and Group 2)

Allocation of channels to conversion groups is completely programmable

Memory regions are serviced either by interrupt or by DMA

Programmable interrupt threshold counter is available for each group

Programmable magnitude threshold interrupt for each group for any one channel

Option to read either 8-, 10-, or 12-bit values from memory regions

Single or continuous conversion modes

Embedded self-test

Embedded calibration logic

Enhanced power-down mode

–

Optional feature to automatically power down ADC core when no conversion is in progress

•

External event pin (ADEVT) programmable as general-purpose I/O

6.4.2 Event Trigger Options

The ADC module supports three conversion groups: Event Group, Group1, and Group2. Each of these

three groups can be configured to be triggered by a hardware event. In that case, the application can

select from among eight event sources to be the trigger for a group's conversions.

6.4.2.1 MibADC1 Event Trigger Hookup

Table 6-16 lists the event sources that can trigger the conversions for the MibADC1 groups.

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Table 6-16. MibADC1 Event Trigger Selection

GROUP SOURCE SELECT BITS

(G1SRC, G2SRC OR EVSRC)

CONTROL FOR

OPTION A

CONTROL FOR

OPTION B

EVENT NO.

PINMMR161[0]

PINMMR161[1]

TRIGGER SOURCE

000

—

AD1EVT

N2HET1[8]

N2HET2[5]

e_TPWM_B

N2HET1[10]

N2HET1[27]

RTI1 Comp0

e_TPWM_A1

N2HET1[12]

N2HET1[17]

N2HET1[14]

N2HET1[19]

N2HET2[1]

GIOB[0]

PINMMR161[8] = x

PINMMR161[8] = 1

PINMMR161[8] = 0

—

PINMMR161[9] = x

PINMMR161[9] = 0

PINMMR161[9] = 1

—

001

010

011

100

101

—

PINMMR161[16] = x

PINMMR161[16] = 1

PINMMR161[16] = 0

—

PINMMR161[17] = x

PINMMR161[17] = 0

PINMMR161[17] = 1

—

PINMMR161[24] = x

PINMMR161[24] = 1

PINMMR161[24] = 0

PINMMR162[0] = x

PINMMR162[0] = 1

PINMMR162[0] = 0

PINMMR162[8] = x

PINMMR162[8] = 1

PINMMR162[8] = 0

PINMMR161[25] = x

PINMMR161[25] = 0

PINMMR161[25] = 1

PINMMR162[1] = x

PINMMR162[1] = 0

PINMMR162[1] = 1

PINMMR162[9] = x

PINMMR162[9] = 0

PINMMR162[9] = 1

110

111

N2HET1[11]

ePWM_A2

GIOB[1]

N2HET2[13]

ePWM_AB

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NOTE

For ADEVT trigger source, the connection to the MibADC1 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

configuring ADEVT as an output function on to the pad (through the mux control), or by

driving the ADEVT signal from an external trigger source as input. If the mux control module

is used to select different functionality instead of the ADEVT signal, then care must be taken

to disable ADEVT from triggering conversions; there is no multiplexing on the input

connection.

If ePWM_B, ePWM_A2, ePWM_AB, N2HET2[1], N2HET2[5], N2HET2[13], N2HET1[11],

N2HET1[17], or N2HET1[19] is used to trigger the ADC, the connection to the ADC is made

directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered

without having to enable the signal from being output on a device terminal.

NOTE

For N2HETx trigger sources, the connection to the MibADC1 module trigger input is made

from the input side of the output buffer (at the N2HETx module boundary). This way, a

trigger condition can be generated even if the N2HETx signal is not selected to be output on

the pad.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of

the RTI module. That is, the interrupt condition can be used as a trigger source even if the

actual interrupt is not signaled to the CPU.

6.4.2.2 MibADC2 Event Trigger Hookup

Table 6-17 lists the event sources that can trigger the conversions for the MibADC2 groups.

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Table 6-17. MibADC2 Event Trigger Selection

GROUP SOURCE SELECT BITS

(G1SRC, G2SRC, or EVSRC)

CONTROL FOR

OPTION A

CONTROL FOR

OPTION B

EVENT NO.

PINMMR161[0]

PINMMR161[1]

TRIGGER SOURCE

000

AD2EVT

N2HET1[8]

N2HET2[5]

e_TPWM_B

N2HET1[10]

N2HET1[27]

RTI1 Comp0

e_TPWM_A1

N2HET1[12]

N2HET1[17]

N2HET1[14]

N2HET1[19]

N2HET2[1]

GIOB[0]

PINMMR162[16] = x

PINMMR162[16] = 1

PINMMR162[16] = 0

PINMMR162[17] = x

PINMMR162[17] = 0

PINMMR162[17] = 1

001

010

011

100

101

PINMMR162[24] = x

PINMMR162[24] = 1

PINMMR162[24] = 0

PINMMR162[25] = x

PINMMR162[25] = 0

PINMMR162[25] = 1

PINMMR163[0] = x

PINMMR163[0] = 1

PINMMR163[0] = 0

PINMMR163[8] = x

PINMMR163[8] = 1

PINMMR163[8] = 0

PINMMR163[16] = x

PINMMR163[16] = 1

PINMMR163[16] = 0

PINMMR163[0] = x

PINMMR163[0] = 0

PINMMR163[0] = 1

PINMMR163[8] = x

PINMMR163[8] = 0

PINMMR163[8] = 1

PINMMR163[16] = x

PINMMR163[16] = 0

PINMMR163[16] = 1

110

111

N2HET1[11]

ePWM_A2

GIOB[1]

N2HET2[13]

ePWM_AB

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NOTE

For AD2EVT trigger source, the connection to the MibADC2 module trigger input is made

from the output side of the input buffer. This way, a trigger condition can be generated either

by configuring AD2EVT as an output function on to the pad (through the mux control), or by

driving the AD2EVT signal from an external trigger source as input. If the mux control module

is used to select different functionality instead of the AD2EVT signal, then care must be

taken to disable AD2EVT from triggering conversions; there is no multiplexing on the input

connections.

If ePWM_B, ePWM_A2, ePWM_AB, N2HET2[1], N2HET2[5], N2HET2[13], N2HET1[11],

N2HET1[17], or N2HET1[19] is used to trigger the ADC, the connection to the ADC is made

directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered

without having to enable the signal from being output on a device terminal.

NOTE

For N2HETx trigger sources, the connection to the MibADC2 module trigger input is made

from the input side of the output buffer (at the N2HETx module boundary). This way, a

trigger condition can be generated even if the N2HETx signal is not selected to be output on

the pad.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of

the RTI module. That is, the interrupt condition can be used as a trigger source even if the

actual interrupt is not signaled to the CPU.

6.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules

As shown in Figure 6-8, the ePWMxSOCA and ePWMxSOCB outputs from each ePWM module are used

to generate four signals – ePWM_B, ePWM_A1, ePWM_A2, and ePWM_AB, that are available to trigger

the ADC based on the application requirement.

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SOCAEN, SOCBEN bits

inside ePWMx modules

Controlled by PINMMR

EPWM1SOCA

EPWM1

module

EPWM1SOCB

EPWM2SOCA

EPWM2SOCB

EPWM2

module

EPWM3SOCA

EPWM3SOCB

EPWM3

module

EPWM4SOCA

EPWM4SOCB

EPWM4

module

EPWM5SOCA

EPWM5SOCB

EPWM5

module

EPWM6SOCA

EPWM6SOCB

EPWM6

module

EPWM7SOCA

EPWM7SOCB

EPWM7

module

ePWM_B ePWM_A1 ePWM_A2 ePWM_AB

Figure 6-8. ADC Trigger Source Generation from ePWMx

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Table 6-18. Control Bit to SOC Output

CONTROL BIT

PINMMR164[0]

PINMMR164[8]

PINMMR164[16]

PINMMR164[24]

PINMMR165[0]

PINMMR165[8]

PINMMR165[16]

SOC OUTPUT

SOC1A_SEL

SOC2A_SEL

SOC3A_SEL

SOC4A_SEL

SOC5A_SEL

SOC6A_SEL

SOC7A_SEL

The SOCA output from each ePWM module is connected to a "switch" shown in Figure 6-8. This switch is

implemented by using the control registers in the PINMMR module. Figure 6-9 is an example of the

implementation is shown for the switch on SOC1A. The switches on the other SOCA signals are

implemented in the same way.

SOC1A

ePWM1

PINMMR164[0]

EPWM1SOCA

From switch on

SOC2A

when PINMMR164[8] = 1

From switch on

SOC2A

when PINMMR164[8] = 0

Figure 6-9. ePWM1SOC1A Switch Implementation

The logic equations for the four outputs from the combinational logic shown in Figure 6-8 are:

ePWM_B = SOC1B or SOC2B or SOC3B or SOC4B or SOC5B or SOC6B or SOC7B

ePWM_A1 = [ SOC1A and not(SOC1A_SEL) ] or [ SOC2A and not(SOC2A_SEL) ] or [ SOC3A and not(SOC3A_SEL) ] or

[ SOC4A and not(SOC4A_SEL) ] or [ SOC5A and not(SOC5A_SEL) ] or [ SOC6A and not(SOC6A_SEL) ] or

[ SOC7A and not(SOC7A_SEL) ]

(1)

(2)

ePWM_A2 = [ SOC1A and SOC1A_SEL ] or [ SOC2A and SOC2A_SEL ] or [ SOC3A and SOC3A_SEL ] or

[ SOC4A and SOC4A_SEL ] or [ SOC5A and SOC5A_SEL ] or [ SOC6A and SOC6A_SEL ] or

[ SOC7A and SOC7A_SEL ]

(3)

(4)

ePWM_AB = ePWM_B or ePWM_A2

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6.4.3 ADC Electrical and Timing Specifications

Table 6-19. MibADC Recommended Operating Conditions

PARAMETER

A-to-D high-voltage reference source

MIN

MAX

UNIT

(1)

AD_REFHI

AD_REFLO

V_AI

AD_REFLO

V_CCAD

(1)

A-to-D low-voltage reference source

V_SSAD

AD_REFHI

Analog input voltage

Analog input clamp current⁽²⁾(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)

AD_REFLO

–2

I_AIC

(1) For V_CCADand V_SSADrecommended operating conditions, see Section 4.4.

(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 6-20. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating

Conditions⁽¹⁾

PARAMETER

DESCRIPTION/CONDITIONS

MIN

MAX UNIT

R_mux

R_samp

C_mux

C_samp

Analog input mux on-resistance

ADC sample switch on-resistance

Input mux capacitance

See Figure 6-10

250

ADC sample capacitance

_SSAD≤ V_IN< V_SSAD+ 100 mV

–300

–280

–200

–1000

–450

–250

–10

200

280

650

250

450

2000

I_AIL

Analog off-state input leakage current V_CCAD= 3.6 V

Analog off-state input leakage current V_CCAD= 5.25 V

V_SSAD+ 100 mV ≤ V_IN≤ V_CCAD– 200 mV

V_CCAD– 200 mV < V_IN≤ V_CCAD

µA

V_SSAD≤ V_IN< V_SSAD+ 300 mV

I_AIL

V_SSAD+ 300 mV ≤ V_IN≤ V_CCAD– 300 mV

V_CCAD– 300 mV < V_IN≤ V_CCAD

V_SSAD≤ V_IN< V_SSAD+ 100 mV

(2)

I_AOSB

Analog on-state input bias current

V_CCAD= 3.6 V

V_SSAD+ 100 mV < V_IN< V_CCAD– 200 mV

V_CCAD– 200 mV < V_IN< V_CCAD

–4

V_SSAD≤ V_IN< V_SSAD+ 300 mV

–12

(2)

I_AOSB

V_CCAD= 5.25 V

V_SSAD+ 300 mV ≤ V_IN≤ V_CCAD– 300 mV

V_CCAD– 300 mV < V_IN≤ V_CCAD

–5

(1) For I_CCADand I_CCREFHIsee Section 4.7.

(2) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is doubled.

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R_ext

P_in

R_mux

S_mux

V_S1

I_AOSB

C_ext

On-State

Bias Current

S_mux

R_ext

P_in

R_mux

V_S2

I_AIL

C_ext

I_AIL

Off-State

Leakages

S_mux

R_ext

P_in

R_mux

S_samp

R_samp

V_S24

I_AIL

C_samp

C_mux

C_ext

I_AIL

Figure 6-10. MibADC Input Equivalent Circuit

Table 6-21. MibADC Timing Specifications

PARAMETER

MIN NOM

MAX UNIT

(1)

t_c(ADCLK)

Cycle time, MibADC clock

0.033

µs

(2)

t_d(SH)

Delay time, sample and hold time

0.2

12-BIT MODE

t_d(C)

Delay time, conversion time

0.4

0.6

µs

(3)

t_d(SHC)

Delay time, total sample/hold and conversion time

10-BIT MODE

t_d(C)

Delay time, conversion time

0.33

0.53

µs

(3)

t_d(SHC)

Delay time, total sample/hold and conversion time

(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK1 by a prescale factor defined by the ADCLOCKCR register

bits 4:0.

(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each

conversion group. The sample time must be determined by accounting for the external impedance connected to the input channel as

well as the internal impedance of the ADC.

(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors (for

example, the prescale settings).

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Table 6-22. MibADC Operating Characteristics Over 3.0 V to 3.6 V Operating Conditions⁽¹⁾⁽²⁾

PARAMETER

DESCRIPTION/CONDITIONS

AD_REFHI- AD_REFLO

MIN

MAX UNIT

Conversion range over which specified

accuracy is maintained

3.6

10-bit mode

12-bit mode

10-bit mode

LSB

Z_SE

Difference between the first ideal transition (from

code 000h to 001h) and the actual transition

Zero Scale Offset

Difference between the range of the measured

code transitions (from first to last) and the range

of the ideal code transitions

F_SE

Full Scale Offset

12-bit mode

LSB

10-bit mode

12-bit mode

10-bit mode

–1

–2

1.5 LSB

E_DN

Difference between the actual step width and the

ideal value. (See Figure 6-11)

Differential nonlinearity error

Integral nonlinearity error

Total unadjusted error (after calibration)

LSB

Maximum deviation from the best straight line

through the MibADC. MibADC transfer

characteristics, excluding the quantization error.

E_IN

12-bit mode

–2

LSB

10-bit mode

12-bit mode

–2

–4

LSB

E_TO

Maximum value of the difference between an

analog value and the ideal midstep value.

(1) 1 LSB = (AD_REFHI– AD_REFLO)/ 2¹²for 12-bit mode

(2) 1 LSB = (AD_REFHI– AD_REFLO)/ 2¹⁰for 10-bit mode

Table 6-23. MibADC Operating Characteristics Over 3.6 V to 5.25 V Operating Conditions⁽¹⁾⁽²⁾

PARAMETER

DESCRIPTION/CONDITIONS

AD_REFHI- AD_REFLO

MIN

MAX UNIT

Conversion range over which specified

accuracy is maintained

3.6

5.25

10-bit mode

12-bit mode

10-bit mode

LSB

Z_SE

Difference between the first ideal transition (from

code 000h to 001h) and the actual transition

Zero Scale Offset

Difference between the range of the measured

code transitions (from first to last) and the range

of the ideal code transitions

F_SE

Full Scale Offset

12-bit mode

LSB

10-bit mode

12-bit mode

10-bit mode

–1

–2

1.5 LSB

E_DN

Difference between the actual step width and the

ideal value. (See Figure 6-11)

Differential nonlinearity error

Integral nonlinearity error

Total unadjusted error (after calibration)

LSB

Maximum deviation from the best straight line

through the MibADC. MibADC transfer

characteristics, excluding the quantization error.

E_IN

12-bit mode

–4.5

LSB

10-bit mode

12-bit mode

–2

–6

LSB

E_TO

Maximum value of the difference between an

analog value and the ideal midstep value.

(1) 1 LSB = (AD_REFHI– AD_REFLO)/ 2¹²for 12-bit mode

(2) 1 LSB = (AD_REFHI– AD_REFLO)/ 2¹⁰for 10-bit mode

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6.4.4 Performance (Accuracy) Specifications

6.4.4.1 MibADC Nonlinearity Errors

The differential nonlinearity error shown in Figure 6-11 (sometimes referred to as differential linearity) is

the difference between an actual step width and the ideal value of 1 LSB.

0 ... 110

0 ... 101

0 ... 100

0 ... 011

Differential Linearity

Error (–½ LSB)

1 LSB

0 ... 010

Differential Linearity

Error (–½ LSB)

0 ... 001

0 ... 000

1 LSB

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI– AD_REFLO)/2¹²

Figure 6-11. Differential Nonlinearity (DNL) Error

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The integral nonlinearity error shown in Figure 6-12 (sometimes referred to as linearity error) is the

deviation of the values on the actual transfer function from a straight line.

0 ... 111

0 ... 110

Ideal

Transition

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 000

Actual

Transition

At Transition

011/100

(–½ LSB)

End-Point Lin. Error

At Transition

001/010 (–1/4 LSB)

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI– AD_REFLO)/2¹²

Figure 6-12. Integral Nonlinearity (INL) Error^(A)

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6.4.4.2 MibADC Total Error

The absolute accuracy or total error of an MibADC as shown in Figure 6-13 is the maximum value of the

difference between an analog value and the ideal midstep value.

0 ... 111

0 ... 110

0 ... 101

0 ... 100

Total Error

At Step 0 ... 101

(–1 1/4 LSB)

0 ... 011

0 ... 010

Total Error

At Step

0 ... 001 (1/2 LSB)

0 ... 001

0 ... 000

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI– AD_REFLO)/2¹²

Figure 6-13. Absolute Accuracy (Total) Error^(A)

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6.5 General-Purpose Input/Output

The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and

bit-programmable. Both GIOA and GIOB support external interrupt capability.

6.5.1 Features

The GPIO module has the following features:

•

Each I/O pin can be configured as:

–

Input

Output

Open Drain

•

The interrupts have the following characteristics:

–

Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)

Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)

Individual interrupt flags (set in GIOFLG register)

Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers

respectively

–

Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers

•

Internal pullup/pulldown allows unused I/O pins to be left unconnected

For information on input and output timings see Section 4.10.1 and Section 4.10.2.

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6.6 Enhanced High-End Timer (N2HET)

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer

micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,

capture or compare inputs, or general-purpose I/O.. It is especially well suited for applications requiring

multiple sensor information and drive actuators with complex and accurate time pulses.

6.6.1 Features

The N2HET module has the following features:

•

Programmable timer for input and output timing functions

Reduced instruction set (30 instructions) for dedicated time and angle functions

256 words of instruction RAM protected by parity

User defined number of 25-bit virtual counters for timer, event counters and angle counters

7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual

counters

•

Up to 32 pins usable for input signal measurements or output signal generation

Programmable suppression filter for each input pin with adjustable limiting frequency

Low CPU overhead and interrupt load

Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU)

or DMA

•

Diagnostic capabilities with different loopback mechanisms and pin status readback functionality

6.6.2 N2HET RAM Organization

The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one

RAM address may be written while another address is read. The RAM words are 96-bits wide, which are

split into three 32-bit fields (program, control, and data).

6.6.3 Input Timing Specifications

The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.

N2HETx

Figure 6-14. N2HET Input Capture Timings

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MAX UNIT

Table 6-24. Dynamic Characteristics for the N2HET Input Capture Functionality

PARAMETER

MIN

Input signal period, PCNT or WCAP for rising edge

to rising edge

(HRP) (LRP) tc_(VCLK2)+ 2

2²⁵(HRP) (LRP) tc_(VCLK2)- 2

Input signal period, PCNT or WCAP for falling edge

to falling edge

(HRP) (LRP) tc_(VCLK2)+ 2

2 (HRP) tc_(VCLK2)+ 2

2²⁵(HRP) (LRP) tc_(VCLK2)- 2

Input signal high phase, PCNT or WCAP for rising

edge to falling edge

Input signal low phase, PCNT or WCAP for falling

edge to rising edge

6.6.4 N2HET1-N2HET2 Interconnections

In some applications the N2HET resolutions must be synchronized. Some other applications require a

single time base to be used for all PWM outputs and input timing captures.

The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures

the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal

to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to

the loop resolution signal sent by the master. The slave does not require this signal after it receives the

first synchronization signal. However, anytime the slave receives the resynchronization signal from the

master, the slave must synchronize itself again..

N2HET1

N2HET2

NHET_LOOP_SYNC

EXT_LOOP_SYNC

NHET_LOOP_SYNC

EXT_LOOP_SYNC

Figure 6-15. N2HET1 – N2HET2 Synchronization Hookup

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6.6.5 N2HET Checking

6.6.5.1 Internal Monitoring

To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be

used to monitor each other’s signals as shown in Figure 6-16. The direction of the monitoring is controlled

by the I/O multiplexing control module.

IOMM mux control signal x

N2HET1[1]

N2HET1[1] / N2HET2[8]

N2HET1

N2HET2[8]

N2HET2

N2HET1[3] / N2HET2[10]

N2HET1[5] / N2HET2[12]

N2HET1[7] / N2HET2[14]

N2HET1[9] / N2HET2[16]

IOMM mux control signal x

N2HET1[11]

N2HET1[11] / N2HET2[18]

N2HET1

N2HET2[18]

N2HET2

Figure 6-16. N2HET Monitoring

6.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)

N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure

the frequency of the pulse-width modulated (PWM) signal on N2HET1[31].

Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to

measure the frequency of the pulse-width modulated (PWM) signal on N2HET2[0].

Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection

to the DCC module is made directly from the output of the N2HETx module (from the input of the output

buffer).

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For more information on DCC see Section 5.7.3.

6.6.6 Disabling N2HET Outputs

Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET

module provides this capability through the "Pin Disable" input signal. This signal, when driven low,

causes the N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. Refer to

the IOMM chapter in the device specific technical reference manual for more details on the "N2HET Pin

Disable" feature.

GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin

Disable" input for N2HET2.

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6.6.7 High-End Timer Transfer Unit (HET-TU)

A High End Timer Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to

or from main memory. A Memory Protection Unit (MPU) is built into the HET-TU.

6.6.7.1 Features

CPU and DMA independent

•

Master Port to access system memory

8 control packets supporting dual buffer configuration

Control packet information is stored in RAM protected by parity

Event synchronization (HET transfer requests)

Supports 32 or 64 bit transactions

Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or

64bit)

•

One shot, circular and auto switch buffer transfer modes

Request lost detection

6.6.7.2 Trigger Connections

Table 6-25. HET TU1 Request Line Connection

Modules

N2HET1

Request Source

HTUREQ[0]

HTUREQ[1]

HTUREQ[2]

HTUREQ[3]

HTUREQ[4]

HTUREQ[5]

HTUREQ[6]

HTUREQ[7]

HET TU1 Request

HET TU1 DCP[0]

HET TU1 DCP[1]

HET TU1 DCP[2]

HET TU1 DCP[3]

HET TU1 DCP[4]

HET TU1 DCP[5]

HET TU1 DCP[6]

HET TU1 DCP[7]

Table 6-26. HET TU2 Request Line Connection

Modules

N2HET2

Request Source

HTUREQ[0]

HTUREQ[1]

HTUREQ[2]

HTUREQ[3]

HTUREQ[4]

HTUREQ[5]

HTUREQ[6]

HTUREQ[7]

HET TU2 Request

HET TU2 DCP[0]

HET TU2 DCP[1]

HET TU2 DCP[2]

HET TU2 DCP[3]

HET TU2 DCP[4]

HET TU2 DCP[5]

HET TU2 DCP[6]

HET TU2 DCP[7]

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6.7 FlexRay Interface

The FlexRay module performs communication according to the FlexRay protocol specification v2.1. The

sample clock bitrate can be programmed to values up to 10 MBit per second. Additional bus driver (BD)

hardware is required for connection to the physical layer.

For communication on a FlexRay network, individual message buffers with up to 254 data bytes are

configurable. The message storage consists of a single-ported message RAM that holds up to 128

message buffers. All functions concerning the handling of messages are implemented in the message

handler. Those functions are the acceptance filtering, the transfer of messages between the two FlexRay

Channel Protocol Controllers and the message RAM, maintaining the transmission schedule as well as

providing message status information.

The register set of the FlexRay module can be accessed directly by the CPU through the VBUS interface.

These registers are used to control, configure and monitor the FlexRay channel protocol controllers,

message handler, global time unit, system universal control, frame/symbol processing, network

management, interrupt control, and to access the message RAM through the I/O buffer.

6.7.1 Features

The FlexRay module has the following features:

•

Conformance with FlexRay protocol specification v2.1

Data rates of up to 10 Mbps on each channel

Up to 128 message buffers

8KB of message RAM for storage of for example, 128 message buffers with max. 48 byte data section

or up to 30 message buffers with 254 byte data section

•

Configuration of message buffers with different payload lengths

One configurable receive FIFO

Each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive

FIFO

•

CPU access to message buffers through input and output buffer

FlexRay Transfer Unit (FTU) for automatic data transfer between data memory and message buffers

without CPU interaction

•

Filtering for slot counter, cycle counter, and channel ID

Maskable module interrupts

Supports Network Management

ECC protection on the message RAM

6.7.2 Electrical and Timing Specifications

Table 6-27. Timing Requirements for FlexRay Inputs⁽¹⁾

Parameter

MIN

MAX

UNIT

t_pw

Input minimum pulse width to meet the FlexRay sampling

requirement

t_c(VCLKA2)+ 2.5⁽²⁾

(1) t_c(VCLKA2)= sample clock cycle time for FlexRay = 1 / f_(VCLKA2)

(2) t_RxAsymDelayparameter

t_pw

0.6*V_CCIO

V_CCIO

Input

0.6*V_CCIO

0.4*V_CCIO

Figure 6-17. FlexRay Inputs

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Table 6-28. FlexRay Jitter Timing⁽¹⁾

PARAMETER

MIN

MAX

102

UNIT

t_Tx1bit

Clock jitter and signal symmetry

FlexRay BSS (byte start sequence) to BSS

Average over 10000 samples

t_Tx10bit

999

1001

t_Tx10bitAvg

999.5

1000.5

Delay difference between rise and fall from Rx pin to sample

point in FlexRay core

(2)

t_RxAsymDelay

t_jit(SCLK)

–

2.5

0.5

Jitter for the 80-MHz Sample Clock generated by the PLL

(1) This parameter will be characterized, but not production-tested.

(2) This value is based on design simulation.

6.7.3 FlexRay Transfer Unit

The FlexRay Transfer Unit is able to transfer data between the input buffer (IBF) and output buffer (OBF)

of the communication controller and the system memory without CPU interaction.

Because the FlexRay module is accessed through the FTU, the FTU must be powered up by the setting

bit 23 in the Peripheral Power Down Registers of the System Module before accessing any FlexRay

module register.

For more information on the FTU see the device specific technical reference manual.

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6.8 Controller Area Network (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication

protocol that efficiently supports distributed real-time control with robust communication rates of up to 1

megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh

environments (e.g., automotive and industrial fields) that require reliable serial communication or

multiplexed wiring.

6.8.1 Features

Features of the DCAN module include:

•

Supports CAN protocol version 2.0 part A, B

Bit rates up to 1 MBit/s

The CAN kernel can be clocked by the oscillator for baud-rate generation.

64 mailboxes on each DCAN

Individual identifier mask for each message object

Programmable FIFO mode for message objects

Programmable loop-back modes for self-test operation

Automatic bus on after Bus-Off state by a programmable 32-bit timer

Message RAM protected by ECC

Direct access to Message RAM during test mode

CAN Rx / Tx pins configurable as general purpose IO pins

Message RAM Auto Initialization

DMA support

For more information on the DCAN see the device specific technical reference manual.

6.8.2 Electrical and Timing Specifications

Table 6-29. Dynamic Characteristics for the DCANx TX and RX pins

Parameter

MIN

MAX

Unit

t_d(CANnTX)

t_d(CANnRX)

Delay time, transmit shift register to CANnTX pin⁽¹⁾

Delay time, CANnRX pin to receive shift register

(1) These values do not include rise/fall times of the output buffer.

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6.9 Local Interconnect Network Interface (LIN)

The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is

an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility.

The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn

to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-

line.

The LIN standard is based on the SCI (UART) serial data link format. The communication concept is

single-master/multiple-slave with a message identification for multicast transmission between any network

nodes.

6.9.1 LIN Features

The following are features of the LIN module:

•

Compatible to LIN 1.3, 2.0 and 2.1 protocols

Multibuffered receive and transmit units DMA capability for minimal CPU intervention

Identification masks for message filtering

Automatic Master Header Generation

–

Programmable Synch Break Field

Synch Field

Identifier Field

•

Slave Automatic Synchronization

–

Synch break detection

Optional baudrate update

Synchronization Validation

2³¹programmable transmission rates with 7 fractional bits

•

Error detection

2 Interrupt lines with priority encoding

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6.10 Serial Communication Interface (SCI)

6.10.1 Features

•

Standard universal asynchronous receiver-transmitter (UART) communication

Supports full- or half-duplex operation

Standard nonreturn to zero (NRZ) format

Double-buffered receive and transmit functions

Configurable frame format of 3 to 13 bits per character based on the following:

–

Data word length programmable from one to eight bits

Additional address bit in address-bit mode

Parity programmable for zero or one parity bit, odd or even parity

Stop programmable for one or two stop bits

•

Asynchronous or isosynchronous communication modes

Two multiprocessor communication formats allow communication between more than two devices.

Sleep mode is available to free CPU resources during multiprocessor communication.

The 24-bit programmable baud rate supports 2²⁴different baud rates provide high accuracy baud rate

selection.

•

Four error flags and Five status flags provide detailed information regarding SCI events.

Capability to use DMA for transmit and receive data.

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6.11 Inter-Integrated Circuit (I2C)

The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface

between the TMS570 microcontroller and devices compliant with Philips Semiconductor I2C-bus

specification version 2.1 and connected by an I2C-bus. This module will support any slave or master I2C

compatible device.

6.11.1 Features

The I2C has the following features:

•

Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number

9398 393 40011)

–

Bit/Byte format transfer

7-bit and 10-bit device addressing modes

General call

START byte

Multimaster transmitter/ slave receiver mode

Multimaster receiver/ slave transmitter mode

Combined master transmit/receive and receive/transmit mode

Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)

•

Free data format

Two DMA events (transmit and receive)

DMA event enable/disable capability

Seven interrupts that can be used by the CPU

Module enable/disable capability

The SDA and SCL are optionally configurable as general purpose I/O

Slew rate control of the outputs

Open drain control of the outputs

Programmable pullup/pulldown capability on the inputs

Supports Ignore NACK mode

NOTE

This I2C module does not support:

•

High-speed (HS) mode

C-bus compatibility mode

The combined format in 10-bit address mode (the I2C sends the slave address second

byte every time it sends the slave address first byte)

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6.11.2 I2C I/O Timing Specifications

Table 6-30. I2C Signals (SDA and SCL) Switching Characteristics⁽¹⁾

STANDARD MODE

FAST MODE

MIN

PARAMETER

UNIT

MIN

MAX

149

Cycle time, Internal Module clock for I2C,

prescaled from VCLK

t_c(I2CCLK)

75.2

149

100

75.2

f_(SCL)

SCL Clock frequency

Cycle time, SCL

400

kHz

µs

t_c(SCL)

2.5

Setup time, SCL high before SDA low (for a

repeated START condition)

t_{su(SCLH-SDAL)}

t_h(SCLL-SDAL)

4.7

0.6

µs

Hold time, SCL low after SDA low (for a repeated

START condition)

t_w(SCLL)

Pulse duration, SCL low

4.7

1.3

0.6

µs

t_w(SCLH)

Pulse duration, SCL high

t_su(SDA-SCLH)

Setup time, SDA valid before SCL high

250

100

Hold time, SDA valid after SCL low (for I2C bus

devices)

t_h(SDA-SCLL)

t_w(SDAH)

t_{su(SCLH-SDAH)}

t_w(SP)

4.7

4.0

3.45⁽²⁾

0.9

µs

Pulse duration, SDA high between STOP and

START conditions

1.3

Setup time, SCL high before SDA high (for STOP

condition)

0.6

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

(3)

C_b

400

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum t_h(SDA-SCLL)for I2C bus devices has only to be met if the device does not stretch the low period (t_w(SCLL)) of the SCL

signal.

(3) C_b= The total capacitance of one bus line in pF.

SDA

t_w(SDAH)

t_su(SDA-SCLH)

t_w(SP)

t_w(SCLL)

t_r(SCL)

t_{su(SCLH-SDAH)}

t_w(SCLH)

SCL

t_c(SCL)

t_h(SCLL-SDAL)

t_f(SCL)

t_h(SCLL-SDAL)

t_{su(SCLH-SDAL)}

t_h(SDA-SCLL)

Stop

Start

Repeated Start

Stop

Figure 6-18. I2C Timings

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NOTE

•

A device must internally provide a hold time of at least 300 ns for the SDA signal

(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling

edge of SCL.

•

The maximum t_h(SDA-SCLL)has only to be met if the device does not stretch the LOW

period (t_w(SCLL)) of the SCL signal.

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the

requirement t_su(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if

the device does not stretch the LOW period of the SCL signal. If such a device does

stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

tr max + t_su(SDA-SCLH)

•

C_b= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-

times are allowed.

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6.12 Multibuffered / Standard Serial Peripheral Interface

The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of

programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.

Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display

drivers, and analog-to-digital converters.

6.12.1 Features

Both Standard and MibSPI modules have the following features:

•

16-bit shift register

Receive buffer register

11-bit baud clock generator

SPICLK can be internally-generated (master mode) or received from an external clock source (slave

mode)

•

Each word transferred can have a unique format

SPI I/Os not used in the communication can be used as digital input/output signals

Table 6-31. MibSPI Configurations

MibSPIx/SPIx

MibSPI1

I/Os

MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA

MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA

MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[5:0], MIBSPI5nENA

MIBSPI2SIMO,MIBSPI2SOMI,MIBSPI2CLK,MIBSPI2nCS[1:0],MIBSPI2nENA

MIBSPI4SIMO,MIBSPI4SOMI,MIBSPI4CLK,MIBSPI4nCS[5:0],MIBSPI4nENA

MibSPI3

MibSPI5

MibSPI2

MibSPI4

6.12.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 256 buffers for MibSPI1 and 128 buffers for all other MibSPI. Each

entry in the Multibuffer RAM consists of 4 parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit

control field and a 16-bit status field. The Multibuffer RAM can be partitioned into multiple transfer groups

with a variable number of buffers each.

Table 6-32. Multibuffered RAM Transfer Groups

MibSPIx/SPIx

MODULES

NO OF CHIP

SELECTS

NO. OF RAM

BUFFERS

NO. OF TRANSFER

GROUPS

MIBSPIxnCS[x]

MibSPI1

MibSPI2

MibSPI3

MibSPI4

MibSPI5

MIBSPI1nCS[5:0]

MIBSPI2nCS[1:0]

MIBSPI3nCS[5:0]

MIBSPI4nCS[5:0]

MIBSPI5nCS[5:0]

256

128

6.12.3 MibSPI Transmit Trigger Events

Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event

and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low

level at a selectable trigger source. For example, up to 15 trigger sources are available which can be used

by each transfer group.

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6.12.3.1 MIBSPI1 Event Trigger Hookup

Table 6-33. MIBSPI1 Event Trigger Hookup

Event #

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

EVENT9

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

TGxCTRL TRIGSRC[3:0]

Trigger

No trigger source

GIOA[0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

N2HET1[8]

N2HET1[10]

N2HET1[12]

N2HET1[14]

N2HET1[16]

N2HET1[18]

Intern Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made

from the input side of the output buffer (at the N2HET1 module boundary). This way, a

trigger condition can be generated even if the N2HET1 signal is not selected to be output on

the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin plus selecting the pin to be a GIOx pin, or by driving

the GIOx pin from an external trigger source. If the mux control module is used to select

different functionality instead of the GIOx signal, then care must be taken to disable GIOx

from triggering MibSPI1 transfers; there is no multiplexing on the input connections.

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6.12.3.2 MIBSPI2 Event Trigger Hookup

Table 6-34. MIBSPI2 Event Trigger Hookup

Event #

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

EVENT9

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

TGxCTRL TRIGSRC[3:0]

Trigger

No trigger source

GIOA[0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

N2HET1[8]

N2HET1[10]

N2HET1[12]

N2HET1[14]

N2HET1[16]

N2HET1[18]

Intern Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made

from the input side of the output buffer (at the N2HET1 module boundary). This way, a

trigger condition can be generated even if the N2HET1 signal is not selected to be output on

the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin plus selecting the pin to be a GIOx pin, or by driving

the GIOx pin from an external trigger source. If the mux control module is used to select

different functionality instead of the GIOx signal, then care must be taken to disable GIOx

from triggering MibSPI1 transfers; there is no multiplexing on the input connections.

6.12.3.3 MIBSPI3 Event Trigger Hookup

Table 6-35. MIBSPI3 Event Trigger Hookup

Event #

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

TGxCTRL TRIGSRC[3:0]

Trigger

No trigger source

GIOA[0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

H2ET1[8]

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Table 6-35. MIBSPI3 Event Trigger Hookup (continued)

Event #

EVENT9

TGxCTRL TRIGSRC[3:0]

Trigger

N2HET1[10]

N2HET1[12]

N2HET1[14]

N2HET1[16]

N2HET1[18]

Intern Tick counter

1010

1011

1100

1101

1110

1111

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

NOTE

For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made

from the input side of the output buffer (at the N2HET1 module boundary). This way, a

trigger condition can be generated even if the N2HET1 signal is not selected to be output on

the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin plus selecting the pin to be a GIOx pin, or by driving

the GIOx pin from an external trigger source. If the mux control module is used to select

different functionality instead of the GIOx signal, then care must be taken to disable GIOx

from triggering MibSPI3 transfers; there is no multiplexing on the input connections.

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6.12.3.4 MIBSPI4 Event Trigger Hookup

Table 6-36. MIBSPI4 Event Trigger Hookup

Event #

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

EVENT9

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

TGxCTRL TRIGSRC[3:0]

Trigger

No trigger source

GIOA[0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

N2HET1[8]

N2HET1[10]

N2HET1[12]

N2HET1[14]

N2HET1[16]

N2HET1[18]

Intern Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made

from the input side of the output buffer (at the N2HET1 module boundary). This way, a

trigger condition can be generated even if the N2HET1 signal is not selected to be output on

the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin plus selecting the pin to be a GIOx pin, or by driving

the GIOx pin from an external trigger source. If the mux control module is used to select

different functionality instead of the GIOx signal, then care must be taken to disable GIOx

from triggering MibSPI1 transfers; there is no multiplexing on the input connections.

6.12.3.5 MIBSPI5 Event Trigger Hookup

Table 6-37. MIBSPI5 Event Trigger Hookup

Event #

TGxCTRL TRIGSRC[3:0]

Trigger

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

No trigger source

GIOA[0]

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

N2HET1[8]

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Table 6-37. MIBSPI5 Event Trigger Hookup (continued)

EVENT9

1010

1011

1100

1101

1110

1111

N2HET1[10]

N2HET1[12]

N2HET1[14]

N2HET1[16]

N2HET1[18]

Intern Tick counter

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

NOTE

For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made

from the input side of the output buffer (at the N2HET1 module boundary). This way, a

trigger condition can be generated even if the N2HET1 signal is not selected to be output on

the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin + selecting the pin to be a GIOx pin, or by driving the

GIOx pin from an external trigger source. If the mux control module is used to select different

functionality instead of the GIOx signal, then care must be taken to disable GIOx from

triggering MibSPI5 transfers; there is no multiplexing on the input connections.

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6.12.4 MibSPI/SPI Master Mode I/O Timing Specifications

Table 6-38. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO

= output, and SPISOMI = input)^(1)(2)(3)

NO. Parameter

t_c(SPC)M

2⁽⁵⁾t_w(SPCH)M

MIN

MAX

Unit

Cycle time, SPICLK⁽⁴⁾

256t_c(VCLK)

0.5t_c(SPC)M+ 3

Pulse duration, SPICLK high (clock

polarity = 0)

0.5t_c(SPC)M– t_r(SPC)M– 3

t_w(SPCL)M

3⁽⁵⁾t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK low (clock

polarity = 1)

0.5t_c(SPC)M– t_f(SPC)M– 3

0.5t_c(SPC)M– t_r(SPC)M– 3

0.5t_c(SPC)M– 6

0.5t_c(SPC)M+ 3

Pulse duration, SPICLK low (clock

polarity = 0)

Pulse duration, SPICLK high (clock

polarity = 1)

4⁽⁵⁾t_{d(SPCH-SIMO)M}Delay time, SPISIMO valid before

SPICLK low (clock polarity = 0)

t_{d(SPCL-SIMO)M}Delay time, SPISIMO valid before

SPICLK high (clock polarity = 1)

5⁽⁵⁾t_{v(SPCL-SIMO)M}

0.5t_c(SPC)M– 6

Valid time, SPISIMO data valid after

SPICLK low (clock polarity = 0)

0.5t_c(SPC)M– t_f(SPC)– 4

0.5t_c(SPC)M– t_r(SPC)– 4

t_f(SPC)+ 2.2

t_{v(SPCH-SIMO)M}Valid time, SPISIMO data valid after

SPICLK high (clock polarity = 1)

6⁽⁵⁾t_{su(SOMI-SPCL)M}Setup time, SPISOMI before SPICLK

low (clock polarity = 0)

t_{su(SOMI-SPCH)M}Setup time, SPISOMI before SPICLK

high (clock polarity = 1)

7⁽⁵⁾t_{h(SPCL-SOMI)M}Hold time, SPISOMI data valid after

SPICLK low (clock polarity = 0)

t_r(SPC)+ 2.2

t_{h(SPCH-SOMI)M}Hold time, SPISOMI data valid after

SPICLK high (clock polarity = 1)

8⁽⁶⁾t_C2TDELAY

Setup time CS active

until SPICLK high

(clock polarity = 0)

CSHOLD = 0 C2TDELAY*t_c(VCLK)+ 2*t_c(VCLK)

- t_f(SPICS)+ t_r(SPC)– 7

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)+ 5.5

CSHOLD = 1 C2TDELAY*t_c(VCLK)+ 3*t_c(VCLK)

- t_f(SPICS)+ t_r(SPC)– 7

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)+ 5.5

Setup time CS active

until SPICLK low

CSHOLD = 0 C2TDELAY*t_c(VCLK)+ 2*t_c(VCLK)

- t_f(SPICS)+ t_f(SPC)– 7

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)+ 5.5

(clock polarity = 1)

CSHOLD = 1 C2TDELAY*t_c(VCLK)+ 3*t_c(VCLK)

- t_f(SPICS)+ t_f(SPC)– 7

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)+ 5.5

9⁽⁶⁾t_T2CDELAY

Hold time SPICLK low until CS inactive

(clock polarity = 0)

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_f(SPC)+ t_r(SPICS)- 7

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_f(SPC)+ t_r(SPICS)+ 11

Hold time SPICLK high until CS

inactive (clock polarity = 1)

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_r(SPC)+ tr(SPICS) - 7

0.5*t_c(SPC)M+

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_r(SPC)+ t_r(SPICS)+ 11

t_SPIENA

SPIENAn Sample point

(C2TDELAY+1) * t_c(VCLK)

t_f(SPICS)– 29

(C2TDELAY+1)*t_c(VCLK)

t_SPIENAW

SPIENAn Sample point from write to

buffer

(C2TDELAY+2)*t_c(VCLK)

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.

(2) t_c(VCLK)= interface clock cycle time = 1 / f_(VCLK)

(3) For rise and fall timings, see Table 4-5.

(4) When the SPI is in Master mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_c(VCLK)≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(VCLK)≥ 40ns.

The external load on the SPICLK pin must be less than 60pF.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

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SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISIMO

Master Out Data Is Valid

Master In Data

Must Be Valid

SPISOMI

Figure 6-19. SPI Master Mode External Timing (CLOCK PHASE = 0)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

SPIENAn

Figure 6-20. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)

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Table 6-39. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO

= output, and SPISOMI = input)^(1)(2)(3)

NO.

Parameter

MIN

MAX

Unit

(4)

t_c(SPC)M

Cycle time, SPICLK

256t_c(VCLK)

0.5t_c(SPC)M+ 3

2⁽⁵⁾t_w(SPCH)M

t_w(SPCL)M

3⁽⁵⁾t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK high (clock

polarity = 0)

0.5t_c(SPC)M– t_r(SPC)M– 3

Pulse duration, SPICLK low (clock

polarity = 1)

0.5t_c(SPC)M– t_f(SPC)M– 3

0.5t_c(SPC)M– t_r(SPC)M– 3

0.5t_c(SPC)M– 6

0.5t_c(SPC)M+ 3

Pulse duration, SPICLK low (clock

polarity = 0)

Pulse duration, SPICLK high (clock

polarity = 1)

4⁽⁵⁾t_{v(SIMO-SPCH)M}

Valid time, SPICLK high after

SPISIMO data valid (clock polarity =

t_{v(SIMO-SPCL)M}

Valid time, SPICLK low after

0.5t_c(SPC)M– 6

SPISIMO data valid (clock polarity =

5⁽⁵⁾t_{v(SPCH-SIMO)M}

t_{v(SPCL-SIMO)M}

6⁽⁵⁾t_{su(SOMI-SPCH)M}

t_{su(SOMI-SPCL)M}

7⁽⁵⁾t_{v(SPCH-SOMI)M}

t_{v(SPCL-SOMI)M}

Valid time, SPISIMO data valid after

SPICLK high (clock polarity = 0)

0.5t_c(SPC)M– t_r(SPC)– 4

Valid time, SPISIMO data valid after

SPICLK low (clock polarity = 1)

0.5t_c(SPC)M– t_f(SPC)– 4

Setup time, SPISOMI before

SPICLK high (clock polarity = 0)

t_r(SPC)+ 2.2

t_f(SPC)+ 2.2

Setup time, SPISOMI before

SPICLK low (clock polarity = 1)

Valid time, SPISOMI data valid after

SPICLK high (clock polarity = 0)

Valid time, SPISOMI data valid after

SPICLK low (clock polarity = 1)

8⁽⁶⁾t_C2TDELAY

Setup time CS

active until SPICLK

high (clock polarity =

CSHOLD = 0

CSHOLD = 1

CSHOLD = 0

CSHOLD = 1

0.5*t_c(SPC)M

0.5*t_c(SPC)M+

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)+ 5.5

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)– 7

0.5*t_c(SPC)M

0.5*t_c(SPC)M+

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)+ 5.5

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_r(SPC)– 7

Setup time CS

active until SPICLK

low (clock polarity =

0.5*t_c(SPC)M

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)– 7

(C2TDELAY+2) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)+ 5.5

0.5*t_c(SPC)M

0.5*t_c(SPC)M+

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)+ 5.5

(C2TDELAY+3) * t_c(VCLK)

t_f(SPICS)+ t_f(SPC)– 7

9⁽⁶⁾t_T2CDELAY

Hold time SPICLK low until CS

inactive (clock polarity = 0)

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPC)+ t_r(SPICS)

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPC)+ t_r(SPICS)

Hold time SPICLK high until CS

inactive (clock polarity = 1)

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPC)+ t_r(SPICS)

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPC)+ t_r(SPICS)

10 t_SPIENA

SPIENAn Sample Point

(C2TDELAY+1)* t_c(VCLK)

t_f(SPICS)– 29

(C2TDELAY+1)*t_c(VCLK)

11 t_SPIENAW

SPIENAn Sample point from write to

buffer

(C2TDELAY+2)*t_c(VCLK)

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2) t_c(VCLK)= interface clock cycle time = 1 / f_(VCLK)

(3) For rise and fall timings, see the Table 4-5.

(4) When the SPI is in Master mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_c(VCLK)≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(VCLK)≥ 40ns.

The external load on the SPICLK pin must be less than 60pF.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

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SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

Master Out Data Is Valid

Data Valid

SPISIMO

SPISOMI

Master In Data

Must Be Valid

Figure 6-21. SPI Master Mode External Timing (CLOCK PHASE = 1)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

SPIENAn

Figure 6-22. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)

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6.12.5 SPI Slave Mode I/O Timings

Table 6-40. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =

input, and SPISOMI = output)^(1)(2)(3)(4)

NO.

Parameter

t_c(SPC)S

MIN

MAX

Unit

Cycle time, SPICLK⁽⁵⁾

2⁽⁶⁾

t_w(SPCH)S

t_w(SPCL)S

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

3⁽⁶⁾

4⁽⁶⁾

t_w(SPCL)S

t_w(SPCH)S

t_{d(SPCH-SOMI)S}

Delay time, SPISOMI valid after SPICLK high (clock

polarity = 0)

t_rf(SOMI)+ 20

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

t_{su(SIMO-SPCL)S}

t_{su(SIMO-SPCH)S}

t_{h(SPCL-SIMO)S}

t_{h(SPCH-SIMO)S}

t_{d(SPCL-SENAH)S}

t_{d(SPCH-SENAH)S}

t_{d(SCSL-SENAL)S}

Delay time, SPISOMI valid after SPICLK low (clock polarity

= 1)

5⁽⁶⁾

6⁽⁶⁾

7⁽⁶⁾

Hold time, SPISOMI data valid after SPICLK high (clock

polarity =0)

Hold time, SPISOMI data valid after SPICLK low (clock

polarity =1)

Setup time, SPISIMO before SPICLK low (clock polarity =

Setup time, SPISIMO before SPICLK high (clock polarity =

Hold time, SPISIMO data valid after SPICLK low (clock

polarity = 0)

Hold time, SPISIMO data valid after S PICLK high (clock

polarity = 1)

Delay time, SPIENAn high after last SPICLK low (clock

polarity = 0)

1.5t_c(VCLK)

t_f(ENAn)

2.5t_c(VCLK)+t_r(ENAn)

Delay time, SPIENAn high after last SPICLK high (clock

polarity = 1)

2.5t_c(VCLK)+ t_r(ENAn)

Delay time, SPIENAn low after SPICSn low (if new data

has been written to the SPI buffer)

t_c(VCLK)+t_f(ENAn)+27

(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.

(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S≥ (PS + 1) t_c(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3) For rise and fall timings, see Table 4-5.

(4) t_c(VCLK)= interface clock cycle time = 1 /f_(VCLK)

(5) When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_c(VCLK)≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)S= 2t_c(VCLK)≥ 40ns.

(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISOMI Data Is Valid

SPISOMI

SPISIMO

SPISIMO Data

Must Be Valid

Figure 6-23. SPI Slave Mode External Timing (CLOCK PHASE = 0)

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPIENAn

SPICSn

Figure 6-24. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)

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Table 6-41. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =

input, and SPISOMI = output)^(1)(2)(3)(4)

NO. Parameter

t_c(SPC)S

2⁽⁶⁾t_w(SPCH)S

t_w(SPCL)S

3⁽⁶⁾t_w(SPCL)S

t_w(SPCH)S

MIN

MAX

Unit

Cycle time, SPICLK⁽⁵⁾

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

4⁽⁶⁾t_{d(SOMI-SPCL)S}

Dealy time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

t_rf(SOMI)+ 20

t_{d(SOMI-SPCH)S}

5⁽⁶⁾t_{h(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

Delay time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity =0)

Hold time, SPISOMI data valid after SPICLK low (clock

polarity =1)

6⁽⁶⁾t_{su(SIMO-SPCH)S}Setup time, SPISIMO before SPICLK high (clock

polarity = 0)

t_{su(SIMO-SPCL)S}Setup time, SPISIMO before SPICLK low (clock polarity

= 1)

7⁽⁶⁾t_{v(SPCH-SIMO)S}

High time, SPISIMO data valid after SPICLK high

(clock polarity = 0)

t_{v(SPCL-SIMO)S}

High time, SPISIMO data valid after SPICLK low (clock

polarity = 1)

t_{d(SPCH-SENAH)S}Delay time, SPIENAn high after last SPICLK high

(clock polarity = 0)

1.5t_c(VCLK)

t_f(ENAn)

t_c(VCLK)

2.5t_c(VCLK)+t_r(ENAn)+ 22

t_c(VCLK)+t_f(ENAn)+ 27

t_{d(SPCL-SENAH)S}Delay time, SPIENAn high after last SPICLK low (clock

polarity = 1)

t_{d(SCSL-SENAL)S}Delay time, SPIENAn low after SPICSn low (if new data

has been written to the SPI buffer)

t_{d(SCSL-SOMI)S}

Delay time, SOMI valid after SPICSn low (if new data

has been written to the SPI buffer)

2t_c(VCLK)+t_rf(SOMI)+ 28

(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3) For rise and fall timings, see Table 4-5.

(4) t_c(VCLK)= interface clock cycle time = 1 /f_(VCLK)

(5) When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_c(VCLK)≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)S= 2t_c(VCLK)≥ 40ns.

(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISOMI

SPISOMI Data Is Valid

SPISIMO Data

Must Be Valid

SPISIMO

Figure 6-25. SPI Slave Mode External Timing (CLOCK PHASE = 1)

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPIENAn

SPICSn

SPISOMI

Slave Out Data Is Valid

Figure 6-26. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)

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6.13 Ethernet Media Access Controller

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the

network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps

in either half- or full-duplex mode, with hardware flow control and quality of service (QoS) support.

The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY

configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the device through a custom interface that allows

efficient data transmission and reception. This custom interface is referred to as the EMAC control

module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to

multiplex and control interrupts.

6.13.1 Ethernet MII Electrical and Timing Specifications

MII_RX_CLK

MII_RXD[3:0]

MII_RX_DV

MII_RX_ER

VALID

Figure 6-27. MII Receive Timing

Table 6-42. Timing Requirements for EMAC MII Receive

NO.

MIN

MAX UNIT

t_{su(MIIRXD - MIIRXCLKH)}

t_{su(MIIRXDV - MIIRXCLKH)}

t_{su(MIIRXER - MIIRXCLKH)}

t_{h(MIIRXCLKH - MIIRXD)}

t_{h(MIIRXCLKH - MIIRXDV)}

t_{h(MIIRXCLKH - MIIRXER)}

Setup time, MII_RXD[3:0] before MII_RX_CLK rising edge

Setup time, MII_RX_DV before MII_RX_CLK rising edge

Setup time, MII_RX_ER before MII_RX_CLK rising edge

Hold time, MII_RXD[3:0] valid after MII_RX_CLK rising edge

Hold time, MII_RX_DV valid after MII_RX_CLK rising edge

Hold time, MII_RX_ER valid after MII_RX_CLK rising edge

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MII_TX_CLK

MII_TXD[3:0]

MII_TXEN

VALID

Figure 6-28. MII Transmit Timing

Table 6-43. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit

NO.

PARAMETER

MIN

MAX UNIT

t_{d(MIIRXCLKH - MIITXD)}

t_{d(MIIRXCLKH - MIITXEN)}

Delay time, MII_TX_CLK rising edge to MII_TXD[3:0] valid

Delay time, MII_TX_CLK rising edge to MII_TXEN valid

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6.13.2 Ethernet RMII Electrical and Timing Specifications

RMII_REFCLK

RMII_TXEN

RMII_TXD[1:0]

RMII_RXD[1:0]

RMII_CRS_DV

RMII_RX_ER

Figure 6-29. RMII Timing Diagram

Table 6-44. Timing Requirements for EMAC RMII Receive and RMII_REFCLK

NO.

MIN

NOM

MAX UNIT

t_c(REFCLK)

Cycle time, RMII_REFCLK

t_w(REFCLKH)

t_w(REFCLKL)

t_{su(RXD-REFCLK)}

t_{h(REFCLK-RXD)}

Pulse width, RMII_REFCLK high

Pulse width, RMII_REFCLK low

Input setup time, RMII_RXD[1:0] valid before RMII_REFCLK high

Input hold time, RMII_RXD[1:0] valid after RMII_REFCLK high

t_{su(CRSDV-REFCLK)}Input setup time, RMII_CRS_DV valid before RMII_REFCLK high

t_{h(REFCLK-CRSDV)}Input hold time, RMII_CRS_DV valid after RMII_REFCLK high

t_{su(RXER-REFCLK)}Input setup time, RMII_RX_ER valid before RMII_REFCLK high

t_{h(REFCLK-RXER)}

Input hold time, RMII_RX_ER valid after RMII_REFCLK high

Table 6-45. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit

NO.

PARAMETER

MIN

MAX

UNIT

Output delay time, RMII_REFCLK high to RMII_TXD[1:0] invalid

Output delay time, RMII_REFCLK high to RMII_TXD[1:0] valid

Output delay time, RMII_REFCLK high to RMII_TXEN invalid

Output delay time, RMII_REFCLK high to RMII_TXEN valid

t_{d(REFCLK-TXD)}

t_{d(REFCLK-TXEN)}

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6.13.3 Management Data Input/Output (MDIO)

MDCLK

MDIO

(input)

Figure 6-30. MDIO Input Timing

Table 6-46. MDIO Input Timing Requirements

NO.

Parameter

Value

Unit

MIN

400

180

MAX

tc(MDCLK)

Cycle time, MDCLK

tw(MDCLK)

Pulse duration, MDCLK high/low

Transition time, MDCLK

tt(MDCLK)

tsu(MDIO-MDCLKH)

Setup time, MDIO data input valid before MDCLK

High

12⁽¹⁾

th(MDCLKH-MDIO)

Hold time, MDIO data input valid after MDCLK

High

(1) This is a discrepancy to IEEE 802.3, but is compatible with many PHY devices.

MDCLK

MDIO

(output)

Figure 6-31. MDIO Output Timing

Table 6-47. MDIO Output Timing Requirements

NO.

Parameter

Value

Unit

MIN

400

MAX

tc(MDCLK)

Cycle time, MDCLK

td(MDCLKL-MDIO)

Delay time, MDCLK low to MDIO data output

valid

100

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7 Applications, Implementation, and Layout

NOTE

Information in the following sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes. Customers should validate and test

their design implementation to confirm system functionality.

7.1 TI Design or Reference Design

TI Designs Reference Design Library is a robust reference design library spanning analog, embedded

processor, and connectivity. Created by TI experts to help you jump start your system design, all TI

Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.

Search and download designs at TIDesigns.

210

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8 Device and Documentation Support

8.1 Device Support

8.1.1 Development Support

Texas Instruments (TI) offers an extensive line of development tools for the Hercules™ Safety generation

of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm

implementations, and fully integrate and debug software and hardware modules.

The following products support development of Hercules™-based applications:

Software Development Tools

•

Code Composer Studio™ Integrated Development Environment (IDE)

–

C/C++ Compiler

Code generation tools

Assembler/Linker

Cycle Accurate Simulator

•

Application algorithms

Sample applications code

Hardware Development Tools

•

Development and evaluation boards

JTAG-based emulators - XDS100 v2, XDS200, XDS560™ v2 emulator

Flash programming tools

Power supply

Documentation and cables

8.1.2 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

devices. Each commercial family member has one of three prefixes: TMX, TMP, or TMS. These prefixes

represent evolutionary stages of product development from engineering prototypes (TMX) through fully

qualified production devices (TMS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device's electrical

specifications.

Final silicon die that conforms to the device's electrical specifications but has not completed

quality and reliability verification.

Fully-qualified production device.

TMX and TMP devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices have been characterized fully, and the quality and reliability of the device have been

demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production

system because their expected end-use failure rate still is undefined. Only qualified production devices are

to be used.

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Figure 8-1 shows the numbering and symbol nomenclature for the TMS570LC5357-EP.

Full Part #

TMS

TMX

570

LC 43

GWT EP

Orderable Part #

Prefix: TM

TMS = Fully Qualified

TMP = Prototype

TMX = Samples

Core Technology:

570 = Cortex R5F

Architecture:

LC = Dual CPUs in Lockstep with caches

(not included in orderable part #)

Flash Memory Size:

43 = 4MB

RAM Size:

5 = 512KB

Peripheral Set:

7 = FlexRay, Ethernet

Die Revision:

A = 1st Die Revision

B = 2nd Die Revision

Package Type:

GWT = 337 BGA Package

Temperature Range:

EP = –55^oC to 125^oC (TJ)

Figure 8-1. TMS570LC5357-EP Device Numbering Conventions

212

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8.2 Documentation Support

8.2.1 Related Documentation from Texas Instruments

The following documents describe the TMS570LC4357 microcontroller..

SPNU563

TMS570LC43x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual

details the integration, the environment, the functional description, and the programming

models for each peripheral and subsystem in the device.

SPNZ180

SPNZ232

TMS570LC4357 Microcontroller, Silicon Revision A, Silicon Errata describes the usage

notes and known exceptions to the functional specifications for the device silicon revision(s).

TMS570LC4x Microcontroller, Silicon Revision B, Silicon Errata describes the usage

notes and known exceptions to the functional specifications for the device silicon revision(s).

8.2.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the

upper right corner, click on Alert me to register and receive a weekly digest of any product information that

has changed. For change details, review the revision history included in any revised document.

8.2.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help —

straight from the experts. Search existing answers or ask your own question to get the quick design help

you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications

and do not necessarily reflect TI's views; see TI's Terms of Use.

8.3 Trademarks

Hercules, Code Composer Studio, XDS560, E2E are trademarks of Texas Instruments.

ETM is a trademark of ARM Limited.

ARM, Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere.

CoreSight is a trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights

reserved..

All other trademarks are the property of their respective owners.

8.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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8.6 Device Identification

8.6.1 Device Identification Code Register

The device identification code register is memory mapped to address FFFF FFF0h and identifies several

aspects of the device including the silicon version. The details of the device identification code register are

provided in Table 8-1. The device identification code register value for this device is:

•

Rev A = 0x8044AD05

Rev B = 0x8044AD0D

CP-15

R-1

TECH

R-0

UNIQUE ID

R-00000000100010

I/O

PERIPH

RAM

ECC

TECH

R-101

FLASH ECC

R-10

VERSION

R-00000

VOLTAGE PARITY

R-0 R-1

R-1

R-0

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 8-2. Device ID Bit Allocation Register

Table 8-1. Device ID Bit Allocation Register Field Descriptions

Bit

Field

Value

Description

CP15

Indicates the presence of coprocessor 15

CP15 present

30-17

UNIQUE ID

100011

Silicon version (revision) bits.

This bitfield holds a unique number for a dedicated device configuration (die).

16-13

TECH

Process technology on which the device is manufactured.

0101

F021

I/O VOLTAGE

I/O voltage of the device.

I/O are 3.3v

PERIPHERAL

PARITY

Peripheral Parity

Parity on peripheral memories

Flash ECC

10-9

FLASH ECC

RAM ECC

Program memory with ECC

Indicates if RAM ECC is present.

ECC implemented

7-3

2-0

REVISION

101

Revision of the Device.

The platform family ID is always 0b101

214

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8.6.2 Die Identification Registers

The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit die id with the

information as listed in Table 8-2.

Table 8-2. Die-ID Registers

Item

X Coord. on Wafer

Y Coord. on Wafer

Wafer #

# of Bits

Bit Location

0xFFFFFF7C[11:0]

0xFFFFFF7C[23:12]

0xFFFFFF7C[31:24]

0xFFFFFF80[23:0]

0xFFFFFF80[31:24]

Lot #

Reserved

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8.7 Module Certifications

The following communications modules have received certification of adherence to a standard.

216

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8.7.1 FlexRay Certifications

NOTE: GWT is identical to ZWT package with the exception of the use of lead solder balls.

Figure 8-3. FlexRay Certification for GWT Package

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8.7.2 DCAN Certification

Figure 8-4. DCAN Certification

218

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8.7.3 LIN Certification

8.7.3.1 LIN Master Mode

Figure 8-5. LIN Certification - Master Mode

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8.7.3.2 LIN Slave Mode - Fixed Baud Rate

Figure 8-6. LIN Certification - Slave Mode - Fixed Baud Rate

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8.7.3.3 LIN Slave Mode - Adaptive Baud Rate

Figure 8-7. LIN Certification - Slave Mode - Adaptive Baud Rate

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9 Mechanical Data

9.1 Packaging Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and

revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

222

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PACKAGE OPTION ADDENDUM

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30-Apr-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TMS5704357BGWTEP

V62/18606-01XF

ACTIVE

NFBGA

GWT

337

Non-RoHS

& Green

SNPB

Level-3-220C-168 HR

-55 to 125

TMS570

4357BGWTEP

Samples

ACTIVE

GWT

Non-RoHS

& Green

SNPB

TMS570

4357BGWTEP

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

30-Apr-2023

OTHER QUALIFIED VERSIONS OF TMS570LC4357-EP :

Catalog : TMS570LC4357

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

Name

Type

(mm) (µm) (mm) (mm) (mm)

TMS5704357BGWTEP

V62/18606-01XF

GWT

NFBGA

337

6 X 15

150

315 135.9 7620

17.5 15.45

Pack Materials-Page 1

PACKAGE OUTLINE

GWT0337A

NFBGA - 1.4 mm max height

PLASTIC BALL GRID ARRAY

16.1

15.9

BALL A1

CORNER

16.1

15.9

0.95

0.84

0.23

0.15

SEATING PLANE

0.12 C

1.40

1.19

14.4 TYP

SYMM

0.45

0.35

(0.8)

SYMM

14.4 TYP

0.55

337X

0.45

0.15

0.05

C A B

10 11 12 13 14 15 16 17 18 19

0.8 TYP

4229175/A 11/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

GWT0337A

NFBGA - 1.4 mm max height

PLASTIC BALL GRID ARRAY

(0.8) TYP

337X ( 0.4)

(0.8) TYP

12 13

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 7X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

EXPOSED METAL

(

0.4)

(

0.4)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

EXPOSED METAL

METAL EDGE

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4229175/A 11/2022

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com

EXAMPLE STENCIL DESIGN

GWT0337A

NFBGA - 1.4 mm max height

PLASTIC BALL GRID ARRAY

(0.8) TYP

337X ( 0.4)

(0.8) TYP

12 13

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.150 mm THICK STENCIL

SCALE: 7X

4229175/A 11/2022

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TMS570LC4357-EP [TI]

相关型号：

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TMS570LS0914

TMS570LS10106

TMS570LS10106BSPGEQR

TMS570LS10116

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