TMS5700332PZQQ1 [TI]
Flash options from 256 KB to 4 MB and performance from 80 MHz to 300 MHz;
| 型号： | TMS5700332PZQQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Flash options from 256 KB to 4 MB and performance from 80 MHz to 300 MHz |
| 文件： | 总155页 (文件大小：2867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS570LS3134
TMS570LS2134
TMS570LS2124
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SPNS165–SEPTEMBER 2011
TMS570LSxxx4 16/32-Bit RISC Flash Microcontroller
Check for Samples: TMS570LS3134
1 TMS570LSxxx4 16/32-Bit RISC Flash Microcontroller
1.1 Features
1
• High-Performance Microcontroller for Safety
• Multiple Communication Interfaces
– 10/100 Mbps Ethernet MAC (EMAC)
Critical Applications
– Dual CPU’s running in lockstep
– ECC on flash and RAM interfaces
•
•
IEEE 802.3 compliant (3.3V-I/O only)
Supports MII and MDIO
– Built-In Self Test for CPU and on-chip RAMs
– Error Signaling Module with Error Pin
– Voltage and Clock Monitoring
– Three CAN Controllers (DCAN)
•
•
64 mailboxes with parity protection each
Compliant to CAN protocol version 2.0B
– Inter-Integrated Circuit (I2C)
• ARM® Cortex™ – R4F 32-bit RISC CPU
– Efficient 1.6DMIPS/MHz with 8-stage pipeline
– Three Multi-buffered Serial Peripheral
– Floating-Point Unit with Single/Double
Interfaces (MibSPI)
Precision
•
128 Words with Parity Protection each
– 12-Region Memory Protection Unit
– Open Architecture with 3rd Party Support
• Operating Conditions
– Two Standard Serial Peripheral Interfaces
(SPI)
– Local Interconnect Network Interface (LIN)
Controller
– Up to 180MHz System Clock
•
Compliant to LIN protocol version 2.1
– Core Supply Voltage (VCC): 1.2V nominal
– I/O Supply Voltage (VCCIO): 3.3V nominal
• Integrated Memory
– Up to 3MB Program Flash with ECC
– Up to 256KB RAM with ECC
– 64KB Flash for emulated EEPROM
• 16- bit External Memory Interface
• Common Platform Architecture
– Consistent memory map across family
– Real-Time Interrupt Timer (RTI) OS Timer
– 96-channel Vectored Interrupt Module (VIM)
– 2-channel Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 16 Channels and 32 Control Packets
– Parity protection for control packet RAM
– DMA Accesses Protected by Dedicated MPU
– Standard Serial Communication Interface
(SCI)
• Two High-End Timer Modules (N2HET)
– N2HET1: 32 programmable channels
– N2HET2: 20 programmable channels
– 160 Word Instruction RAM with parity
protection each
– Each includes Hardware Angle Generator
– Dedicated Transfer Unit for each N2HET
(HTU)
• Two 10/12-bit Multi-Buffered ADC Modules
– ADC1: 24 channels
– ADC2: 16 channels
– 16 shared channels
– 64 result buffers with parity protection each
• Packages
• Frequency-Modulated Phase-Locked-Loop
(FMPLL) with Built-In Slip Detector
• Separate Non-Modulating PLL
– 144-pin Quad Flatpack (PGE) [Green]
– 337-Ball Grid Array (ZWT) [Green]
• IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight Components
• JTAG Security Module
• Trace and Calibration Capabilities
– Embedded Trace Macrocell (ETM-R4)
– Data Modification Module (DMM)
– RAM Trace Port (RTP)
– Parameter Overlay Module (POM)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative
Copyright © 2011, Texas Instruments Incorporated
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
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1.2 Applications
•
•
•
•
•
•
•
•
Braking systems (ABS and ESC)
Electric power steering (EPS)
HEV/EV inverter systems
Battery management systems
Active driver assistance systems
Aerospace and avionics
Railway communications
Off road vehicles
2
TMS570LSxxx4 16/32-Bit RISC Flash Microcontroller
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1.3 Description
The TMS570LSxxx4 is a high performance automotive grade microcontroller family for safety systems.
The safety architecture includes Dual CPUs in lockstep, CPU and Memory Built-In Self Test (BIST) logic,
ECC on both the Flash and the data SRAM, parity on peripheral memories, and loop back capability on
peripheral IOs.
The TMS570LSxxx4 integrates the ARM® Cortex™-R4F Floating Point CPU which offers an efficient 1.6
DMIPS/MHz, and has configurations which can run up to 180MHz providing up to 288 DMIPS. The device
supports the big-endian [BE32] format.
The TMS570LSxxx4 has up to 3MB integrated Flash and up to 256KB data RAM configurations with
single bit error correction and double bit error detection. The flash memory on this device is a nonvolatile,
electrically erasable and programmable memory implemented with a 64-bit-wide data bus interface. The
flash operates on a 3.3V supply input (same level as I/O supply) for all read, program and erase
operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180MHz.
The SRAM supports single-cycle read/write accesses in byte, halfword, and word modes.
The TMS570LSxxx4 device features peripherals for real-time control-based applications, including two
Next Generation High End Timer (N2HET) timing coprocessors with up to 44 total IO terminals and a
12-bit Analog-to-Digital converter supporting up to 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses. A High End Timer
Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to or from main
memory. A Memory Protection Unit (MPU) is built into the HET-TU.
The device has two 12-bit-resolution MibADCs with 24 total channels and 64 words of parity protected
buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are
three separate groupings. Each sequence can be converted once when triggered or configured for
continuous conversion mode.
The device has multiple communication interfaces: three MibSPIs, up to two SPIs, one LIN, one SCI, three
DCANs, one I2C, one Ethernet. The SPI provides a convenient method of serial interaction for high-speed
communications between similar shift-register type devices. The LIN supports the Local Interconnect
standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero
(NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster
communication protocol that efficiently supports distributed real-time control with robust communication
rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and
harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or
multiplexed wiring. The Ethernet module supports MII and MDIO interfaces.
The I2C module is a multi-master communication module providing an interface between the
microcontroller and an I2C compatible device via the I2C serial bus. The I2C supports both 100 Kbps and
400 Kbps speeds.
The frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply the external
frequency reference to a higher frequency for internal use. The FMPLL provides one of the seven possible
clock source inputs to the global clock module (GCM). The GCM module manages the mapping between
the available clock sources and the device clock domains.
The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock on the ECLK pin/ball. The ECLK frequency is a user-programmable ratio of the peripheral
interface clock (VCLK) frequency. This low frequency output can be monitored externally as an indicator of
the device operating frequency.
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TMS570LSxxx4 16/32-Bit RISC Flash Microcontroller
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The Direct Memory Access Controller (DMA) has 16 channels, 32 control packets and parity protection on
its memory. A Memory Protection Unit (MPU) is built into the DMA to protect memory against erroneous
transfers.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or
external Error pin/ball is triggered when a fault is detected. The nERROR can be monitored externally as
an indicator of a fault condition in the microcontroller.
The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous
memories or other slave devices.
Several interfaces are implemented to enhance the debugging capabilities of application code. In addition
to the built in ARM Cortex™-R4F CoreSight™ debug features. An External Trace Macrocell (ETM)
provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port
Module (RTP) is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU
or any other master. A Data Modification Module (DMM) gives the ability to write external data into the
device memory. Both the RTP and DMM have no or only minimum impact on the program execution time
of the application code. A Parameter Overlay Module (POM) can re-route Flash accesses to internal
memory or to the EMIF, thus avoiding the re-programming steps necessary for parameter updates in
Flash.
With integrated safety features and a wide choice of communication and control peripherals, the
TMS570LSxxx4 is an ideal solution for high performance real time control applications with safety critical
requirements.
4
TMS570LSxxx4 16/32-Bit RISC Flash Microcontroller
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1.4 Functional Block Diagram
Color Legend for Power Domains
RAM
Core/RAM
Core
always on
# 1
# 2
# 3
# 4
# 5
# 1
# 2
64K
3M
256K
64K RAM
with
Flash
with
ECC
# 3
64K
ECC
64K
ETM-R4
RTP
DMA
POM
DMM
HTU1
HTU2
EMAC
Dual Cortex-R4F
CPUs in Lockstep
Switched Central Resource Switched Central Resource Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
64 KB Flash
Peripheral Central Resource Bridge
SYS
CRC Switched Central Resource
for EEPROM
Emulation
with ECC
nPORRST
nRST
IOMM
ECLK
EMAC Slaves
nERROR
ESM
MDCLK
MDIO
PMM
VIM
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MIBSPI1_CLK
MDIO
DCAN1
MII_RXD[3:0]
MII_RXER
MII_TXD[3:0]
MII_TXEN
MII_TXCLK
MII_RXCLK
DCAN2
DCAN3
MII
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MII_CRS
MII_RXDV
MII_COL
MibSPI1
SPI2
RTI
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
EMIF_nWAIT
EMIF_CLK
DCC1
EMIF_CKE
SPI2_nCS[1:0]
SPI2_nENA
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[21:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
DCC2
EMIF
MibSPI3
SPI4
SPI4_CLK
EMIF_nWE
SPI4_SIMO
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
EMIF_nRAS
EMIF_nCAS
EMIF_nRW
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
MibSPI5
MibADC1
MibADC2
N2HET1 N2HET2 GIO
I2C
LIN_RX
LIN_TX
LIN
SCI
SCI_RX
SCI_TX
Figure 1-1. Functional Block Diagram
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TMS570LSxxx4 16/32-Bit RISC Flash Microcontroller
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1
TMS570LSxxx4 16/32-Bit RISC Flash
Microcontroller .......................................... 1
4.6 Clocks .............................................. 57
4.7 Clock Monitoring .................................... 65
1.1 Features .............................................. 1
1.2 Applications .......................................... 2
1.3 Description ........................................... 3
1.4 Functional Block Diagram ............................ 5
1.1 Device Configuration ................................. 7
Device Package and Terminal Functions ......... 10
4.8 Glitch Filters ........................................ 67
4.9 Device Memory Map ................................ 68
4.10 Flash Memory ...................................... 75
4.11 Tightly-Coupled RAM Interface Module ............ 78
4.12 Parity Protection for Accesses to peripheral RAMs
...................................................... 78
4.13 On-Chip SRAM Initialization and Testing ........... 80
4.14 External Memory Interface (EMIF) ................. 82
4.15 Vectored Interrupt Manager ........................ 89
4.16 DMA Controller ..................................... 92
4.17 Real Time Interrupt Module ........................ 94
4.18 Error Signaling Module ............................. 96
2
3
2.2 PGE QFP Package Pinout (144-Pin) ............... 10
2.3
ZWT BGA Package Ball-Map (337 Ball Grid Array)
...................................................... 11
2.4 Terminal Functions ................................. 12
Device Operating Conditions ....................... 40
3.1
Absolute Maximum Ratings Over Operating
4.19 Reset / Abort / Error Sources ..................... 100
Free-Air Temperature Range, ...................... 40
4.20 Digital Windowed Watchdog ...................... 102
4.21 Debug Subsystem ................................. 103
3.2
3.3
Device Recommended Operating Conditions ...... 40
Switching Characteristics over Recommended
5
Peripheral Information and Electrical
Operating Conditions for Clock Domains ........... 41
Specifications ......................................... 114
3.4 Wait States Required ............................... 41
3.5
5.1 Peripheral Legend ................................. 114
Power Consumption Over Recommended
5.2
Multi-Buffered 12bit Analog-to-Digital Converter
Operating Conditions ............................... 42
Input/Output Electrical Characteristics Over
..................................................... 114
3.6
5.3 General-Purpose Input/Output .................... 125
5.4 Enhanced High-End Timer (N2HET) .............. 126
5.5 Controller Area Network (DCAN) .................. 130
Recommended Operating Conditions .............. 43
3.7 Output Buffer Drive Strengths ...................... 43
3.8 Input Timings ....................................... 44
3.9 Output Timings ..................................... 45
3.10 Low-EMI Output Buffers ............................ 47
5.6
Local Interconnect Network Interface (LIN) ....... 131
Serial Communication Interface (SCI) ............ 132
5.7
5.8 Inter-Integrated Circuit (I2C) ...................... 133
5.9
Multi-Buffered / Standard Serial Peripheral Interface
4
System Information and Electrical Specifications
..................................................... 136
............................................................. 49
4.1 Device Power Domains ............................. 49
4.2 Voltage Monitor Characteristics .................... 50
5.10 Ethernet Media Access Controller ................ 148
6
Mechanical Data ...................................... 151
6.1 Thermal Data ...................................... 151
6.2 Packaging Information ............................ 151
4.3
Power Sequencing and Power On Reset .......... 51
4.4 Warm Reset (nRST) ................................ 53
4.5 ARM© Cortex-R4F™ CPU Information ............. 54
6
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1.1 Device Configuration
1.1.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g.,TMS570LS3137U). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
The figure below illustrates the numbering and symbol nomenclature for the TMS570LSxxx4 .
Full Part #
TMS
TMX
570
570
LS 31
31
3
3
4
4
A
A
ZWT
ZWT
Q
Q
Q1
Q1
R
R
Orderable Part #
Prefix: TM
TMS = Fully Qualified
TMP = Prototype
TMX = Samples
Core Technology:
570 = Cortex R4F
Architecture:
LS = Dual CPUs in Lockstep
(not included in orderable part #)
Flash Memory Size:
31 = 3MB
21 = 2MB
RAM Memory Size:
3 = 256kB
2 = 192kB
Peripheral Set:
4 = No FlexRay, no Ethernet
Die Revision:
Blank = Initial Die
A = 1st Die Revision
Package Type:
ZWT = 337 BGA Package
PGE = 144 Pin Package
Temperature Range:
Q = -40...+125oC
Quality Designator:
Q1 = Automotive
Shipping Options:
R = Tape and Reel
Figure 1-1. TMS570LSxxx4 Device Numbering Conventions
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1.1.2 Orderable Part Numbers
Table 1-1. Orderable Part Numbers
Orderable Part #
Part #
Flash
2MB
2MB
2MB
2MB
3MB
3MB
RAM
192kB
192kB
256kB
256kB
256kB
256kB
EMAC
FlexRay
TMX5702124APGEQQ1
TMX5702124AZWTQQ1
TMX5702134APGEQQ1
TMX5702134AZWTQQ1
TMS5703134APGEQQ1
TMX5703134AZWTQQ1
TMS570LS2124
TMS570LS2124
TMS570LS2134
TMS570LS2134
TMS570LS3134
TMS570LS3134
-
-
-
-
-
-
-
-
-
-
-
-
1.1.3 Device Identification
1.1.3.1 Device Identification Code Register
The device identification code register identifies several aspects of the device including the silicon version.
The details of the device identification code register are shown in Table 1-2. The device identification code
register value for this device is:
•
Rev 0 = 0x802AAD05
Figure 1-2. Device ID Bit Allocation Register
31
CP-15
R-1
30
29
13
28
27
26
25
24
23
22
21
20
19
3
18
17
16
TECH
R-0
UNIQUE ID
R-00000000010101
15
14
12
11
10
9
8
7
6
5
4
2
1
1
0
0
1
TECH
I/O
PERIPH FLASH ECC
RAM
ECC
VERSION
VOLT PARITY
AGE
R-101
R-0
R-1
R-10
R-1
R-00000
R-1
R-0
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8
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Table 1-2. Device ID Bit Allocation Register Field Descriptions
Bit
Field
Value
Description
31
CP15
Indicates the presence of coprocessor 15
CP15 present
1
30-17
UNIQUE ID
10101
Silicon version (revision) bits.
This bitfield holds a unique number for a dedicated device configuration (die).
16-13
12
TECH
Process technology on which the device is manufactured.
0101
0
F021
I/O VOLTAGE
I/O voltage of the device.
I/O are 3.3v
11
PERIPHERAL
PARITY
Peripheral Parity
1
10
1
Parity on peripheral memories
Flash ECC
10-9
8
FLASH ECC
RAM ECC
Program memory with ECC
Indicates if RAM memory ECC is present.
ECC implemented
7-3
2-0
REVISION
101
Revision of the Device.
The platform family ID is always 0b101
1.1.3.2 Die Identification Registers
The four die ID registers at addresses 0xFFFFE1F0, 0xFFFFE1F4, 0xFFFFE1F8 and FFFFE1FC form a
128-bit dieid with the information as shown in Table Table 1-3.
Table 1-3. Die-ID Registers
Item
X Coord. on Wafer
Y Coord. on Wafer
Wafer #
# of Bits
Bit Location
7..0
8
8
15..8
6
21..16
Lot #
24
82
45..22
Reserved
127..46
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2 Device Package and Terminal Functions
2.2 PGE QFP Package Pinout (144-Pin)
AD1IN[10] / AD2IN[10]
AD1IN[01]
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
nTRST
TDI
TDO
AD1IN[09] / AD2IN[09]
VCCAD
VSSAD
ADREFLO
ADREFHI
TCK
RTCK
VCC
VSS
nRST
nERROR
N2HET1[10]
ECLK
AD1IN[21] / AD2IN[05]
AD1IN[20] / AD2IN[04]
AD1IN[19] / AD2IN[03]
AD1IN[18] / AD2IN[02]
VCCIO
VSS
VSS
AD1IN[07]
AD1IN[0]
AD1IN[17] / AD2IN[01]
AD1IN[16] / AD2IN[0]
VCC
VCC
N2HET1[12]
N2HET1[14]
FRAYRX1
N2HET1[30]
CAN2TX
VSS
MIBSPI3NCS[0]
MIBSPI3NENA
MIBSPI3CLK
MIBSPI3SIMO
MIBSPI3SOMI
VSS
CAN2RX
MIBSPI1NCS[1]
LINRX
LINTX
FRAYTX1
VCCP
VSS
VCCIO
VCC
VCC
VSS
nPORRST
VCC
VSS
VCC
VSS
VSS
VCCIO
N2HET1[16]
N2HET1[18]
N2HET1[20]
FRAYTXEN1
VCC
N2HET1[15]
MIBSPI1NCS[2]
N2HET1[13]
N2HET1[06]
MIBSPI3NCS[1]
VSS
Figure 2-3. PGE QFP Package Pinout (144-Pin)
Note: Pins can have multiplexed functions. Only the default function is depicted in above diagram.
10
Device Package and Terminal Functions
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2.3 ZWT BGA Package Ball-Map (337 Ball Grid Array)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
AD1IN[15] AD1IN[22]
AD1IN[11]
/
AD2IN[11]
N2HET1 MIBSPI5 MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 N2HET1
SIMO[0]
DMM_
DATA[0]
AD1IN
[06]
19
18
17
16
15
14
13
12
11
VSS
VSS
TMS
CAN3RX AD1EVT
/
/
AD2IN[15] AD2IN[06]
VSSAD
VSSAD 19
[10]
NCS[0]
SIMO
NENA
CLK
[28]
AD1IN[08] AD1IN[14] AD1IN[13]
N2HET1 MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 N2HET1
SOMI[0]
DMM_
DATA[1]
AD1IN
[04]
AD1IN
[02]
VSS
TDI
TCK
TDO
nTRST
CAN3TX
NC
/
AD2IN[08] AD2IN[14] AD2IN[13]
/
/
VSSAD 18
AD1IN[09]
[08]
CLK
SOMI
NENA
[0]
AD1IN[10]
/
AD2IN[10]
EMIF_
ADDR[21]
EMIF_
nWE
MIBSPI5
SOMI[1]
DMM_
CLK
MIBSPI5 MIBSPI5 N2HET1
[31]
EMIF_
nCS[3]
EMIF_
nCS[2]
EMIF_
nCS[4]
EMIF_
nCS[0]
AD1IN
[05]
AD1IN
[03]
AD1IN
[01]
RST
NC
NC
/
AD2IN[09]
17
SIMO[3] SIMO[2]
AD1IN[23] AD1IN[12] AD1IN[19]
FRAY EMIF_
TXEN1 ADDR[20]
EMIF_
BA[1]
MIBSPI5
SIMO[1]
DMM_
NENA
MIBSPI5 MIBSPI5
SOMI[3] SOMI[2]
DMM_
SYNC
RTCK
NC
NC
NC
NC
/
/
AD2IN[07] AD2IN[12] AD2IN[03]
/
ADREFLO VSSAD 16
ADREFHI VCCAD 15
ETM
DATA[16] /
EMIF_
ETM
DATA[17] /
EMIF_
ETM
DATA[18] /
EMIF_
ETM
DATA[19] /
EMIF_
AD1IN[21] AD1IN[20]
FRAY
RX1
FRAY
TX1
EMIF_ ETM
ADDR[19] ADDR[18] DATA[06] DATA[05] DATA[04] DATA[03] DATA[02]
EMIF_
ETM
ETM
ETM
ETM
NC
NC
NC
/
AD2IN[05] AD2IN[04]
/
DATA[0]
DATA[1]
DATA[2]
DATA[3]
AD1IN[18]
/
AD2IN[02]
N2HET1
[26]
EMIF_ ETM
ADDR[17] ADDR[16] DATA[07]
EMIF_
AD1IN
[07]
AD1IN
[0]
nERROR
VCCIO
VCCIO
VCCIO
VCCIO
VCC
VCCIO
VCCIO
VCC
VCC
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCPLL
VCC
NC
NC
14
13
12
11
AD1IN[17] AD1IN[16]
/
AD2IN[01] AD2IN[0]
ETM
DATA[12] /
NC
N2HET1 N2HET1
[17]
EMIF_
ADDR[15]
EMIF_BA[0]
ETM
DATA[01]
/
NC
NC
NC
[19]
ETM
DATA[13] /
NC
N2HET1
[04]
EMIF_
ADDR[14]
EMIF_nOE
ETM
DATA[0]
MIBSPI5
NCS[3]
ECLK
VSS
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
NC
NC
NC
NC
ETM
ETME
TRACE
CTL
N2HET1 N2HET1
[14] [30]
EMIF_
ADDR[13]
DATA[14] /
EMIF_
nDQM[1]
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ETM
ETM
TRACE
CLKOUT
EMIF_
ADDR[12]
MIBSPI3
NCS[0]
DATA[15] /
EMIF_
nDQM[0]
10 CAN1TX CAN1RX
NC
GIOB[3] 10
ETM
DATA[08] /
EMIF_
ETM
TRACE
CLKIN
N2HET1
[27]
FRAY EMIF_
TXEN2 ADDR[11]
MIBSPI3 MIBSPI3
NENA
9
8
7
6
5
4
3
2
1
VCC
VCCIO
VCCIO
VCCIO
VCCIO
NC
9
8
7
6
5
4
3
2
1
CLK
ADDR[5]
ETM
DATA[09] /
EMIF_
ETM
FRAY
RX2
FRAY
TX2
EMIF_
ADDR[10]
MIBSPI3 MIBSPI3
SIMO
DATA[31] /
EMIF_
DATA[15]
VCCP
VCCIO
VCCIO
NC
SOMI
ADDR[4]
ETM
DATA[10] /
EMIF_
ETM
EMIF_
ADDR[9]
N2HET1
[09]
DATA[30] /
EMIF_
DATA[14]
nPORRST
LINRX
LINTX
NC
ADDR[3]
ETM
ETM
MIBSPI5
NCS[1]
EMIF_
ADDR[8]
N2HET1 MIBSPI5
[05] NCS[2]
DATA[11] /
EMIF_
ADDR[2]
DATA[29] /
EMIF_
DATA[13]
GIOA[4]
NC
VCCIO
VCCIO
FLTP2
VCCIO
FLTP1
VCC
VCC
VCCIO
VCCIO
NC
ETM
DATA[20] /
EMIF_
ETM
DATA[21] /
EMIF_
ETM
DATA[22] /
EMIF_
ETM
DATA[23] /
EMIF_
ETM
DATA[24] /
EMIF_
ETM
DATA[25] /
EMIF_
ETM
ETM
ETM
EMIF_ EMIF_
ADDR[7] ADDR[1]
MIBSPI3 N2HET1
[02]
DATA[26] /
EMIF_
DATA[10]
DATA[27] /
EMIF_
DATA[11]
DATA[28] /
EMIF_
DATA[12]
GIOA[0] GIOA[5]
N2HET1 N2HET1
NC
NCS[1]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
DATA[9]
EMIF_ EMIF_
ADDR[6] ADDR[0]
N2HET1 N2HET1
[21]
EMIF_
nCAS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
[16]
[12]
[23]
N2HET1 N2HET1 MIBSPI3
NCS[3]
SPI2
NENA
N2HET1 MIBSPI1 MIBSPI1
[11] NCS[1] NCS[2]
MIBSPI1
NCS[3]
EMIF_
CLK
EMIF_
CKE
N2HET1
[25]
SPI2
NCS[0]
EMIF_
nWAIT
EMIF_
nRAS
N2HET1
[06]
GIOA[6]
NC
NC
[29]
[22]
MIBSPI3
NCS[2]
SPI2
SOMI
KELVIN_
GND
N2HET1 N2HET1 MIBSPI1
[20]
N2HET1
[01]
VSS
GIOA[1]
SPI2 CLK GIOB[2] GIOB[5] CAN2TX GIOB[6] GIOB[1]
GIOB[0]
TEST
VSS
[13]
NCS[0]
SPI2
SIMO
N2HET1
[18]
N2HET1 N2HET1
[24]
N2HET1 N2HET1
[07]
VSS
A
VSS
B
GIOA[2]
C
GIOA[3] GIOB[7] GIOB[4] CAN2RX
OSCIN
K
OSCOUT GIOA[7]
NC
R
VSS
V
VSS
W
[15]
[03]
D
E
F
G
H
J
L
M
N
P
T
U
Figure 2-4. ZWT Package Pinout. Top View
Note: Balls can have multiplexed functions. Only the default function is depicted in above diagram, except
for the EMIF signals that are multiplexed with ETM signals.
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2.4 Terminal Functions
Section 2.4.1 and Section 2.4.2 identify the external signal names, the associated pin/ball numbers along
with the mechanical package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether
the pin/ball has any internal pullup/pulldown, whether the pin/ball can be configured as a GIO, and a
functional pin/ball description. The first signal name listed is the primary function for that terminal. The
signal name in Bold is the function being described. Refer to the I/O Multiplexing Module (IOMM) User
Guide for information on how to select between different multiplexed functions.
NOTE
All I/O signals except nRST are configured as inputs while nPORRST is low and immediately
after nPORRST goes High.
All output-only signals are configured as inputs while nPORRST is low, and are configured
as outputs immediately after nPORRST goes High.
While nPORRST is low, the input buffers are disabled, and the output buffers are tri-stated.
2.4.1 PGE Package
2.4.1.1 Multi-Buffered Analog-to-Digital Converters (MibADC)
Table 2-4. PGE Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
ADREFHI(1)
66
Input
-
-
ADC high reference
supply
ADREFLO(1)
VCCAD(1)
VSSAD(1)
67
69
68
86
Input
Power
Ground
ADC low reference supply
Operating supply for ADC
AD1EVT/MII_RX_ER
Input Pull Down Programmable, ADC1 event trigger input,
20uA or GIO
MIBSPI3NCS[0]/AD2EVT
55
I/O
Pull Up
Programmable, ADC2 event trigger input,
20uA
or GIO
AD1IN[0]
60
71
73
74
76
78
80
61
Input
-
-
ADC1 analog input
AD1IN[01]
AD1IN[02]
AD1IN[03]
AD1IN[04]
AD1IN[05]
AD1IN[06]
AD1IN[07]
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
12 Device Package and Terminal Functions
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Table 2-4. PGE Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2) (continued)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
AD1IN[08] / AD2IN[08]
AD1IN[09] / AD2IN[09]
AD1IN[10] / AD2IN[10]
AD1IN[11] / AD2IN[11]
AD1IN[12] / AD2IN[12]
AD1IN[13] / AD2IN[13]
AD1IN[14] / AD2IN[14]
AD1IN[15] / AD2IN[15]
AD1IN[16] / AD2IN[0]
AD1IN[17] / AD2IN[01]
AD1IN[18] / AD2IN[02]
AD1IN[19] / AD2IN[03]
AD1IN[20] / AD2IN[04]
AD1IN[21] / AD2IN[05]
AD1IN[22] / AD2IN[06]
AD1IN[23] / AD2IN[07]
83
70
72
75
77
79
82
85
58
59
62
63
64
65
81
84
Input
-
-
ADC1/ADC2 shared
analog inputs
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2.4.1.2 Enhanced High-End Timer Modules (N2HET)
Table 2-5. PGE Enhanced High-End Timer Modules (N2HET)
Terminal
Signal Default Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
N2HET1[0]/SPI4CLK
25
23
30
24
36
31
38
33
106
35
118
6
I/O
Pull Down
Programmable,
20uA
N2HET1
capture
compare, or GIO.
time
or
input
output
N2HET1[01]/SPI4NENA/N2HET2[8]
N2HET1[02]/SPI4SIMO
Each terminal has
suppression filter that
ignores input pulses
smaller
programmable duration.
a
N2HET1[03]/SPI4NCS[0]/N2HET2[10]
N2HET1[04]
N2HET1[05]/SPI4SOMI/N2HET2[12]
N2HET1[06]/SCIRX
than
a
N2HET1[07]/N2HET2[14]
N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/
N2HET1[09]/N2HET2[16]
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
N2HET1[12]/MII_CRS
124
39
125
41
139
130
140
40
141
15
96
91
37
92
4
N2HET1[13]/SCITX
N2HET1[14]
N2HET1[15]/MIBSPI1NCS[4]
N2HET1[16]
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
N2HET1[18]
MIBSPI1NCS[2]/N2HET1[19]/MDIO
N2HET1[20]
N2HET1[22]
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
N2HET1[26]/MII_RXD[1]
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
N2HET1[28]/MII_RXCLK/MII_RX_AVCLK4
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
N2HET1[30]/MII_RX_DV
107
3
127
54
9
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]
GIOA[2]/N2HET2[0]
I/O
Pull Down
Programmable,
20uA
N2HET2
capture
time
or
input
output
GIOA[6]/N2HET2[4]
16
22
23
24
31
33
35
6
compare, or GIO
GIOA[7]/N2HET2[6]
Each terminal has
a
N2HET1[01]/SPI4NENA/N2HET2[8]
N2HET1[03]/SPI4NCS[0]/N2HET2[10]
N2HET1[05]/SPI4SOMI/N2HET2[12]
N2HET1[07]/N2HET2[14]
suppression filter that
ignores input pulses
smaller
than
a
programmable duration.
N2HET1[09]/N2HET2[16]
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
14
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2.4.1.3 General-Purpose Input / Output (GIO)
Table 2-6. PGE General-Purpose Input / Output (GIO)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
GIOA[2]/N2HET2[0]
GIOA[5]/EXTCLKIN
GIOA[6]/N2HET2[4]
GIOA[7]/N2HET2[6]
9
I/O
Pull Down Programmable, General-purpose I/O.
20uA
All GIO terminals are
capable of generating
interrupts to the CPU on
rising / falling / both
edges.
14
16
22
2.4.1.4 Controller Area Network Controllers (DCAN)
Table 2-7. PGE Controller Area Network Controllers (DCAN)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
CAN1RX
CAN1TX
CAN2RX
CAN2TX
CAN3RX
CAN3TX
90
89
I/O
Pull Up
Programmable, CAN1 receive, or GIO
20uA
CAN1 transmit, or GIO
129
128
12
CAN2 receive, or GIO
CAN2 transmit, or GIO
CAN3 receive, or GIO
CAN3 transmit, or GIO
13
2.4.1.5 Local Interconnect Network Interface Module (LIN)
Table 2-8. PGE Local Interconnect Network Interface Module (LIN)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
LINRX
LINTX
131
132
I/O
Pull Up
Programmable, LIN receive, or GIO
20uA
LIN transmit, or GIO
2.4.1.6 Standard Serial Communication Interface (SCI)
Table 2-9. PGE Standard Serial Communication Interface (SCI)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
N2HET1[06]/SCIRX
N2HET1[13]/SCITX
38
39
I/O
Pull Down Programmable, SCI receive, or GIO
20uA
SCI transmit, or GIO
2.4.1.7 Inter-Integrated Circuit Interface Module (I2C)
Table 2-10. PGE Inter-Integrated Circuit Interface Module (I2C)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
4
3
I/O
Pull Up
Programmable, I2C serial data, or GIO
20uA
I2C serial clock, or GIO
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2.4.1.8 Standard Serial Peripheral Interface (SPI)
Table 2-11. PGE Standard Serial Peripheral Interface (SPI)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
N2HET1[0]/SPI4CLK
25
24
23
30
I/O
Pull Down Programmable, SPI4 clock, or GIO
20uA
N2HET1[03]/SPI4NCS[0]/N2HET2[10]
N2HET1[01]/SPI4NENA/N2HET2[8]
N2HET1[02]/SPI4SIMO
SPI4 chip select, or GIO
SPI4 enable, or GIO
SPI4 slave-input
master-output, or GIO
N2HET1[05]/SPI4SOMI/N2HET2[12]
31
SPI4 slave-output
master-input, or GIO
2.4.1.9 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)
Table 2-12. PGE Multi-Buffered Serial Peripheral Interface Modules (MibSPI)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
MIBSPI1CLK
95
105
130
40
I/O
Pull Up
Programmable, MibSPI1 clock, or GIO
20uA
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
MIBSPI1NCS[2]/N2HET1[19]/MDIO
N2HET1[15]/MIBSPI1NCS[4]
MibSPI1 chip select, or
GIO
41
Pull Down Programmable, MibSPI1 chip select, or
20uA GIO
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]
MIBSPI1SIMO
91
96
Pull Up
Programmable, MibSPI1 enable, or GIO
20uA
93
MibSPI1 slave-in
master-out, or GIO
N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]
106
Pull Down Programmable, MibSPI1 slave-in
20uA master-out, or GIO
MIBSPI1SOMI
94
105
53
55
37
4
Pull Up
Programmable, MibSPI1 slave-out
20uA master-in, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
MIBSPI3CLK
I/O
Pull Up
Programmable, MibSPI3 clock, or GIO
20uA
MIBSPI3NCS[0]/AD2EVT/GIOB[2]
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
MibSPI3 chip select, or
GIO
3
6
Pull Up
Pull Up
Programmable, MibSPI3 chip select, or
20uA
GIO
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]
54
Programmable, MibSPI3 chip select, or
20uA
GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]
54
52
MibSPI3 enable, or GIO
MIBSPI3SIMO
MibSPI3 slave-in
master-out, or GIO
MIBSPI3SOMI
51
MibSPI3 slave-out
master-in, or GIO
16
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Table 2-12. PGE Multi-Buffered Serial Peripheral Interface Modules (MibSPI) (continued)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
MIBSPI5CLK/MII_TXEN
100
32
I/O
Pull Up
Programmable, MibSPI5 clock, or GIO
20uA
MIBSPI5NCS[0]
MibSPI5 chip select, or
GIO
MIBSPI5NENA/MII_RXD[3]
MIBSPI5SIMO[0]/MII_TXD[1]
97
99
MibSPI5 enable, or GIO
MibSPI5 slave-in
master-out, or GIO
MIBSPI5SOMI[0]/MII_TXD[0]
98
MibSPI5 slave-out
master-in, or GIO
2.4.1.10 Ethernet Controller
Table 2-13. PGE Ethernet Controller: MDIO Interface
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
MIBSPI1NCS[2]/N2HET1[19]/MDIO
37
40
Output Pull Up
I/O Pull Up
-
Serial clock output
Fixed, 20uA
Serial data input/output
Table 2-14. PGE Ethernet Controller: Media Independent Interface (MII)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
N2HET1[12]/MII_CRS
130
124
Input Pull Up
-
Collision detect
Pull Down Fixed, 20uA
Carrier sense and receive
valid
N2HET1[28]/MII_RXCLK/MII_RX_AVCLK4
N2HET1[30]/MII_RX_DV
107
127
86
I/O
Pull Down
-
MII output receive clock
Received data valid
Receive error
Input Pull Down Fixed, 20uA
AD1EVT/MII_RX_ER
N2HET1[28]/MII_RX_CLK/MII_RX_AVCLK4
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]
N2HET1[26]/MII_RXD[1]
107
92
I/O
Receive clock
Input
Receive data
92
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]
MIBSPI5NENA/MII_RXD[3]
96
Pull Up
Fixed, 20uA
97
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4
MIBSPI5SOMI[0]/MII_TXD[0]
118
118
98
I/O
Pull Down
-
-
MII output transmit clock
Transmit clock
Output Pull Up
Transmit data
MIBSPI5SIMO[0]/MII_TXD[1]
99
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]
MIBSPI5CLK/MII_TXEN
105
106
100
Pull Down
Pull Up
-
-
Transmit enable
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2.4.1.11 System Module Interface
Table 2-15. PGE System Module Interface
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
nPORRST
46
Input
Pull Down 100uA
Power-on reset, cold reset
External power supply
monitor circuitry must
drive nPORRST low when
any of the supplies to the
microcontroller fall out of
thespecified range. This
terminal has a glitch filter.
See Section 4.8.
nRST
116
I/O
Pull Up
100uA
System reset, warm reset,
bidirectional.
The internal circuitry
indicates any reset
condition by driving nRST
low.
The external circuitry can
assert a system reset by
driving nRST low. To
ensure that an external
reset is not arbitrarily
generated, TI
recommends that an
external pull-up resistor is
connected to this terminal.
This terminal has a glitch
filter. See Section 4.8.
nERROR
117
I/O
Pull Down 20uA
ESM Error Signal
Indicates error of high
severity. See
Section 4.18.
2.4.1.12 Clock Inputs and Outputs
Table 2-16. PGE Clock Inputs and Outputs
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
OSCIN
18
Input
-
-
From external
crystal/resonator, or
external clock input
KELVIN_GND
OSCOUT
19
20
Input
Kelvin ground for oscillator
Output
To external
crystal/resonator
ECLK
119
14
I/O
Pull Down Programmable, External prescaled clock
20uA
output, or GIO.
GIOA[5]/EXTCLKIN
Input Pull Down 20uA
External clock input #1
18
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2.4.1.13 Test and Debug Modules Interface
Table 2-17. PGE Test and Debug Modules Interface
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
TEST
nTRST
RTCK
TCK
34
I/O
Input
Output
Input
I/O
Pull Down Fixed, 100uA
Test enable
109
113
112
110
111
108
JTAG test hardware reset
JTAG return test clock
JTAG test clock
-
-
Pull Down Fixed, 100uA
Pull Up
TDI
JTAG test data in
JTAG test data out
JTAG test select
TDO
I/O
Pull Down
TMS
I/O
Pull Up
2.4.1.14 Flash Supply and Test Pads
Table 2-18. PGE Flash Supply and Test Pads
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
VCCP
FLTP1
FLTP2
134
7
Input
-
-
Flash pump supply
Flash test pads. These
terminals are reserved for
TI use only. For proper
operation these terminals
must connect only to a
test pad or not be
8
connected at all [no
connect (NC)].
2.4.1.15 Supply for Core Logic: 1.2V nominal
Table 2-19. PGE Supply for Core Logic: 1.2V nominal
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
17
29
-
-
-
Core supply
45
48
49
57
87
101
114
123
137
143
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2.4.1.16 Supply for I/O Cells: 3.3V nominal
Table 2-20. PGE Supply for I/O Cells: 3.3V nominal
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
10
26
Input
-
-
Operating supply for I/Os
42
104
120
136
2.4.1.17 Ground Reference for All Supplies Except VCCAD
Table 2-21. PGE Ground Reference for All Supplies Except VCCAD
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
144
PGE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
11
21
Input
-
-
Ground reference
27
28
43
44
47
50
56
88
102
103
115
121
122
135
138
20
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2.4.2 ZWT Package
2.4.2.1 Multi-Buffered Analog-to-Digital Converters (MibADC)
Table 2-22. ZWT Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
ADREFHI(1)
V15
Input
-
-
-
ADC high reference
supply
ADREFLO(1)
VCCAD(1)
VSSAD
V16
W15
V19
Input
Power
Ground
ADC low reference supply
Operating supply for ADC
ADC supply power
-
W16
W18
W19
N19
AD1EVT/MII_RX_ER
Input Pull Down Programmable, ADC1 event trigger input,
20uA or GIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]
V10
I/O
Pull Up
Programmable, ADC2 event trigger input,
20uA
or GIO
AD1IN[0]
W14
V17
V18
T17
U18
R17
T19
V14
P18
W17
U17
U19
T16
T18
R18
P19
V13
U13
U14
U16
U15
T15
R19
R16
Input
-
-
ADC1 analog input
AD1IN[01]
AD1IN[02]
AD1IN[03]
AD1IN[04]
AD1IN[05]
AD1IN[06]
AD1IN[07]
AD1IN[08] / AD2IN[08]
AD1IN[09] / AD2IN[09]
AD1IN[10] / AD2IN[10]
AD1IN[11] / AD2IN[11]
AD1IN[12] / AD2IN[12]
AD1IN[13] / AD2IN[13]
AD1IN[14] / AD2IN[14]
AD1IN[15] / AD2IN[15]
AD1IN[16] / AD2IN[0]
AD1IN[17] / AD2IN[01]
AD1IN[18] / AD2IN[02]
AD1IN[19] / AD2IN[03]
AD1IN[20] / AD2IN[04]
AD1IN[21] / AD2IN[05]
AD1IN[22] / AD2IN[06]
AD1IN[23] / AD2IN[07]
Input
-
-
ADC1/ADC2 shared
analog inputs
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
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2.4.2.2 Enhanced High-End Timer Modules (N2HET)
Table 2-23. ZWT Enhanced High-End Timer Modules (N2HET)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
N2HET1[0]/SPI4CLK
K18
V2
I/O
Pull Down Programmable,
20uA
N2HET1
capture
compare, or GIO.
time
or
input
output
N2HET1[01]/SPI4NENA/N2HET2[8]
N2HET1[02]/SPI4SIMO
N2HET1[03]/SPI4NCS[0]/N2HET2[10]
N2HET1[04]
W5
U1
Each terminal has
suppression filter that
ignores
smaller
programmable duration.
a
B12
V6
input
than
pulses
a
N2HET1[05]/SPI4SOMI/N2HET2[12]
N2HET1[06]/SCIRX
W3
T1
N2HET1[07]/N2HET2[14]
N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]
N2HET1[09]/N2HET2[16]
N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
N2HET1[12]/MII_CRS
N2HET1[13]/SCITX
E18
V7
D19
E3
B4
N2
N2HET1[14]
A11
N1
N2HET1[15]/MIBSPI1NCS[4]
N2HET1[16]
A4
N2HET1[17]
A13
J1
N2HET1[18]
N2HET1[19]
B13
P2
N2HET1[20]
N2HET1[21]
H4
N2HET1[22]
B3
N2HET1[23]
J4
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]
N2HET1[25]
P1
M3
A14
A9
N2HET1[26]/MII_RXD[1]
N2HET1[27]
N2HET1[28]/MII_RX_CLK/MII_RX_AVCLK4
N2HET1[29]
K19
A3
N2HET1[30]/MII_RX_DV
N2HET1[31]
B11
J17
22
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Table 2-23. ZWT Enhanced High-End Timer Modules (N2HET) (continued)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
GIOA[2]/N2HET2[0]
C1
D4
E1
I/O
Pull Down Programmable,
20uA
N2HET2
capture
compare, or GIO.
time
or
input
output
EMIF_ADDR[0]/N2HET2[1]
GIOA[3]/N2HET2[2]
Each terminal has
suppression filter that
a
EMIF_ADDR[1]/N2HET2[3]
D5
H3
D16
M1
N17
V2
GIOA[6]/N2HET2[4]
ignores
smaller
input
than
pulses
a
EMIF_BA[1]/N2HET2[5]
programmable duration.
GIOA[7]/N2HET2[6]
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]
N2HET1[01]/SPI4NENA/N2HET2[8]
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]
N2HET1[03]/SPI4NCS[0]/N2HET2[10]
EMIF_ADDR[6]/RTP_DATA[13]/NHET2[11]
N2HET1[05]/SPI4SOMI/N2HET2[12]
EMIF_ADDR[7]/RTP_DATA[12]/NHET2[13]
N2HET1[07]/N2HET2[14]
K17
U1
C4
V6
C5
T1
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15]
N2HET1[09]/N2HET2[16]
C6
V7
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
E3
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2.4.2.3 General-Purpose Input / Output (GIO)
Table 2-24. ZWT General-Purpose Input / Output (GIO)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
GIOA[0]
A5
C2
C1
E1
A6
B5
H3
M1
M2
K2
F2
I/O
Pull Down Programmable, General-purpose I/O.
20uA
All GIO terminals are
capable of generating
interrupts to the CPU on
rising / falling / both
edges.
GIOA[1]
GIOA[2]/N2HET2[0]
GIOA[3]/N2HET2[2]
GIOA[4]
GIOA[5]/EXTCLKIN
GIOA[6]/N2HET2[4]
GIOA[7]/N2HET2[6]
GIOB[0]
GIOB[1]
GIOB[2]
GIOB[3]
W10
G1
G2
J2
GIOB[4]
GIOB[5]
GIOB[6]
GIOB[7]
F1
24
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2.4.2.4 Controller Area Network Controllers (DCAN)
Table 2-25. ZWT Controller Area Network Controllers (DCAN)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
CAN1RX
CAN1TX
CAN2RX
CAN2TX
CAN3RX
CAN3TX
B10
A10
H1
I/O
Pull Up
Programmable, CAN1 receive, or GIO
20uA
CAN1 transmit, or GIO
CAN2 receive, or GIO
CAN2 transmit, or GIO
CAN3 receive, or GIO
CAN3 transmit, or GIO
H2
M19
M18
2.4.2.5 Local Interconnect Network Interface Module (LIN)
Table 2-26. ZWT Local Interconnect Network Interface Module (LIN)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
LINRX
LINTX
A7
B7
I/O
Pull Up
Programmable, LIN receive, or GIO
20uA
LIN transmit, or GIO
2.4.2.6 Standard Serial Communication Interface (SCI)
Table 2-27. ZWT Standard Serial Communication Interface (SCI)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
N2HET1[06]/SCIRX
N2HET1[13]/SCITX
W3
N2
I/O
Pull Down Programmable, SCI receive, or GIO
20uA
SCI transmit, or GIO
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2.4.2.7 Inter-Integrated Circuit Interface Module (I2C)
Table 2-28. ZWT Inter-Integrated Circuit Interface Module (I2C)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
B2
C3
I/O
Pull Up
Programmable, I2C serial data, or GIO
20uA
I2C serial clock, or GIO
2.4.2.8 Standard Serial Peripheral Interface (SPI)
Table 2-29. ZWT Standard Serial Peripheral Interface (SPI)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
SPI2CLK
E2
N3
D3
D3
D1
I/O
Pull Up
Programmable, SPI2 clock, or GIO
20uA
SPI2NCS[0]
SPI2 chip select, or GIO
SPI2NENA/SPI2NCS[1]
SPI2NENA/SPI2NCS[1]
SPI2SIMO
SPI2 chip select, or GIO
SPI2 enable, or GIO
SPI2 slave-input
master-output, or GIO
SPI2SOMI
D2
SPI2 slave-output
master-input, or GIO
N2HET1[0]/SPI4CLK
K18
U1
I/O
Pull Down Programmable, SPI4 clock, or GIO
20uA
N2HET1[03]/SPI4NCS[0]/N2HET2[10]
N2HET1[01]/SPI4NENA/N2HET2[8]
N2HET1[02]/SPI4SIMO
SPI4 chip select, or GIO
V2
SPI4 enable, or GIO
W5
SPI4 slave-input
master-output, or GIO
N2HET1[05]/SPI4SOMI/N2HET2[12]
V6
SPI4 slave-output
master-input, or GIO
26
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2.4.2.9 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)
Table 2-30. ZWT Multi-Buffered Serial Peripheral Interface Modules (MibSPI)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
MIBSPI1CLK
F18
R2
I/O
Pull Up
Programmable, MibSPI1 clock, or GIO
20uA
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
MIBSPI1NCS[1]/N2HET1[17]/MII_COL
MIBSPI1NCS[2]/N2HET1[19]/MDIO
MIBSPI1NCS[3]/N2HET1[21]
MibSPI1 chip select, or
GIO
F3
G3
J3
N2HET1[15]/MIBSPI1NCS[4]
N1
Pull Down Programmable, MibSPI1 chip select, or
20uA GIO
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]
MIBSPI1NENA/N2HET1[23]/MII_RXD[2]
MIBSPI1SIMO
P1
G19
F19
Pull Up
Programmable, MibSPI1 enable, or GIO
20uA
MibSPI1 slave-in
master-out, or GIO
N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]
E18
Pull Down Programmable, MibSPI1 slave-in
20uA master-out, or GIO
MIBSPI1SOMI
G18
R2
V9
Pull Up
Programmable, MibSPI1 slave-out
20uA master-in, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]
MIBSPI3CLK
I/O
Pull Up
Programmable, MibSPI3 clock, or GIO
20uA
MIBSPI3NCS[0]/AD2EVT/GIOB[2]
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]
V10
V5
MibSPI3 chip select, or
GIO
B2
C3
E3
Pull Up
Pull Up
Programmable, MibSPI3 chip select, or
20uA
GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]
W9
Programmable, MibSPI3 chip select, or
20uA
GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]
W9
W8
MibSPI3 enable, or GIO
MIBSPI3SIMO
MibSPI3 slave-in
master-out, or GIO
MIBSPI3SOMI
V8
MibSPI3 slave-out
master-in, or GIO
MIBSPI5CLK/DMM_DATA[4]/MII_TXEN
MIBSPI5NCS[0]/DMM_DATA[5]
H19
E19
B6
I/O
Pull Up
Programmable, MibSPI5 clock, or GIO
20uA
MibSPI5 chip select, or
GIO
MIBSPI5NCS[1]/DMM_DATA[6]
MIBSPI5NCS[2]/DMM_DATA[2]
W6
MIBSPI5NCS[3]/DMM_DATA[3]
T12
H18
J19
E16
H17
G17
J18
E17
H16
G16
MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]
MIBSPI5SIMO[1]/DMM_DATA[9]
MIBSPI5SIMO[2]/DMM_DATA[10]
MIBSPI5SIMO[3]/DMM_DATA[11]
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]
MIBSPI5SOMI[1]/DMM_DATA[13]
MIBSPI5SOMI[2]/DMM_DATA[14]
MIBSPI5SOMI[3]/DMM_DATA[15]
MibSPI5 enable, or GIO
MibSPI5 slave-in
master-out, or GIO
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2.4.2.10 Ethernet Controller
Table 2-31. ZWT Ethernet Controller: MDIO Interface
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
MIBSPI1NCS[2]/N2HET1[19]/MDIO
V5
G3
Output Pull Up
I/O Pull Up
-
Serial clock output
Fixed, 20uA
Serial data input/output
28
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2.4.2.11 External Memory Interface (EMIF)
Table 2-32. External Memory Interface (EMIF)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
EMIF_CKE
EMIF_CLK
L3
K3
Output Pull Down
I/O
-
EMIF Clock Enablen
EMIF clock. This is an
output signal in functional
mode. It is gated off by
default, so that the signal
is tri-stated. PINMUX29[8]
must be cleared to enable
this output.
EMIF_nWE/EMIF_RNW
D17
E12
P3
Output Pull Up
Pull Down
-
EMIF Read-Not-Write
EMIF Read Enable
ETMDATA[13]/EMIF_nOE
-
EMIF_nWAIT
I/O
Pull Up
Fixed, 20uA
EMIF Extended Wait
Signal
EMIF_nWE/EMIF_RNW
D17
R4
Output Pull Up
Output
-
EMIF Write Enable.
EMIF_nCAS
EMIF column address
strobe
EMIF_nRAS
R3
Output
Output
EMIF row address strobe
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]
N17
EMIF chip select,
synchronous
EMIF_nCS[2]
L17
K17
M17
Output
Output
Output
EMIF chip selects,
asynchronous
This applies to chip
selects 2, 3 and 4
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]
EMIF_nCS[4]/RTP_DATA[07]
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Table 2-32. External Memory Interface (EMIF) (continued)
Terminal
Signal Name
Signal
Type
Default
Pull State
Pull Type
Description
337
ZWT
ETMDATA[15]/EMIF_nDQM[0]
E10
E11
Output Pull Down
Output
-
EMIF Data Mask or Write
Strobe.
Data mask for SDRAM
devices, write strobe for
connected asynchronous
devices.
ETMDATA[14]/EMIF_nDQM[1]
ETMDATA[12]/EMIF_BA[0]
EMIF_BA[1]/N2HET2[5]
E13
D16
Output
Output
EMIF bank address or
address line
EMIF bank address or
address line
EMIF_ADDR[0]/N2HET2[1]
D4
D5
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output Pull Down
Output
Output
Output
Output
EMIF address
EMIF_ADDR[1]/N2HET2[3]
ETMDATA[11]/EMIF_ADDR[2]
ETMDATA[10]/EMIF_ADDR[3]
ETMDATA[09]/EMIF_ADDR[4
ETMDATA[08]/EMIF_ADDR[5]
EMIF_ADDR[6]/RTP_DATA[13]
EMIF_ADDR[7]/RTP_DATA[12]
EMIF_ADDR[8]/RTP_DATA[11]
EMIF_ADDR[9]/RTP_DATA[10]
EMIF_ADDR[10]/RTP_DATA[09]
EMIF_ADDR[11]/RTP_DATA[08]
EMIF_ADDR[12]/RTP_DATA[06]
EMIF_ADDR[13]/RTP_DATA[05]
EMIF_ADDR[14]/RTP_DATA[04]
EMIF_ADDR[15]/RTP_DATA[03]
EMIF_ADDR[16]/RTP_DATA[02]
EMIF_ADDR[17]/RTP_DATA[01]
EMIF_ADDR[18]/RTP_DATA[0]
EMIF_ADDR[19]/RTP_nENA
EMIF_ADDR[20]/RTP_nSYNC
EMIF_ADDR[21]/RTP_CLK
E6
E7
E8
E9
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
D14
C14
D15
C15
C16
C17
K15
L15
M15
N15
E5
-
ETMDATA[16]/EMIF_DATA[0]
ETMDATA[17]/EMIF_DATA[1]
ETMDATA[18]/EMIF_DATA[2]
ETMDATA[19]/EMIF_DATA[3]
ETMDATA[20]/EMIF_DATA[4]
ETMDATA[21]/EMIF_DATA[5]
ETMDATA[22]/EMIF_DATA[6]
ETMDATA[23]/EMIF_DATA[7]
ETMDATA[24]/EMIF_DATA[8]
ETMDATA[25]/EMIF_DATA[9]
ETMDATA[26]/EMIF_DATA[10]
ETMDATA[27]/EMIF_DATA[11]
ETMDATA[28]/EMIF_DATA[12]
ETMDATA[29]/EMIF_DATA[13]
ETMDATA[30]/EMIF_DATA[14]
ETMDATA[31]/EMIF_DATA[15]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pull Down Fixed, 20uA
EMIF Data
F5
G5
K5
L5
M5
N5
P5
R5
R6
R7
R8
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2.4.2.12 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
Table 2-33. Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
ETMTRACECLKIN/EXTCLKIN2
R9
R10
R11
R12
R13
J15
H15
G15
F15
E15
E14
E9
Input Pull Down Fixed, 20uA
ETM Trace Clock Input
ETM Trace Clock Output
ETM trace control
ETM data
ETMTRACECLKOUT
Output Pull Down
Output Pull Down
-
-
ETMTRACECTL
ETMDATA[0]
ETMDATA[01]
ETMDATA[02]
ETMDATA[03]
ETMDATA[04]
ETMDATA[05]
ETMDATA[06]
ETMDATA[07]
ETMDATA[08]/EMIF_ADDR[5]
ETMDATA[09]/EMIF_ADDR[4]
ETMDATA[10]/EMIF_ADDR[3]
ETMDATA[11]/EMIF_ADDR[2]
ETMDATA[12]/EMIF_BA[0]
ETMDATA[13]/EMIF_nOE
ETMDATA[14]/EMIF_nDQM[1]
ETMDATA[15]/EMIF_nDQM[0]
ETMDATA[16]/EMIF_DATA[0]
ETMDATA[17]/EMIF_DATA[1]
ETMDATA[18]/EMIF_DATA[2]
ETMDATA[19]/EMIF_DATA[3]
ETMDATA[20]/EMIF_DATA[4]
ETMDATA[21]/EMIF_DATA[5]
ETMDATA[22]/EMIF_DATA[6]
ETMDATA[23]/EMIF_DATA[7]
ETMDATA[24]/EMIF_DATA[8]
ETMDATA[25]/EMIF_DATA[9]
ETMDATA[26]/EMIF_DATA[10]
ETMDATA[27]/EMIF_DATA[11]
ETMDATA[28]/EMIF_DATA[12]
ETMDATA[29]/EMIF_DATA[13]
ETMDATA[30]/EMIF_DATA[14]
ETMDATA[31]/EMIF_DATA[15]
E8
E7
E6
E13
E12
E11
E10
K15
L15
M15
N15
E5
F5
G5
K5
L5
M5
N5
P5
R5
R6
R7
R8
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2.4.2.13 RAM Trace Port (RTP)
Table 2-34. RAM Trace Port (RTP)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
EMIF_ADDR[21]/RTP_CLK
EMIF_ADDR[19]/RTP_nENA
C17
C15
I/O
I/O
Pull Down Programmable, RTP packet clock, or GIO
20uA
RTP packet handshake,
or GIO
EMIF_ADDR[20]/RTP_nSYNC
C16
I/O
I/O
RTP synchronization, or
GIO
EMIF_ADDR[18]/RTP_DATA[0]
EMIF_ADDR[17]/RTP_DATA[01]
EMIF_ADDR[16]/RTP_DATA[02]
EMIF_ADDR[15]/RTP_DATA[03]
EMIF_ADDR[14]/RTP_DATA[04]
EMIF_ADDR[13]/RTP_DATA[05]
EMIF_ADDR[12]/RTP_DATA[06]
EMIF_nCS[4]/RTP_DATA[07]
D15
C14
D14
C13
C12
C11
C10
M17
RTP packet data, or GIO
Pull Up
Programmable,
20uA
EMIF_ADDR[11]/RTP_DATA[08]
EMIF_ADDR[10]/RTP_DATA[09]
EMIF_ADDR[9]/RTP_DATA[10]
EMIF_ADDR[8]/RTP_DATA[11]
EMIF_ADDR[7]/RTP_DATA[12]
EMIF_ADDR[6]/RTP_DATA[13]
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]
C9
C8
Pull Down Programmable,
20uA
C7
C6
C5
C4
N17
K17
Pull Up
Programmable,
20uA
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2.4.2.14 Data Modification Module (DMM)
Table 2-35. Data Modification Module (DMM)
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
DMM_CLK
DMM_nENA
DMM_SYNC
F17
F16
J16
I/O
Pull Up
Programmable, DMM clock, or GIO
20uA
DMM handshake, or GIO
DMM synchronization, or
GIO
DMM_DATA[0]
DMM_DATA[1]
L19
L18
W6
DMM data, or GIO
MIBSPI5NCS[2]/DMM_DATA[2]
MIBSPI5NCS[3]/DMM_DATA[3]
T12
H19
E19
B6
MIBSPI5CLK/DMM_DATA[4]/MII_TXEN
MIBSPI5NCS[0]/DMM_DATA[5]
MIBSPI5NCS[1]/DMM_DATA[6]
MIBSPI5NENA/DMM_DATA[7]/MII_RXD[3]
MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]
MIBSPI5SIMO[1]/DMM_DATA[9]
MIBSPI5SIMO[2]/DMM_DATA[10]
MIBSPI5SIMO[3]/DMM_DATA[11]
MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]
MIBSPI5SOMI[1]/DMM_DATA[13]
MIBSPI5SOMI[2]/DMM_DATA[14]
MIBSPI5SOMI[3]/DMM_DATA[15]
H18
J19
E16
H17
G17
J18
E17
H16
G16
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2.4.2.15 System Module Interface
Table 2-36. ZWT System Module Interface
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
nPORRST
W7
Input
Pull Down 100uA
Power-on reset, cold reset
External power supply
monitor circuitry must
drive nPORRST low when
any of the supplies to the
microcontroller fall out of
thespecified range. This
terminal has a glitch filter.
See Section 4.8.
nRST
B17
I/O
Pull Up
100uA
System reset, warm reset,
bidirectional.
The internal circuitry
indicates any reset
condition by driving nRST
low.
The external circuitry can
assert a system reset by
driving nRST low. To
ensure that an external
reset is not arbitrarily
generated, TI
recommends that an
external pull-up resistor is
connected to this terminal.
This terminal has a glitch
filter. See Section 4.8.
nERROR
B14
I/O
Pull Down 20uA
ESM Error Signal
Indicates error of high
severity. See
Section 4.18.
2.4.2.16 Clock Inputs and Outputs
Table 2-37. ZWT Clock Inputs and Outputs
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
OSCIN
K1
Input
-
-
From external
crystal/resonator, or
external clock input
KELVIN_GND
OSCOUT
L2
L1
Input
Kelvin ground for oscillator
Output
To external
crystal/resonator
ECLK
A12
I/O
Pull Down Programmable, External prescaled clock
20uA
output, or GIO.
GIOA[5]/EXTCLKIN
B5
R9
Input Pull Down 20uA
External clock input #1
External clock input #2
ETMTRACECLKIN/EXTCLKIN2
Input
Input
VCCPLL
P11
-
Dedicated core supply for
PLL's
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2.4.2.17 Test and Debug Modules Interface
Table 2-38. ZWT Test and Debug Modules Interface
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
TEST
nTRST
RTCK
TCK
U2
I/O
Input
Output
Input
I/O
Pull Down Fixed, 100uA
Test enable
D18
A16
B18
A17
C18
C19
JTAG test hardware reset
JTAG return test clock
JTAG test clock
-
-
Pull Down Fixed, 100uA
Pull Up
TDI
JTAG test data in
JTAG test data out
JTAG test select
TDO
I/O
Pull Down
TMS
I/O
Pull Up
2.4.2.18 Flash Supply and Test Pads
Table 2-39. ZWT Flash Supply and Test Pads
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
VCCP
FLTP1
FLTP2
F8
J5
Input
-
-
Flash pump supply
Flash test pads. These
terminals are reserved for
TI use only. For proper
operation these terminals
must connect only to a
test pad or not be
H5
connected at all [no
connect (NC)].
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2.4.2.19 No Connects
Table 2-40. No Connects
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D6
D7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
No Connects. These balls
are not connected to any
internal logic and can be
connected to the PCB
ground without affecting
the functionality of the
device.
Any other ball marked as
"NC" may be internally
connected to some
functionality. It is
D8
D9
D10
D11
D12
E4
recommended for such
balls to be left
unconnected.
F4
G4
K4
L4
M4
N4
N18
P4
P15
P16
P17
R1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R14
R15
T5
T6
T7
T8
T13
T14
V4
W4
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2.4.2.20 Supply for Core Logic: 1.2V nominal
Table 2-41. ZWT Supply for Core Logic: 1.2V nominal
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
F9
F10
H10
J14
K6
-
-
-
Core supply
-
K8
K12
K14
L6
M10
P10
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2.4.2.21 Supply for I/O Cells: 3.3V nominal
Table 2-42. ZWT Supply for I/O Cells: 3.3V nominal
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
F6
F7
Input
-
-
Operating supply for I/Os
F11
F12
F13
F14
G6
G14
H6
H14
J6
L14
M6
M14
N6
N14
P6
P7
P8
P9
P12
P13
P14
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2.4.2.22 Ground Reference for All Supplies Except VCCAD
Table 2-43. ZWT Ground Reference for All Supplies Except VCCAD
Terminal
Signal
Type
Default
Pull State
Pull Type
Description
Signal Name
337
ZWT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A1
A2
Input
-
-
Ground reference
A18
A19
B1
B19
H8
H9
H11
H12
J8
J9
J10
J11
J12
K9
K10
K11
L8
L9
L10
L11
L12
M8
M9
M11
M12
V1
W1
W2
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3 Device Operating Conditions
(1)
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range,
(2)
VCC
-0.3 V to 1.43 V
-0.3 V to 4.1 V
-0.3 V to 5.5 V
-0.3 V to 4.1 V
±20 mA
(2)
Supply voltage range:
Input voltage range:
VCCIO, VCCP
VCCAD
All input pins
IIK (VI < 0 or VI > VCCIO
)
All pins, except AD1IN[23:0] and AD2IN[15:0]
Input clamp current:
IIK (VI < 0 or VI > VCCAD
)
±10 mA
AD1IN[23:0] and AD2IN[15:0]
Total
±40 mA
-40°C to 105°C
-40°C to 125°C
-65°C to 150°C
Operating free-air temperature range, TA:
Operating junction temperature range, TJ:
Storage temperature range, Tstg
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated
grounds.
3.2 Device Recommended Operating Conditions(1)
MIN
1.14
1.14
3
NOM
1.2
1.2
3.3
3.3
5.0
3.3
0
MAX UNIT
VCC
Digital logic supply voltage (Core)
PLL Supply Voltage
1.32
1.32
3.6
V
V
V
V
VCCPLL
VCCIO
VCCAD
Digital logic supply voltage (I/O)
MibADC supply voltage
3
3.6
4.5
3
5.25
3.6
VCCP
VSS
Flash pump supply voltage
V
V
Digital logic supply ground
VSSAD
VADREFHI
VADREFLO
TA
MibADC supply ground
-0.1
VSSAD
VSSAD
-40
0.1
VCCAD
VCCAD
105
V
A-to-D high-voltage reference source
A-to-D low-voltage reference source
Operating free-air temperature
Operating junction temperature
V
V
°C
°C
TJ
-40
150
(1) All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD
40
Device Operating Conditions
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3.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains
Table 3-1. Clock Domain Timing Specifications
Parameter
fHCLK
Description
Conditions
Pipeline mode
Min
Max
Unit
HCLK - System clock frequency
PGE
160
MHz
enabled
Pipeline mode
disabled
45
180
45
MHz
MHz
MHz
ZWT
Pipeline mode
enabled
Pipeline mode
disabled
fGCLK
fVCLK
GCLK - CPU clock frequency
fHCLK
100
MHz
MHz
VCLK - Primary peripheral clock
frequency
fVCLK2
VCLK2 - Secondary peripheral clock
frequency
100
100
100
100
50
MHz
MHz
MHz
MHz
MHz
MHz
fVCLK3
VCLK3 - Secondary peripheral clock
frequency
fVCLKA1
fVCLKA2
fVCLKA4
fRTICLK
VCLKA1 - Primary asynchronous
peripheral clock frequency
VCLKA2 - Secondary asynchronous
peripheral clock frequency
VCLKA4 - Secondary asynchronous
peripheral clock frequency
RTICLK - clock frequency
fVCLK
3.4 Wait States Required
RAM
0
0
Address Waitstates
0MHz
fHCLK(max)
Data Waitstates
0MHz
fHCLK(max)
Flash
1
Address Waitstates
0
120MHz
fHCLK(max)
0MHz
Data Waitstates
0
1
2
3
fHCLK(max)
0MHz
45MHz
90MHz
135MHz
Figure 3-1. ZWT Wait States Scheme
As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without
any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 45MHz in non-pipelined
mode. The flash supports a maximum CPU clock speed of 160MHz in pipelined mode for the PGE Package and
180MHz for the ZWT package, with one address wait state and three data wait states.
The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait
state.
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UNIT
3.5 Power Consumption Over Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
fHCLK = 160MHz for
PGE Package
350 for PGE
Package
fHCLK = 180MHz for
ZWT Package
VCC digital supply current (operating mode)
mA
375 for ZWT
Package
fVCLK
=
90MHz,
Flash in pipelined
mode, VCCmax
ICC
LBIST clock rate =
90MHz
VCC Digital supply current (LBIST mode)
mA
mA
400
Peak
PBIST ROM clock
frequency = 90MHz
TBD
VCC Digital supply current
(PBIST mode)
RMS
405
10
ICCPLL
ICCIO
VCCPLL digital supply current (operating mode)
VCCIO Digital supply current (operating mode.
VCCPLL = VCCPLLmax
No DC load, VCCmax
mA
mA
15
Single ADC
operational,
VCCADmax
15
ICCAD
VCCAD supply current (operating mode)
mA
mA
Both ADCs
operational,
VCCADmax
30
5
Single ADC
operational,
ADREFHImax
ICCREFHI
ADREFHI supply current (operating mode)
Both ADCs
operational,
ADREFHImax
10
34
read operation
VCCPmax
program, VCCPmax
37
55
read from 1 bank
and program
another bank,
VCCPmax
ICCP
VCCP pump supply current
mA
erase, VCCPmax
27
42
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3.6 Input/Output Electrical Characteristics Over Recommended Operating Conditions(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
mV
V
Input hysteresis
All inputs (except
FRAYRX1,
FRAYRX2)
180
Vhys
FRAYRX1, FRAYRX2
All inputs(2) (except
FRAYRX1,
100
-0.3
0.8
VIL
Low-level input voltage
High-level input voltage
FRAYRX2)
FRAYRX1, FRAYRX2
All inputs(2) (except
FRAYRX1,
0.4 VCCIO
V
2
VCCIO + 0.3
V
VIH
FRAYRX2)
FRAYRX1, FRAYRX2
0.6 VCCIO
V
IOL = IOLmax
0.2 VCCIO
0.2
IOL = 50 µA, standard
output mode
VOL
Low-level output voltage
V
IOL = 50 µA, low-EMI
output mode (see
Section 3.10)
0.2 VCCIO
IOH = IOHmax
0.8 VCCIO
VCCIO -0.2
IOH = 50 µA, standard
output mode
VOH
IIC
II
High-level output voltage
Input clamp current (I/O pins)
Input current (I/O pins)
V
IOH = 50 µA, low-EMI
output mode (see
Section 3.10)
0.8 VCCIO
VI < VSSIO - 0.3 or VI
> VCCIO + 0.3
-2
2
mA
µA
IIH Pulldown 20µA
IIH Pulldown 100µA
IIL Pullup 20µA
IIL Pullup 100µA
All other pins
VI = VCCIO
5
40
40
195
-5
VI = VCCIO
VI = VSS
-40
-195
-1
VI = VSS
-40
1
No pullup or pulldown
CI
Input capacitance
Output capacitance
2
pF
pF
CO
3
(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.
(2) This does not apply to the nPORRST pin.
3.7 Output Buffer Drive Strengths
Table 3-2. Output Buffer Drive Strengths
Low-level Output Current,
IOL for VI=VOLmax
or
Signals
High-level Output Current,
IOH for VI=VOHmin
FRAYTX2, FRAYTX1, FRAYTXEN1, FRAYTXEN2,
MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3],
MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3],
8mA
TMS, TDI, TDO, RTCK,
SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR,
N2HET2[1], N2HET2[3],
All EMIF Outputs and I/Os, All ETM Outputs
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Table 3-2. Output Buffer Drive Strengths (continued)
Low-level Output Current,
IOL for VI=VOLmax
or
Signals
High-level Output Current,
IOH for VI=VOHmin
TEST,
4mA
MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK,
nRST
AD1EVT,
CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,
DMM_CLK, DMM_DATA[0], DMM_DATA[1], DMM_nENA, DMM_SYNC,
GIOA[0-7], GIOB[0-7],
LINRX, LINTX,
2mA zero-dominant
MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA,
MIBSPI5NCS[0-3], MIBSPI5NENA,
N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7],
N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14],
N2HET2[15], N2HET2[16], N2HET2[18],
SPI2NCS[0], SPI2NENA, SPI4NCS[0], SPI4NENA
ECLK,
selectable 8mA / 2mA
SPI2CLK, SPI2SIMO, SPI2SOMI
The default output buffer drive strength is 8mA for these signals.
3.8 Input Timings
tpw
VCCIO
Input
VIH
VIH
VIL
VIL
0
Figure 3-2. TTL-Level Inputs
Table 3-3. Timing Requirements for Inputs(1)
Parameter
MIN
tc(VCLK) + 10(2)
MAX
Unit
tpw
Input minimum pulse width
ns
(1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
(2) The timing shown above is only valid for pin used in GIO mode.
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3.9 Output Timings
Table 3-4. Switching Characteristics for Output Timings versus Load Capacitance (CL)
Parameter
MIN
MAX
2.5
4
Unit
Rise time, tr
Fall time, tf
Rise time, tr
Fall time, tf
Rise time, tr
Fall time, tf
Rise time, tr
Fall time, tf
Rise time, tr
Fall time, tf
8mA low EMI pins
(see Table 3-2)
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL= 50 pF
ns
7.2
12.5
2.5
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.2
12.5
5.6
10.4
16.8
23.2
5.6
10.4
16.8
23.2
8
4mA low EMI pins
(see Table 3-2)
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
2mA-z low EMI pins
(see Table 3-2)
15
23
33
8
15
23
33
2
Selectable 8mA / 2mA-z
pins
8mA mode
4
(see Table 3-2)
8
11
2
4
8
11
8
2mA-z mode
15
23
33
8
15
23
33
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tr
t
f
VCCIO
Output
VOH
VOH
VOL
VOL
0
Figure 3-3. CMOS-Level Outputs
Table 3-5. Timing Requirements for Outputs(1)
Parameter
MIN
MAX
UNIT
td(parallel_out)
Delay between low to high, or high to low transition of general-purpose output signals
that can be configured by an application in parallel, e.g. all signals in a GIOA port, or
all N2HET1 signals, etc.
5
ns
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check
Table 3-2 for output buffer drive strength information on each signal.
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3.10 Low-EMI Output Buffers
The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of
emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of
the output buffer, and is particularly effective with capacitive loads.
This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the
system module GPCR1 register for the desired module or signal, as shown in . The adaptive impedance
control circuit monitors the DC bias point of the output signal. The buffer internally generates two
reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of VCCIO,
respectively.
Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then
the output buffer’s impedance will increase to hi-Z. A high degree of decoupling between the internal
ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing,
e.g. the buffer is driving low on a resistive path to ground. Current loads on the buffer which attempt to pull
the output voltage above VREFLOW will be opposed by the buffer’s output impedance so as to maintain
the output voltage at or below VREFLOW.
Conversely, once the output buffer has driven the output to a high level, if the output voltage is above
VREFHIGH then the output buffer’s impedance will again increase to hi-Z. A high degree of decoupling
between internal power bus ad output pin will occur with capacitive loads or any loads in which no current
is flowing, e.g. buffer is driving high on a resistive path to VCCIO. Current loads on the buffer which
attempt to pull the output voltage below VREFHIGH will be opposed by the buffer’s output impedance so
as to maintain the output voltage at or above VREFHIGH.
The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance
control mode cannot respond to high-frequency noise coupling into the buffer’s power buses. In this
manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.
Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will
allow a positive current load to pull the output voltage up to VCCIO + 0.6V without opposition. Also, a
negative current load will pull the output voltage down to VSSIO – 0.6V without opposition. This is not an
issue since the actual clamp current capability is always greater than the IOH / IOL specifications.
The low-EMI output buffers are automatically configured to be in the standard buffer mode when the
device enters a low-power mode.
Table 3-6. Low-EMI Output Buffer Hookup
Module or Signal Name
Control Register to Enable Low-EMI Mode
GPREG1.0
Module: MibSPI1
Module: SPI2
Module: MibSPI3
Reserved
GPREG1.1
GPREG1.2
GPREG1.3
Module: MibSPI5
Module: FlexRay
Module: SPI2
Module: SPI2
Signal: TMS
GPREG1.4
GPREG1.5
GPREG1.6
GPREG1.7
GPREG1.8
Signal: TDI
GPREG1.9
Signal: TDO
GPREG1.10
GPREG1.11
GPREG1.12
GPREG1.13
GPREG1.14
GPREG1.15
Signal: RTCK
Signal: TEST
Signal: nERROR
Reserved
Module: RTP
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4 System Information and Electrical Specifications
4.1 Device Power Domains
The device core logic is split up into multiple power domains in order to optimize the power for a given
application use case. There are 8 core power domains in total: PD1, PD2, PD3, PD4, PD5, RAM_PD1,
RAM_PD2 and RAM_PD3.
The actual contents of these power domains are indicated in .
PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other core power domains
can be turned ON/OFF one time during device initialization as per the application requirement. Refer to
the Power Management Module (PMM) chapter of the device technical reference manual for more details.
NOTE
The clocks to a module must be turned off before powering down the core domain that
contains the module.
NOTE
The logic in the modules that are powered down loses its power completely. Any access to
modules that are powered down results in an abort being generated. When power is
restored, the modules power-up to their default states (after normal power-up). No register or
memory contents are preserved in the core domains that are turned off.
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4.2 Voltage Monitor Characteristics
A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the
requirement for a specific sequence when powering up the core and I/O voltage supplies.
4.2.1 Important Considerations
•
The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the
device is held in reset when the voltage supplies are out of range.
•
The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other
supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a
source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and
VCCP supplies.
4.2.2 Voltage Monitor Operation
The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO
signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when
the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and
PGMCU being low isolates the core logic as well as the I/O controls during the power-up or power-down
of the supplies. This allows the core and I/O supplies to be powered up or down in any order.
When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When
the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output
pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device
enters a low power mode.
The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 4.3.3.1 for the timing
information on this glitch filter.
Table 4-1. Voltage Monitoring Specifications
PARAMETER
VCC low - VCC level below this
MIN
TYP
MAX
UNIT
0.8
0.9
1.0
V
threshold is detected as too low.
Voltage monitoring
thresholds
VCC high - VCC level above this
threshold is detected as too high.
1.40
1.9
1.7
2.4
2.1
2.9
VMON
VCCIO low - VCCIO level below this
threshold is detected as too low.
4.2.3 Supply Filtering
The VMON has the capability to filter glitches on the VCC and VCCIO supplies.
The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the
maximum specification cannot be filtered.
Table 4-2. VMON Supply Glitch Filtering Capability
Parameter
MIN
MAX
1us
Width of glitch on VCC that can be filtered
Width of glitch on VCCIO that can be filtered
250ns
250ns
1us
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4.3 Power Sequencing and Power On Reset
4.3.1 Power-Up Sequence
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The
power-up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see
Table 4-4 for more details), core voltage rising above the minimum core supply threshold and the release
of power-on reset. The high frequency oscillator will start up first and its amplitude will grow to an
acceptable level. The oscillator start up time is dependent on the type of oscillator and is provided by the
oscillator vendor. The different supplies to the device can be powered up in any order.
The device goes through the following sequential phases during power up.
Table 4-3. Power-Up Phases
Oscillator start-up and validity check
eFuse autoload
1032 oscillator cycles
1180 oscillator cycles
688 oscillator cycles
617 oscillator cycles
3517 oscillator cycles
Flash pump power-up
Flash bank power-up
Total
The CPU reset is released at the end of the above sequence and fetches the first instruction from address
0x00000000.
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4.3.2 Power-Down Sequence
The different supplies to the device can be powered down in any order.
4.3.3 Power-On Reset: nPORRST
This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core
supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an
internal pulldown.
4.3.3.1 nPORRST Electrical and Timing Requirements
Table 4-4. Electrical Requirements for nPORRST
NO Parameter
MIN
MAX
Unit
VCCPORL
VCC low supply level when nPORRST must be active during
power-up
0.5
V
VCCPORH
VCC high supply level when nPORRST must remain active during
power-up and become active during power down
1.14
V
V
V
VCCIOPORL
VCCIOPORH
VIL(PORRST)
VCCIO / VCCP low supply level when nPORRST must be active during
power-up
1.1
VCCIO / VCCP high supply level when nPORRST must remain active
during power-up and become active during power down
3.0
Low-level input voltage of nPORRST VCCIO > 2.5V
Low-level input voltage of nPORRST VCCIO < 2.5V
0.2 * VCCIO
0.5
V
V
3
tsu(PORRST)
Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL
0
ms
during power-up
6
7
th(PORRST)
tsu(PORRST)
Hold time, nPORRST active after VCC > VCCPORH
1
2
ms
Setup time, nPORRST active before VCC < VCCPORH during power
µs
down
8
9
th(PORRST)
th(PORRST)
tf(nPORRST)
Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH
Hold time, nPORRST active after VCC < VCCPORL
1
0
ms
ms
ns
500
2000
Filter time nPORRST pin;
pulses less than MIN will be filtered out, pulses greater than MAX
will generate a reset.
3.3 V
1.2 V
VCCIOPORH
VCCIOPORH
VCCIO / VCCP
8
6
VCCPORH
VCC
VCCPORH
7
6
VCCIOPORL
7
VCCIOPORL
VCCPORL
VCCPORL
VCC (1.2 V)
VCCIO / VCCP(3.3 V)
3
9
VIL
VIL
VIL
VIL(PORRST)
VIL(PORRST)
nPORRST
NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.
Figure 4-1. nPORRST Timing Diagram
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4.4 Warm Reset (nRST)
This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset
condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the
output buffer is implemented as an open drain (drives low only). To ensure an external reset is not
arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. It also has an internal pullup
4.4.1 Causes of Warm Reset
Table 4-5. Causes of Warm Reset
DEVICE EVENT
SYSTEM STATUS FLAG
Exception Status Register, bit 15
Global Status Register, bit 0
Power-Up Reset
Oscillator fail
PLL slip
Global Status Register, bits 8 and 9
Exception Status Register, bit 13
Exception Status Register, bit 5
Exception Status Register, bit 4
Exception Status Register, bit 3
Watchdog exception / Debugger reset
CPU Reset (driven by the CPU STC)
Software Reset
External Reset
4.4.2 nRST Timing Requirements
Table 4-6. nRST Timing Requirements(1)
PARAMETER
MIN
MAX
UNIT
tv(RST)
Valid time, nRST active after
nPORRST inactive
1180 tc(OSC) + 1048tc(OSC)
ns
Valid time, nRST active (all other
System reset conditions)
8tc(VCLK)
500
tf(nRST)
2000
ns
Filter time nRST pin;
pulses less than MIN will be
filtered out, pulses greater than
MAX will generate a reset
(1) Specified values do NOT include rise/fall times. For rise and fall timings, see the switching characteristics for output timings versus load
capacitance table.
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4.5 ARM© Cortex-R4F™ CPU Information
4.5.1 Summary of ARM Cortex-R4F™ CPU Features
The features of the ARM Cortex-R4F™ CPU include:
•
•
An integer unit with integral EmbeddedICE-RT logic.
High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)
for Level two (L2) master and slave interfaces.
•
•
•
•
•
Floating Point Coprocessor
Dynamic branch prediction with a global history buffer, and a 4-entry return stack
Low interrupt latency.
Non-maskable interrupt.
A Harvard Level one (L1) memory system with:
–
Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking
memories
–
ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
•
•
Dual core logic for fault detection in safety-critical applications.
An L2 memory interface:
–
–
Single 64-bit master AXI interface
64-bit slave AXI interface to TCM RAM blocks
•
•
•
•
A debug interface to a CoreSight Debug Access Port (DAP).
A trace interface to a CoreSight ETM-R4.
A Performance Monitoring Unit (PMU).
A Vectored Interrupt Controller (VIC) port.
For more information on the ARM Cortex-R4F™ CPU please see www.arm.com.
4.5.2 ARM Cortex-R4F™ CPU Features Enabled by Software
The following CPU features are disabled on reset and must be enabled by the application if required.
•
•
•
•
ECC On Tightly-Coupled Memory (TCM) Accesses
Harware Vectored Interrupt (VIC) Port
Floating Point Coprocessor
Memory Protection Unit (MPU)
4.5.3 Dual Core Implementation
The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the
CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2
clock cycles as shown in Figure 4-3.
The CPUs have a diverse CPU placement given by following requirements:
•
•
different orientation; e.g. CPU1 = "north" orientation, CPU2 = "flip west" orientation
dedicated guard ring for each CPU
Flip West
North
Figure 4-2. Dual - CPU Orientation
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4.5.4 Duplicate clock tree after GCLK
The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU
running at the same frequency and in phase to the clock of CPU1. See Figure 4-3.
4.5.5 ARM Cortex-R4F™ CPU Compare Module (CCM) for Safety
This device has two ARM Cortex-R4F™ CPU cores, where the output signals of both CPUs are compared
in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed
in a different way as shown in the figure below.
Output + Control
CCM-R4
2 cycle delay
CCM-R4
compare
compare
error
CPU1CLK
CPU 1
CPU 2
2 cycle delay
CPU2CLK
Input + Control
Figure 4-3. Dual Core Implementation
To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of
both CPUs before the registers are used, including function calls where the register values are pushed
onto the stack.
4.5.6 CPU Self-Test
The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the
Deterministic Logic BIST Controller as the test engine.
The main features of the self-test controller are:
•
•
•
Ability to divide the complete test run into independent test intervals
Capable of running the complete test as well as running few intervals at a time
Ability to continue from the last executed interval (test set) as well as ability to restart from the
beginning (First test set)
•
•
•
Complete isolation of the self-tested CPU core from rest of the system during the self-test run
Ability to capture the Failure interval number
Timeout counter for the CPU self-test run as a fail-safe feature
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4.5.6.1 Application Sequence for CPU Self-Test
1. Configure clock domain frequencies.
2. Select number of test intervals to be run.
3. Configure the timeout period for the self-test run.
4. Enable self-test.
5. Wait for CPU reset.
6. In the reset handler, read CPU self-test status to identify any failures.
7. Retrieve CPU state if required.
For more information see the TMS570LS31X/21X Technical Reference Manual (SPNU499).
4.5.6.2 CPU Self-Test Clock Configuration
The maximum clock rate for the self-test is 90MHz. The STCCLK is divided down from the CPU clock.
This divider is configured by the STCCLKDIV register at address 0xFFFFE108.
For more information see the TMS570LS31X/21X Technical Reference Manual (SPNU499).
4.5.6.3 CPU Self-Test Coverage
Table 4-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test
cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.
Table 4-7. CPU Self-Test Coverage
INTERVALS
TEST COVERAGE, %
0
TEST CYCLES
0
0
1
62.13
70.09
74.49
77.28
79.28
80.90
82.02
83.10
84.08
84.87
85.59
86.11
86.67
87.16
87.61
87.98
88.38
88.69
88.98
89.28
89.50
89.76
90.01
90.21
1365
2
2730
3
4095
4
5460
5
6825
6
8190
7
9555
8
10920
12285
13650
15015
16380
17745
19110
20475
21840
23205
24570
25935
27300
28665
30030
31395
32760
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
56
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4.6 Clocks
4.6.1 Clock Sources
The table below lists the available clock sources on the device. Each of the clock sources can be enabled
or disabled using the CSDISx registers in the system module. The clock source number in the table
corresponds to the control bit in the CSDISx register for that clock source.
The table also shows the default state of each clock source.
Table 4-8. Available Clock Sources
Clock
Source #
Name
Description
Default State
0
1
2
3
4
OSCIN
PLL1
Main Oscillator
Output From PLL1
Enabled
Disabled
Disabled
Disabled
Enabled
Reserved
EXTCLKIN1
CLK80K
Reserved
External Clock Input #1
Low Frequency Output of Internal Reference Oscillator
High Frequency Output of Internal Reference
Oscillator
5
CLK10M
Enabled
6
7
PLL2
Output From PLL2
Disabled
Disabled
EXTCLKIN2
External Clock Input #2
4.6.1.1 Main Oscillator
The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors
across the external OSCIN and OSCOUT pins as shown in Figure 4-4. The oscillator is a single stage
inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test
measurement and low power modes.
TI strongly encourages each customer to submit samples of the device to the resonator/crystal
vendors for validation. The vendors are equipped to determine what load capacitors will best tune
their resonator/crystal to the microcontroller device for optimum start-up and operation over
temperature/voltage extremes.
An external oscillator source can be used by connecting a 3.3V clock signal to the OSCIN pin and leaving
the OSCOUT pin unconnected (open) as shown in the figure below.
(see Note B)
OSCIN
Kelvin_GND
OSCOUT
OSCIN
OSCOUT
C1
C2
External
Clock Signal
(toggling 0-3.3V)
(see Note A)
Crystal
(a)
(b)
Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor.
Note B: Kelvin_GND should not be connected to any other GND.
Figure 4-4. Recommended Crystal/Clock Connection
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4.6.1.1.1 Timing Requirements for Main Oscillator
Table 4-9. Timing Requirements for Main Oscillator
Parameter
MIN
50
Type
MAX
200
Unit
ns
tc(OSC)
Cycle time, OSCIN (when using a sine-wave input)
tc(OSC_SQR)
Cycle time, OSCIN, (when input to the OSCIN is a
square wave )
12.5
200
ns
tw(OSCIL)
tw(OSCIH)
Pulse duration, OSCIN low (when input to the OSCIN
is a square wave)
6
6
ns
ns
Pulse duration, OSCIN high (when input to the OSCIN
is a square wave)
58
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4.6.1.2 Low Power Oscillator
The Low Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single
macro.
4.6.1.2.1 Features
The main features of the LPO are:
•
•
•
Supplies a clock at extremely low power for power-saving modes. This is connected as clock source #
4 of the Global Clock Module.
Supplies a high-frequency clock for non-timing-critical systems. This is connected as clock source # 5
of the Global Clock Module.
Provides a comparison clock for the crystal oscillator failure detection circuit.
BIAS_EN
LFEN
CLK80K
LF_TRIM
Low
Power
Oscillator
HFEN
CLK10M
HF_TRIM
CLK10M_VALID
nPORRST
Figure 4-5. LPO Block Diagram
Figure 4-5 shows a block diagram of the internal reference oscillator. This is a low power oscillator (LPO)
and provides two clock sources: one nominally 80KHz and one nominally 10MHz.
4.6.1.2.2 LPO Electrical and Timing Specifications
Table 4-10. LPO Specifications
Parameter
MIN
Type
MAX
19.5
10
Unit
MHz
µs
LPO - HF oscillator
untrimmed frequency
5.5
9.6
startup time from STANDBY (LPO BIAS_EN High for
at least 900µs)
cold startup time
900
180
100
µs
kHz
µs
LPO - LF oscillator
untrimmed frequency
36
85
startup time from STANDBY (LPO BIAS_EN High for
at least 900µs)
cold startup time
2000
µs
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4.6.1.3 Phase Locked Loop (PLL) Clock Modules
The PLL is used to multiply the input frequency to some higher frequency.
The main features of the PLL are:
•
Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The
frequency modulation capability of PLL2 is permanently disabled.
Configurable frequency multipliers and dividers.
Built-in PLL Slip monitoring circuit.
•
•
•
Option to reset the device on a PLL slip detection.
4.6.1.3.1 Block Diagram
Figure 4-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and
PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the
multiplier and dividers for PLL2.
/NR
/OD
/R
PLLCLK
OSCIN
INTCLK
VCOCLK
post_ODCLK
PLL
/1 to /64
/1 to /8
/1 to /32
fPLLCLK = (fOSCIN / NR) * NF / (OD * R)
/NF
/1 to /256
/NR2
/OD2
/R2
PLL2CLK
OSCIN
VCOCLK2
INTCLK2
post_ODCLK2
/1 to /64
PLL#2
/1 to /8
/1 to /32
fPLL2CLK = (fOSCIN / NR2) * NF2 / (OD2 * R2)
/NF2
/1 to /256
Figure 4-6. ZWT PLLx Block Diagram
4.6.1.3.2 PLL Timing Specifications
Table 4-11. PLL Timing Specifications
PARAMETER
MIN
MAX
f(OSC_SQR)
UNIT
fINTCLK
PLL1 Reference Clock frequency
1
MHz
MHz
fpost_ODCLK
Post-ODCLK – PLL1 Post-divider input
400
clock frequency
fVCOCLK
VCOCLK – PLL1 Output Divider (OD) input
550
MHz
clock frequency
fINTCLK2
PLL2 Reference Clock frequency
1
f(OSC_SQR)
400
MHz
MHz
fpost_ODCLK2
Post-ODCLK – PLL2 Post-divider input
clock frequency
fVCOCLK2
VCOCLK – PLL2 Output Divider (OD) input
550
MHz
clock frequency
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4.6.1.4 External Clock Inputs
The device supports up to two external clock inputs. This clock input must be a square wave input. The
electrical and timing requirements for these clock inputs are specified below.
Table 4-12. External Clock Timing and Electrical Specifications
Parameter
fEXTCLKx
Description
External clock input frequency
EXTCLK high-pulse duration
EXTCLK low-pulse duration
Low-level input voltage
Min
Max
Unit
MHz
ns
80
tw(EXTCLKIN)H
tw(EXTCLKIN)L
viL(EXTCLKIN)
viH(EXTCLKIN)
6
6
ns
-0.3
2
0.8
V
High-level input voltage
VCCIO + 0.3
V
4.6.2 Clock Domains
4.6.2.1 Clock Domain Descriptions
The table below lists the device clock domains and their default clock sources. The table also shows the
system module control register that is used to select an available clock source for each clock domain.
Table 4-13. Clock Domain Descriptions
Clock Domain Name
Default Clock
Source
Clock Source
Selection Register
Description
HCLK
OSCIN
GHVSRC
•
•
Is disabled via the CDDISx registers bit 1
Used for all system modules including DMA, ESM
GCLK
OSCIN
GHVSRC
•
•
•
•
Always the same frequency as HCLK
In phase with HCLK
Is disabled separately from HCLK via the CDDISx registers bit 0
Can be divided by 1up to 8 when running CPU self-test (LBIST)
using the CLKDIV field of the STCCLKDIV register at address
0xFFFFE108
GCLK2
OSCIN
GHVSRC
•
•
•
•
Always the same frequency as GCLK
2 cycles delayed from GCLK
Is disabled along with GCLK
Gets divided by the same divider setting as that for GCLK when
running CPU self-test (LBIST)
VCLK
OSCIN
OSCIN
GHVSRC
GHVSRC
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK via the CDDISx registers bit 2
VCLK2
•
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Frequency must be an integer multiple of VCLK frequency
Is disabled separately from HCLK via the CDDISx registers bit 3
VCLK3
OSCIN
GHVSRC
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK via the CDDISx registers bit 8
VCLKA1
VCLKA2
VCLK
VCLK
VCLK
VCLKASRC
VCLKASRC
VCLKACON
•
•
Defaults to VCLK as the source
Is disabled via the CDDISx registers bit 4
•
•
Defaults to VCLK as the source
Is disabled via the CDDISx registers bit 5
VCLKA3_S
•
•
•
Defaults to VCLK as the source
Frequency can be as fast as HCLK frequency.
Is disabled via the CDDISx registers bit 10
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Table 4-13. Clock Domain Descriptions (continued)
Clock Domain Name
Default Clock
Clock Source
Description
Source
Selection Register
VCLKA3_DIVR
VCLK
VCLKACON1
•
•
Divided down from the AVCLK3_S using the VCLKA3R field of
the VCLKACON1 register at address 0xFFFFE140
Frequency can be VCLKA3_S/1, VCLKA3_S/2, ..., or
VCLKA3_S/8
•
•
Default frequency is VCLKA3_S/2
Is disabled separately via the VCLKACON1 register
VCLKA3_DIV_CDDIS bit only if the VCLKA3_S clock is not
disabled
VCLKA4
RTICLK
VCLK
VCLK
VCLKACON1
RCLKSRC
•
•
Defaults to VCLK as the source
Is disabled via the CDDISx registers bit 11
•
•
Defaults to VCLK as the source
If a clock source other than VCLK is selected for RTICLK, then
the RTICLK frequency must be less than or equal to VCLK/3
–
Application can ensure this by programming the RTI1DIV
field of the RCLKSRC register, if necessary
•
Is disabled via the CDDISx registers bit 6
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4.6.2.2 Mapping of Clock Domains to Device Modules
Each clock domain has a dedicated functionality as shown in the figures below.
GCM
0
GCLK, GCLK2 (to CPU)
OSCIN
FMzPLL
X1..256
(SSPLL)
/1..8
HCLK (to SYSTEM)
1
/1..32
/1..64
*
/1..16
VCLK_peri (VCLK to peripherals on PCR1)
VCLK_sys (VCLK to system modules)
VCLK2 (to NHETx and HTUx)
4
5
80kHz
/1..16
/1..16
Low Power
Oscillator
10MHz
VCLK3 (to EMIF, and Ethernet)
PLL # 2 (SSPLL)
6
/1..32
*
/1..64 X1..256
/1..8
0
1
3
4
5
6
3
7
* the frequency at this node must not
exceed the maximum HCLK specifiation.
EXTCLKIN1
EXTCLKIN2
VCLKA1 (to DCANx)
7
VCLK
VCLK3
0
1
3
VCLKA4
4
5
6
VCLKA2 (to FlexRay)
7
VCLK
Ethernet
0
1
3
4
VCLKA4 (to Ethernet, as alternate
for MIITXCLK and/or MIIRXCLK)
5
6
7
0
1
VCLK
3
4
/1, 2, 4, or 8
5
6
7
RTICLK (to RTI, DWWD)
EMIF
VCLK
VCLKA1
VCLK
VCLK2
VCLKA2
VCLK2
VCLKA2
HRP
/1..64
/2,3..224
/1,2..32
/1,2..65536
/1,2..256
/1,2,..4
/1,2,..256
/1,2,..1024
FlexRay
TU
NHETx
TU
GTUC1,2
LRP
/20..25
Prop_seg
Phase_seg2
FlexRay
Baud
Rate
I2C baud
rate
ECLK
SPI
Baud Rate
ADCLK
LIN / SCI
Baud Rate
Phase_seg1
I2C
Loop
High
Resolution Clock
SPIx,MibSPIx
LIN, SCI
External Clock
MibADCx
FlexRay
EXTCLKIN1
NTU[3]
CAN Baud Rate
DCANx
PLL#2 output
Start of cycle
Macro Tick
NTU[2]
NTU[1]
NTU[0]
NHETx
RTI
Figure 4-7. Device Clock Domains
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4.6.3 Clock Test Mode
The TMS570 platform architecture defines a special mode that allows various clock signals to be brought
out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is
very useful for debugging purposes and can be configured via the CLKTEST register in the system
module.
Table 4-14. Clock Test Mode Options
SEL_ECP_PIN
SEL_GIO_PIN
=
=
SIGNAL ON ECLK
SIGNAL ON N2HET1[12]
CLKTEST[3-0]
CLKTEST[11-8]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Oscillator
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Oscillator Valid Status
Main PLL Valid status
Reserved
Main PLL free-running clock output
Reserved
EXTCLKIN1
Reserved
CLK80K
Reserved
CLK10M
CLK10M Valid status
Secondary PLL Valid Status
Reserved
Secondary PLL free-running clock output
EXTCLKIN2
GCLK
CLK80K
RTI Base
Reserved
VCLKA1
VCLKA2
Reserved
VCLKA4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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4.7 Clock Monitoring
The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low
power oscillator (LPO).
The LPO provides two different clock sources – a low frequency (CLK80K) and a high frequency
(CLK10M).
The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN
frequency falls out of a frequency window, the CLKDET flags this condition in the global status register
(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the CLK10M clock (limp
mode clock).
The valid OSCIN frequency range is defined as: fCLK10M / 4 < fOSCIN < fCLK10M * 4.
4.7.1 Clock Monitor Timings
Table 4-15. LPO and Clock Detection
Parameter
Clock Detection
MIN
Type
MAX
Unit
oscillator fail frequency - lower threshold, using
untrimmed LPO output
1.375
2.4
4.875
MHz
oscillator fail frequency - higher threshold, using
untrimmed LPO output
22
38.4
9.6
78
MHz
LPO - HF oscillator
LPO - LF oscillator
LPO
untrimmed frequency
5.5
19.5
10
MHz
startup time from STANDBY (LPO BIAS_EN High for
at least 900ms)
µs
cold startup time
900
150
180
100
µs
µA
kHz
µs
ICC, CLK10M and CLK80K active
untrimmed frequency
36
85
startup time from STANDBY (LPO BIAS_EN High for
at least 900ms)
cold startup time
2000
27
µs
µA
µA
ICC, only CLK80K active
total ICC STANDBY current
20
upper
threshold
lower
threshold
guaranteed fail
guaranteed pass
guaranteed fail
f[MHz]
1.375
4.875
22
78
Figure 4-8. LPO and Clock Detection, Untrimmed CLK10M
4.7.2 External Clock (ECLK) Output Functionality
The ECLK pin can be configured to output a pre-scaled clock signal indicative of an internal device clock.
This output can be externally monitored as a safety diagnostic.
4.7.3 Dual Clock Comparators
The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by
counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of
spec, an error signal is generated. For example, the DCC1 can be configured to use CLK10M as the
reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration
allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.
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An additional use of this module is to measure the frequency of a selectable clock source, using the input
clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a
fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width
pulse (1 cycle) after a pre-programmed number of pulses. This pulse sets as an error signal if counter 1
does not reach 0 within the counting window generated by counter 0.
4.7.3.1 Features
Takes two different clock sources as input to two independent counter blocks.
•
•
One of the clock sources is the known-good, or reference clock; the second clock source is the "clock
under test."
•
•
Each counter block is programmable with initial, or seed values.
The counter blocks start counting down from their seed values at the same time; a mismatch from the
expected frequency for the clock under test generates an error signal which is used to interrupt the
CPU.
4.7.3.2 Mapping of DCC Clock Source Inputs
Table 4-16. DCC1 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
oscillator (OSCIN)
high frequency LPO
test clock (TCK)
others
0x5
0xA
Table 4-17. DCC1 Counter 1 Clock Sources
KEY [3:0]
CLOCK SOURCE [3:0]
CLOCK NAME
N2HET1[31]
others
-
0x0
Main PLL free-running clock output
PLL #2 free-running clock output
low frequency LPO
high frequency LPO
flash HD pump oscillator
EXTCLKIN1
0x1
0x2
0xA
0x3
0x4
0x5
0x6
EXTCLKIN2
0x7
ring oscillator
0x8 - 0xF
VCLK
Table 4-18. DCC2 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
others
0xA
oscillator (OSCIN)
test clock (TCK)
Table 4-19. DCC2 Counter 1 Clock Sources
KEY [3:0]
others
0xA
CLOCK SOURCE [3:0]
CLOCK NAME
N2HET2[0]
Reserved
VCLK
-
00x0 - 0x7
0x8 - 0xF
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4.8 Glitch Filters
A glitch filter is present on the following signals.
Table 4-20. Glitch Filter Timing Specifications
Pin
Parameter
MIN
MAX
Unit
nPORRST
tf(nPORRST)
tf(nRST)
500
2000
ns
Filter time nPORRST pin;
pulses less than MIN will be filtered out, pulses greater than
MAX will generate a reset(1)
nRST
TEST
500
500
2000
2000
ns
ns
Filter time nRST pin;
pulses less than MIN will be filtered out, pulses greater than
MAX will generate a reset
tf(TEST)
Filter time TEST pin;
pulses less than MIN will be filtered out, pulses greater than
MAX will pass through
(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,
I/O pins, etc.) without also generating a valid reset signal to the CPU.
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4.9 Device Memory Map
4.9.1 Memory Map Diagram
The figure below shows the device memory map.
0xFFFFFFFF
SYSTEM Modules
0xFFF80000
Peripherals - Frame 1
0xFF000000
0xFE000000
CRC
RESERVED
0xFCFFFFFF
Peripherals - Frame 2
RESERVED
0xFC000000
0xF07FFFFF
Flash Module Bus2 Interface
(Flash ECC, OTP and EEPROM accesses)
0xF0000000
RESERVED
0x202FFFFF
0x20000000
0x0843FFFF
0x08400000
Flash (3MB) (Mirrored Image)
RESERVED
RAM - ECC
RESERVED
0x0803FFFF
RAM (256KB)
0x08000000
0x002FFFFF
0x00000000
RESERVED
Flash (3MB)
Figure 4-9. Memory Map
The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash
image is 0x2000 0000.
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4.9.2 Memory Map Table
Please refer to and for a block diagrams showing the devices interconnect.
Table 4-21. Device Memory Map
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUA
SIZE L SIZE
MODULE NAME
START
END
Memories tightly coupled to the ARM Cortex-R4F CPU
TCM Flash
CS0
0x0000_0000
0x0800_0000
0x00FF_FFFF
0x0BFF_FFFF
16MB
64MB
3MB
TCM RAM + RAM
ECC
CSRAM0
256KB
Abort
Flash mirror
frame
Mirrored Flash
0x2000_0000
0x20FF_FFFF
16MB
3MB
External Memory Accesses
EMIF Chip Select
2 (asynchronous)
EMIF select 2
EMIF select 3
EMIF select 4
EMIF select 0
0x6000_0000
0x6400_0000
0x6800_0000
0x8000_0000
0x63FF_FFFF
0x67FF_FFFF
0x6BFF_FFFF
0x87FF_FFFF
64MB
16MB
16MB
16MB
EMIF Chip Select
3 (asynchronous)
64MB
64MB
Access to "Reserved" space will
generate Abort
EMIF Chip Select
4 (asynchronous)
EMIF Chip Select
0 (synchronous)
128MB 128MB
Flash Module Bus2 Interface
Customer OTP,
TCM Flash Banks
0xF000_0000
0xF000_FFFF
0xF000_FFFF
64KB
16KB
4KB
Customer OTP,
EEPROM Bank
0xF000_E000
0xF004_0000
8KB
8KB
Customer
OTP–ECC, TCM
Flash Banks
0xF004_1FFF
0xF004_1FFF
2KB
1KB
Customer
OTP–ECC,
0xF004_1C00
1KB
EEPROM Bank
TI OTP, TCM
Flash Banks
0xF008_0000
0xF008_E000
0xF00C_0000
0xF00C_1C00
0xF008_FFFF
0xF008_FFFF
0xF00C_1FFF
0xF00C_1FFF
64KB
8KB
8KB
1KB
16KB
4KB
2KB
1KB
Abort
TI OTP, EEPROM
Bank
TI OTP–ECC,
TCM Flash Banks
TI OTP–ECC,
EEPROM Bank
EEPROM
Bank–ECC
0xF010_0000
0xF020_0000
0xF040_0000
0xF013_FFFF
0xF03F_FFFF
0xF04F_FFFF
256KB
2MB
8KB
64KB
384KB
EEPROM Bank
Flash Data Space
ECC
1MB
Ethernet and EMIF slave interfaces
CPPI Memory
Slave (Ethernet
RAM)
0xFC52_0000
0xFCF7_8000
0xFC52_1FFF
0xFCF7_87FF
8KB
2KB
8KB
2KB
Abort
CPGMAC Slave
(Ethernet Slave)
No error
CPGMACSS
Wrapper
(Ethernet
Wrapper)
0xFCF7_8800
0xFCFF_E800
0xFCF7_88FF
0xFCFF_E8FF
256B
256B
256B
256B
No error
Abort
EMIF Registers
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Table 4-21. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUA
MODULE NAME
SIZE
L SIZE
START
END
Cyclic Redundancy Checker (CRC) Module Registers
CRC
CRC frame
0xFE00_0000
0xFEFF_FFFF
Peripheral Memories
0xFF0B_FFFF
16MB
512B
Accesses above 0x200 generate abort.
MIBSPI5 RAM
MIBSPI3 RAM
MIBSPI1 RAM
PCS[5]
PCS[6]
PCS[7]
0xFF0A_0000
0xFF0C_0000
0xFF0E_0000
128KB
128KB
128KB
2KB
2KB
2KB
Abort for accesses above 2KB
Abort for accesses above 2KB
Abort for accesses above 2KB
0xFF0D_FFFF
0xFF0F_FFFF
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
DCAN3 RAM
DCAN2 RAM
DCAN1 RAM
MIBADC2 RAM
MIBADC1 RAM
N2HET2 RAM
N2HET1 RAM
PCS[13]
PCS[14]
PCS[15]
PCS[29]
PCS[31]
PCS[34]
PCS[35]
0xFF1A_0000
0xFF1C_0000
0xFF1E_0000
0xFF3A_0000
0xFF3E_0000
0xFF44_0000
0xFF46_0000
0xFF1B_FFFF
0xFF1D_FFFF
0xFF1F_FFFF
0xFF3B_FFFF
0xFF3F_FFFF
0xFF45_FFFF
128KB
128KB
128KB
128KB
128KB
128KB
128KB
2KB
2KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
2KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
8KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
8KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
16KB
16KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
0xFF47_FFFF
0xFF4D_FFFF
N2HET2 TU2
RAM
PCS[38]
PCS[39]
0xFF4C_0000
0xFF4E_0000
128KB
128KB
1KB
1KB
Abort
Abort
N2HET1 TU1
RAM
0xFF4F_FFFF
Debug Components
0xFFA0_0FFF
CoreSight Debug
ROM
Reads return zeros, writes have no
effect
CSCS0
CSCS1
CSCS2
0xFFA0_0000
0xFFA0_1000
0xFFA0_2000
4KB
4KB
4KB
4KB
4KB
4KB
Cortex-R4F
Debug
Reads return zeros, writes have no
effect
0xFFA0_1FFF
0xFFA0_2FFF
Reads return zeros, writes have no
effect
ETM-R4
Reads return zeros, writes have no
effect
CoreSight TPIU
POM
CSCS3
CSCS4
0xFFA0_3000
0xFFA0_4000
0xFFA0_3FFF
0xFFA0_4FFF
4KB
4KB
4KB
4KB
Abort
Peripheral Control Registers
Reads return zeros, writes have no
effect
HTU1
HTU2
PS[22]
PS[22]
PS[17]
0xFFF7_A400
0xFFF7_A4FF
0xFFF7_A5FF
0xFFF7_B8FF
256B
256B
256B
256B
Reads return zeros, writes have no
effect
0xFFF7_A500
0xFFF7_B800
256B
256B
Reads return zeros, writes have no
effect
N2HET1
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Table 4-21. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUA
MODULE NAME
SIZE
256B
256B
512B
512B
256B
512B
512B
512B
256B
256B
512B
512B
512B
512B
512B
L SIZE
256B
256B
512B
512B
256B
512B
512B
512B
256B
256B
512B
512B
512B
512B
512B
START
END
Reads return zeros, writes have no
effect
N2HET2
GIO
PS[17]
PS[16]
PS[15]
PS[15]
PS[10]
PS[8]
PS[8]
PS[7]
PS[6]
PS[6]
PS[2]
PS[2]
PS[1]
PS[1]
PS[0]
0xFFF7_B900
0xFFF7_B9FF
Reads return zeros, writes have no
effect
0xFFF7_BC00
0xFFF7_C000
0xFFF7_C200
0xFFF7_D400
0xFFF7_DC00
0xFFF7_DE00
0xFFF7_E000
0xFFF7_E400
0xFFF7_E500
0xFFF7_F400
0xFFF7_F600
0xFFF7_F800
0xFFF7_FA00
0xFFF7_FC00
0xFFF7_BCFF
0xFFF7_C1FF
0xFFF7_C3FF
0xFFF7_D4FF
0xFFF7_DDFF
0xFFF7_DFFF
0xFFF7_E1FF
0xFFF7_E4FF
0xFFF7_E5FF
0xFFF7_F5FF
0xFFF7_F7FF
0xFFF7_F9FF
0xFFF7_FBFF
0xFFF7_FDFF
Reads return zeros, writes have no
effect
MIBADC1
MIBADC2
I2C
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
DCAN1
DCAN2
DCAN3
LIN
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
SCI
Reads return zeros, writes have no
effect
MibSPI1
SPI2
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
MibSPI3
SPI4
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
MibSPI5
System Modules Control Registers and Memories
DMA RAM
VIM RAM
PPCS0
PPCS2
0xFFF8_0000
0xFFF8_0FFF
4KB
4KB
Abort
Wrap around for accesses to
unimplemented address offsets lower
than 0x3FF. Abort generated for
accesses beyond 0x3FF.
0xFFF8_2000
0xFFF8_2FFF
4KB
1KB
RTP RAM
Flash Module
eFuse Controller
PPCS3
PPCS7
PPCS12
0xFFF8_3000
0xFFF8_7000
0xFFF8_C000
0xFFF8_3FFF
0xFFF8_7FFF
0xFFF8_CFFF
4KB
4KB
4KB
4KB
4KB
4KB
Abort
Abort
Abort
Power
Management
Module (PMM)
PPSE0
0xFFFF_0000
0xFFFF_01FF
512B
512B
Abort
Test Controller
(FMTM)
Reads return zeros, writes have no
effect
PPSE1
PPS0
0xFFFF_0400
0xFFFF_E000
0xFFFF_07FF
0xFFFF_E0FF
1KB
1KB
Reads return zeros, writes have no
effect
PCR registers
256B
256B
System Module -
Frame 2 (see
device TRM)
Reads return zeros, writes have no
effect
PPS0
0xFFFF_E100
0xFFFF_E1FF
256B
256B
Reads return zeros, writes have no
effect
PBIST
STC
PPS1
PPS1
0xFFFF_E400
0xFFFF_E600
0xFFFF_E5FF
0xFFFF_E6FF
512B
256B
512B
256B
Generates address error interrupt, if
enabled
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Table 4-21. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUA
MODULE NAME
SIZE
L SIZE
START
END
IOMM
Multiplexing
Control Module
Reads return zeros, writes have no
effect
PPS2
0xFFFF_EA00
0xFFFF_EBFF
512B
512B
Reads return zeros, writes have no
effect
DCC1
DMA
PPS3
PPS4
PPS5
PPS5
PPS5
PPS5
PPS6
PPS6
PPS6
PPS7
PPS7
PPS7
0xFFFF_EC00
0xFFFF_F000
0xFFFF_F400
0xFFFF_F500
0xFFFF_F600
0xFFFF_F700
0xFFFF_F800
0xFFFF_F900
0xFFFF_FA00
0xFFFF_FC00
0xFFFF_FD00
0xFFFF_FE00
0xFFFF_ECFF
0xFFFF_F3FF
0xFFFF_F4FF
0xFFFF_F5FF
0xFFFF_F6FF
0xFFFF_F7FF
0xFFFF_F8FF
0xFFFF_F9FF
0xFFFF_FAFF
0xFFFF_FCFF
0xFFFF_FDFF
0xFFFF_FEFF
256B
1KB
256B
1KB
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
DCC2
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
Reads return zeros, writes have no
effect
ESM
Reads return zeros, writes have no
effect
CCMR4
DMM
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
RAM ECC even
RAM ECC odd
RTP
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
RTI + DWWD
VIM Parity
VIM
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
System Module -
Frame 1 (see
device TRM)
Reads return zeros, writes have no
effect
PPS7
0xFFFF_FF00
0xFFFF_FFFF
256B
256B
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4.9.3 Master/Slave Access Privileges
The table below lists the access permissions for each bus master on the device. A bus master is a module
that can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.
Table 4-22. Master / Slave Access Matrix
MASTERS
ACCESS MODE
SLAVES ON MAIN SCR
CRC
Flash Module
Bus2 Interface:
OTP, ECC,
Non-CPU
Accesses to
Program Flash
and CPU Data
RAM
EMIF, Ethernet,
Slave Interfaces
Peripheral
Control
Registers, All
Peripheral
Memories, And
All System
Module Control
Registers And
Memories
EEPROM Bank
CPU READ
CPU WRITE
DMA
User/Privilege
User/Privilege
User
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
POM
User
DMM
User
DAP
Privilege
Privilege
Privilege
User
HTU1
HTU2
No
EMAC
No
4.9.3.1 Special Notes on Accesses to Certain Slaves
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU
(master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned OFF.
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4.9.4 POM Overlay Considerations
•
The POM overlay can map onto up to 8MB of the internal or external memory space. The starting
address and the size of the memory overlay are configurable via the POM module control registers.
Care must be taken to ensure that the overlay is mapped on to available memory.
•
•
•
ECC must be disabled by software via CP15 in case POM overlay is enabled; otherwise ECC errors
will be generated.
POM overlay must not be enabled when the flash and internal RAM memories are swapped via the
MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
When POM is used to overlay the flash on to internal or external RAM, there is a bus contention
possibility when another master accesses the TCM flash. This results in a system hang.
–
–
–
The POM module implements a timeout feature to detect this exact scenario. The timeout needs to
be enabled whenever POM overlay is enabled.
The timeout can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global
Control register (POMGLBCTRL, address = 0xFFA04000).
In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO)
flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is
generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a
data fetch.
–
The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM module
is set. If so, then the application can assume that the timeout is caused by a bus contention
between the POM transaction and another master accessing the same memory region. The abort
handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been
caused due to a timeout from the POM.
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4.10 Flash Memory
4.10.1 Flash Memory Configuration
Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a
customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense
amplifiers, and control logic.
Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical
construction constraints.
Flash Pump: A charge pump which generates all the voltages required for reading, programming, or
erasing the flash banks.
Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.
Table 4-23. Flash Memory Banks and Sectors
Memory Arrays (or Banks)(1)
Sector
No.
Segment
Low Address
High Address
BANK0 (1.5MBytes)
0
1
32K Bytes
32K Bytes
32K Bytes
32K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
0x0000_0000
0x0000_8000
0x0001_0000
0x0001_8000
0x0002_0000
0x0004_0000
0x0006_0000
0x0008_0000
0x000A_0000
0x000C_0000
0x000E_0000
0x0010_0000
0x0012_0000
0x0014_0000
0x0016_0000
0x0018_0000
0x001A_0000
0x001C_0000
0x001E_0000
0x0020_0000
0x0022_0000
0x0024_0000
0x0026_0000
0x0028_0000
0x002A_0000
0x002C_0000
0x002E_0000
0xF020_0000
0xF020_4000
0xF020_8000
0xF020_C000
0x0000_7FFF
0x0000_FFFF
0x0001_7FFF
0x0001_FFFF
0x0003_FFFF
0x0005_FFFF
0x0007_FFFF
0x0009_FFFF
0x000B_FFFF
0x000D_FFFF
0x000F_FFFF
0x0011_FFFF
0x0013_FFFF
0x0015_FFFF
0x0017_FFFF
0x0019_FFFF
0x001B_FFFF
0x001D_FFFF
0x001F_FFFF
0x0021_FFFF
0x0023_FFFF
0x0025_FFFF
0x0027_FFFF
0x0029_FFFF
0x002B_FFFF
0x002D_FFFF
0x002F_FFFF
0xF020_3FFF
0xF020_7FFF
0xF020_BFFF
0xF020_FFFF
2
3
4
5
6
7
8
9
10
11
12
13
14
0
BANK1 (1.5MBytes)
1
2
3
4
5
6
7
8
9
10
11
0
BANK7 (64kBytes) for EEPROM emulation(2)(3)
1
2
3
(1) The Flash banks are 144-bit wide bank with ECC support.
(2) The flash bank7 can be programmed while executing code from flash bank0 or bank1.
(3) Code execution is not allowed from flash bank7.
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4.10.2 Main Features of Flash Module
•
•
•
•
•
•
Support for multiple flash banks for program and/or data storage
Simultaneous read access on a bank while performing program or erase operation on any other bank
Integrated state machines to automate flash erase and program operations
Software interface for flash program and erase operations
Pipelined mode operation to improve instruction access interface bandwidth
Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU
–
Error address is captured for host system debugging
•
Support for a rich set of diagnostic features
4.10.3 ECC Protection for Flash Accesses
All accesses to the program flash memory are protected by Single Error Correction Double Error Detection
(SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of
instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on
the 64 bits received and compares it with the ECC code returned by the flash module. A signle-bit error is
corrected and flagged by the CPU, while a multi-bit error is only flagged. The CPU signals an ECC error
via its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the
"X" bit of the Performance Monitor Control Register, c9.
MRC p15,#0,r1,c9,c12,#0
ORR r1, r1, #0x00000010
MCR p15,#0,r1,c9,c12,#0
MRC p15,#0,r1,c9,c12,#0
;Enabling Event monitor states
;Set 4th bit (‘X’) of PMNC register
The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM
and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC
checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN
bits of the System Control coprocessor's Auxiliary Control Register, c1.
MRC p15, #0, r1, c1, c0, #1
ORR r1, r1, #0x0e000000
DMB
;Enable ECC checking for ATCM and BTCMs
MCR p15, #0, r1, c1, c0, #1
4.10.4 Flash Access Speeds
For information on flash memory access speeds and the relevant wait states required, refer to Section 3.4.
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4.10.5 Flash Program and Erase Timings
Table 4-24. Timing Specifications for Flash
Parameter
Wide Word (144bit) programming time
3MByte programming time(1)
MIN
NOM
MAX
tbd
Unit
µs
s
tprog (144bit)
tprog (Total)
40
-40°C to 125°C
tbd
0°C to 60°C, for first
8
tbd
s
25 cycles
tprog (Total)
EEPROM Emulation 64kByte programming
time(1)
-40°C to 12°5C
tbd
tbd
ms
ms
0°C to 60°C, for first
25 cycles
165
30
terase (sector)
Sector erase time
-40°C to 125°C
tbd
tbd
ms
ms
0°C to 60°C, for first
25 cycles
terase (bank)
terase (bank)
terase (bank)
twec
Bank erase time(2)
Bank erase time(2)
EEPROM Emulation Bank erase time(2)
Flash Bank 0
Flash Bank 1
Flash Bank 7
300
240
80
tbd
tbd
ms
ms
tbd
ms
Write/erase cycles
Flash Bank 0
Flash Bank 1
1000
cycles
twec
Write/erase cycles
Flash Bank 7
100000
cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time.
(2) Nominal conditions for the above specifications mean the first 25 program / erase cycles at an ambient temperature between 0c to 60c
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4.11 Tightly-Coupled RAM Interface Module
Figure 4-10 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F™ CPU.
VBUSP I/F PMT I/F
36 Bit
Upper 32 bits data &
4 ECC bits
wide
RAM
Cortex R4F™
EVEN Address
TCM BUS
TCRAM
B0
TCM
36 Bit
Interface 1
wide
RAM
64 Bit data bus
Lower32 bits data &
4 ECC bits
A
TCM
36 Bit
wide
RAM
Upper 32 bits data &
4 ECC bits
B1
TCM
ODD Address
TCM BUS
TCRAM
Interface 2
64 Bit data bus
36 Bit
wide
RAM
Lower32 bits data &
4 ECC bits
VBUSP I/F PMT I/F
Figure 4-10. TCRAM Block Diagram
4.11.1 Features
The features of the Tightly Coupled RAM (TCRAM) Module are:
•
•
•
•
•
•
•
•
Acts as slave to the Cortex-R4F CPU's BTCM interface
Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code
Monitors CPU Event Bus and generates single or multi-bit error interrupts
Stores addresses for single and multi-bit errors
Supports RAM trace module
Provides CPU address bus integrity checking by supporting parity checking on the address bus
Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved
RAM banks and generating independent RAM access control signals to the two banks
•
•
Supports auto-initialization of the RAM banks along with the ECC bits
No support for bit-wise RAM accesses
4.11.2 TCRAMW ECC Support
The TCRAMW passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. It also
stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The
TCRAMW monitors the CPU's event bus and provides registers for indicating single/multi-bit errors and
also for identifying the address that caused the single or multi-bit error. The event signaling and the ECC
checking for the RAM accesses must be enabled inside the CPU.
For more information see the TMS570LS31X/21X Technical Reference Manual (SPNU499).
4.12 Parity Protection for Accesses to peripheral RAMs
Accesses to all peripheral RAMs are protected by odd/even parity checking. During a read access the
parity is calculated based on the data read from the peripheral RAM and compared with the good parity
value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates
a parity error signal that is mapped to the Error Signaling Module. The module also captures the
peripheral RAM address that caused the parity error.
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The parity protection for peripheral RAMs is not enabled by default and must be enabled by the
application. Each individual peripheral contains control registers to enable the parity protection for
accesses to its RAM.
NOTE
The CPU read access gets the actual data from the peripheral. The application can choose
to generate an interrupt whenever a peripheral RAM parity error is detected.
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4.13 On-Chip SRAM Initialization and Testing
4.13.1 On-Chip SRAM Self-Test Using PBIST
4.13.1.1 Features
•
•
•
Extensive instruction set to support various memory test algorithms
ROM-based algorithms allow application to run TI production-level memory tests
Independent testing of all on-chip SRAM
4.13.1.2 PBIST RAM Groups
Table 4-25. PBIST RAM Grouping
Test Pattern (Algorithm)
March 13N(1)
two port
(cycles)
March 13N(1)
single port
(cycles)
triple read
slow read
triple read
fast read
Memory
RAM Group
Test Clock
MEM Type
ALGO MASK
0x1
ALGO MASK
0x2
ALGO MASK
0x4
ALGO MASK
0x8
PBIST_ROM
STC_ROM
DCAN1
1
ROM CLK
ROM CLK
VCLK
VCLK
VCLK
HCLK
VCLK
VCLK
VCLK
VCLK
VCLK
HCLK
VCLK
VCLK
HCLK
VCLK
VCLK
VCLK
HCLK
HCLK
ROM
X
X
X
X
2
ROM
3
Dual Port
Dual Port
Dual Port
Single Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Single Port
Single Port
25200
25200
25200
DCAN2
4
DCAN3
5
ESRAM1
MIBSPI1
MIBSPI3
MIBSPI5
VIM
6
266280
7
33440
33440
33440
12560
4200
8
9
10
11
12
13
14
15
18
19
20
21
22
23
24
25
28
MIBADC1
DMA
18960
31680
6480
N2HET1
HET TU1
RTP
37800
4200
MIBADC2
N2HET2
HET TU2
ESRAM5
ESRAM6
31680
6480
266280
266280
8700
6360
Dual Port
ETHERNET
ESRAM8
VCLK3
HCLK
Single Port
Single Port
133160
266280
(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for
application testing.
The PBIST ROM clock frequency is limited to 90MHz, if 90MHz < HCLK <= HCLKmax, or HCLK, if HCLK
<= 90MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV
field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
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4.13.2 On-Chip SRAM Auto Initialization
This microcontroller allows some of the on-chip memories to be initialized via the Memory Hardware
Initialization mechanism in the System module. This hardware mechanism allows an application to
program the memory arrays with error detection capability to a known state based on their error detection
scheme (odd/even parity or ECC).
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects
the memories that are to be initialized.
For more information on these registers see the TMS570LS31X/21X Technical Reference Manual
(SPNU499).
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in
Table 4-26.
Table 4-26. Memory Initialization
ADDRESS RANGE
CONNECTING MODULE
MSINENA REGISTER BIT #
BASE ADDRESS
0x08000000
0x08010000
0x08020000
0x08030000
0xFF0A0000
0xFF0C0000
0xFF0E0000
0xFF1A0000
0xFF1C0000
0xFF1E0000
0xFF3A0000
0xFF3E0000
0xFF440000
0xFF460000
0xFF4C0000
0xFF4E0000
0xFFF80000
0xFFF82000
0xFFF83000
ENDING ADDRESS
0x0800FFFF
0x0801FFFF
0x0802FFFF
0x0803FFFF
0xFF0BFFFF
0xFF0DFFFF
0xFF0FFFFF
0xFF1BFFFF
0xFF1DFFFF
0xFF1FFFFF
0xFF3BFFFF
0xFF3FFFFF
0xFF57FFFF
0xFF47FFFF
0xFF4DFFFF
0xFF4FFFFF
0xFFF80FFF
0xFFF82FFF
0xFFF83FFF
RAM (PD#1)
RAM (RAM_PD#1)
RAM (RAM_PD#2)
RAM (RAM_PD#3)
MIBSPI5 RAM
MIBSPI3 RAM
MIBSPI1 RAM
DCAN3 RAM
DCAN2 RAM
DCAN1 RAM
MIBADC2 RAM
MIBADC1 RAM
N2HET2 RAM
N2HET1 RAM
HET TU2 RAM
HET TU1 RAM
DMA RAM
0(1)
0(1)
0(1)
0(1)
12(2)
11(2)
7(2)
10
6
5
14
8
15
3
16
4
1
VIM RAM
2
RTP RAM
n/a
Ethernet RAM (CPPI Memory
Slave)
0xFC520000
0xFC521FFF
n/a
(1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized.
(2) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the multi-buffered mode is enabled. This is
independent of whether the application chooses to initialize the MibSPIx RAMs using the system module auto-initialization method.
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4.14 External Memory Interface (EMIF)
4.14.1 Features
The EMIF includes many features to enhance the ease and flexibility of connecting to external
asynchronous memories or SDRAM devices. The EMIF features includes support for:
•
•
•
•
•
•
•
3 addressable chip select for asynchronous memories of up to 16MB each
1 addressable chip select space for SDRAMs up to 128MB
8 or 16-bit data bus width
Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time
Select strobe mode
Extended Wait mode
Data bus parking
4.14.2 Electrical and Timing Specifications
4.14.2.1 Read Timing (Asynchronous RAM)
3
1
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_nDQM[1:0]
4
8
5
9
6
7
29
30
10
EMIF_nOE
13
12
EMIF_DATA[15:0]
EMIF_nWE
Figure 4-11. Asynchronous Memory Read Timing
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Extended Due to EMIF_WAIT
SETUP
STROBE
STROBE HOLD
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
14
11
EMIF_nOE
EMIF_WAIT
2
2
Asserted
Deasserted
Figure 4-12. EMIFnWAIT Read Timing Requirements
4.14.2.2 Write Timing (Asynchronous RAM)
15
1
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_nDQM[1:0]
16
17
19
21
23
18
20
24
22
EMIF_nWE
27
26
EMIF_DATA[15:0]
EMIF_nOE
Figure 4-13. Asynchronous Memory Write Timing
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Extended Due to EMIF_WAIT
SETUP
STROBE
STROBE HOLD
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
28
25
EMIF_nWE
EMIF_WAIT
2
2
Asserted
Deasserted
Figure 4-14. EMIFnWAIT Write Timing Requirements
4.14.2.3 Read Timing (Synchronous RAM)
BASIC SDRAM
1
READ OPERATION
2
2
EMIF_CLK
4
3
5
7
7
EMIF_nCS[0]
6
EMIF_nDQM[1:0]
EMIF_BA[1:0]
8
8
EMIF_ADDR[21:0]
19
20
2 EM_CLK Delay
18
17
EMIF_DATA[15:0]
EMIF_nRAS
11
12
13
14
EMIF_nCAS
EMIF_nWE
Figure 4-15. Basic SDRAM Read Operation
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4.14.2.4 Write Timing (Synchronous RAM)
1
BASIC SDRAM
WRITE OPERATION
2
2
EMIF_CLK
EMIF_CS[0]
3
5
7
7
9
4
6
EMIF_DQM[1:0]
EMIF_BA[1:0]
8
8
EMIF_ADDR[21:0]
10
EMIF_DATA[15:0]
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
11
12
13
15
16
Figure 4-16. Basic SDRAM Write Operation
4.14.2.5 EMIF Asynchronous Memory Timing
Table 4-27. EMIF Asynchronous Memory Timing Requirements
NO.
Value
NOM
Unit
MIN
MAX
Reads and Writes
2
tw(EM_WAIT)
Pulse duration, EMIFnWAIT
2E
ns
assertion and deassertion
Reads
12
13
14
tsu(EMDV-EMOEH)
th(EMOEH-EMDIV)
tsu(EMOEL-EMWAIT)
Setup time, EMIFDATA[15:0]
valid before EMIFnOE high
3
ns
ns
ns
Hold time, EMIFDATA[15:0]
valid after EMIFnOE high
0.5
Setup Time, EMIFnWAIT
asserted before end of Strobe
Phase(1)
4E+3
Writes
28
tsu(EMWEL-EMWAIT)
Setup Time, EMIFnWAIT
asserted before end of Strobe
Phase(1)
4E+3
ns
(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure Figure 4-12 and Figure Figure 4-14 describe EMIF transactions that include extended wait states inserted during the
STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start
of where the HOLD phase would begin if there were no extended wait cycles.
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Table 4-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3)
NO
Parameter
Value
NOM
Unit
MIN
MAX
Reads and Writes
1
3
td(TURNAROUND)
Turn around time
(TA)*E -3
Reads
(RS+RST+RH)* (RS+RST+RH)* (RS+RST+RH)*
E -3 E + 3
(RS+RST+RH+( (RS+RST+RH+( (RS+RST+RH+(
(TA)*E
(TA)*E + 3
ns
tc(EMRCYCLE)
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
ns
ns
E
EWC*16))*E -3
EWC*16))*E
EWC*16))*E +
3
4
5
tsu(EMCEL-EMOEL)
Output setup time,
EMIFnCS[4:2] low to EMIFnOE
low (SS = 0)
(RS)*E-3
(RS)*E
(RS)*E+3
ns
ns
Output setup time,
EMIFnCS[4:2] low to EMIFnOE
low (SS = 1)
-3
0
+3
th(EMOEH-EMCEH)
Output hold time, EMIFnOE high
to EMIFnCS[4:2] high (SS = 0)
(RH)*E -3
-3
(RH)*E
0
(RH)*E + 3
+3
ns
ns
ns
ns
ns
Output hold time, EMIFnOE high
to EMIFnCS[4:2] high (SS = 1)
6
7
8
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMBAV-EMOEL)
Output setup time, EMIFBA[1:0]
valid to EMIFnOE low
(RS)*E-3
(RH)*E-3
(RS)*E-3
(RS)*E
(RH)*E
(RS)*E
(RS)*E+3
(RH)*E+3
(RS)*E+3
Output hold time, EMIFnOE high
to EMIFBA[1:0] invalid
Output setup time,
EMIFADDR[21:0] valid to
EMIFnOE low
9
th(EMOEH-EMAIV)
tw(EMOEL)
Output hold time, EMIFnOE high
to EMIFADDR[21:0] invalid
(RH)*E-3
(RH)*E
(RH)*E+3
ns
ns
ns
ns
10
EMIFnOE active low width (EW
= 0)
(RST)*E-3
(RST)*E
(RST)*E+3
EMIFnOE active low width (EW
= 1)
(RST+(EWC*16 (RST+(EWC*16 (RST+(EWC*16
)) *E-3
))*E
)) *E+3
11
15
td(EMWAITH-EMOEH)
Delay time from EMIFnWAIT
deasserted to EMIFnOE high
3E-3
4E
4E+3
Writes
(WS+WST+WH (WS+WST+WH (WS+WST+WH
)* E-3 )*E )* E+3
tc(EMWCYCLE)
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
ns
ns
(WS+WST+WH (WS+WST+WH (WS+WST+WH
+( EWC*16))*E +(E WC*16))*E +( EWC*16))*E
-3
+ 3
16
17
tsu(EMCEL-EMWEL)
Output setup time,
EMIFnCS[4:2] low to EMIFnWE
low (SS = 0)
(WS)*E -3
(WS)*E
0
(WS)*E + 3
ns
ns
ns
Output setup time,
EMIFnCS[4:2] low to EMIFnWE
low (SS = 1)
-3
+3
th(EMWEH-EMCEH)
Output hold time, EMIFnWE
high to EMIFnCS[4:2] high (SS =
0)
(WH)*E-3
(WH)*E
(WH)*E+3
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1],
WH[8–1], and MEWC[1–256]. See the EMIF User’s guide for more information.
(2) E = EMIF_CLK period in ns.
(3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note
that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See
the EMIF User’s Guide for more information.
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Table 4-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)
Parameter
Value
NOM
0
Unit
MIN
MAX
Output hold time, EMIFnWE
high to EMIFCS[4:2] high (SS =
1)
-3
+3
ns
18
19
20
21
22
tsu(EMDQMV-EMWEL)
Output setup time, EMIFBA[1:0]
valid to EMIFnWE low
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E
(WS)*E+3
(WH)*E+3
(WS)*E+3
(WH)*E+3
(WS)*E+3
ns
ns
ns
ns
ns
th(EMWEH-EMDQMIV)
tsu(EMBAV-EMWEL)
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
Output hold time, EMIFnWE
high to EMIFBA[1:0] invalid
Output setup time, EMIFBA[1:0]
valid to EMIFnWE low
Output hold time, EMIFnWE
high to EMIFBA[1:0] invalid
Output setup time,
EMIFADDR[21:0] valid to
EMIFnWE low
23
24
th(EMWEH-EMAIV)
tw(EMWEL)
Output hold time, EMIFnWE
high to EMIFADDR[21:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
ns
ns
ns
ns
EMIFnWE active low width (EW
= 0)
(WST)*E-3
(WST)*E
(WST)*E+3
EMIFnWE active low width (EW
= 1)
(WST+(EWC*1 (WST+(EWC*1 (WST+(EWC*1
6)) *E-3
6))*E
6)) *E+3
25
26
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
Delay time from EMIFnWAIT
deasserted to EMIFnWE high
3E-3
4E
4E+3
Output setup time,
EMIFDATA[15:0] valid to
EMIFnWE low
(WS)*E-3
(WH)*E-3
(WS)*E
(WH)*E
(WS)*E+3
(WH)*E+3
27
th(EMWEH-EMDIV)
Output hold time, EMIFnWE
ns
high to EMIFDATA[15:0] invalid
Table 4-29. EMIF Synchronous Memory Timing Requirements
NO.
Parameter
tsu(EMIFDV-EM_CLKH)
MIN
MAX
Unit
19
Input setup time, read data valid on
EMIFDATA[15:0] before EMIF_CLK
rising
1
ns
20
th(CLKH-DIV)
Input hold time, read data valid on
EMIFDATA[15:0] after EMIF_CLK
rising
1.5
ns
Table 4-30. EMIF Synchronous Memory Switching Characteristics
NO.
1
Parameter
tc(CLK)
MIN
15
5
MAX
Unit
ns
Cycle time, EMIF clock EMIF_CLK
2
tw(CLK)
Pulse width, EMIF clock EMIF_CLK
high or low
ns
3
4
5
6
7
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
td(CLKH-AV)
Delay time, EMIF_CLK rising to
EMIFnCS[0] valid
7
7
7
ns
ns
ns
ns
ns
Output hold time, EMIF_CLK rising to
EMIFnCS[0] invalid
1
1
Delay time, EMIF_CLK rising to
EMIFnDQM[1:0] valid
Output hold time, EMIF_CLK rising to
EMIFnDQM[1:0] invalid
Delay time, EMIF_CLK rising to
EMIFADDR[21:0] and EMIFBA[1:0]
valid
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Table 4-30. EMIF Synchronous Memory Switching Characteristics (continued)
NO.
Parameter
MIN
MAX
Unit
8
toh(CLKH-AIV)
Output hold time, EMIF_CLK rising to
EMIFADDR[21:0] and EMIFBA[1:0]
invalid
1
ns
9
td(CLKH-DV)
Delay time, EMIF_CLK rising to
EMIFDATA[15:0] valid
7
7
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
tdis(CLKH-DHZ)
tena(CLKH-DLZ)
Output hold time, EMIF_CLK rising to
EMIFDATA[15:0] invalid
1
1
1
1
1
Delay time, EMIF_CLK rising to
EMIFnRAS valid
Output hold time, EMIF_CLK rising to
EMIFnRAS invalid
Delay time, EMIF_CLK rising to
EMIFnCAS valid
Output hold time, EMIF_CLK rising to
EMIFnCAS invalid
Delay time, EMIF_CLK rising to
EMIFnWE valid
Output hold time, EMIF_CLK rising to
EMIFnWE invalid
Delay time, EMIF_CLK rising to
EMIFDATA[15:0] tri-stated
Output hold time, EMIF_CLK rising to
EMIFDATA[15:0] driving
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4.15 Vectored Interrupt Manager
The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the
many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow
of program execution. Normally, these events require a timely response from the central processing unit
(CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to
an interrupt service routine (ISR).
4.15.1 VIM Features
The VIM module has the following features:
•
Supports 96 interrupt channels.
Provides programmable priority and enable for interrupt request lines.
–
•
•
Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
Provides two software dispatch mechanisms when the CPU VIC port is not used.
–
–
Index interrupt
Register vectored interrupt
•
Parity protected vector interrupt table against soft errors.
4.15.2 Interrupt Request Assignments
Table 4-31. Interrupt Request Assignments
Modules
Interrupt Sources
Default VIM Interrupt
Channel
ESM
Reserved
RTI
ESM High level interrupt (NMI)
Reserved
0
1
RTI compare interrupt 0
RTI compare interrupt 1
RTI compare interrupt 2
RTI compare interrupt 3
RTI overflow interrupt 0
RTI overflow interrupt 1
RTI timebase interrupt
GIO interrupt A
2
RTI
3
RTI
4
RTI
5
RTI
6
RTI
7
RTI
8
GIO
9
N2HET1
HET TU1
MIBSPI1
LIN
N2HET1 level 0 interrupt
HET TU1 level 0 interrupt
MIBSPI1 level 0 interrupt
LIN level 0 interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MIBADC1
MIBADC1
DCAN1
SPI2
MIBADC1 event group interrupt
MIBADC1 sw group 1 interrupt
DCAN1 level 0 interrupt
SPI2 level 0 interrupt
Reserved
Reserved
CRC
CRC Interrupt
ESM
ESM Low level interrupt
Software interrupt (SSI)
PMU Interrupt
SYSTEM
CPU
GIO
GIO interrupt B
N2HET1
HET TU1
MIBSPI1
N2HET1 level 1 interrupt
HET TU1 level 1 interrupt
MIBSPI1 level 1 interrupt
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Table 4-31. Interrupt Request Assignments (continued)
Modules
Interrupt Sources
Default VIM Interrupt
Channel
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67-72
73
74
75
76
77
78
LIN
LIN level 1 interrupt
MIBADC1 sw group 2 interrupt
DCAN1 level 1 interrupt
SPI2 level 1 interrupt
MIBADC1 magnitude compare interrupt
Reserved
MIBADC1
DCAN1
SPI2
MIBADC1
Reserved
DMA
FTCA interrupt
DMA
LFSA interrupt
DCAN2
DMM
DCAN2 level 0 interrupt
DMM level 0 interrupt
MIBSPI3 level 0 interrupt
MIBSPI3 level 1 interrupt
HBCA interrupt
MIBSPI3
MIBSPI3
DMA
DMA
BTCA interrupt
EMIF
AEMIFINT3
DCAN2
DMM
DCAN2 level 1 interrupt
DMM level 1 interrupt
DCAN1 IF3 interrupt
DCAN3 level 0 interrupt
DCAN2 IF3 interrupt
FPU interrupt
DCAN1
DCAN3
DCAN2
FPU
Reserved
SPI4
Reserved
SPI4 level 0 interrupt
MibADC2 event group interrupt
MibADC2 sw group1 interrupt
Reserved
MIBADC2
MIBADC2
Reserved
MIBSPI5
SPI4
MIBSPI5 level 0 interrupt
SPI4 level 1 interrupt
DCAN3 level 1 interrupt
MIBSPI5 level 1 interrupt
MibADC2 sw group2 interrupt
Reserved
DCAN3
MIBSPI5
MIBADC2
Reserved
MIBADC2
DCAN3
FMC
MibADC2 magnitude compare interrupt
DCAN3 IF3 interrupt
FSM_DONE interrupt
Reserved
Reserved
N2HET2
SCI
N2HET2 level 0 interrupt
SCI level 0 interrupt
HET TU2 level 0 interrupt
I2C level 0 interrupt
Reserved
HET TU2
I2C
Reserved
N2HET2
SCI
N2HET2 level 1 interrupt
SCI level 1 interrupt
HET TU2 level 1 interrupt
C0_MISC_PULSE
HET TU2
Ethernet
Ethernet
Ethernet
C0_TX_PULSE
C0_THRESH_PULSE
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Table 4-31. Interrupt Request Assignments (continued)
Modules
Interrupt Sources
Default VIM Interrupt
Channel
Ethernet
HWAG1
HWAG2
DCC1
C0_RX_PULSE
HWA_INT_REQ_H
HWA_INT_REQ_H
DCC done interrupt
DCC2 done interrupt
Reserved
79
80
81
82
DCC2
83
Reserved
HWAG1
HWAG2
Reserved
84-87
88
HWA_INT_REQ_L
HWA_INT_REQ_L
Reserved
89
90-95
NOTE
Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR
entry; therefore only request channels 0..94 can be used and are offset by 1 address in the
VIM RAM.
NOTE
The EMIF_nWAIT signal has a pull-up on it. The EMIF module generates a "Wait Rise"
interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt
condition is indicated as soon as the device is powered up. This can be ignored if the
EMIF_nWAIT signal is not used in the application. If the EMIF_nWAIT signal is actually used
in the application, then the external slave memory must always drive the EMIF_nWAIT signal
such that an interrupt is not caused due to the default pull-up on this signal.
NOTE
The lower-order interrupt channels are higher priority channels than the higher-order interrupt
channels.
NOTE
The application can change the mapping of interrupt sources to the interrupt channels via the
interrupt channel control registers (CHANCTRLx) inside the VIM module.
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4.16 DMA Controller
The DMA controller is used to transfer data between two locations in the memory map in the background
of CPU operations. Typically, the DMA is used to:
•
•
•
Transfer blocks of data between external and internal data memories
Restructure portions of internal data memory
Continually service a peripheral
4.16.1 DMA Features
•
•
•
•
•
•
•
•
•
•
•
•
•
CPU independent data transfer
One master port - PortB (64 bits wide) that interfaces to the TMS570 Memory System.
FIFO buffer(4 entries deep and each 64bit wide)
Channel control information is stored in RAM protected by parity
16 channels with individual enable
Channel chaining capability
32 peripheral DMA requests
Hardware and Software DMA requests
8, 16, 32 or 64-bit transactions supported
Multiple addressing modes for source/destination (fixed, increment, offset)
Auto-initiation
Power-management mode
Memory Protection with four configurable memory regions
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4.16.2 Default DMA Request Map
The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The
module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By
default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.
Some DMA requests have multiple sources, as shown in Table 4-32. The application must ensure that
only one of these DMA request sources is enabled at any time.
Table 4-32. DMA Request Line Connection
Modules
MIBSPI1
DMA Request Sources
MIBSPI1[1](1)
DMA Request
DMAREQ[0]
DMAREQ[1]
DMAREQ[2]
DMAREQ[3]
DMAREQ[4]
DMAREQ[5]
DMAREQ[6]
DMAREQ[7]
DMAREQ[8]
DMAREQ[9]
DMAREQ[10]
DMAREQ[11]
DMAREQ[12]
DMAREQ[13]
DMAREQ[14]
DMAREQ[15]
DMAREQ[16]
DMAREQ[17]
DMAREQ[18]
DMAREQ[19]
DMAREQ[20]
MIBSPI1
MIBSPI1[0](2)
SPI2
SPI2 receive
SPI2
SPI2 transmit
MIBSPI1 / MIBSPI3 / DCAN2
MIBSPI1 / MIBSPI3 / DCAN2
DCAN1 / MIBSPI5
MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3
MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2
DCAN1 IF2 / MIBSPI5[2]
MIBADC1 / MIBSPI5
MIBSPI1 / MIBSPI3 / DCAN1
MIBSPI1 / MIBSPI3 / DCAN2
MIBADC1 / I2C / MIBSPI5
MIBADC1 / I2C / MIBSPI5
RTI / MIBSPI1 / MIBSPI3
RTI / MIBSPI1 / MIBSPI3
MIBSPI3 / MibADC2 / MIBSPI5
MIBSPI3 / MIBSPI5
MIBADC1 event / MIBSPI5[3]
MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1
MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1
MIBADC1 G1 / I2C receive / MIBSPI5[4]
MIBADC1 G2 / I2C transmit / MIBSPI5[5]
RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6]
RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7]
MIBSPI3[1](1) / MibADC2 event / MIBSPI5[6]
MIBSPI3[0](2) / MIBSPI5[7]
MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2
MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2
RTI / MIBSPI5
MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1
MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2
RTI DMAREQ2 / MIBSPI5[8]
RTI / MIBSPI5
RTI DMAREQ3 / MIBSPI5[9]
N2HET1 / N2HET2 / DCAN3
N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3
IF2
N2HET1 / N2HET2 / DCAN3
N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3
IF3
DMAREQ[21]
MIBSPI1 / MIBSPI3 / MIBSPI5
MIBSPI1 / MIBSPI3 / MIBSPI5
MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10]
MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11]
DMAREQ[22]
DMAREQ[23]
DMAREQ[24]
N2HET1 / N2HET2 / SPI4 / MIBSPI5
N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4
receive / MIBSPI5[12]
N2HET1 / N2HET2 / SPI4 / MIBSPI5
N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4
transmit / MIBSPI5[13]
DMAREQ[25]
CRC / MIBSPI1 / MIBSPI3
CRC / MIBSPI1 / MIBSPI3
LIN / MIBSPI5
CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12]
CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13]
LIN receive / MIBSPI5[14]
DMAREQ[26]
DMAREQ[27]
DMAREQ[28]
DMAREQ[29]
DMAREQ[30]
LIN / MIBSPI5
LIN transmit / MIBSPI5[15]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5
MIBSPI1[14] / MIBSPI3[14] / SCI receive /
MIBSPI5[1](1)
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5
MIBSPI1[15] / MIBSPI3[15] / SCI transmit /
MIBSPI5[0](2)
DMAREQ[31]
(1) SPI1, SPI3, SPI5 receive in standard SPI mode
(2) SPI1, SPI3, SPI5 transmit in standard SPI mode
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4.17 Real Time Interrupt Module
The real-time interrupt (RTI) module provides timer functionality for operating systems and for
benchmarking code. The RTI module can incorporate several counters that define the timebases needed
for scheduling an operating system.
The timers also allow you to benchmark certain areas of code by reading the values of the counters at the
beginning and the end of the desired code range and calculating the difference between the values.
4.17.1 Features
The RTI module has the following features:
•
•
Two independent 64 bit counter blocks
Four configurable compares for generating operating system ticks or DMA requests. Each event can
be driven by either counter block 0 or counter block 1.
•
•
Fast enabling/disabling of events
Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block
4.17.2 Block Diagrams
Figure 4-17 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI
module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only
available as time base inputs for the counter block 0.
31
0
Compare
up counter
RTICPUCx
OVLINTx
31
0
=
Up counter
RTIUCx
31
0
RTICLK
To Compare
Unit
Free running counter
RTIFRCx
NTU0
NTU1
NTU2
NTU3
31
0
31
0
Capture
up counter
RTICAUCx
Capture
free running counter
RTICAFRCx
CAP event source 0
CAP event source 1
External
control
Figure 4-17. Counter Block Diagram
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31
Update
compare
0
RTIUDCPy
+
31
0
DMAREQy
INTy
Compare
RTICOMPy
From counter
block 0
=
From counter
block 1
Compare
control
Figure 4-18. Compare Block Diagram
4.17.3 Clock Source Options
The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.
The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the
System module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.
For more information on clock sources refer to Table 4-8 and Table 4-13.
4.17.4 Network Time Synchronization Inputs
The RTI module supports 4 Network Time Unit (NTU) inputs that signal internal system events, and which
can be used to synchronize the time base used by the RTI module. On this device, these NTU inputs are
connected as shown below.
Table 4-33. Network Time Synchronization Inputs
NTU Input
Source
Macrotick
0
1
2
3
Start of Cycle
PLL2 Clock output
EXTCLKIN1 clock input
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4.18 Error Signaling Module
The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller.
The error condition is handled based on a fixed severity level assigned to it. Any severe error condition
can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used
as an indicator to an external monitor circuit to put the system into a safe state.
4.18.1 Features
The features of the Error Signaling Module are:
•
128 interrupt/error channels are supported, divided into 3 different groups
–
–
–
64 channels with maskable interrupt and configurable error pin behavior
32 error channels with non-maskable interrupt and predefined error pin behavior
32 channels with predefined error pin behavior only
•
•
•
Error pin to signal severe device failure
Configurable timebase for error signal
Error forcing capability
4.18.2 ESM Channel Assignments
The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order
of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest
severity. The device response to each error is determined by the severity group it is connected to.
Table 4-35 shows the channel assignment for each group.
Table 4-34. ESM Groups
ERROR GROUP
Group1
INTERRUPT CHARACTERISTICS
maskable, low or high priority
non-maskable, high priority
no interrupt generated
INFLUENCE ON ERROR PIN
configurable
fixed
Group2
Group3
fixed
Table 4-35. ESM Channel Assignments
ERROR SOURCES
GROUP
Group1
Group1
Group1
Group1
Group1
Group1
CHANNELS
Reserved
MibADC2 - parity
DMA - MPU
0
1
2
3
4
5
DMA - parity
Reserved
DMA - imprecise read error
FMC - correctable error: bus1 and bus2 interfaces
(does not include accesses to EEPROM bank)
Group1
6
N2HET1/N2HET2 - parity
HET TU1/HET TU2 - parity
HET TU1/HET TU2 - MPU
PLL - Slip
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
7
8
9
10
11
12
13
14
15
16
17
Clock Monitor - interrupt
Reserved
DMA - imprecise write error
Reserved
VIM RAM - parity
Reserved
MibSPI1 - parity
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Table 4-35. ESM Channel Assignments (continued)
ERROR SOURCES
MibSPI3 - parity
GROUP
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
CHANNELS
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
MibADC1 - parity
Reserved
DCAN1 - parity
DCAN3 - parity
DCAN2 - parity
MibSPI5 - parity
Reserved
RAM even bank (B0TCM) - correctable error
CPU - selftest
RAM odd bank (B1TCM) - correctable error
Reserved
DCC1 - error
CCM-R4 - selftest
Reserved
Reserved
Reserved
FMC - correctable error (EEPROM bank access)
FMC - uncorrectable error (EEPROM bank access)
IOMM - Mux configuration error
Power domain controller compare error
Power domain controller self-test error
eFuse Controller Error – this error signal is generated when any bit in the eFuse
controller error status register is set. The application can choose to generate an
interrupt whenever this bit is set to service any eFuse controller error conditions.
Group1
Group1
40
41
eFuse Controller - Self Test Error. This error signal is generated only when a self
test on the eFuse controller generates an error condition. When this error signal is
set, group 1 channel 40 error signal will also be set.
PLL2 - Slip
Ethernet Controller master interface
Reserved
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Table 4-35. ESM Channel Assignments (continued)
ERROR SOURCES
DCC2 - error
Reserved
GROUP
Group1
Group1
CHANNELS
62
63
Reserved
Reserved
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
0
1
CCMR4 - compare
Reserved
2
3
FMC - uncorrectable error (address parity on bus1 accesses)
4
Reserved
5
RAM even bank (B0TCM) - uncorrectable error
6
Reserved
7
RAM odd bank (B1TCM) - uncorrectable error
8
Reserved
9
RAM even bank (B0TCM) - address bus parity error
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
RAM odd bank (B1TCM) - address bus parity error
Reserved
Reserved
Reserved
Flash (ATCM) - ECC live lock detect
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RTI_WWD_NMI
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
eFuse Controller - autoload error
Reserved
Group3
Group3
Group3
Group3
Group3
Group3
Group3
0
1
2
3
4
5
6
RAM even bank (B0TCM) - ECC uncorrectable error
Reserved
RAM odd bank (B1TCM) - ECC uncorrectable error
Reserved
FMC - uncorrectable error: bus1 and bus2 interfaces
(does not include address parity error and errors on accesses to EEPROM bank)
Group3
7
Reserved
Reserved
Reserved
Reserved
Group3
Group3
Group3
Group3
8
9
10
11
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Table 4-35. ESM Channel Assignments (continued)
ERROR SOURCES
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GROUP
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
CHANNELS
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
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4.19 Reset / Abort / Error Sources
Table 4-36. Reset/Abort/Error Sources
ESM HOOKUP
group.channel
ERROR SOURCE
SYSTEM MODE
ERROR RESPONSE
CPU TRANSACTIONS
User/Privilege
Precise write error (NCNB/Strongly Ordered)
Precise read error (NCB/Device or Normal)
Imprecise write error (NCB/Device or Normal)
Precise Abort (CPU)
Precise Abort (CPU)
Imprecise Abort (CPU)
n/a
n/a
n/a
User/Privilege
User/Privilege
Undefined Instruction Trap
(CPU)(1)
Illegal instruction
User/Privilege
n/a
n/a
MPU access violation
User/Privilege
SRAM
Abort (CPU)
B0 TCM (even) ECC single error (correctable)
User/Privilege
ESM
1.26
3.3
Abort (CPU), ESM =>
B0 TCM (even) ECC double error (non-correctable)
User/Privilege
User/Privilege
nERROR
B0 TCM (even) uncorrectable error (i.e. redundant address
decode)
ESM => NMI
2.6
B0 TCM (even) address bus parity error
User/Privilege
User/Privilege
ESM => NMI
2.10
1.28
B1 TCM (odd) ECC single error (correctable)
ESM
Abort (CPU), ESM =>
B1 TCM (odd) ECC double error (non-correctable)
User/Privilege
User/Privilege
3.5
nERROR
B1 TCM (odd) uncorrectable error (i.e. redundant address
decode)
ESM => NMI
ESM => NMI
2.8
B1 TCM (odd) address bus parity error
User/Privilege
2.12
FLASH
FMC correctable error - Bus1 and Bus2 interfaces (does not
include accesses to EEPROM bank)
User/Privilege
User/Privilege
ESM
1.6
3.7
FMC uncorrectable error - Bus1 accesses
(does not include address parity error)
Abort (CPU), ESM =>
nERROR
FMC uncorrectable error - Bus2 accesses
(does not include address parity error and EEPROM bank
accesses)
User/Privilege
ESM => nERROR
3.7
FMC uncorrectable error - address parity error on Bus1
accesses
User/Privilege
ESM => NMI
2.4
FMC correctable error - Accesses to EEPROM bank
FMC uncorrectable error - Accesses to EEPROM bank
User/Privilege
User/Privilege
ESM
ESM
1.35
1.36
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
response)
User/Privilege
ESM
ESM
1.5
External imprecise error on write (Illegal transaction with ok
response)
User/Privilege
1.13
Memory access permission violation
Memory parity error
User/Privilege
User/Privilege
ESM
ESM
1.2
1.3
DMM TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
response)
User/Privilege
ESM
ESM
1.5
External imprecise error on write (Illegal transaction with ok
response)
User/Privilege
1.13
HET TU1 (HTU1)
NCNB (Strongly Ordered) transaction with slave error response
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
User/Privilege
User/Privilege
User/Privilege
Interrupt => VIM
Interrupt => VIM
ESM
n/a
n/a
1.9
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage
of the CPU.
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Table 4-36. Reset/Abort/Error Sources (continued)
ESM HOOKUP
group.channel
ERROR SOURCE
SYSTEM MODE
ERROR RESPONSE
Memory parity error
User/Privilege
ESM
1.8
HET TU2 (HTU2)
NCNB (Strongly Ordered) transaction with slave error response
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
User/Privilege
User/Privilege
User/Privilege
User/Privilege
N2HET1
Interrupt => VIM
Interrupt => VIM
ESM
n/a
n/a
1.9
1.8
Memory parity error
ESM
Memory parity error
Memory parity error
User/Privilege
N2HET2
ESM
ESM
ESM
1.7
1.7
User/Privilege
ETHERNET MASTER INTERFACE
User/Privilege
MIBSPI
Any error reported by slave being accessed
1.43
MibSPI1 memory parity error
MibSPI3 memory parity error
MibSPI5 memory parity error
User/Privilege
User/Privilege
User/Privilege
MIBADC
ESM
ESM
ESM
1.17
1.18
1.24
MibADC1 Memory parity error
MibADC2 Memory parity error
User/Privilege
User/Privilege
DCAN
ESM
ESM
1.19
1.1
DCAN1 memory parity error
DCAN2 memory parity error
DCAN3 memory parity error
User/Privilege
User/Privilege
User/Privilege
PLL
ESM
ESM
ESM
1.21
1.23
1.22
PLL slip error
User/Privilege
User/Privilege
CLOCK MONITOR
User/Privilege
DCC
ESM
ESM
1.10
1.42
PLL #2 slip error
Clock monitor interrupt
ESM
1.11
DCC1 error
DCC2 error
User/Privilege
User/Privilege
CCM-R4
ESM
ESM
1.30
1.62
Self test failure
Compare failure
User/Privilege
User/Privilege
VIM
ESM
1.31
2.2
ESM => NMI
Memory parity error
User/Privilege
VOLTAGE MONITOR
n/a
ESM
Reset
ESM
ESM
1.15
n/a
VMON out of voltage range
CPU Selftest (LBIST) error
Mux configuration error
CPU SELFTEST (LBIST)
User/Privilege
PIN MULTIPLEXING CONTROL
User/Privilege
POWER DOMAIN CONTROL
User/Privilege
User/Privilege
eFuse Controller
User/Privilege
1.27
1.37
PSCON compare error
PSCON self-test error
ESM
ESM
1.38
1.39
eFuse Controller error
ESM
3.1
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Table 4-36. Reset/Abort/Error Sources (continued)
ESM HOOKUP
group.channel
ERROR SOURCE
SYSTEM MODE
ERROR RESPONSE
eFuse Controller - Any bit set in the error status register
eFuse Controller self-test error
User/Privilege
User/Privilege
ESM
ESM
1.40
1.41
WINDOWED WATCHDOG
n/a
WWD Non-Maskable Interrupt exception
ESM
2.24
ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset
n/a
n/a
n/a
n/a
n/a
n/a
Reset
Reset
Reset
Reset
Reset
Reset
n/a
n/a
n/a
n/a
n/a
n/a
Oscillator fail / PLL slip(2)
Watchdog exception
CPU Reset (driven by the CPU STC)
Software Reset
External Reset
(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.
4.20 Digital Windowed Watchdog
This device includes a digital windowed watchdog (DWWD) module that protects against runaway code
execution.
The DWWD module allows the application to configure the time window within which the DWWD module
expects the application to service the watchdog. A watchdog violation occurs if the application services the
watchdog outside of this window, or fails to service the watchdog at all. The application can choose to
generate a system reset or a non-maskable interrupt to the CPU in case of a watchdog violation.
The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog
can only be disabled upon a system reset.
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4.21 Debug Subsystem
4.21.1 Block Diagram
The device contains an ICEPICK module to allow JTAG access to the scan chains.
Boundary Scan
Boundary Scan I/F
BSR/BSDL
Debug
ROM1
TRST
TMS
TCK
RTCK
TDI
TDO
Debug APB
DAP
Secondary Tap 0
APB Mux
AHB-AP
APB slave
Cortex
R4F
POM
ETM
TPIU
from
PCR1/Bridge
to SCR1 via A2A
RTP
DMM
TAP 0
Secondary Tap 1
TAP 1
Secondary Tap 2
AJSM
Figure 4-19. ZWT Debug Subsystem Block Diagram
4.21.2 Debug Components Memory Map
Table 4-37. Debug Components Memory Map
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUA
MODULE NAME
SIZE
4KB
4KB
4KB
4KB
L SIZE
START
END
CoreSight Debug
ROM
Reads return zeros, writes have no
effect
CSCS0
CSCS1
CSCS2
CSCS3
0xFFA0_0000
0xFFA0_0FFF
4KB
Cortex-R4F
Debug
Reads return zeros, writes have no
effect
0xFFA0_1000
0xFFA0_2000
0xFFA0_3000
0xFFA0_1FFF
0xFFA0_2FFF
0xFFA0_3FFF
4KB
Reads return zeros, writes have no
effect
ETM-R4
4KB
Reads return zeros, writes have no
effect
CoreSight TPIU
4KB
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4.21.3 JTAG Identification Code
The JTAG ID code for this device is 0x0D8A002F. This is the same as the device ICEPick Identification
Code.
4.21.4 Debug ROM
The Debug ROM stores the location of the components on the Debug APB bus:
Table 4-38. Debug ROM table
ADDRESS
0x000
DESCRIPTION
pointer to Cortex-R4F
ETM-R4
VALUE
0x0000 1003
0x0000 2003
0x0000 3003
0x0000 4003
0x0000 0000
0x001
0x002
TPIU
0x003
POM
0x004
end of table
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4.21.5 JTAG Scan Interface Timings
Table 4-39. JTAG Scan Interface Timing(1)
No.
Parameter
Min
MAX
Unit
MHz
MHz
ns
fTCK
TCK frequency (at HCLKmax)
12
fRTCK
RTCK frequency (at TCKmax and HCLKmax)
Delay time, TCK to RTCK
10
1
2
3
4
5
td(TCK -RTCK)
tsu(TDI/TMS - RTCKr)
th(RTCKr -TDI/TMS)
th(RTCKr -TDO)
td(TCKf -TDO)
24
10
Setup time, TDI, TMS before RTCK rise (RTCKr)
Hold time, TDI, TMS after RTCKr
15
0
ns
ns
Hold time, TDO after RTCKf
0
ns
Delay time, TDO valid after RTCK fall (RTCKf)
ns
(1) Timings for TDO are specified for a maximum of 50pF load on TDO
TCK
RTCK
1
1
TMS
TDI
2
3
TDO
4
5
Figure 4-20. JTAG Timing
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4.21.6 Advanced JTAG Security Module
This device includes a an Advanced JTAG Security Module (AJSM). which provides maximum security to
the device’s memory content by allowing users to secure the device after programming.
Flash Module Output
OTP Contents
(example)
. . .
. . .
H
L
H
L
H
L
L
H
Unlock By Scan
Register
H
H
L
L
Internal Tie-Offs
(example only)
L
L
H
H
UNLOCK
128-bit comparator
Internal Tie-Offs
(example only)
H
L
L
H
H
L
L
H
Figure 4-21. AJSM Unlock
The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP
address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The
outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this
combinational logic is compared against a secret hard-wired 128-bit value. A match results in the
UNLOCK signal being asserted, so that the device is now unsecure.
A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing
a 0 to 1 is not possible since the visible unlock code is stored in the One Time Programmable (OTP) flash
region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the
device.
Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By
Scan" register of the AJSM module. The value to be scanned is such that the XOR of the OTP contents
and the Unlock-By-Scan register contents results in the original visible unlock code.
The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).
A secure device only permits JTAG accesses to the AJSM scan chain via the Secondary Tap # 2 of the
ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in
this state.
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4.21.7 Embedded Trace Macrocell (ETM-R4)
The device contains a ETM-R4 module with a 32-bit internal data port. The ETM-R4 module is connected
to a TPIU with a 32-bit data bus; the TPIU provides a 35-bit (32-bit data, 3-bit control) external interface
for trace. The ETM-R4 is CoreSight compliant and follows the ETM v3 specification; for more details see
ARM CoreSight ETM-R4 TRM specification.
4.21.7.1 ETM TRACECLKIN Selection
The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The
selection is done by the EXTCTRLOUT[1:0] control bits of the TPIU; the default is '00'. The address of this
register is TPIU base address + 0x404.
Before you begin accessing TPIU registers, TPIU should be unlocked via coresight key and 1 or 2 should
be written to this register.
Table 4-40. TPIU / TRACECLKIN Selection
EXTCTRLOUT[1:0]
TPIU/TRACECLKIN
tied-zero
00
01
10
11
VCLK
ETMTRACECLKIN
tied-zero
4.21.7.2 Timing Specifications
tl(ETM)
th(ETM)
tr(ETM)
tf(ETM)
tcyc(ETM)
Figure 4-22. ETMTRACECLKOUT Timing
Table 4-41. ETMTRACECLK Timing
Parameter
MIN
Description
tcyc(ETM)
tl(ETM)
t(HCLK) * 4
20ns
20ns
3ns
Clock period
Low pulse width
High pulse width
th(ETM)
tr(ETM)
tf(ETM)
Clock and data rise time
Clock and data fall time
3ns
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ETMTRACECLK
ETMDATA
tsu(ETM)
tsu(ETM)
th(ETM)
th(ETM)
Figure 4-23. ETMDATA Timing
Table 4-42. ETMDATA Timing
Parameter
MIN
Description
tsu(ETM)
th(ETM)
2.5ns
1.5ns
Data setup time
Data hold time
NOTE
The ETMTRACECLK and ETMDATA timing is based on a 15pF load and for ambient
temperature lower than 85°C.
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4.21.8 RAM Trace Port (RTP)
The RTP provides the ability to datalog the RAM contents of the TMS570 devices or accesses to
peripherals without program intrusion. It can trace all data write or read accesses to internal RAM. In
addition, it provides the capability to directly transfer data to a FIFO to support a CPU-controlled
transmission of the data. The trace data is transmitted over a dedicated external interface.
4.21.8.1 Features
The RTP offers the following features:
•
Two modes of operation - Trace Mode and Direct Data Mode
– Trace Mode
•
•
•
•
•
•
Non-intrusive data trace on write or read operation
Visibility of RAM content at any time on external capture hardware
Trace of peripheral accesses
2 configurable trace regions for each RAM module to limit amount of data to be traced
FIFO to store data and address of data of multiple read/write operations
Trace of CPU and/or DMA accesses with indication of the master in the transmitted data packet
–
Direct Data Mode
•
Directly write data with the CPU or trace read operations to a FIFO, without transmitting header
and address information
•
•
•
•
Dedicated synchronous interface to transmit data to external devices
Free-running clock generation or clock stop mode between transmissions
Up to 100 Mbit per sec/pin transfer rate for transmitting data
Pins not used in functional mode can be used as GIOs
4.21.8.2 Timing Specifications
tl(RTP)
th(RTP)
tf
tr
tcyc(RTP)
Figure 4-24. RTPCLK Timing
Table 4-43. RTPCLK Timing
Parameter
MIN
Description
tcyc(RTP)
tc(HCLK) * 2
Clock period, prescaled from HCLK; must not be faster
than HCLK / 2
th(RTP)
tl(RTP)
((tcyc(RTP))/2) - ((tr+tf)/2)
((tcyc(RTP))/2) - ((tr+tf)/2)
High pulse width
Low pulse width
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tssu(RTP)
tsh(RTP)
RTPSYNC
RTPCLK
RTPDATA
tdsu(RTP)
tdh(RTP)
Figure 4-25. RTPDATA Timing
Table 4-44. RTPDATA Timing
Parameter
MIN
Description
tdsu(RTP)
tdh(RTP)
tssu(RTP)
tsh(RTP)
3ns
2ns
3ns
2ns
Data setup time
Data hold time
SYNC setup time
SYNC hold time
tena(RTP)
tdis(RTP)
1
2
3
4
5
6
7
8
9
10 11
12 13
14
15 16
HCLK
RTPCLK
RTPnENA
RTPSYNC
RTPDATA
d1
d2
d3
d4
Divide by 1
d5
d6
d7
d8
Figure 4-26. RTPnENA timing
Table 4-45. RTPnENA timing
Parameter
MIN
3tc(HCLK)
tr(RTPSYNC)
12ns
MAX
Description
tdis(RTP)
+
+
time RTPnENA must go high before what would be the next RTPSYNC,
to guarantee delaying the next packet
tena(RTP)
4tc(HCLK)
tr(RTPSYNC)
+
5tc(HCLK)
tr(RTPSYNC)
12ns
+
+
time after RTPnENA goes low before a packet that has been halted,
resumes
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4.21.9 Data Modification Module (DMM)
The Data Modification Module (DMM) provides the capability to modify data in the entire 4 GB address
space of the TMS570 devices from an external peripheral, with minimal interruption of the application.
4.21.9.1 Features
The DMM module has the following features:
•
•
Acts as a bus master, thus enabling direct writes to the 4GB address space without CPU intervention
Writes to memory locations specified in the received packet (leverages packets defined by trace mode
of the RAM trace port (RTP) module
•
Writes received data to consecutive addresses, which are specified by the DMM module (leverages
packets defined by direct data mode of RTP module)
•
•
•
Configurable port width (1, 2, 4, 8, 16 pins)
Up to 100 Mbit/s pin data rate
Unused pins configurable as GIO pins
4.21.9.2 Timing Specifications
tl(DMM)
th(DMM)
tf
tr
tcyc(DMM)
Figure 4-27. DMMCLK Timing
Table 4-46. DMMCLK Timing
Parameter
MIN
Description
tcyc(DMM)
th(DMM)
tl(DMM)
tc(HCLK) * 2
Clock period
((tcyc(DMM))/2) - ((tr+tf)/2) High pulse width
((tcyc(DMM))/2) - ((tr+tf)/2) Low pulse width
tssu(DMM)
tsh(DMM)
DMMSYNC
DMMCLK
DMMDATA
tdsu(DMM)
tdh(DMM)
Figure 4-28. DMMDATA Timing
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Table 4-47. DMMDATA Timing
Parameter
MIN
Description
tssu(DMM)
tsh(DMM)
tdsu(DMM)
tdh(DMM)
2ns
3ns
2ns
3ns
SYNC active to clk falling edge setup time
clk falling edge to SYNC deactive hold time
DATA to clk falling edge setup time
clk falling edge to DATA hold time
HCLK
DMMCLK
DMMSYNC
D00
D01
D10
D11
D20
D21
D30
D31
D40
D41
D50
DMMDATA
DMMnENA
Figure 4-29. DMMnENA Timing
Figure 4-29 shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data
width = 8, portwidth = 4) where none of the packets received by the DMM are sent out, leading to filling up
of the internal buffers. The DMMnENA signal is shown asserted, after the first two packets have been
received and synchronised to the HCLK domain. Here, the DMM has the capacity to accept packets D4x,
D5x, D6x, D7x. Packet D8 would result in an overflow. Once DMMnENA is asserted, the DMM expects to
stop receiving packets after 4 HCLK cycles; once DMMnENA is de-asserted, the DMM can handle
packets immediately (after 0 HCLK cycles).
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4.21.10 Boundary Scan Chain
The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary
scan chain is connected to the Boundary Scan Interface of the ICEPICK module.
Device Pins (conceptual)
TRST
TMS
TCK
TDI
Boundary
Scan
Boundary Scan Interface
TDO
RTCK
TDI
TDO
BSDL
Figure 4-30. Boundary Scan Implementation (Conceptual Diagram)
Data is serially shifted into all boundary-scan buffers via TDI, and out via TDO.
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5 Peripheral Information and Electrical Specifications
5.1 Peripheral Legend
Table 5-1. Peripheral Legend
Abbreviation
MibADC
CCM-R4F
CRC
Full Name
Analog To Digital Converter
CPU Compare Module - CortexR4F
Cyclic Redundancy Check
Controller Area Network
Dual Clock Comparator
Direct Memory Access
DCAN
DCC
DMA
DMM
Data Modification Module
External Memory Interface
Error Signaling Module
EMIF
ESM
ETM-R4F
FTU
Embedded Trace Macrocell - CortexR4F
FlexRay Transfer Unit
GIO
General-Purpose Input/Output
High End Timer Transfer Unit
Inter-Integrated Circuit
HTU
I2C
LIN
Local Interconnect Network
Multibuffer Serial Peripheral Interface
Platform High-End Timer
MIBSPI
N2HET
POM
RTI
Parameter Overlay Module
Real-Time Interrupt Module
RAM Trace Port
RTP
SCI
Serial Communications Interface
Serial Peripheral Interface
Vectored Interrupt Manager
SPI
VIM
5.2 Multi-Buffered 12bit Analog-to-Digital Converter
The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that
enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could
be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given
with respect to ADREFLO unless otherwise noted.
Table 5-2. MibADC Overview
Description
Resolution
Value
12 bits
Assured
Monotonic
Output conversion code
00h to FFFh [00 for VAI ≤ ADREFLO; FFF for VAI ≥ ADREFHI]
5.2.1 Features
•
•
•
•
•
•
10-/12-bit resolution
ADREFHI and ADREFLO pins (high and low reference voltages)
Total Sample/Hold/Convert time: 600ns Typical Minimum at 30MHz ADCLK
One memory region per conversion group is available (event, group 1, group 2)
Allocation of channels to conversion groups is completely programmable
Memory regions are serviced either by interrupt or by DMA
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•
•
•
•
•
•
•
Programmable interrupt threshold counter is available for each group
Programmable magnitude threshold interrupt for each group for any one channel
Option to read either 8-bit, 10-bit or 12-bit values from memory regions
Single or continuous conversion modes
Embedded self-test
Embedded calibration logic
Enhanced power-down mode
–
Optional feature to automatically power down ADC core when no conversion is in progress
•
External event pin (ADEVT) programmable as general-purpose I/O
5.2.2 Event Trigger Options
The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3
groups can be configured to be hardware event-triggered. In that case, the application can select from
among 8 event sources to be the trigger for a group's conversions.
5.2.2.1 Default MIBADC1 Event Trigger Hookup
Table 5-3. MIBADC1 Event Trigger Hookup
Event #
Source Select Bits For G1, G2 Or Event
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
Trigger
1
2
3
4
5
6
7
8
000
001
010
011
100
101
110
111
ADEVT
N2HET1[8]
N2HET1[10]
RTI compare 0 interrupt
N2HET1[12]
N2HET1[14]
GIOB[0]
GIOB[1]
NOTE
For ADEVT, N2HET1 and GIOB trigger sources, the connection to the MibADC1 module
trigger input is made from the output side of the input buffer. This way, a trigger condition
can be generated either by configuring the function as output onto the pad (via the mux
control), or by driving the function from an external trigger source as input. If the mux control
module is used to select different functionality instead of the ADEVT, N2HET1[x] or GIOB[x]
signals, then care must be taken to disable these signals from triggering conversions; there
is no multiplexing on the input connections.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
5.2.2.2 Alternate MIBADC1 Event Trigger Hookup
Table 5-4. Alternate MIBADC1 Event Trigger Hookup
Event #
Source Select Bits for G1, G2 or Event
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
Trigger
1
2
000
001
ADEVT
N2HET2[5]
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Table 5-4. Alternate MIBADC1 Event Trigger Hookup (continued)
Event #
Source Select Bits for G1, G2 or Event
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
Trigger
3
4
5
6
7
8
010
N2HET1[27]
011
100
101
110
111
RTI compare 0 interrupt
N2HET1[17]
N2HET1[19]
N2HET1[11]
N2HET2[13]
The selection between the default MIBADC1 event trigger hook-up versus the alternate event trigger
hook-up is done by multiplexing control module register 30 bits 0 and 1.
If 30[0] = 1, then the default MibADC1 event trigger hook-up is used.
If 30[0] = 0 and 30[1] = 1, then the alternate MibADC1 event trigger hook-up is used.
NOTE
For ADEVT trigger source, the connection to the MibADC1 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
configuring ADEVT as an output function on to the pad (via the mux control), or by driving
the ADEVT signal from an external trigger source as input. If the mux control module is used
to select different functionality instead of the ADEVT signal, then care must be taken to
disable ADEVT from triggering conversions; there is no multiplexing on the input connection.
NOTE
For N2HETx trigger sources, the connection to the MibADC1 module trigger input is made
from the input side of the output buffer (at the N2HETx module boundary). This way, a
trigger condition can be generated even if the N2HETx signal is not selected to be output on
the pad.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
5.2.2.3 Default MIBADC2 Event Trigger Hookup
Table 5-5. MIBADC2 Event Trigger Hookup
Event #
Source Select Bits for G1, G2 or Event
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
Trigger
1
2
3
4
5
6
7
8
000
001
010
011
100
101
110
111
AD2EVT
N2HET1[8]
N2HET1[10]
RTI compare 0
N2HET1[12]
N2HET1[14]
GIOB[0]
GIOB[1]
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NOTE
For AD2EVT, N2HET1 and GIOB trigger sources, the connection to the MibADC2 module
trigger input is made from the output side of the input buffer. This way, a trigger condition
can be generated either by configuring the function as output onto the pad (via the mux
control), or by driving the function from an external trigger source as input. If the mux control
module is used to select different functionality instead of the AD2EVT, N2HET1[x] or GIOB[x]
signals, then care must be taken to disable these signals from triggering conversions; there
is no multiplexing on the input connections.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
5.2.2.4 Alternate MIBADC2 Event Trigger Hookup
Table 5-6. Alternate MIBADC2 Event Trigger Hookup
Event #
Source Select Bits for G1, G2 or Event
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
Trigger
1
2
3
4
5
6
7
8
000
001
010
011
100
101
110
111
AD2EVT
N2HET2[5]
N2HET1[27]
RTI compare 0
N2HET1[17]
N2HET1[19]
N2HET1[11]
N2HET2[13]
The selection between the default MIBADC2 event trigger hook-up versus the alternate event trigger
hook-up is done by multiplexing control module register 30 bits 0 and 1.
If 30[0] = 1, then the default MibADC2 event trigger hook-up is used.
If 30[0] = 0 and 30[1] = 1, then the alternate MibADC2 event trigger hook-up is used.
NOTE
For AD2EVT trigger source, the connection to the MibADC2 module trigger input is made
from the output side of the input buffer. This way, a trigger condition can be generated either
by configuring AD2EVT as an output function on to the pad (via the mux control), or by
driving the AD2EVT signal from an external trigger source as input. If the mux control module
is used to select different functionality instead of the AD2EVT signal, then care must be
taken to disable AD2EVT from triggering conversions; there is no multiplexing on the input
connections.
NOTE
For N2HETx trigger sources, the connection to the MibADC2 module trigger input is made
from the input side of the output buffer (at the N2HETx module boundary). This way, a
trigger condition can be generated even if the N2HETx signal is not selected to be output on
the pad.
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NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
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5.2.3 ADC Electrical and Timing Specifications
Table 5-7. MibADC Recommended Operating Conditions
Parameter
MIN
ADREFLO
VSSAD
ADREFLO
- 2
MAX
VCCAD
ADREFHI
ADREFHI
2
Unit
V
ADREFHI
ADREFLO
VAI
A-to-D high-voltage reference source
A-to-D low-voltage reference source
Analog input voltage
V
V
IAIC
Analog input clamp current
mA
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
Table 5-8. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions(1)
Parameter
Description/Conditions
MIN
Type MAX
Unit
Rmux
Analog input mux
on-resistance
See Figure 5-1
250
Ω
Rsamp
ADC sample switch
on-resistance
See Figure 5-1
250
Ω
Cmux
Csamp
IAIL
Input mux capacitance
See Figure 5-1
See Figure 5-1
16
13
pF
pF
nA
ADC sample capacitance
Analog off-state input
leakage current, for VCCAD
3.6V maximum
Off-state input leakage per
ADC input pin
V
SSAD < VIN < VSSAD
+
300
=
=
100mV
VSSAD + 100mV < VIN
VCCAD - 200mV
<
200
500
1
nA
nA
µA
nA
µA
VCCAD - 200mV < VIN
VCCAD
<
IAIL
Analog off-state input
leakage current, for VCCAD
5.5V maximum
Off-state input leakage per
ADC input pin
VIN > VSSAD
,
VIN < VSSAD + 300mV
V
V
IN > VSSAD + 300mV,
IN < VCCAD - 300mV
250
1
V
V
IN > VCCAD - 300mV,
IN < VCCAD
IADREFHI
ICCAD
ADREFHI input current
Static supply current
ADREFHI = VCCAD, ADREFLO = VSSAD
Normal operating mode
3
15
5
mA
mA
µA
ADC core in power down mode
(1) 1 LSB = (ADREFHI – ADREFLO)/ 212 for the MibADC
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Rext
Pin
Rmux
Smux
VS1
39*IAIL
Cext
On-State
Leakage
Smux
Rext
Pin
Rmux
VS2
IAIL
Cext
IAIL
IAIL
Off-State
Leakages
Smux
Rext
Pin
Rmux
Ssamp
Rsamp
VS24
IAIL
Csamp
Cmux
Cext
IAIL
IAIL
Figure 5-1. MibADC Input Equivalent Circuit
Table 5-9. MibADC Timing Specifications
Parameter
Cycle time, MibADC clock
MIN
0.033
0.2
NOM
MAX
Unit
µs
(1)
tc(ADCLK)
(2)
td(SH)
Delay time, sample and hold
time
µs
12-bit mode
td©)
Delay time, conversion time
0.4
0.6
µs
µs
(3)
td(SHC)
Delay time, total sample/hold
and conversion time
10-bit mode
td©)
Delay time, conversion time
0.33
0.53
µs
µs
(4)
td(SHC)
Delay time, total sample/hold
and conversion time
(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits
4:0.
(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each
conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as
well as the ADC’s internal impedance.
(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the
prescale settings.
(4) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the
prescale settings.
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Table 5-10. MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions
Parameter
Description/Conditions
MIN
Type
MAX
Unit
CR
Conversion range over ADREFHI - ADREFLO
3
5.5
V
which specified
accuracy is
maintained
ZSET
Zero Scale Offset
Difference between the first ideal transition
(from code 000h to 001h) and the actual
transition
10-bit
mode
1
2
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
12-bit
mode
FSET
EDNL
EINL
Full Scale Offset
Difference between the range of the
measured code transitions (from first to last)
and the range of the ideal code transitions
10-bit
mode
2
12-bit
mode
3
Differential
nonlinearity error
Difference between the actual step width and 10-bit
the ideal value. (See Figure 76)
± 1.5
± 2
± 2
± 2
± 2
± 4
mode
12-bit
mode
Integral nonlinearity
error
Maximum deviation from the best straight line 10-bit
through the MibADC. MibADC transfer
characteristics, excluding the quantization
error.
mode
12-bit
mode
ETOT
Total unadjusted error Maximum value of the difference between an 10-bit
(after calibration)
analog value and the ideal midstep value.
mode
12-bit
mode
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5.2.4 Performance (Accuracy) Specifications
5.2.4.1 MibADC Nonlinearity Errors
The differential nonlinearity error shown in Figure Figure 5-2 (sometimes referred to as differential
linearity) is the difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
0 ... 101
0 ... 100
0 ... 011
Differential Linearity
Error (–½ LSB)
1 LSB
0 ... 010
Differential Linearity
Error (–½ LSB)
0 ... 001
0 ... 000
1 LSB
0
1
2
3
4
5
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/212
Figure 5-2. Differential Nonlinearity (DNL) Error
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The integral nonlinearity error shown in Figure Figure 5-3 (sometimes referred to as linearity error) is the
deviation of the values on the actual transfer function from a straight line.
0 ... 111
0 ... 110
Ideal
Transition
0 ... 101
0 ... 100
0 ... 011
0 ... 010
0 ... 001
0 ... 000
Actual
Transition
At Transition
011/100
(–½ LSB)
End-Point Lin. Error
At Transition
001/010 (–1/4 LSB)
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/212
Figure 5-3. Integral Nonlinearity (INL) Error
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5.2.4.2 MibADC Total Error
The absolute accuracy or total error of an MibADC as shown in Figure Figure 5-4 is the maximum value of
the difference between an analog value and the ideal midstep value.
0 ... 111
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011
0 ... 010
Total Error
At Step
0 ... 001 (1/2 LSB)
0 ... 001
0 ... 000
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/212
Figure 5-4. Absolute Accuracy (Total) Error
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5.3 General-Purpose Input/Output
The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and
bit-programmable. Both GIOA and GIOB support external interrupt capability.
5.3.1 Features
The GPIO module has the following features:
•
Each IO pin can be configured as:
–
–
–
Input
Output
Open Drain
•
The interrupts have the following characteristics:
–
–
–
–
Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)
Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)
Individual interrupt flags (set in GIOFLG register)
Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers
respectively
–
Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers
•
Internal pullup/pulldown allows unused I/O pins to be left unconnected
For information on input and output timings see Section 3.8 and Section 3.9
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5.4 Enhanced High-End Timer (N2HET)
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O.. It is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses.
5.4.1 Features
The N2HET module has the following features:
•
•
•
•
•
Programmable timer for input and output timing functions
Reduced instruction set (30 instructions) for dedicated time and angle functions
160 words of instruction RAM protected by parity
User defined number of 25-bit virtual counters for timer, event counters and angle counters
7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual
counters
•
•
•
•
Up to 32 pins usable for input signal measurements or output signal generation
Programmable suppression filter for each input pin with adjustable limiting frequency
Low CPU overhead and interrupt load
Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU)
or DMA
•
Diagnostic capabilities with different loopback mechanisms and pin status readback functionality
5.4.2 N2HET RAM Organization
The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one
RAM address may be written while another address is read. The RAM words are 96-bits wide, which are
split into three 32-bit fields (program, control, and data).
5.4.3 Input Timing Specifications
The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.
1
NHETx
3
4
2
Figure 5-5. N2HET Input Capture Timings
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Table 5-11. Dynamic Characteristics for the N2HET Input Capture Functionality
PARAMETER
MIN(1) (2)
MAX(1) (2)
UNIT
1
2
3
4
Input signal period, PCNT or WCAP for rising edge 2 (hr) (lr) tc(VCLK2) + 2
to rising edge
225 (hr) (lr) tc(VCLK2) - 2
ns
Input signal period, PCNT or WCAP for falling edge 2 (hr) (lr) tc(VCLK2) + 2
to falling edge
225 (hr) (lr) tc(VCLK2) - 2
225 (hr) (lr) tc(VCLK2) - 2
225 (hr) (lr) tc(VCLK2) - 2
ns
ns
ns
Input signal high phase, PCNT or WCAP for rising
edge to falling edge
(hr) (lr) tc(VCLK2) + 2
Input signal low phase, PCNT or WCAP for falling
edge to rising edge
(hr) (lr) tc(VCLK2) + 2
(1) hr = High-resolution prescaler, configured using the HRPFC field of the Prescale Factor Register (HETPFR).
(2) lr = Loop-resolution prescaler, configured using the LFPRC field of the Prescale Factor Register (HETPFR)
Both N2HET1 and N2HET2 have three channels each that are enhanced to be able to capture inputs with
smaller pulse widths than that specified in Table 5-11. These are N2HET1 channels 15, 20 and 31, and
N2HET2 channels 12, 14 and 16.
The input capture capability for these channels is specified in the following table.
Table 5-12. Input Capture Capability for N2HET Channels with Enhancements
PARAMETER
MIN
MAX
UNIT
1
2
3
4
Input signal period, PCNT or WCAP for rising edge (hr) (lr) tc(VCLK2) + 2
to rising edge
225 (hr) (lr) tc(VCLK2) - 2
ns
Input signal period, PCNT or WCAP for falling edge (hr) (lr) tc(VCLK2) + 2
to falling edge
225 (hr) (lr) tc(VCLK2) - 2
225 (hr) (lr) tc(VCLK2) - 2
225 (hr) (lr) tc(VCLK2) - 2
ns
ns
ns
Input signal high phase, PCNT or WCAP for rising
edge to falling edge
2 (hr) tc(VCLK2) + 2
Input signal low phase, PCNT or WCAP for falling
edge to rising edge
2 (hr) tc(VCLK2) + 2
5.4.4 N2HET1-N2HET2 Interconnections
In some applications the N2HET resolutions must be synchronized. Some other applications require a
single time base to be used for all PWM outputs and input timing captures.
The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures
the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal
to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to
the loop resolution signal sent by the master. The slave does not require this signal after it receives the
first synchronization signal. However, anytime the slave receives the re-synchronization signal from the
master, the slave must synchronize itself again..
NHET1
NHET2
NHET_LOOP_SYNC
EXT_LOOP_SYNC
NHET_LOOP_SYNC
EXT_LOOP_SYNC
Figure 5-6. N2HET1 – N2HET2 Synchronization Hookup
5.4.5 N2HET Checking
5.4.5.1 Internal Monitoring
To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be
used to monitor each other’s signals as shown in Figure 5-7. The direction of the monitoring is controlled
by the I/O multiplexing control module.
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IOMM mux control signal x
NHET1[1,3,5,7,9,11]
NHET1[1,3,5,7,9,11] / NHET2[8,10,12,14,16,18]
NHET1
NHET2[8,10,12,14,16,18]
NHET2
Figure 5-7. N2HET Monitoring
5.4.5.2 Output Monitoring using Dual Clock Comparator (DCC)
N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure
the frequency of the pulse-width modulated (PWM) signal on N2HET1[31].
Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to
measure the frequency of the pulse-width modulated (PWM) signal on N2HET2[0].
Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection
to the DCC module is made directly from the output of the N2HETx module (from the input of the output
buffer).
For more information on DCC see Section 4.7.3.
5.4.6 Disabling N2HET Outputs
Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET
module provides this capability via the "Pin Disable" input signal. This signal, when driven low, causes the
N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. Please refer to the
RM48x Technical Reference Manual (SPNU481) for more details on the "N2HET Pin Disable" feature.
GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin
Disable" input for N2HET2.
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5.4.7 High-End Timer Transfer Unit (HET-TU)
A High End Timer Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to
or from main memory. A Memory Protection Unit (MPU) is built into the HET-TU.
5.4.7.1 Features
CPU and DMA independent
•
•
•
•
•
•
•
Master Port to access system memory
8 control packets supporting dual buffer configuration
Control packet information is stored in RAM protected by parity
Event synchronization (HET transfer requests)
Supports 32 or 64 bit transactions
Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or
64bit)
•
•
One shot, circular and auto switch buffer transfer modes
Request lost detection
5.4.7.2 Trigger Connections
Table 5-13. HET TU1 Request Line Connection
Modules
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
Request Source
HTUREQ[0]
HTUREQ[1]
HTUREQ[2]
HTUREQ[3]
HTUREQ[4]
HTUREQ[5]
HTUREQ[6]
HTUREQ[7]
HET TU1 Request
HET TU1 DCP[0]
HET TU1 DCP[1]
HET TU1 DCP[2]
HET TU1 DCP[3]
HET TU1 DCP[4]
HET TU1 DCP[5]
HET TU1 DCP[6]
HET TU1 DCP[7]
Table 5-14. HET TU2 Request Line Connection
Modules
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
Request Source
HTUREQ[0]
HTUREQ[1]
HTUREQ[2]
HTUREQ[3]
HTUREQ[4]
HTUREQ[5]
HTUREQ[6]
HTUREQ[7]
HET TU2 Request
HET TU2 DCP[0]
HET TU2 DCP[1]
HET TU2 DCP[2]
HET TU2 DCP[3]
HET TU2 DCP[4]
HET TU2 DCP[5]
HET TU2 DCP[6]
HET TU2 DCP[7]
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5.5 Controller Area Network (DCAN)
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication
protocol that efficiently supports distributed real-time control with robust communication rates of up to 1
megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh
environments (e.g., automotive and industrial fields) that require reliable serial communication or
multiplexed wiring.
5.5.1 Features
Features of the DCAN module include:
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 MBit/s
The CAN kernel can be clocked by the oscillator for baud-rate generation.
64 mailboxes on each DCAN
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Message RAM protected by parity
Direct access to Message RAM during test mode
CAN Rx / Tx pins configurable as general purpose IO pins
Message RAM Auto Initialization
DMA support
For more information on the DCAN see the TMS570LS31X/21X Technical Reference Manual (SPNU499).
5.5.2 Electrical and Timing Specifications
Table 5-15. Dynamic Characteristics for the DCANx TX and RX pins
Parameter
MIN
MAX
15
Unit
ns
td(CANnTX)
td(CANnRX)
Delay time, transmit shift register to CANnTX pin(1)
Delay time, CANnRX pin to receive shift register
5
ns
(1) These values do not include rise/fall times of the output buffer.
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5.6 Local Interconnect Network Interface (LIN)
The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is
an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility.
The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn
to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a
K-line.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is
single-master/multiple-slave with a message identification for multi-cast transmission between any network
nodes.
5.6.1 LIN Features
The following are features of the LIN module:
•
•
•
•
Compatible to LIN 1.3, 2.0 and 2.1 protocols
Multi-buffered receive and transmit units DMA capability for minimal CPU intervention
Identification masks for message filtering
Automatic Master Header Generation
–
–
–
Programmable Synch Break Field
Synch Field
Identifier Field
•
Slave Automatic Synchronization
–
–
–
Synch break detection
Optional baudrate update
Synchronization Validation
•
•
•
231 programmable transmission rates with 7 fractional bits
Error detection
2 Interrupt lines with priority encoding
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5.7 Serial Communication Interface (SCI)
5.7.1 Features
•
•
•
•
•
Standard universal asynchronous receiver-transmitter (UART) communication
Supports full- or half-duplex operation
Standard nonreturn to zero (NRZ) format
Double-buffered receive and transmit functions
Configurable frame format of 3 to 13 bits per character based on the following:
–
–
–
–
Data word length programmable from one to eight bits
Additional address bit in address-bit mode
Parity programmable for zero or one parity bit, odd or even parity
Stop programmable for one or two stop bits
•
•
•
•
Asynchronous or isosynchronous communication modes
Two multiprocessor communication formats allow communication between more than two devices.
Sleep mode is available to free CPU resources during multiprocessor communication.
The 24-bit programmable baud rate supports 224 different baud rates provide high accuracy baud rate
selection.
•
•
Four error flags and Five status flags provide detailed information regarding SCI events.
Capability to use DMA for transmit and receive data.
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5.8 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module is a multi-master communication module providing an interface
between the TMS570 microcontroller and devices compliant with Philips Semiconductor I2C-bus
specification version 2.1 and connected by an I2C-bus. This module will support any slave or master I2C
compatible device.
5.8.1 Features
The I2C has the following features:
•
Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number
9398 393 40011)
–
–
–
–
–
–
–
–
Bit/Byte format transfer
7-bit and 10-bit device addressing modes
General call
START byte
Multi-master transmitter/ slave receiver mode
Multi-master receiver/ slave transmitter mode
Combined master transmit/receive and receive/transmit mode
Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)
•
•
•
•
•
•
•
•
•
•
Free data format
Two DMA events (transmit and receive)
DMA event enable/disable capability
Seven interrupts that can be used by the CPU
Module enable/disable capability
The SDA and SCL are optionally configurable as general purpose I/O
Slew rate control of the outputs
Open drain control of the outputs
Programmable pullup/pulldown capability on the inputs
Supports Ignore NACK mode
NOTE
This I2C module does not support:
•
•
•
High-speed (HS) mode
C-bus compatibility mode
The combined format in 10-bit address mode (the I2C sends the slave address second
byte every time it sends the slave address first byte)
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5.8.2 I2C I/O Timing Specifications
Table 5-16. I2C Signals (SDA and SCL) Switching Characteristics(1)
Parameter
Standard Mode
Fast Mode
Unit
MIN
MAX
MIN
MAX
tc(I2CCLK)
Cycle time, Internal Module clock for I2C,
prescaled from VCLK
75.2
149
75.2
149
ns
tc(SCL)
Cycle time, SCL
10
2.5
0.6
ms
ms
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
repeated START condition)
4.7
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated
START condition)
4
0.6
ms
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
ms
ms
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDA-SCLH)
th(SDA-SCLL)
Setup time, SDA valid before SCL high
250
0
Hold time, SDA valid after SCL low (for I2C bus
devices)
3.45(2)
0.9
ms
tw(SDAH)
Pulse duration, SDA high between STOP and
START conditions
4.7
4.0
1.3
0.6
0
ms
ms
tsu(SCLH-SDAH)
tw(SP)
Setup time, SCL high before SDA high (for STOP
condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(3)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
(3) Cb = The total capacitance of one bus line in pF.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SP)
tw(SCLL)
tr(SCL)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
tf(SCL)
th(SCLL-SDAL)
tsu(SCLH-SDAL)
th(SDA-SCLL)
Stop
Start
Repeated Start
Stop
Figure 5-8. I2C Timings
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NOTE
•
A device must internally provide a hold time of at least 300 ns for the SDA signal
(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
•
•
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW
period (tw(SCLL)) of the SCL signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the
requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr max + tsu(SDA-SCLH)
.
•
Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster
fall-times are allowed.
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5.9 Multi-Buffered / Standard Serial Peripheral Interface
The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display
drivers, and analog-to-digital converters.
5.9.1 Features
Both Standard and MibSPI modules have the following features:
•
•
•
•
16-bit shift register
Receive buffer register
8-bit baud clock generator, supports max up to 20Mhz baud rate
SPICLK can be internally-generated (master mode) or received from an external clock source (slave
mode)
•
•
Each word transferred can have a unique format
SPI I/Os not used in the communication can be used as digital input/output signals
Table 5-17. MibSPI/SPI Configurations
MibSPIx/SPIx
MibSPI1
I/Os
MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA
MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA
SPI2SIMO, ZSPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA
MibSPI3
MibSPI5
SPI2
SPI4
SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA
5.9.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a
16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each.
5.9.3 MibSPI Transmit Trigger Events
Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event
and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low
level at a selectable trigger source. For example, up to 15 trigger sources are available which can be
utilized by each transfer group. These trigger options are listed in Table 5-18, Section 5.9.3.2 and
Section 5.9.3.3 for MibSPI1, MibSPi3 and MibSPI5 respectively.
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5.9.3.1 MIBSPI1 Event Trigger Hookup
Table 5-18. MIBSPI1 Event Trigger Hookup
Event #
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
EVENT9
EVENT10
EVENT11
EVENT12
EVENT13
EVENT14
TGxCTRL TRIGSRC[3:0]
Trigger
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No trigger source
GIOA[0]
GIOA[1]
GIOA[2]
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
N2HET1[8]
N2HET1[10]
N2HET1[12]
N2HET1[14]
N2HET1[16]
N2HET1[18]
Intern Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin plus selecting the pin to be a GIOx pin, or by driving
the GIOx pin from an external trigger source. If the mux control module is used to select
different functionality instead of the GIOx signal, then care must be taken to disable GIOx
from triggering MibSPI1 transfers; there is no multiplexing on the input connections.
5.9.3.2 MIBSPI3 Event Trigger Hookup
Table 5-19. MIBSPI3 Event Trigger Hookup
Event #
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
EVENT9
TGxCTRL TRIGSRC[3:0]
Trigger
No trigger source
GIOA[0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
GIOA[1]
GIOA[2]
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
HET[8]
N2HET1[10]
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Table 5-19. MIBSPI3 Event Trigger Hookup (continued)
Event #
EVENT10
EVENT11
EVENT12
EVENT13
EVENT14
TGxCTRL TRIGSRC[3:0]
Trigger
N2HET1[12]
N2HET1[14]
N2HET1[16]
N2HET1[18]
Intern Tick counter
1011
1100
1101
1110
1111
NOTE
For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin plus selecting the pin to be a GIOx pin, or by driving
the GIOx pin from an external trigger source. If the mux control module is used to select
different functionality instead of the GIOx signal, then care must be taken to disable GIOx
from triggering MibSPI3 transfers; there is no multiplexing on the input connections.
5.9.3.3 MIBSPI5 Event Trigger Hookup
Table 5-20. MIBSPI5 Event Trigger Hookup
Event #
TGxCTRL TRIGSRC[3:0]
Trigger
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
EVENT9
EVENT10
EVENT11
EVENT12
EVENT13
EVENT14
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No trigger source
GIOA[0]
GIOA[1]
GIOA[2]
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
N2HET1[8]
N2HET1[10]
N2HET1[12]
N2HET1[14]
N2HET1[16]
N2HET1[18]
Intern Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
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NOTE
For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin + selecting the pin to be a GIOx pin, or by driving the
GIOx pin from an external trigger source. If the mux control module is used to select different
functionality instead of the GIOx signal, then care must be taken to disable GIOx from
triggering MibSPI5 transfers; there is no multiplexing on the input connections.
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5.9.4 MibSPI/SPI Master Mode I/O Timing Specifications
Table 5-21. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO. Parameter
tc(SPC)M
2(5) tw(SPCH)M
MIN
MAX
Unit
ns
1
Cycle time, SPICLK(4)
40
256tc(VCLK)
0.5tc(SPC)M + 3
Pulse duration, SPICLK high (clock
polarity = 0)
0.5tc(SPC)M – tr(SPC)M – 3
ns
tw(SPCL)M
3(5) tw(SPCL)M
tw(SPCH)M
Pulse duration, SPICLK low (clock
polarity = 1)
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M – 5
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
Pulse duration, SPICLK low (clock
polarity = 0)
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK high (clock
polarity = 1)
4(5) td(SPCH-SIMO)M Delay time, SPISIMO valid before
SPICLK low (clock polarity = 0)
td(SPCL-SIMO)M Delay time, SPISIMO valid before
SPICLK high (clock polarity = 1)
5(5) tv(SPCL-SIMO)M
0.5tc(SPC)M – 5
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M – tf(SPC) – 3
0.5tc(SPC)M – tr(SPC) – 3
0.5tf(SPC) + 2
tv(SPCH-SIMO)M Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
6(5) tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
7(5) th(SPCL-SOMI)M Hold time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.5tf(SPC) + 2
5
th(SPCH-SOMI)M Hold time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
8(6) tC2TDELAY
5
Setup time CS active
until SPICLK high
(clock polarity = 0)
CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK)
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tr(SPC) + 3
-
-
-
-
- tf(SPICS) + tr(SPC) – 15
CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK)
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tr(SPC) + 3
- tf(SPICS) + tr(SPC) – 15
Setup time CS active
until SPICLK low
CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK)
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tf(SPC) + 3
- tf(SPICS) + tf(SPC) – 15
(clock polarity = 1)
CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK)
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tf(SPC) + 3
- tf(SPICS) + tf(SPC) – 15
9(6) tT2CDELAY
Hold time SPICLK low CS until inactive
(clock polarity = 0)
0.5*tc(SPC)M
T2CDELAY*tc(VCLK) + tc(VCLK)
tf(SPC) + tr(SPICS) - 5
+
0.5*tc(SPC)M
T2CDELAY*tc(VCLK) + tc(VCLK)
tf(SPC) + tr(SPICS) + 8
+
ns
ns
-
-
-
-
Hold time SPICLK high until CS
inactive (clock polarity = 1)
0.5*tc(SPC)M
T2CDELAY*tc(VCLK) + tc(VCLK)
tr(SPC) + tr(SPICS) - 5
+
0.5*tc(SPC)M +
T2CDELAY*tc(VCLK) + tc(VCLK)
tr(SPC) + tr(SPICS) + 8
10
11
tSPIENA
SPIENAn Sample point
(C2TDELAY+1) * tc(VCLK)
f(SPICS) – 25
-
(C2TDELAY+1)*tc(VCLK)
ns
ns
t
tSPIENAW
SPIENAn Sample point from write to
buffer
(C2TDELAY+2)*tc(VCLK)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
6
7
Master In Data
Must Be Valid
SPISOMI
Figure 5-9. SPI Master Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
8
9
10
11
SPIENAn
Figure 5-10. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
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Table 5-22. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO.
Parameter
MIN
MAX
Unit
ns
(4)
1
tc(SPC)M
Cycle time, SPICLK
40
256tc(VCLK)
0.5tc(SPC)M + 3
2(5) tw(SPCH)M
tw(SPCL)M
3(5) tw(SPCL)M
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 0)
0.5tc(SPC)M – tr(SPC)M – 3
ns
Pulse duration, SPICLK low (clock
polarity = 1)
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M – 5
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
Pulse duration, SPICLK low (clock
polarity = 0)
ns
ns
Pulse duration, SPICLK high (clock
polarity = 1)
4(5) tv(SIMO-SPCH)M
Valid time, SPICLK high after
SPISIMO data valid (clock polarity =
0)
tv(SIMO-SPCL)M
Valid time, SPICLK low after
0.5tc(SPC)M – 5
SPISIMO data valid (clock polarity =
1)
5(5) tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
6(5) tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
7(5) tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
0.5tc(SPC)M – tr(SPC) – 3
ns
ns
ns
ns
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
0.5tc(SPC)M – tf(SPC) – 3
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
tr(SPC)
tf(SPC)
5
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
5
8(6) tC2TDELAY
Setup time CS
active until SPICLK
high (clock polarity =
0)
CSHOLD = 0
CSHOLD = 1
CSHOLD = 0
CSHOLD = 1
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tr(SPC) + 3
(C2TDELAY+2) * tc(VCLK)
-
-
-
-
-
-
-
-
tf(SPICS) + tr(SPC) – 15
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tr(SPC) + 3
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tr(SPC) – 15
Setup time CS
active until SPICLK
low (clock polarity =
1)
0.5*tc(SPC)M
+
0.5*tc(SPC)M
+
ns
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tf(SPC) – 15
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tf(SPC) + 3
-
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tf(SPC) + 3
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tf(SPC) – 15
-
9(6) tT2CDELAY
Hold time SPICLK low CS until
inactive (clock polarity = 0)
T2CDELAY*tc(VCLK)
tc(VCLK) - tf(SPC) + tr(SPICS)
4
+
T2CDELAY*tc(VCLK)
tc(VCLK) - tf(SPC) + tr(SPICS)
8
+
ns
ns
+
+
Hold time SPICLK high until CS
inactive (clock polarity = 1)
T2CDELAY*tc(VCLK)
tc(VCLK) - tr(SPC) + tr(SPICS)
4
+
T2CDELAY*tc(VCLK)
tc(VCLK) - tr(SPC) + tr(SPICS)
8
+
10 tSPIENA
SPIENAn Sample Point
(C2TDELAY+1)* tc(VCLK)
-
(C2TDELAY+1)*tc(VCLK)
ns
ns
tf(SPICS) – 25
11 tSPIENAW
SPIENAn Sample point from write to
buffer
(C2TDELAY+2)*tc(VCLK)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Master Out Data Is Valid
Data Valid
SPISIMO
SPISOMI
6
7
Master In Data
Must Be Valid
Figure 5-11. SPI Master Mode External Timing (CLOCK PHASE = 1)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
8
9
10
11
SPIENAn
Figure 5-12. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
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5.9.5 SPI Slave Mode I/O Timings
Table 5-23. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =
input, and SPISOMI = output)(1)(2)(3)(4)
NO.
1
Parameter
tc(SPC)S
MIN
40
MAX
Unit
ns
Cycle time, SPICLK(5)
256tc(VCLK)
2(6)
tw(SPCH)S
tw(SPCL)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
14
ns
14
3(6)
4(6)
tw(SPCL)S
14
ns
ns
tw(SPCH)S
td(SPCH-SOMI)S
14
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0)
trf(SOMI) + 18
trf(SOMI) + 18
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
th(SPCL-SIMO)S
th(SPCH-SIMO)S
td(SPCL-SENAH)S
td(SPCH-SENAH)S
td(SCSL-SENAL)S
Delay time, SPISOMI valid after SPICLK low (clock polarity
= 1)
5(6)
6(6)
7(6)
8
Hold time, SPISOMI data valid after SPICLK high (clock
polarity =0)
2
ns
ns
ns
ns
ns
Hold time, SPISOMI data valid after SPICLK low (clock
polarity =1)
2
Setup time, SPISIMO before SPICLK low (clock polarity =
0)
2
Setup time, SPISIMO before SPICLK high (clock polarity =
1)
2
2
Hold time, SPISIMO data valid after SPICLK low (clock
polarity = 0)
Hold time, SPISIMO data valid after S PICLK high (clock
polarity = 1)
2
Delay time, SPIENAn high after last SPICLK low (clock
polarity = 0)
1.5tc(VCLK)
1.5tc(VCLK)
tf(ENAn)
2.5tc(VCLK)+tr(ENAn)
Delay time, SPIENAn high after last SPICLK high (clock
polarity = 1)
2.5tc(VCLK)+
tr(ENAn)
9
Delay time, SPIENAn low after SPICSn low (if new data
has been written to the SPI buffer)
tc(VCLK)+tf(ENAn)+1
4
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI Data Is Valid
SPISOMI
SPISIMO
6
7
SPISIMO Data
Must Be Valid
Figure 5-13. SPI Slave Mode External Timing (CLOCK PHASE = 0)
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
8
SPIENAn
SPICSn
9
Figure 5-14. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)
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Table 5-24. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =
input, and SPISOMI = output)(1)(2)(3)(4)
NO. Parameter
tc(SPC)S
2(6) tw(SPCH)S
tw(SPCL)S
3(6) tw(SPCL)S
tw(SPCH)S
MIN
40
MAX
Unit
ns
1
Cycle time, SPICLK(5)
256tc(VCLK)
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
14
ns
14
14
ns
ns
14
4(6) td(SOMI-SPCL)S
Dealy time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
trf(SOMI) + 18
trf(SOMI) + 18
td(SOMI-SPCH)S
5(6) th(SPCL-SOMI)S
th(SPCH-SOMI)S
Delay time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity =0)
2
ns
ns
ns
ns
Hold time, SPISOMI data valid after SPICLK low (clock
polarity =1)
2
6(6) tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock
polarity = 0)
2
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity
= 1)
7(6) tv(SPCH-SIMO)S
2
2
High time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
tv(SPCL-SIMO)S
High time, SPISIMO data valid after SPICLK low (clock
polarity = 1)
2
8
td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high
(clock polarity = 0)
1.5tc(VCLK)
1.5tc(VCLK)
tf(ENAn)
tc(VCLK)
2.5tc(VCLK)+tr(ENAn)
2.5tc(VCLK)+tr(ENAn)
tc(VCLK)+tf(ENAn)+14
2tc(VCLK)+trf(SOMI)+8
td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock
polarity = 1)
9
td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data
has been written to the SPI buffer)
ns
ns
10
td(SCSL-SOMI)S
Delay time, SOMI valid after SPICSn low (if new data
has been written to the SPI buffer)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 5-15. SPI Slave Mode External Timing (CLOCK PHASE = 1)
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
8
SPIENAn
SPICSn
9
10
SPISOMI
Slave Out Data Is Valid
Figure 5-16. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)
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5.10 Ethernet Media Access Controller
The Ethernet Media Access Controller (EMAC) provides an efficient interface between RM4x and the
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode, with hardware flow control and quality of service (QoS) support.
The EMAC controls the flow of packet data from the RM4x device to the PHY. The MDIO module controls
PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the RM4x device through a custom interface that
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
5.10.1 Ethernet MII Electrical and Timing Specifications
1
2
MII_MRCLK
MII_MRXD
MII_MRXDV
MII_MRXER
VALID
Figure 5-17. MII Receive Timing
Table 5-25. MII Receive Timing
Parameter
Description
MIN
8ns
8ns
8ns
8ns
MAX
tsu(GMIIMRXD)
tsu(GMIIMRXDV)
tsu(GMIIMRXER)
th(GMIIMRXD)
Setup time, GMIIMRXD to GMIIMRCLK rising edge
Setup time, GMIIMRXDV to GMIIMRCLK rising edge
Setup time, GMIIMRXER to GMIIMRCLK rising edge
Hold time, GMIIMRXD valid after GMIIRCLK rising
edge
th(GMIIMRXDV)
th(GMIIMRXER)
Hold time, GMIIMRXDV valid after GMIIRCLK rising
edge
8ns
8ns
Hold time, GMIIMRXDV valid after GMIIRCLK rising
edge
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1
MII_MTCLK
MII_MTXD
VALID
MII_MTXEN
Figure 5-18. MII Transmit Timing
Table 5-26. MII Transmit Timing
Parameter
td(GMIIMTXD)
td(GMIIMTXEN)
Description
MIN
5ns
5ns
MAX
25ns
25ns
Delay time, GMIIMTCLK rising edge to GMIIMTXD
Delay time, GMIIMTCLK rising edge to GMIIMTXEN
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5.10.2 Management Data Input/Output (MDIO)
1
3
3
MDCLK
4
5
MDIO
(input)
Figure 5-19. MDIO Input Timing
Table 5-27. MDIO Input Timing Requirements
NO.
Parameter
Value
Unit
MIN
400
180
-
MAX
1
2
3
4
tc(MDCLK)
Cycle time, MDCLK
-
-
ns
ns
ns
ns
tw(MDCLK)
Pulse duration, MDCLK high/low
Transition time, MDCLK
tt(MDCLK)
5
-
tsu(MDIO-MDCLKH)
Setup time, MDIO data input valid before MDCLK
High
10
5
th(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK
High
10
-
ns
1
MDCLK
7
MDIO
(output)
Figure 5-20. MDIO Output Timing
Table 5-28. MDIO Output Timing Requirements
NO.
Parameter
Value
Unit
MIN
400
0
MAX
-
1
7
tc(MDCLK)
Cycle time, MDCLK
ns
ns
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output
valid
100
150
Peripheral Information and Electrical Specifications
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SPNS165–SEPTEMBER 2011
6 Mechanical Data
6.1 Thermal Data
Table 6-1 shows the thermal resistance characteristics for the QFP - PGE mechanical package.
Table 6-2 shows the thermal resistance characteristics for the BGA - ZWT mechanical package.
Table 6-1. Thermal Resistance Characteristics
(PGE Package)
PARAMETER
RΘJA
°C / W
45
5
RΘJC
Table 6-2. Thermal Resistance Characteristics
(ZWT Package)
PARAMETER
RΘJA
°C / W
18.8
7.1
RΘJC
6.2 Packaging Information
The following packaging information reflects the most current released data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
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Mechanical Data
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PACKAGE OPTION ADDENDUM
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29-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TMS5702124BPGEQQ1
TMS5702124BZWTQQ1
TMS5702134BPGEQQ1
TMS5702134BZWTQQ1
TMS5703134BPGEQQ1
TMX5703134BPGEQQ1
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
ACTIVE
LQFP
NFBGA
LQFP
PGE
ZWT
PGE
ZWT
PGE
PGE
144
337
144
337
144
144
60
90
60
90
60
1
TBD
TBD
TBD
TBD
TBD
TBD
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NFBGA
LQFP
LQFP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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