TMS27PC020-15JL [TI]
READ-ONLY MEMORIES; 只读存储器
| 型号： | TMS27PC020-15JL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | READ-ONLY MEMORIES |
| 文件： | 总15页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
J PACKAGE
(TOP VIEW)
Organization . . . 262144 by 8 Bits
Single 5-V Power Supply
V
V
CC
Operationally Compatible With Existing
Megabit EPROMs
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
PGM
A17
A14
A13
A8
A9
A11
G
2
3
Industry Standard 32-Pin Dual-In-line
Package and 32-Lead Plastic Leaded Chip
Carrier
4
5
6
All Inputs/Outputs Fully TTL Compatible
7
±10% V
Tolerance
CC
8
Max Access/Min Cycle Time
± 10%
9
V
A10
E
10
11
12
13
14
15
16
CC
’27C/PC020-10
’27C/PC020-12
’27C/PC020-15
’27C/PC020-20
’27C/PC020-25
100 ns
120 ns
150 ns
200 ns
250 ns
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
GND
8-Bit Output For Use in
Microprocessor-Based Systems
Very High-Speed SNAP! Pulse
Programming
TMS27PC020
FM PACKAGE
(TOP VIEW)
Power Saving CMOS Technology
3-State Output Buffers
400 mV Minimum DC Noise Immunity With
Standard TTL Loads
4
3 2 1 32 31 30
A7
A6
A14
5
29
Latchup Immunity of 250 mA on All Input
and Output Pins
6
28 A13
27 A8
26 A9
A5
7
No Pullup Resistors Required
A4
8
9
25
24
23
22
21
A3
A11
G
Low Power Dissipation (V
= 5.5 V)
CC
10
11
12
13
A2
– Active . . . 165 mW Worst Case
– Standby . . . 0.55 mW Worst Case
(CMOS-Input Levels)
A1
A10
E
A0
DQ0
DQ7
Temperature Range Options
14 15 16 17 18 19 20
description
The TMS27C020 series are 262144 by 8-bit
(2097152-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).
PIN NOMENCLATURE
A0–A17
Address Inputs
DQ0–DQ7
Inputs (programming)/Outputs
Chip Enable
E
G
GND
PGM
Output Enable
Ground
Program
5-V Power Supply
13-V Power Supply
The TMS27PC020 series are one-time program-
mable (OTP) electrically programmable read-only
memories (PROMs).
V
CC
V
PP
†
† Only in program mode
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
description (continued)
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C020 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C020 is also offered with two choices of
temperature ranges of 0° to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). See Table 1.
The TMS27PC020 is offered in a 32-lead plastic leaded chip carrier using 1,25 mm (50 mil) lead spacing
(FM suffix). The TMS27PC020 is offered with two choices of temperature ranges of 0°C to 70°C (FML suffix)
and – 40°C to 85°C (FME suffix). See Table 1.
Table 1. Temperature Range Suffixes
SUFFIX FOR OPERATING
TEMPERATURE RANGES
FUNCTION
0°C TO 70°C
–40 °C TO 85°C
TMS27C040-XXX
TMS27PC040-XXX
JL
JE
FML
FME
These EPROMs operate from a single 5-V supply (in the read mode), they are ideal for use in
microprocessor-based systems. One other (13 V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The seven modes of operation for the TMS27C020 and TMS27PC020 are listed in Table 2. The read mode
requiresasingle5-Vsupply. AllinputsareTTLlevelexceptforV duringprogramming(13V), andV (12V)on
PP
H
A9forthesignaturemode.
Table 2. Operation Modes
†
MODE
FUNCTION
OUTPUT
DISABLE
PROGRAM
INHIBIT
READ
STANDBY
PROGRAMMING
VERIFY
SIGNATURE MODE
E
G
V
V
V
V
V
V
V
V
V
V
IL
IL
IH
IL
IL
IH
IL
V
IH
X
V
IH
X
X
IL
IL
IL
PGM
X
X
X
V
IL
V
IH
X
V
X
V
V
V
V
V
V
V
V
V
PP
CC
CC
PP
PP
PP
CC
V
CC
V
V
CC
X
V
CC
X
V
CC
X
CC
X
CC
X
CC
X
CC
A9
A0
V ‡
V ‡
H
H
X
X
X
X
X
X
V
IL
V
IH
CODE
DQ0–DQ7
Data Out
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
MFG
97
DEVICE
32
†
‡
X can be V or V
IL
H
IH
= 12 V ± 0.5 V
V
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
read/output disable
When the outputs of two or more TMS27C020s or TMS27PC020s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C020 and TMS72PC020 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup
without compromising performance or packing density.
power down
Active I
supply current can be reduced from 30 mA to 500 µA by applying a high TTL input on E and to
CC
100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure
Before programming, the TMS27C020 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose
2
2
(UV intensity × exposure time) is 15-W s/cm . A typical 12-mW/cm , filterless UV lamp erases the device in
21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are
in the high state. It should be noted that normal ambient light contains the correct wavelength for erasure.
Therefore, when using the TMS27C020, the window should be covered with an opaque label. After erasure (all
bits in logic high state), logic lows are programmed into the desired locations. A programmed low can be erased
only by ultraviolet light.
SNAP! Pulse programming
The TMS27C020 and TMS27PC020 are programmed using the TI SNAP! Pulse programming algorithm,
illustrated by the flowchart in Figure 1, which programs in a nominal time of twenty-six seconds. Actual
programming time varies as a function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to ten 100-µs pulses
per byte are provided before a failure is recognized.
The programming mode is achieved when V equals 13 V, V
in parallel (eight bits) on pins DQ0 through DQ7. Once addresses and data are stable, PGM is pulsed low.
= 6.5 V, E = V , G = V . Data is presented
IL IH
PP
CC
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
V
= V = 5 V ± 10%.
CC
PP
program inhibit
Programming can be inhibited by maintaining a high level input on the E or PGM pins.
program verify
Programmed bits can be verified with V equals 13 V when G = V , E = V , and PGM = V .
PP
IL
IL
IH
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other
addresses must be held low. The signature code for the TMS27C020 is 9732. A0 low selects the manufacturer’s
code 97 (Hex), and A0 high selects the device code 32 (Hex), as shown in Table 3.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
signature mode (continued)
Table 3. Signature Mode
PINS
†
IDENTIFIER
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
97
MANUFACTURER CODE
DEVICE CODE
V
1
0
0
0
0
1
1
1
0
0
1
0
1
1
1
0
IL
V
IH
32
†
E = G = V , A1–A8 = V , A9 = V , A10–A17 = V , V
IL IL IL PP
= V
.
CC
H
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
Start
Address = First Location
Program
Mode
V
CC
= 6.5 V ± 0.25 V, V = 13 V ± 0.25 V
PP
Program One Pulse = t = 100 µs
Increment Address
w
No
Last
Address?
Yes
Address = First Location
X = 0
Program One Pulse = t = 100 µs
w
No
Fail
Increment
Address
Verify
One Byte
X = X + 1
X = 10?
Interactive
Mode
Pass
No
Last
Address?
Yes
Yes
Device Failed
V
CC
= V
= 5 V ± 0.5 V
PP
Compare
All Bytes
to Original
Data
Fail
Final
Verification
Pass
Device Passed
Figure 1. SNAP! Pulse Programming Flowchart
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
†
logic symbol
EPROM 262 144 × 8
12
11
10
9
8
7
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
13
14
15
17
18
19
20
21
A
A
A
A
A
A
A
A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
6
5
27
26
23
25
4
28
29
3
0
A
262 143
A9
A10
A11
A12
A13
A14
A15
A16
A17
2
30
17
22
24
E
[PWR DOWN]
&
EN
G
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers are for the J package.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V
CC
PP
Supply voltage range, V : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to V
+ 1 V
CC
A9 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 13.5 V
Output voltage range, with respect to V (see Note 1) : . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to V + 1 V
SS
CC
Operating free-air temperature range (’27C020-_ _ JL, ’27PC020_ _FML) : . . . . . . . . . . . . . . . . . 0°C to 70°C
Operating free-air temperature range (’27C020-_ _JE, ’27PC020-_ _FME) : . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, T : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN
4.5
NOM
MAX
5.5
UNIT
Read mode (see Note 2)
5
V
V
V
V
V
V
V
V
Supply voltage
CC
PP
IH
SNAP! Pulse programming algorithm
6.25
6.5
6.75
Read mode
V
V
–0.6
V
CC
13
V
+0.6
CC
CC
Supply voltage
SNAP! Pulse programming algorithm
12.75
2
13.25
TTL
V
V
+0.5
CC
High-level dc input voltage
Low-level dc input voltage
V
V
CMOS
TTL
–0.2
CC
–0.5
+0.5
CC
0.8
IL
CMOS
–0.5
GND+0.2
’27C020-_ _JL,
’27PC020-_ _FML
T
Operating free-air temperature
Operating free-air temperature
0
70
°C
°C
A
’27C020-_ _JE,
’27PC020-_ _FME
T
A
– 40
85
NOTE 2:
V
must be applied before or at the same time as V
PP
and removed after or at the same time as V . The device must not be
PP
is applied.
CC
CC
inserted into or removed from the board when V
or V
PP
electrical characteristics over full ranges of operating conditions
PARAMETER
TEST CONDITIONS
= –20 µA
MIN
V – 0.2
MAX
UNIT
I
I
I
I
OH
OH
OL
OL
CC
2.4
V
V
High-level dc output voltage
V
OH
= – 2 mA
= 2.1 mA
= 20 µA
0.4
0.1
±1
Low-level dc output voltage
V
OL
I
I
I
I
Input current (leakage)
Output current (leakage)
V = 0 V to 5.5 V
µA
µA
µA
mA
I
I
V
V
V
V
V
V
= 0 V to V
CC
±1
O
O
V
V
supply current
= V
= 5.5 V
10
PP1
PP2
PP
PP
PP
CC
CC
CC
= 13 V
= 5.5 V, . . . E = V
supply current (during program pulse)
50
PP
TTL-input level
CMOS-input level
500
100
IH
CC
IL
I
V
supply current (standby)
supply current (active)
µA
CC1
CC2
CC
CC
= 5.5 V,
E = V
± 0.2 V
= 5.5 V,
E = V
CC
I
V
t
= minimum cycle time,
30
mA
cycle
†
outputs open
†
Minimum cycle time = maximum access time.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz†
‡
PARAMETER
TEST CONDITIONS
V = 0 V, f = 1 MHz
= 0 V, f = 1 MHz
MIN NOM
MAX
8
UNIT
pF
C
C
Input capacitance
Output capacitance
4
6
I
I
V
O
10
pF
O
†
‡
Capacitance measurements are made on sample basis only.
All typical values are at T = 25°C and nominal voltages.
A
switching characteristics over full ranges of recommended operating conditions (see Notes 3
and 4)
’27C020-10
’27PC020-10
’27C020-12
’27PC020-12
’27C020-15
’27PC020-15
27C020-20
27PC020-20
’27C020-25
’27PC020-25
TEST
CONDITIONS
PARAMETER
UNIT
ns
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Access
from address
time
t
t
t
100
120
150
200
250
a(A)
Access
from chip en-
able
time
100
55
120
55
150
75
200
75
250
100
ns
a(E)
Output enable
time from G
ns
en(G)
CL = 100 pF,
1 Series 74
TTL load,
Output disable
time from G or
Input t ≤ 20 ns,
r
t
0
0
50
0
0
50
0
0
60
0
0
60
0
0
80
ns
ns
dis
E,
whichever
Input t ≤ 20 ns
f
†
occurs first
Output data
valid time after
change of ad-
dress, E, or G,
whichever oc-
t
v(A)
§
curs first
§
Value calculated from 0.5-V delta to measured output level. This parameter is sampled and not 100% tested.
NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high
and 0.8 V for logic low. (See Figure 2).
4. Common test conditions apply for t
except during programming.
dis
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
switching characteristics for programming: V
(see Note 3)
= 6.5 V and V = 13 V (SNAP! Pulse), T = 25°C
PP
CC
A
PARAMETER
MIN
MAX
UNIT
ns
t
t
Output disable time from G
Output enable time from G
0
100
150
dis(G)
ns
en(G)
NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (See Figure 2).
timing requirements for programming
MIN
95
2
TYP
MAX
UNIT
µs
t
t
t
t
t
t
t
t
t
Pulse duration, program
Setup time, address
Setup time, E
SNAP! Pulse programming algorithm
100
105
w(PGM)
µs
su(A)
2
µs
su(E)
Setup time, G
2
µs
su(G)
su(D)
Setup time, data
2
µs
Setup time, V
Setup time, V
2
µs
su(VPP)
su(VCC)
h(A)
PP
2
µs
CC
Hold time, address
Hold time, data
0
µs
2
µs
h(D)
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
2.08 V
R
= 800 Ω
L
Output
Under Test
C
= 100 pF
L
(see Note A)
2.4 V
0.4 V
2 V
0.8 V
2 V
0.8 V
NOTES: A.
C includes probe and fixture capacitance.
L
B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing
measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs
and outputs.
Figure 2. The ac Testing Output Load Circuit and Waveform
V
V
IH
A0–A17
Addresses Valid
IL
t
a(A)
V
V
IH
E
IL
t
a(E)
V
V
IH
G
IL
t
dis
ten(G)
t
v(A)
V
V
IH
DQ0–DQ7
Hi-Z
Output Valid
Hi-Z
IL
Figure 3. Read-Cycle Timing
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
Verify
Program
V
V
IH
Address
N + 1
A0–A17
Address Stable
IL
t
t
h(A)
su(A)
V
/V
IH OH
Data-Out
Valid
DQ0–DQ7
Data-In Stable
V /V
IL OL
†
t
t
dis(G)
su(D)
‡
V
V
PP
V
PP
CC
t
su(VPP)
su(VCC)
‡
V
V
CC
V
CC
CC
t
V
V
IH
E
IL
t
h(D)
t
su(E)
V
V
IH
PGM
G
IL
t
su(G)
t
†
w(PGM)
t
en(G)
V
V
IH
IL
†
‡
t
and t
are characteristics of the device but must be accommodated by the programmer.
and 6.5-V V for SNAP! Pulse programming.
dis(G)
13-V V
en(G)
PP
CC
Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
FM (R-PQCC-J32)
PLASTIC J-LEADED CHIP CARRIER
Seating Plane
0.004 (0,10)
0.140 (3,56)
0.132 (3,35)
0.495 (12,57)
0.485 (12,32)
0.129 (3,28)
0.123 (3,12)
0.453 (11,51)
0.447 (11,35)
0.049 (1,24)
0.043 (1,09)
0.008 (0,20) NOM
1
30
4
29
5
0.020 (0,51)
0.015 (0,38)
0.595 (15,11)
0.585 (14,86)
0.553 (14,05)
0.547 (13,89)
0.030 (0,76)
TYP
21
13
14
20
0.050 (1,27)
4040201-4/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-016
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
J (R-CDIP-T**)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 PIN SHOWN
B
13
24
C
12
1
Lens Protrusion
0.010 (0,25) MAX
0.065 (1,65)
0.045 (1,14)
0.090 (2,29)
0.060 (1,53)
0.175 (4,45)
A
0.140 (3,56)
0.018 (0,46) MIN
Seating Plane
0°–10°
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
PINS**
DIM
24
28
32
40
NARR
WIDE
NARR
WIDE
NARR
WIDE
NARR
WIDE
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
MAX
A
MIN
MAX
B
MIN
MAX
C
MIN
4040084/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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