TMP108AIYFFT [TI]
Low Power Digital Temperature Sensor With Two-Wire Serial Interface in WCSP; 低功耗数字温度传感器，在WCSP两线串行接口
| 型号： | TMP108AIYFFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low Power Digital Temperature Sensor With Two-Wire Serial Interface in WCSP |
| 文件： | 总19页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMP108
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SBOS663 –APRIL 2013
Low Power Digital Temperature Sensor
With Two-Wire Serial Interface in WCSP
Check for Samples: TMP108
1
FEATURES
DESCRIPTION
TMP108 is a digital-output temperature sensor with a
dynamically-programmable limit window, and under-
and overtemperature alert functions. These features
provide optimized temperature control without the
need of frequent temperature readings by the
controller or application processor.
23
•
Dynamically-Programmable Limit Window with
Under- and Overtemperature Alerts
•
Accuracy:
±0.75°C (max) from –20°C to +85°C
±1°C (max) from –40°C to +125°C
•
Low Quiescent Current:
6 μA Active (max) from –40°C to +125°C
The TMP108 features SMBus™ and two-wire
interface compatibility, and allows up to four devices
on one bus with the SMBus alert function.
•
•
•
Supply Range: 1.4 V to 3.6 V
Resolution: 12 Bits (0.0625°C)
The TMP108 is ideal for thermal management
optimization in a variety of consumer, computer, and
environmental applications. The device is specified
over a temperature range of –40°C to +125°C.
Package: 1.2-mm × 0.8-mm, 6-Ball WCSP
APPLICATIONS
•
•
•
•
•
Smartphone and Tablet Thermal Management
Battery Management
Thermostat Control
TMP108
Under- and Overtemperature Protection
Environmental Monitoring and HVAC
Diode
A1
B1
C1
Control
Logic
A2
B2
C2
Temp
V+
A0
GND
SCL
SDA
Sensor
DS
Serial
ADC
Interface
Config
and Temp
Register
ALERT
OSC
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SMBus is a trademark of Intel, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TMP108
SBOS663 –APRIL 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
TMP108
3.6
UNIT
V
Supply voltage
Input voltage for SDA and SCL(2)
Input voltage for A0 and ALERT
Operating temperature
Storage temperature
–0.5 to 3.6
–0.5 to (V+) + 0.3
–55 to +150
–60 to +150
+150
V
V
°C
°C
°C
V
Junction temperature
Electrostatic
discharge (ESD)
ratings
Human body model (HBM)
Charged device model (CDM)
2000
1000
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) If A0 is connected to SCL or SDA, the input voltage rating for A0 applies to SCL or SDA.
PIN CONFIGURATION
YFF PACKAGE
DSBGA-6
(TOP VIEW)
A1
B1
C1
A2
B2
C2
V+
A0
GND
SCL
SDA
ALERT
PIN DESCRIPTIONS
PIN
NAME
PIN
NUMBER
DESCRIPTION
A0
ALERT
GND
SCL
B1
C1
A2
B2
C2
A1
Address selection pin
Alert output pin
Ground
Input clock pin
SDA
V+
Input/output data pin
Supply Voltage (1.4 V to 3.6 V)
2
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ELECTRICAL CHARACTERISTICS
At TA = +25°C, and V+ = +1.8 V, unless otherwise noted.
TMP108
TYP
PARAMETER
TEMPERATURE INPUT
Range
CONDITIONS
MIN
MAX
UNIT
–40
+125
±0.75
±1
°C
°C
–20°C to +85°C
–40°C to +125°C
±0.15
±0.3
Accuracy (temperature
error)
°C
Accuracy vs supply
±0.03
±0.3
°C/V
DIGITAL INPUT/OUTPUT
VIH
VIL
IIN
Input logic high level
Input logic low level
Input current
0.7 (V+)
-0.5
V+
0.3 (V+)
1
V
V
0 V < VIN < (V+) +0.3 V
V+ > 2 V, IOUT = 3 mA
V+ < 2 V, IOUT = 3 mA
μA
V
0.4
VOL
Output logic low level
0.2 (V+)
V
ALERT internal pull-up
resistor
ALERT to V+
80
21
100
120
kΩ
Resolution
12
27
0.25
1
Bit
Conversion time
One-Shot mode
33
ms
CR1 = 0, CR0 = 0
CR1 = 0, CR0 = 1 (default)
CR1 = 1, CR0 = 0
CR1 = 1, CR0 = 1
Conv/s
Conv/s
Conv/s
Conv/s
ms
Conversion modes
4
16
28
Timeout time
21
35
POWER SUPPLY
Operating supply range,
1.4
3.6
V
V+ pin
Serial bus inactive, CR1 = 0, CR0 = 1 (default)
2
3.5
6
μA
μA
Serial bus inactive, CR1 = 0, CR0 = 1 (default), –40°C to +125°C
Serial bus active, SCL frequency = 400 kHz, CR1 = 0,
CR0 = 1 (default)
IQ
Quiescent current
12
82
μA
μA
Serial bus active, SCL frequency = 3.4 MHz, CR1 = 0,
CR0 = 1 (default)
Serial bus inactive
0.3
10
80
1
μA
μA
μA
ISD
Shutdown current
Serial bus active, SCL frequency = 400 kHz
Serial bus active, SCL frequency = 3.4 MHz
TEMPERATURE
Specified range
Storage range
–40
–55
+125
+150
°C
°C
THERMAL INFORMATION
TMP108
THERMAL METRIC(1)
YFF (DSBGA)
UNITS
6 PINS
132.7
1.7
θJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
θJC(top)
θJB
23
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
6
ψJB
22.6
N/A
θJC(bottom)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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TYPICAL CHARACTERISTICS
At TA = +25°C and V+ = 1.8 V, unless otherwise noted.
12
10
8
10
V+ = 1.4 V
V+ = 1.8 V
V+ = 3.6 V
V+ = 1.4 V
9
V+ = 1.8 V
8
7
6
5
4
3
2
1
0
V+ = 3.6 V
6
4
2
0
œ50
0
50
100
150
œ50
0
50
100
150
C001
C002
Temperature (°C)
Temperature (°C)
Figure 1. QUIESCENT CURRENT vs TEMPERATURE (1
Conversion per Second)
Figure 2. SHUTDOWN CURRENT vs TEMPERATURE
40
90
V+ = 1.4 V
TA=œ55°C
38
80
70
60
50
40
30
20
10
0
V+ = 1.8 V
T
= +25°C
A
36
34
32
30
28
26
24
22
20
V+ = 3.6 V
TA=+125°C
1k
œ50
0
50
100
150
10k
100k
Bus Frequency (Hz)
1M
10M
C003
C004
Temperature (°C)
Figure 3. CONVERSION TIME vs TEMPERATURE
Figure 4. QUIESCENT CURRENT vs BUS FREQUENCY
1.0
0.8
Mean œ 31
Mean
0.6
Mean + 31
0.4
0.2
0.0
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
œ50
œ25
0
25
50
75
100
125
150
C005
Temperature (°C)
Temperature Error (°C)
C006
Figure 5. TEMPERATURE ERROR vs TEMPERATURE
Figure 6. TEMPERATURE ERROR AT +25°C
4
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APPLICATION INFORMATION
The TMP108 is a digital temperature sensor optimal for thermal management and thermal protection
applications. The TMP108 is two-wire and SMBus Interface compatible, and is specified over a temperature
range of –40°C to +125°C.
The TMP108 temperature sensor is the chip itself; the solder bumps provide the primary thermal path as a result
of the lower thermal resistance of metal. The temperature sensor result is equivalent to the local temperature of
the printed circuit board (PCB) on which the sensor is mounted.
The TMP108 only requires pull-up resistors on SCL and SDA; although, a 0.01 μF bypass capacitor is
recommended, as shown in Figure 7. There is an internal 100 kΩ pull-up resistor connected to supply on the
ALERT pin. If required, use an external resistor of smaller value on the ALERT pin for a stronger pull-up to V+.
The SCL and SDA lines can be pulled up to a supply that is equal to or higher than V+ through the pull-up
resistors. To configure one of four different addresses on the bus, connect A0 to either V+, GND, SCL, or SDA. If
A0 is connected to SCL or SDA, make their pull-up supply equal to V+.
1.4 V to 3.6 V
V+
A1
V+
TMP108
B2
C2
C1
SCL
SDA
100 kW
B1
Two-Wire
Controller
A0
ALERT
GND
A2
GND
Figure 7. Typical Application Circuit
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POINTER REGISTER
Figure 8 shows the internal register structure of the TMP108. Use the 8-bit pointer register to address a given
data register. The pointer register uses the two LSBs (see Table 10) to identify which of the data registers
respond to a read or write command. Table 1 identifies the bits of the pointer register byte. Table 2 describes the
pointer address of the registers available in the TMP108. The power-up reset value of the P1 and P0 bits is '00'.
Pointer
Register
Temperature
Register
SCL
Configuration
Register
I/O
Control
Interface
TLOW
Register
SDA
THIGH
Register
Figure 8. Internal Register Structure
Table 1. Pointer Register Byte
P7
P6
P5
P4
P3
P2
P1
P0
0
0
0
0
0
0
Register Bits
Table 2. Pointer Addresses
P1
0
P0
0
REGISTER
Temperature register (read only, default)
Configuration register (read/write)
TLOW register (read/write)
0
1
1
0
1
1
THIGH register (read/write)
6
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TEMPERATURE REGISTER
The temperature register is configured as a 12-bit, read-only register that stores the output of the most recent
conversion. Two bytes must be read to obtain data, as shown in Table 3 and Table 4. Note that byte 1 is the
most significant byte, followed by byte 2, the least significant byte. The first 12 bits are used to indicate
temperature. There is no requirement to read the least significant byte if that information is not needed (for
example, for resolution lower than 1°C). Table 5 summarizes the temperature data format. One LSB equals
0.0625°C. Negative numbers are represented in binary twos complement format. Following power-up or reset,
the temperature register reads 0°C until the first conversion is complete. The unused bits in the temperature
register always read '0'.
Table 3. Byte 1 of Temperature Register
D7
D6
D5
D4
D3
D2
D1
D0
T11
T10
T9
T8
T7
T6
T5
T4
Table 4. Byte 2 of Temperature Register
D7
D6
D5
D4
D3
D2
D1
D0
T3
T2
T1
T0
0
0
0
0
Table 5. Temperature Data Format(1)
DIGITAL OUTPUT
TEMPERATURE (°C)
BINARY
HEX
128
127.9375
100
80
0111 1111 1111
0111 1111 1111
0110 0100 0000
0101 0000 0000
0100 1011 0000
0011 0010 0000
0001 1001 0000
0000 0000 0100
0000 0000 0000
1111 1111 1100
1110 0111 0000
1100 1001 0000
7FF
7FF
640
500
4B0
320
190
004
000
FFC
E70
C90
75
50
25
0.25
0
–0.25
–25
–55
(1) The temperature sensor ADC resolution is 0.0625°C/count.
Table 5 does not supply a full list of all temperatures. Use the following rules to obtain the digital data format for
a given temperature.
To convert positive temperatures to a digital data format:
Divide the temperature by the resolution. Then, convert the result to binary code with a 12-bit, left-justified
format, and MSB = 0 to denote a positive sign.
Example: (+50°C)/(0.0625°C/count) = 800 = 320h = 0011 0010 0000
To convert negative temperatures to a digital data format:
Divide the absolute value of the temperature by the resolution, and convert the result to binary code with a
12-bit, left-justified format. Then, generate the twos complement of the result by complementing the binary
number and adding one. Denote a negative number with MSB = 1.
Example: (|–25°C|)/(0.0625°C/count) = 400 = 190h = 0001 1001 0000
Twos complement format: 1110 0110 1111 + 1 = 1110 0111 0000
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CONFIGURATION REGISTER
The configuration register is a 16-bit read and write register used to store bits that control the operational modes
of the temperature sensor. Read and write operations are performed MSB first. The format and power-up (reset)
default value of the configuration register is shown in Table 6, followed by an explanation of the register bits.
Other options for the default values are available by request.
Table 6. Configuration and Power-Up/Reset Format
BYTE
D7
ID
D6
CR1
0
D5
CR0
1
D4
FH
0
D3
FL
0
D2
TM
1
D1
M1
1
D0
M0
0
1
0
POL
0
0
HYS1
0
HYS0
1
0
0
0
0
2
0
0
0
0
0
Hysteresis Control (HYS1 and HYS0)
When operating in comparator mode, the hysteresis control bits (HYS1 and HYS0) configure the hysteresis for
the limit comparison of the TMP108 to 0°C, 1°C, 2°C, or 4°C. The default hysteresis is 1°C. Table 7 shows the
settings for HYS1 and HYS0.
Table 7. Hysteresis Settings
HYS1
HYS0
HYSTERESIS
0°C
0
0
1
1
0
1
0
1
1°C (default)
2°C
4°C
Polarity (POL)
The polarity of the ALERT pin can be programmed using the POL bit. If POL = '0' (default), the ALERT is active
low. For POL = '1', the ALERT pin is active high, and the state of the ALERT pin is inverted.
Mode Bits (M1 and M0)
The mode bits, M1 and M0, can be set to three different modes: shutdown, one-shot, or continuous conversion.
Shutdown Mode (M1 = '0', M0 = '0')
Shutdown mode saves power by shutting down all device circuitry other than the serial interface, thus reducing
current consumption to typically less than 0.5 μA. Shutdown mode is enabled when M1 and M0 = '00'. The
device shuts down when current conversion is completed.
One-Shot Mode (M1 = '0', M0 = '1')
The TMP108 features a one-shot temperature measurement mode. When the device is in shutdown mode,
writing a ‘01’ to the M1 and M0 bits starts a single temperature conversion. During the conversion, the M1 and
M0 bits reads '01'. The device returns to the shutdown state at the completion of the single conversion. After the
conversion, the M1 and M0 bits read '00'. This feature is useful for reducing the power consumption of the
TMP108 when continuous temperature monitoring is not required.
As a result of the short conversion time, the TMP108 can achieve a higher conversion rate. A single conversion
typically takes 27 ms and a read can take place in less than 20 μs. However, when using one-shot mode, 30 or
more conversions per second are possible.
Continuous Conversion Mode (M1 = '1')
When the TMP108 is in continuous conversion mode (M1 = '1'), a single conversion is performed at a rate
determined by the conversion rate bits (CR1 and CR0 in the configuration register). The TMP108 performs a
single conversion, and then goes in standby and waits for the appropriate delay set by the CR1 and CR0 bits.
See Table 8 for CR1 and CR0 settings.
8
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Thermostat Mode (TM)
The thermostat mode bit indicates to the device whether to operate in comparator mode (TM = '0') or interrupt
mode (TM = '1', default). For more information on comparator and interrupt modes, see the High- and Low-Limit
Registers section.
Temperature Watchdog Flags (FL and FH)
The TMP108 uses temperature watchdog flags in the configuration register that indicate the result of comparing
the device temperature at the end of every conversion to the values stored in the temperature limit registers
(THIGH and TLOW). If the temperature of the TMP108 exceeds the value in the THIGH register, then the flag-high bit
(FH) in the configuration register is set to '1'. If the temperature falls below the value in the TLOW register, then
the flag-low bit (FL) is set to '1'. If both flag bits remain '0', then the temperature is within the temperature range
set by the temperature limit registers. In interrupt mode, when any of the flags is set by an under- or
overtemperature event, the SMBus ALERT Response only clears the pin and not the flags. Reading the
configuration register clears both the flags and the pin.
Conversion Rate
The conversion rate bits, CR1 and CR0, configure the TMP108 for conversion rates of 0.25 Hz, 1 Hz, 4 Hz, or 16
Hz. The default rate is 1 Hz. The TMP108 has a typical conversion time of 27 ms. To achieve different
conversion rates, the TMP108 makes a conversion, and then powers down and waits for the appropriate delay
set by CR1 and CR0. Table 8 shows the settings for CR1 and CR0.
Table 8. Conversion Rate Settings
CR1
CR0
CONVERSION RATE
0.25 Hz
IQ (TYP)
1 μA
0
0
1
1
0
1
0
1
1 Hz (default)
4 Hz
2 μA
5 μA
16 Hz
18 μA
After power-up or a general-call reset, the TMP108 immediately starts a conversion, as shown in Figure 9. The
first result is available after 27 ms (typical). The active quiescent current during conversion is 40 μA (typical at
+25°C). The quiescent current during delay is 0.7 μA (typical at +25°C).
Delay(1)
Delay(1)
27 ms
27 ms
27 ms
Startup
Start of
Conversion
Start of
Conversion
(1) Delay is set by the CR1 and CR0 bits in the configuration register.
Figure 9. Conversion Start
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HIGH- AND LOW-LIMIT REGISTERS
In comparator mode (TM = '0'), the ALERT pin becomes active when the temperature exceeds the value in the
THIGH register or drops below the value in the TLOW register. The ALERT pin remains active until the temperature
returns to a value that is within the range set by:
(TLOW + HYS) and (THIGH – HYS)
where
•
HYS is the hysteresis set by the hysteresis control bits (HYS1 and HYS0).
(1)
In interrupt mode (TM = '1'), the ALERT pin becomes active when the temperature exceeds the value in the
THIGH register or drops below the value in the TLOW register, and remains active until a read operation of the
configuration register occurs (also clears the values latched in the watchdog flags, FL and FH), or the device
successfully responds to the SMBus alert response address. The ALERT pin is also cleared by resetting the
device with the general call reset command.
Both operational modes are represented in Figure 10 and Figure 11.
Table 9 and Table 10 describe the format for the THIGH and TLOW registers. Note that the most significant byte is
sent first, followed by the least significant byte. Power-up (reset) default values are THIGH = +127.9375°C and
TLOW = –128°C. These values ensure that upon power-up, the limit window is set to maximum, and the ALERT
pin does not become active until the desired limit values are programmed in the registers. Other default values
for the temperature limits are availlable by request. The format of the data for THIGH and TLOW is the same as for
the temperature register.
Table 9. Bytes 1 and 2 of THIGH Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
H11
H10
H9
H8
H7
H6
H5
H4
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
2
H3
H2
H1
H0
0
0
0
0
Table 10. Bytes 1 and 2 of TLOW Register
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
1
L11
L10
L9
L8
L7
L6
L5
L4
BYTE
D7
D6
D5
D4
D3
D2
D1
D0
2
L3
L2
L1
L0
0
0
0
0
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THIGH
Measured
Temperature
TLOW
ALERT
(POL = 0)
FL
FH
Time
(1) (1)
(1) (1)
(1)
(1)
(1)
(1) Update THIGH and TLOW limit. Read the configuration register to clear the flags and the ALERT pin.
Figure 10. Interrupt Mode
THIGH
THIGH œ HYS
Measured
Temperature
TLOW + HYS
TLOW
ALERT
(POL = 0)
FL
FH
Time
Figure 11. Comparator Mode
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SERIAL INTERFACE
The TMP108 operates as a slave device only on the two-wire bus and SMBus. Connections to the bus are made
using the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike-suppression filters
and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP108 supports the
transmission protocol for both fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3.4 MHz) modes. All data bytes
are transmitted MSB first.
SERIAL BUS ADDRESS
To communicate with the TMP108, the master must first communicate with slave devices using a slave address
byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing
either a read or write operation. The TMP108 features an address pin that allows up to four devices to be
addressed on a single bus. The TMP108 latches the status of the address pin at the start of a communication.
Table 11 describes the pin logic levels and the corresponding address values. Other values for the fixed address
bits are available by request.
Table 11. Address Pin and Slave Addresses
DEVICE TWO-WIRE ADDRESS
A0 PIN CONNECTION
1001000
1001001
1001010
1001011
Ground
V+
SDA
SCL
BUS OVERVIEW
The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the start and stop conditions.
To address a specific device, initiate a start condition by pulling the data line (SDA) from a high to a low logic
level while SCL is high. All slaves on the bus shift in the slave address byte; the last bit indicates whether a read
or write operation follows. During the ninth clock pulse, the slave being addressed responds to the master by
generating an acknowledge bit and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high because any change in SDA while SCL is high is interpreted
as a start or stop signal.
After all data have been transferred, the master generates a stop condition indicated by pulling SDA from low to
high, while SCL is high.
WRITING/READING OPERATION
Accessing a particular register on the TMP108 is accomplished by writing the appropriate value to the pointer
register. The value for the pointer register is the first byte transferred after the slave address byte with the R/W
bit low. Every write operation to the TMP108 requires a value for the pointer register (see Figure 13).
When reading from the TMP108, the last value stored in the pointer register by a write operation is used to
determine which register is read by a read operation. To change the register pointer for a read operation, a new
value must be written to the pointer register. This action is accomplished by issuing a slave address byte with the
R/W bit low, followed by the pointer register byte. No additional data are required. The master can then generate
a start condition and send the slave address byte with the R/W bit high to initiate the read command. See
Figure 14 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to
continually send the pointer register bytes because the TMP108 stores the pointer register value until it is
changed by the next write operation.
Note that register bytes are sent with the most significant byte first, followed by the least significant byte.
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SLAVE MODE OPERATIONS
The TMP108 can operate as a slave receiver or slave transmitter.
Slave Receiver Mode:
The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP108 then
acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The
TMP108 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the
register addressed by the pointer register. The TMP108 acknowledges reception of each data byte. The master
can terminate data transfer by generating a start or stop condition.
Slave Transmitter Mode:
The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges
reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of
the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte
transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The
master can terminate data transfer by generating a not-acknowledge bit on reception of any data byte, or by
generating a start or stop condition.
SMBus ALERT FUNCTION
The TMP108 supports the SMBus alert function. When the TMP108 operates in interrupt mode (TM = '1'), the
ALERT pin may be connected as an SMBus alert signal. When a master senses that an alert condition is present
on the ALERT line, the master sends an SMBus alert command (00011001) to the bus. If the ALERT pin is
active, the device acknowledges the SMBus alert command and responds by returning its slave address on the
SDA line. The eighth bit (LSB) of the slave address byte indicates whether the alert condition is caused by the
temperature exceeding THIGH or falling below TLOW. The LSB is high if the temperature is greater than THIGH, or
low if the temperature is less than TLOW. See Figure 15 for details of this sequence.
If multiple devices on the bus respond to the SMBus alert command, arbitration during the slave address portion
of the SMBus alert command determines which device clears its alert status first. If the TMP108 wins the
arbitration, its ALERT pin becomes inactive at the completion of the SMBus alert command. If the TMP108 loses
the arbitration, its ALERT pin remains active.
GENERAL CALL
The TMP108 responds to a two-wire general call address (0000000) if the eighth bit is '0'. The device
acknowledges the general call address and responds to commands in the second byte. If the second byte is
00000100, the TMP108 latches the status of the address pin, but does not reset. If the second byte is 00000110,
the TMP108 internal registers are reset to power-up values. The TMP108 does not support the general address
acquire command.
HIGH-SPEED (Hs) MODE
In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an SMBus
Hs-mode master code (00001xxx) as the first byte after a start condition to switch the bus to high-speed
operation. The TMP108 does not acknowledge this byte, but does switch its input filters on SDA and SCL and its
output filters on SDA to operate in Hs-mode, allowing transfers at up to 3.4 MHz. After the Hs-mode master code
has been issued, the master transmits a two-wire slave address to initiate a data-transfer operation. The bus
continues to operate in Hs-mode until a stop condition occurs on the bus. Upon receiving the stop condition, the
TMP108 switches the input and output filters back to fast-mode operation.
TIMEOUT FUNCTION
The TMP108 resets the serial interface if SCL or SDA are held low for 28 ms (typ) between a start and stop
condition. If the TMP108 is pulled low, it releases the bus and then waits for a start condition. To avoid activating
the timeout function, it is necessary to maintain a communication speed of at least 1 kHz for the SCL operating
frequency.
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TIMING DIAGRAMS
The TMP108 is two-wire and SMBus compatible. Figure 12 to Figure 15 describe the various operations on the
TMP108. Parameters for Figure 12 are defined in Table 12. Bus definitions are:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high defines a
start condition. Each data transfer is initiated with a start condition.
Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a
stop condition. Each data transfer is terminated with a repeated start or stop condition.
Data Transfer: The number of data bytes transferred between a start and a stop condition is not limited, and is
determined by the master device. The receiver acknowledges the transfer of data. It is also possible to use the
TMP108 for single-byte updates. To update only the MS byte, terminate communication by issuing a start or stop
condition on the bus.
Acknowledge: Each receiving device, when addressed, must generate an acknowledge bit. A device that
acknowledges must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable
low during the high period of the acknowledge clock pulse. Setup and hold times must be taken into account.
When a master receives data, the termination of the data transfer can be signaled by the master generating a
not-acknowledge ('1') on the last byte transmitted by the slave.
Table 12. Timing Diagram Definitions
FAST MODE
MIN
HIGH-SPEED MODE
PARAMETER
TEST CONDITIONS
SCL operating frequency, V+ ≥ 1.8 V
SCL operating frequency, V+ < 1.8 V
MAX
0.4
MIN
0.001
0.001
MAX
UNIT
MHz
MHz
0.001
3.4
2.5
f(SCL)
0.001
0.4
Bus free time between stop and start conditions, V+
≥ 1.8 V
1300
1300
600
160
260
160
ns
ns
ns
t(BUF)
Bus free time between stop and start conditions, V+
< 1.8 V
Hold time after repeated start condition.
After this period, the first clock is generated.
t(HDSTA)
t(SUSTA)
t(SUSTO)
Repeated start condition setup time
Stop condition setup time
Data hold time, V+ ≥ 1.8 V
Data hold time, V+ < 1.8 V
Data setup time, V+ ≥ 1.8 V
Data setup time, V+ < 1.8 V
SCL clock low period, V+ ≥ 1.8 V
SCL clock low period, V+ < 1.8 V
SCL clock high period
600
600
0
160
160
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
900
900
70
t(HDDAT)
t(SUDAT)
t(LOW)
0
0
130
100
100
1300
1300
600
10
50
160
260
60
t(HIGH)
tR , tF - SDA
tR , tF - SCL
tR
Data rise/fall time
300
300
80
40
Clock rise/fall time
Clock/data rise time for SCLK ≤ 100 kHz
1000
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TWO-WIRE TIMING DIAGRAMS
t(LOW)
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH) t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 12. Two-Wire Timing Diagram
1
9
1
9
SCL
SDA
¼
A1(1) A0(1)
1
0
0
1
0
R/W
0
0
0
0
0
0
P1
P0
¼
Start By
Master
ACK By
ACK By
Device
Device
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Slave Address Byte
1
9
1
9
SCL
(Continued)
SDA
D7 D6
D5
D4 D3
D2 D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
(Continued)
ACK By
Device
ACK By
Stop By
Master
Device
Frame 3 Data Byte 1
Frame 4 Data Byte 2
(1) The value of A0 and A1 are determined by the A0 pin.
Figure 13. Two-Wire Timing Diagram for Write Word Format
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1
9
1
9
¼
SCL
SDA
1
0
0
1
0
A1(1) A0(1)
R/W
0
0
0
0
0
0
P1
P0
Start By
Master
ACK By
ACK By
Stop By
Master
Device
Device
Frame 1 Two-Wire Slave Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
¼
(Continued)
SDA
A1(1) A0(1)
¼
0
1
0
0
1
R/W
D7
D6
D5
D4 D3
D2
D1
D0
(Continued)
Start By
Master
ACK By
From
Device
ACK By
Master(2)
Device
Frame 3 Two-Wire Slave Address Byte
Frame 4 Data Byte 1 Read Register
1
SCL
9
(Continued)
SDA
D7 D6
D5
D4
D3
D2
D1
D0
(Continued)
From
ACK By
Master(3)
Stop By
Master
Device
Frame 5 Data Byte 2 Read Register
(1) The value of A0 and A1 are determined by the A0 pin.
(2) Master should leave SDA high to terminate a single-byte read operation.
(3) Master should leave SDA high to terminate a two-byte read operation.
Figure 14. Two-Wire Timing Diagram for Read Word Format
ALERT
SCL
1
9
1
9
A1(1) A0(1)
SDA
0
0
0
1
1
0
0
R/W
1
0
0
1
Status
Start By
Master
ACK By
From
NACK By Stop By
Master Master
Device
Device
Frame 1 SMBus ALERT Response Address Byte
Frame 2 Slave Address From Device
(1) The value of A0 and A1 are determined by the A0 pin.
Figure 15. Timing Diagram for SMBus Alert
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2013
PACKAGING INFORMATION
Orderable Device
TMP108AIYFFR
TMP108AIYFFT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
DSBGA
DSBGA
YFF
6
6
3000
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
Level-1-260C-UNLIM
T8
T8
ACTIVE
YFF
250
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
D: Max = 1.216 mm, Min =1.156 mm
E: Max = 0.816 mm, Min =0.756 mm
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