TM248NBJ36U-80 [TI]
2MX36 FAST PAGE DRAM MODULE, 80ns, SMA72, SIMM-72;
| 型号： | TM248NBJ36U-80 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2MX36 FAST PAGE DRAM MODULE, 80ns, SMA72, SIMM-72 动态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM124MBJ36F, TM124MBJ36U 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBJ36F, TM248NBJ36U 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS662 – MAY 1996
Organization
Presence Detect
TM124MBJ36F . . . 1 048 576 × 36
TM248NBJ36F . . . 2 097 152 × 36
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME
OR
Single 5-V Power Supply (±10% Tolerance)
t
t
t
WRITE
CYCLE
(MIN)
RAC
AA
CAC
72-Pin Single In-Line Memory Module
(SIMM) for Use With Socket
(MAX)
’124MBJ36F-60 60 ns
’124MBJ36F-70 70 ns
’124MBJ36F-80 80 ns
’248NBJ36F-60 60 ns
’248NBJ36F-70 70 ns
’248NBJ36F-80 80 ns
(MAX)
30 ns
35 ns
40 ns
30 ns
35 ns
40 ns
(MAX)
15 ns
18 ns
20 ns
15 ns
18 ns
20 ns
110 ns
130 ns
150 ns
110 ns
130 ns
150 ns
TM124MBJ36F – Utilizes Two 16-Megabit
and One 4-Megabit Dynamic
Random-Access Memories (DRAMs) in
Plastic Small-Outline J-Lead (SOJ)
Packages
TM248NBJ36F – Utilizes Four 16-Megabit
and Two 4-Megabit DRAMs in Plastic SOJ
Packages
Low Power Dissipation
Operating Free-Air Temperature Range
0°C to 70°C
Long Refresh Period . . . 16 ms
(1024 Cycles)
†
Gold-Tabbed Versions Available:
– TM124MBJ36F
– TM248NBJ36F
All Inputs, Outputs, Clocks Fully
TTL-Compatible
Tin-Lead (Solder) Tabbed Versions
Available:
– TM124MBJ36U
3-State Output
Common CAS Control for Nine Common
Data-In and Data-Out Lines in Four Blocks
– TM248NBJ36U
Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
description
TM124MBJ36F
The TM124MBJ36F is a 4-MByte DRAM organized as four times 1048576 × 9 in a 72-pin SIMM. The SIMM
is composed of two TMS418160DZ 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package, and
one TMS44460DJ 1048576 × 4-bit DRAM in a 24/26-lead plastic SOJ package mounted on a substrate with
decoupling capacitors. The TMS418160DZ and TMS44460DJ are described in the TMS418160 and
TMS44460 data sheets, respectively. The TM124MBJ36F SIMM is available in the single-sided BJ leadless
module for use with sockets.
TM248NBJ36F
The TM248NBJ36F is an 8-MByte DRAM organized as four times 2097152 × 9 in a 72-pin SIMM. The SIMM
is composed of four TMS418160DZ 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package, and
two TMS44460DJ 1048576 × 4-bit DRAMs, each in a 24/26-lead plastic SOJ package mounted on a substrate
with decoupling capacitors. The TMS418160DZ and TMS44460DJ are described in the TMS418160 and
TMS44460 data sheets, respectively. The TM248NBJ36F SIMM is available in the double-sided BJ leadless
module for use with sockets.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBJ36F, TM124MBJ36U 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBJ36F, TM248NBJ36U 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS662 – MAY 1996
BJ SINGLE IN-LINE MEMORY MODULE
(TOP VIEW)
TM124MBJ36F
(SIDE VIEW)
TM248NBJ36F
(SIDE VIEW)
V
1
2
3
4
SS
DQ0
DQ18
DQ1
DQ19
DQ2
5
6
DQ20
DQ3
7
8
DQ21
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CC
NC
A0
A1
A2
A3
A4
A5
A6
NC
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
NC
V
CC
A8
A9
RAS3
RAS2
DQ26
DQ8
DQ17
DQ35
SS
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
V
PIN NOMENCLATURE
A0–A9
Address Inputs
CAS0–CAS3
DQ0–DQ35
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
NC
W
NC
DQ9
PD1– PD4
RAS0–RAS3
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
V
V
CC
Ground
SS
W
Write Enable
PRESENCE DETECT
PD1 PD2
V
CC
SIGNAL
(PIN)
PD3
(69)
PD4
(70)
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
(67) (68)
80 ns
70 ns
60 ns
80 ns
70 ns
60 ns
V
V
V
V
V
V
NC
V
SS
SS
SS
SS
SS
SS
SS
TM124MBJ36F
TM248NBJ36F
V
SS
NC
NC
NC
NC
PD1
PD2
PD3
PD4
NC
NC
NC
NC
NC
NC
V
SS
NC
V
SS
NC
NC
NC
V
SS
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBJ36F, TM124MBJ36U 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBJ36F, TM248NBJ36U 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS662 – MAY 1996
operation
The TM124MBJ36F operates as two TMS418160DZs and one TMS44460DJ connected as shown in the
functional block diagram and Table 1. The TM248NBJ36F operates as four TMS418160DZs and two
TMS44460DJs connected as shown in the functional block diagram and Table 1. The common I/O feature
dictates the use of early write cycles to prevent contention on D and Q.
Table 1. Connection Table
RASx
DATA BLOCK
CASx
†
SIDE 1
SIDE 2
DQ0–DQ7
DQ8
RAS0
RAS2
RAS1
RAS3
CAS0
CAS0
DQ9–DQ16
DQ17
RAS0
RAS2
RAS1
RAS3
CAS1
CAS1
DQ18–DQ25
DQ26
CAS2
CAS2
RAS2
RAS2
RAS3
RAS3
DQ27–DQ34
DQ35
CAS3
CAS3
†
Side 2 applies to the TM248NBJ36F.
single in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124MBJ36F and TM248NBJ36F: Nickel plate and gold plate over copper
Contact area for TM124MBJ36U and TM248NBJ36U: Nickel plate and tin/lead over copper
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBJ36F, TM124MBJ36U 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBJ36F, TM248NBJ36U 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS662 – MAY 1996
functional block diagram [TM124MBJ36F and TM248NBJ36F, side 1]
10
A0–A9
RAS0
W
1M × 16
1M × 16
10
10
10
8
8
8
8
A0–A9
DQ0–
DQ7
A0–A9
DQ0–
DQ7
DQ9–DQ16
DQ0– DQ7
DQ27–DQ34
DQ18–DQ25
RAS
W
RAS
W
CAS1
CAS0
CAS3
CAS2
LCAS
UCAS
DQ8–
DQ15
LCAS
UCAS
DQ8–
DQ15
1M × 4
A0–A9
RAS
DQ1
DQ2
DQ3
DQ4
DQ26
DQ8
DQ17
DQ35
W
CAS2
CAS0
CAS1
CAS3
CAS1
CAS2
CAS3
CAS4
functional block diagram [TM248NBJ36F, side 2]
10
A0–A9
RAS1
W
1M × 16
1M × 16
10
10
10
8
8
8
A0–A9
DQ0–
DQ7
A0–A9
RAS
DQ0–
DQ7
DQ0–DQ7
DQ18–DQ25
RAS
W
W
8
CAS2
CAS3
LCAS
UCAS
DQ8–
DQ15
LCAS
UCAS
DQ8–
DQ15
CAS0
CAS1
DQ9–DQ16
DQ27–DQ34
1M × 4
A0–A9
RAS
DQ1
DQ2
DQ3
DQ4
DQ35
DQ17
DQ8
W
CAS3
CAS1
CAS0
CAS2
CAS1
CAS2
CAS3
CAS4
DQ26
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBJ36F, TM124MBJ36U 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBJ36F, TM248NBJ36U 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS662 – MAY 1996
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation
TM124MBJ36F, TM124MBJ36U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W
TM248NBJ36F, TM248NBJ36U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
5.5
6.5
0.8
70
UNIT
V
V
V
V
Supply voltage
4.5
2.4
– 1
0
5
CC
IH
IL
High-level input voltage
V
Low-level input voltage (see Note 2)
Operating free-air temperature
V
T
A
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’124MBJ36F-60 ’124MBJ36F-70 ’124MBJ36F-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
= 4.2 mA
2.4
2.4
2.4
V
V
OH
OH
0.4
0.4
0.4
OL
OL
V
= 5.5 V, V = 0 V to 6.5 V,
I
CC
All other pins = 0 V to V
I
I
I
Input current (leakage)
± 10
± 10
± 10
µA
I
CC
V
V
= 5.5 V,
CC
= 0 V to V ,
CC
Output current (leakage)
± 10
485
6
± 10
450
6
± 10
420
6
µA
O
O
CAS high
Read- or write-cycle
current
V
V
= 5.5 V, Minimum cycle
mA
mA
CC1
CC
= 2.4 V (TTL),
IH
After 1 memory cycle,
RAS and CAS high
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After 1 memory cycle,
RAS and CAS high
3
3
3
mA
V
= 5.5 V, Minimum cycle,
CC
Average refresh current
(RAS only or CBR)
RAS cycling,
I
I
485
270
450
240
420
210
mA
mA
CC3
CAS high (RAS only);
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
PC
CAS cycling
Average page current
CC4
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBJ36F, TM124MBJ36U 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBJ36F, TM248NBJ36U 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS662 – MAY 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
†
temperature (unless otherwise noted)
’248NBJ36F-60 ’248NBJ36F-70 ’248NBJ36F-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
± 10
± 20
491
0.4
± 10
± 20
456
0.4
± 10
± 20
426
OL
OL
Input current
(leakage)
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
All other pins = 0 V to V
I
I
I
µA
µA
mA
I
CC
Output current
(leakage)
V
V
= 5.5 V,
CC
= 0 V to V , CAS high
O
O
CC
Read- or write-cycle
current (see Note 3)
V
= 5.5 V,
Minimum cycle
CC1
CC
V
IH
= 2.4 V (TTL),
After 1 memory cycle,
RAS and CAS high
12
6
12
6
12
6
mA
mA
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After 1 memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
Average refresh
current (RAS only or
CBR) (see Note 3)
I
I
970
276
900
246
840
216
mA
mA
CC3
CAS high (RAS only);
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= MIN,
Average page current
(see Note 4)
CC
RAS low,
PC
CAS cycling
CC4
†
For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
NOTES: 3. Measured with a maximum of one address change while RAS = V
IL
4. Measured with a maximum of one address change while CAS = V
IH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
’124MBJ36F
’248NBJ36F
PARAMETER
UNIT
MIN
MAX
22
MIN
MAX
37
C
C
C
C
C
Input capacitance, address inputs
pF
pF
pF
pF
pF
i(A)
Input capacitance, RAS inputs
Input capacitance, CAS inputs
Input capacitance, write-enable input
Output capacitance on DQ pins
17
17
i(R)
19
33
i(C)
28
49
i(W)
o(DQ)
10
17
NOTE 5: Bias on pins under test is 0 V.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBJ36F, TM124MBJ36U 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBJ36F, TM248NBJ36U 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS662 – MAY 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’124MBJ36F-60 ’124MBJ36F-70 ’124MBJ36F-80
’248NBJ36F-60 ’248NBJ36F-70 ’248NBJ36F-80
PARAMETER
UNIT
MIN
MAX
30
MIN
MAX
35
MIN
MAX
40
t
t
t
t
t
t
t
Access time from column address
Access time from CAS low
ns
ns
ns
ns
ns
ns
ns
AA
15
18
20
CAC
RAC
CPA
CLZ
OH
Access time from RAS low
60
70
80
Access time from column precharge
CAS to output in low-impedance state
Output disable time from start of CAS high
Output disable time after CAS high (see Note 6)
35
40
45
0
3
0
0
3
0
0
3
0
15
18
20
OFF
NOTE 6:
t
is specified when the output is no longer driven.
OFF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’124MBJ36F-60 ’124MBJ36F-70 ’124MBJ36F-80
’248NBJ36F-60 ’248NBJ36F-70 ’248NBJ36F-80
UNIT
MIN
110
40
MAX
MIN
130
45
MAX
MIN
150
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 7)
Cycle time, page-mode read or write (see Notes 7 and 8)
Pulse duration, page mode, RAS low
Pulse duration, nonpage mode, RAS low
Pulse duration, CAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
PC
60 100 000
70 100 000
80 100 000
RASP
RAS
CAS
CP
60
15
10
40
10
0
10 000
10 000
70
18
10
50
10
0
10 000
10 000
80
20
10
60
10
0
10 000
10 000
Pulse duration, CAS high (precharge)
Pulse duration, RAS high (precharge)
Pulse duration, W low
RP
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data before CAS low
ASC
ASR
DS
0
0
0
0
0
0
Setup time, W high before CAS low
Setup time, W low before CAS high
Setup time, W low before RAS high
Setup time, W low before CAS low
Hold time, column address after CAS low
Hold time, RAS high from CAS precharge
Hold time, data after CAS low
0
0
0
RCS
CWL
RWL
WCS
CAH
RHCP
DH
15
15
0
18
18
0
20
20
0
10
35
10
10
0
15
40
15
10
0
15
45
15
10
0
Hold time, row address after RAS low
Hold time, W high after CAS high (see Note 9)
Hold time, W high after RAS high (see Note 9)
Hold time, W low after CAS low
RAH
RCH
RRH
WCH
0
0
0
10
15
15
NOTES: 7. All cycles assume t = 5 ns.
T
8. To assure t
min, t
should be ≥ t .
PC
or t
ASC
must be satisfied for a read cycle.
RCH
CP
9. Either t
RRH
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBJ36F, TM124MBJ36U 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBJ36F, TM248NBJ36U 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS662 – MAY 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’124MBJ36F-60 ’124MBJ36F-70 ’124MBJ36F-80
’248NBJ36F-60 ’248NBJ36F-70 ’248NBJ36F-80
UNIT
MIN
10
5
MAX
MIN
10
5
MAX
MIN
10
5
MAX
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
CHR
CRP
CSH
CSR
RAD
RAL
CAL
RCD
RPC
RSH
REF
T
Delay time, RAS low to CAS high
60
5
70
5
80
5
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 10)
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 10)
Delay time, RAS high to CAS low (CBR only)
Delay time, CAS low to RAS high
15
30
30
20
0
30
45
15
35
35
20
0
35
52
15
40
40
20
0
40
60
15
18
20
Refresh time interval
16
30
16
30
16
30
Transition time
3
3
3
NOTE 10: The maximum value is specified only to assure access time.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBJ36F, TM124MBJ36U 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBJ36F, TM248NBJ36U 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS662 – MAY 1996
MECHANICAL DATA
BJ (R-PSIM-N72)
SINGLE-IN-LINE MEMORY MODULE
4.255 (108,08)
4.245 (107,82)
0.054 (1,37)
0.047 (1,19)
0.125 (3,18) TYP
0.050 (1,27)
0.040 (1,02) TYP
0.010 (0,25) MAX
0.128 (3,25)
0.120 (3,05)
0.400 (10,16) TYP
0.705 (17,91)
0.695 (17,65)
0.208 (5,28) MAX
0.360 (9,14) MAX
(For Double-Sided SIMM)
4088178/A 01/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
device symbolization (TM124MBJ36F illustrated)
TM124MBJ36F
-SS
YYMMT
YY = Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed Code
NOTE: Location of symbolization may vary.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current and complete.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1998, Texas Instruments Incorporated
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