TLV9062 [TI]
双路、5.5V、10MHz 运算放大器;型号: | TLV9062 |
厂家: | TEXAS INSTRUMENTS |
描述: | 双路、5.5V、10MHz 运算放大器 放大器 运算放大器 |
文件: | 总82页 (文件大小:6093K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
适用于成本敏感型系统的 TLV906xS 10MHz、RRIO、CMOS 运算放大器
1 具有
3 说明
1
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轨至轨输入和输出
TLV9061(单通道)、TLV9062(双通道)和
TLV9064(四通道)是单路、双路和四路低压(1.8V
至 5.5V)运算放大器,具有轨至轨输入和输出摆幅能
力。这些器件是具有高成本效益的解决方案,适用于需
要低工作 电压、 小型封装尺寸和高容性负载驱动能力
的应用。虽然 TLV906x 的容性负载驱动能力为
100pF,但电阻式开环输出阻抗便于在更高的容性负载
下更轻松地实现稳定。此类运算放大器专为低工作电压
(1.8V 至 5.5V)而设计,性能规格类似于 OPAx316
和 TLVx316 器件。
低输入偏移电压:±0.3mV
单位增益带宽:10MHz
低宽带噪声:10nV/√Hz
低输入偏置电流:0.5pA
低静态电流:538µA
单位增益稳定
内部射频干扰 (RFI) 和电磁干扰 (EMI) 滤波器
可在电源电压低至 1.8V 的电压下运行
由于采用了电阻式开环输出阻抗,因此在更高的容
性负载下可更轻松地实现稳定
中 TLV9061 DPW (X2SON) 封装中的封装预览说明
•
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关断版本:TLV906xS
器件信息(1)
扩展温度范围:–40°C 至 +125°C
器件型号
封装
SOT-23 (5)
封装尺寸(标称值)
1.60mm × 2.90mm
1.25mm × 2.00mm
1.65mm × 1.20mm
0.80mm × 0.80mm
2 应用
SC70 (5)
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电动自行车
TLV9061
SOT553 (5)
X2SON (5)
烟雾探测器
HVAC:采暖、通风和空调
电机控制:交流感应
冰箱
TLV9002S 中增加了
TLV9061S 器件
SOT-23 (6)
1.60mm × 2.90mm
SOIC (8)
3.91mm × 4.90mm
3.00mm × 4.40mm
3.00mm × 3.00mm
2.00mm × 2.00mm
1.50mm x 2.00mm
3.00mm × 3.00mm
1.50mm x 2.00mm
8.65mm × 3.91mm
4.40mm × 5.00mm
3.00mm × 3.00mm
2.00mm × 2.00mm
可穿戴设备
TSSOP (8)
VSSOP (8)
WSON (8)
X2QFN (10)
VSSOP (10)
X2QFN (10)
SOIC (14)
笔记本电脑
TLV9062
洗衣机
传感器信号调节
电源模块
TLV9062S 中增加了
TLV9062S 器件
条形码扫描器
有源滤波器
TSSOP (14)
WQFN (16)
WQFN (14)
低侧电流检测
TLV9064
TLV9064S 中增加了
TLV9064S 器件
WQFN (16)
3.00mm × 3.00mm
(1) 如需了解所有可用封装,请参阅产品说明书末尾的可订购产品
附录。
单极低通滤波器
RF
小信号过冲与负载电容间的关系
RG
60
50
40
30
20
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
10
0
Overshoot+
Overshoot-
1
1 + sR1C1
=
1 +
(
((
(
RG
0
50
100
150
200
250
300
Capacitive Load (pF)
C025
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBOS839
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
www.ti.com.cn
目录
9.2 功能框图.................................................................. 22
9.3 特性 描述................................................................. 23
9.4 器件功能模式........................................................... 23
10 应用和实现 ............................................................ 24
10.1 应用信息................................................................ 24
10.2 典型 应用............................................................... 24
11 电源建议................................................................ 28
11.1 输入和 ESD 保护................................................... 28
12 布局 ....................................................................... 29
12.1 布局指南................................................................ 29
12.2 布局示例................................................................ 30
13 器件和文档支持 ..................................................... 31
13.1 文档支持................................................................ 31
13.2 相关链接................................................................ 31
13.3 接收文档更新通知 ................................................. 31
13.4 社区资源................................................................ 31
13.5 商标....................................................................... 31
13.6 静电放电警告......................................................... 31
13.7 术语表 ................................................................... 31
14 机械、封装和可订购信息....................................... 32
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具有.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 (续).............................................................. 4
器件比较表............................................................... 5
引脚配置和功能........................................................ 6
规格........................................................................ 12
8.1 绝对最大额定值....................................................... 12
8.2 ESD 额定值 ............................................................ 12
8.3 建议的工作条件....................................................... 12
8.4 热性能信息:TLV9061 ............................................ 13
8.5 热性能信息:TLV9062 ............................................ 13
8.6 热性能信息:TLV9062S.......................................... 13
8.7 热性能信息:TLV9064 ............................................ 13
8.8 电气特性:VS(总电源电压)= (V+) – (V–) = 1.8V 至
5.5V.......................................................................... 14
8.9 典型特性.................................................................. 16
详细 说明................................................................ 22
9.1 概要......................................................................... 22
9
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision D (June 2018) to Revision E
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已添加 在器件信息表 .............................................................................................................................................................. 1
已添加 在器件信息 表 ............................................................................................................................................................. 1
Added 在器件比较 表.............................................................................................................................................................. 5
Added 在引脚配置和功能 部分中增加了 TLV9061S DBV (SOT-23) 引脚图 .......................................................................... 7
Added 在引脚功能:TLV9061S 表中 ..................................................................................................................................... 7
Added 在引脚配置和功能 部分中增加了 TLV9064 RTE (WQFN) 引脚图............................................................................. 10
Added 在引脚功能:TLV9064 表 ......................................................................................................................................... 10
Added 在引脚功能:TLV9064 表 ......................................................................................................................................... 11
Added 在引脚配置和功能 部分中增加了 TLV9064S RTE (WQFN) 引脚图 .......................................................................... 11
Changes from Revision C (March 2018) to Revision D
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已添加 对文档标题中的“TLV906x”添加了关断后缀................................................................................................................. 1
已添加 在特性 列表中增加了“关断版本”项目符号 ................................................................................................................... 1
已添加 在器件信息 表 ............................................................................................................................................................. 1
已添加 在说明 (续)部分增加了关断文字............................................................................................................................. 4
Added 在绝对最大额定值 表................................................................................................................................................. 12
Added 在建议运行条件 表 .................................................................................................................................................... 12
Added 在建议运行条件 表 .................................................................................................................................................... 12
Added 在建议运行条件 表的“额定温度”参数中增加了........................................................................................................... 12
Added 热性能信息:TLV9062S 热性能表数据 ..................................................................................................................... 13
已添加 关断功能 部分 ........................................................................................................................................................... 23
已添加 比较器典型应用 部分................................................................................................................................................. 26
2
版权 © 2017–2018, Texas Instruments Incorporated
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
www.ti.com.cn
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
Changes from Revision B (October 2017) to Revision C
Page
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已更改 将器件状态从“生产数据/混合状态”改为“生产数据” ...................................................................................................... 1
已删除 删除了器件信息 表 ...................................................................................................................................................... 1
Deleted 删除了 TLV9061 DPW (X2SON) 封装引脚图中的封装预览说明 .............................................................................. 6
Changed 更改了 ESD 额定值 表的格式以显示所有封装所对应的不同结果.......................................................................... 12
Deleted 删除了热性能信息:TLV9061 表............................................................................................................................. 13
Changes from Revision A (June 2017) to Revision B
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Added 在引脚配置和功能 部分中添加 8 引脚 PW 封装.......................................................................................................... 8
Added 在热性能信息 表中添加了 DSG (WSON) 封装.......................................................................................................... 13
Added 在 TLV9062 热性能信息 表中添加了 PW (TSSOP) .................................................................................................. 13
Changed 将最大输入失调电压值从 ±1.6mV 更改为 2mV..................................................................................................... 14
Changed 将最大输入失调电压值从 ±1.5V 更改为 ±1.6mV................................................................................................... 14
Changed 将最小共模抑制比输入电压范围从 86dB 更改为 80dB ......................................................................................... 14
Changed 将典型输入电流噪声密度值从 10 更改为 23fA/√Hz............................................................................................... 14
Changed 将 THD + N 测试条件从 VS = 5V 更改为 VS = 5.5V.............................................................................................. 14
Added 在 THD + N 参数中添加 VCM = 2.5V 测试条件(位于电气特性 表中)..................................................................... 14
Added 将最大输出电压摆幅值从 25mV 更改为 60mV.......................................................................................................... 14
Changed 将最大输出电压摆幅值从 15mV 更改为 20mV...................................................................................................... 14
Changes from Original (March 2017) to Revision A
Page
•
已更改 将器件状态从“预告信息”改为“生产数据”...................................................................................................................... 1
版权 © 2017–2018, Texas Instruments Incorporated
3
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
www.ti.com.cn
5 说明 (续)
TLV900x 器件具有关断模式,允许放大器切换至典型电流消耗低于 1µA 的待机模式。
TLV906xS 系列有助于简化系统设计,因为该系列具有稳定的单位增益,集成了 RFI 和 EMI 抑制滤波器,而且在
过驱条件下不会出现反相。
针对所有通道类型(单通道、双通道和四通道)提供微型封装(如 SOT-553 和 WSON、)以及行业标准封装(如
SOIC、MSOP、SOT-23 和 TSSOP)。
4
Copyright © 2017–2018, Texas Instruments Incorporated
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
www.ti.com.cn
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
6 器件比较表
中增加了 RUC 和 RUG 封装
封装引线
通道
器件
数
DBV
DCK
5
DRL
5
DPW
5
D
8
DSG
—
DGK
—
DGS
—
PW
—
8
RTE
—
RUC
—
RUG
—
TLV9061
TLV9062
TLV9064
1
2
4
5、6
—
—
—
—
8
8
8
10
—
—
10
—
—
—
—
14
—
—
—
14
16
14
—
Copyright © 2017–2018, Texas Instruments Incorporated
5
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
www.ti.com.cn
7 引脚配置和功能
TLV9061 DBV 和 DRL 封装
5 引脚 SOT-23 和 SOT-553
俯视图
TLV9061 DCK 封装
5 引脚 SC70
俯视图
OUT
V-
1
2
3
5
4
V+
+IN
V-
1
5
4
V+
2
3
+IN
-IN
-IN
OUT
TLV9061 DPW 封装
5 引脚 X2SON
俯视图
OUT
1
5
4
V+
3
Vœ
œIN
2
+IN
Not to scale
引脚功能:TLV9061
引脚
I/O
说明
SOT-23、SOT-
名称
SC70
X2SON
553
–IN
4
3
3
1
2
4
I
I
反相输入
同相输入
输出
+IN
OUT
SHDN
V–
1
4
1
O
I
—
2
—
2
—
3
关断(低电平有效)
—
—
负(最低)电源或接地(对于单电源供电)
正(最高)电源
V+
5
5
5
6
Copyright © 2017–2018, Texas Instruments Incorporated
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
www.ti.com.cn
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
TLV9061S DBV 封装
6 引脚 SOT-23
俯视图
OUT
Vœ
1
2
3
6
5
4
V+
SHDN
œIN
+IN
Not to scale
引脚功能:TLV9061S
引脚
I/O
说明增加了 TLV9061S DBV (SOT-23) 封装引脚信息
名称
–IN
编号
4
3
1
5
2
6
I
I
反相输入
+IN
同相输入
输出
OUT
SHDN
V–
O
I
关断(低电平有效)
—
—
负(最低)电源或接地(对于单电源供电)
正(最高)电源
V+
Copyright © 2017–2018, Texas Instruments Incorporated
7
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
www.ti.com.cn
TLV9062 D、DGK、PW 封装
8 引脚 SOIC、VSSOP、TSSOP
俯视图
TLV9062 DSG 封装
带有外露散热焊盘的 8 引脚 WSON 封装
俯视图
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
8
7
6
5
V+
OUT A
-IN A
+IN A
V-
1
2
3
4
OUT B
-IN B
+IN B
Exposed
Thermal
Die Pad
on
OUT B
-IN B
+IN B
Underside(1)
引脚功能:TLV9062
引脚
I/O
说明
名称
编号
2
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
NC
I
I
反相输入,通道 A
3
同相输入,通道 A
反相输入,通道 B
同相输入,通道 B
输出,通道 A
6
I
5
I
1
O
O
—
I
7
输出,通道 B
—
—
—
4
无内部连接
SHDN A
SHDN B
V–
关断(逻辑低电平),启用(逻辑高电平),通道 A
关断(逻辑低电平),启用(逻辑高电平),通道 B
负(最低)电源或接地(对于单电源供电)
正(最高)电源
I
—
—
V+
8
TLV9062S DGS 封装
10 引脚 VSSOP
俯视图
V+
OUT A
–IN A
1
2
3
4
5
10
9
OUT B
–IN B
+IN B
SHDN B
A
+IN A
V–
8
B
7
SHDN A
6
引脚功能:TLV9062S
引脚
I/O
说明
名称
编号
2
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
NC
I
I
反相输入,通道 A
3
同相输入,通道 A
反相输入,通道 B
同相输入,通道 B
输出,通道 A
8
I
7
I
1
O
O
—
I
9
输出,通道 B
—
5
无内部连接
SHDN A
SHDN B
V–
关断(逻辑低电平),启用(逻辑高电平),通道 A
关断(逻辑低电平),启用(逻辑高电平),通道 B
负(最低)电源或接地(对于单电源供电)
6
I
4
—
8
Copyright © 2017–2018, Texas Instruments Incorporated
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
www.ti.com.cn
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
引脚功能:TLV9062S (continued)
引脚
I/O
说明
名称
编号
V+
10
—
正(最高)电源
Copyright © 2017–2018, Texas Instruments Incorporated
9
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
www.ti.com.cn
TLV9064 D、PW 封装
14 引脚 SOIC、TSSOP
俯视图
OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
A
D
13 -IN D
12 +IN D
11 V-
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
B
C
OUT C
TLV9064 RTE 封装
带有外露散热焊盘的 16 引脚 WQFN 封装
俯视图
+IN A
V+
1
2
3
4
12
11
10
9
+IN D
Vœ
Thermal
Pad
+IN B
œIN B
+IN C
œIN C
Not to scale
引脚功能:TLV9064
引脚
I/O
说明中增加了 RUC 封装引脚信息中增加了 TLV9064 RTE 引脚信息
SOIC、
TSSOP
名称
WQFN
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
NC
2
3
16
1
I
I
反相输入,通道 A
同相输入,通道 A
反相输入,通道 B
同相输入,通道 B
反相输入,通道 C
同相输入,通道 C
反相输入,通道 D
同相输入,通道 D
无内部连接
6
4
I
5
3
I
9
9
I
10
13
12
—
1
10
13
12
6、7
15
5
I
I
I
—
O
O
O
O
OUT A
OUT B
OUT C
OUT D
输出,通道 A
7
输出,通道 B
8
8
输出,通道 C
14
14
输出,通道 D
10
Copyright © 2017–2018, Texas Instruments Incorporated
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
www.ti.com.cn
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
引脚功能:TLV9064 (continued)
引脚
I/O
说明中增加了 RUC 封装引脚信息中增加了 TLV9064 RTE 引脚信息
SOIC、
TSSOP
名称
WQFN
SHDN A/B
SHDN C/D
V–
—
—
11
4
—
—
11
2
I
关断(逻辑低电平),启用(逻辑高电平),通道 A/B
关断(逻辑低电平),启用(逻辑高电平),通道 C/D
负(最低)电源或接地(对于单电源供电)
正(最高)电源
I
—
—
V+
TLV9064S RTE 封装
带有外露散热焊盘的 16 引脚 WQFN 封装
俯视图
+IN A
1
2
3
4
12
11
10
9
+IN D
Vœ
V+
+IN B
œIN B
Thermal
Pad
+IN C
œIN C
Not to scale
引脚功能:TLV9064S
引脚
I/O
说明
名称
编号
16
1
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
SHDN A/B
SHDN C/D
V–
I
I
反相输入,通道 A
同相输入,通道 A
反相输入,通道 B
同相输入,通道 B
反相输入,通道 C
同相输入,通道 C
反相输入,通道 D
同相输入,通道 D
输出,通道 A
4
I
3
I
9
I
10
13
12
15
5
I
I
I
O
O
O
O
I
输出,通道 B
8
输出,通道 C
14
6
输出,通道 D
关断(逻辑低电平),启用(逻辑高电平),通道 A/B
关断(逻辑低电平),启用(逻辑高电平),通道 C/D
负(最低)电源或接地(对于单电源供电)
正(最高)电源
7
I
11
2
—
—
V+
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8 规格
8.1 绝对最大额定值
在自然通风温度下测得(除非另有说明)(1)
最小值
(V–) – 0.5
-10
最大值
单位
电源电压
6
(V+) + 0.5
(V+) – (V–) + 0.2
10
V
共模
电压(2)
V
信号输入引脚
输出短路(3)
温度
差模
电流(2)
mA
mA
连续
额定温度,TA
结温,TJ
–40
125
150
150
°C
贮存温度,Tstg
–65
(1) 应力超出“绝对最大额定值”下所列的值可能会对器件造成永久损坏。这些列出的值仅仅是极端条件下的应力额定值,并不表示器件在这些条
件下以及在“建议运行条件”以外的任何其他条件下能够正常运行。长时间处于绝对最大额定条件下可能会影响器件的可靠性。
(2) 输入引脚被二极管钳制至电源轨。对于摆幅能超过电源轨 0.5V 的输入信号,应将其电流限制在 10mA 或者更低。
(3) 接地短路,每个封装对应一个放大器。
8.2 ESD 额定值
值
单位
TLV9061 DPW (X2SON) 封装
V(ESD) 静电放电
所有其他封装
V(ESD) 静电放电
人体放电模型 (HBM),符合 ANSI/ESDA/JEDEC JS-001(1)
充电器件模型 (CDM),符合 JEDEC 规范 JESD22-C101(2)
±2500
±1500
V
人体放电模型 (HBM),符合 ANSI/ESDA/JEDEC JS-001(1)
充电器件模型 (CDM),符合 JEDEC 规范 JESD22-C101(2)
±4000
±1500
V
(1) JEDEC 文档 JEP155 指出:500V HBM 时能够在标准 ESD 控制流程下安全生产。
(2) JEDEC 文档 JEP157 指出:250V CDM 时能够在标准 ESD 控制流程下安全生产。
中增加了 (VS = [V+] – [V–]) 电源电压参数中增加了“输入电压范围”和“输出电压范围”参数和值中增加了关断引脚建议运行条件“TA”符号
8.3 建议的工作条件
在自然通风温度范围内测得(除非另有说明)
最小值
1.8
最大值
5.5
单位
VS
电源电压 (VS = [V+] – [V–])
输入电压范围
V
V
VI
(V–) – 0.1
V–
(V+)+0.1
V+
VO
输出电压范围
V
VSHDN_IH
VSHDN_IL
TA
关断引脚上的高电平输入电压(放大器为启用状态)
关断引脚上的低电平输入电压(放大器为禁用状态)
额定温度范围
1.1
V+
V
V-
0.2
V
–40
125
°C
12
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中 DPW (X2SON) 封装中的封装预览说明
8.4 热性能信息:TLV9061
TLV9061
热指标(1)
DBV (SOT-23)
5/6 引脚
221.7
DCK (SC70)
5 引脚
263.3
75.5
DPW (X2SON)
5 引脚
467
单位
RθJA
结至环境热阻
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
结至外壳(顶部)热阻
结至电路板热阻
144.7
211.6
49.7
51
332.2
ψJT
结至顶部特征参数
结至电路板特征参数
结至外壳(底部)热阻
26.1
1
29.3
ψJB
49
50.3
330.6
RθJC(bot)
不适用
不适用
125
(1) 有关传统和新热指标的更多信息,请参阅应用报告《半导体和 IC 封装热指标》。
8.5 热性能信息:TLV9062
TLV9062
DGK (VSSOP) DSG (WSON)
热指标(1)
D (SOIC)
8 引脚
157.6
104.6
99.7
PW (TSSOP)
8 引脚
205.8
单位
8 引脚
201.2
85.7
8 引脚
94.4
116.5
61.3
13
RθJA
结至环境热阻
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) 结至外壳(顶部)热阻
106.7
RθJB
ψJT
结至电路板热阻
122.9
21.2
133.9
结至顶部特征参数
结至电路板特征参数
55.6
34.4
ψJB
99.2
121.4
不适用
61.7
34.4
132.6
RθJC(bot) 结至外壳(底部)热阻
不适用
不适用
(1) 有关传统和新热指标的更多信息,请参阅应用报告《半导体和 IC 封装热指标》。
8.6 热性能信息:TLV9062S
TLV9062S
DGS (VSSOP)
10 引脚
170.4
热指标(1)
单位
RθJA
结至环境热阻
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
结至外壳(顶部)热阻
结至电路板热阻
84.9
113.5
ψJT
结至顶部特征参数
结至电路板特征参数
结至外壳(底部)热阻
16.4
ψJB
112.3
RθJC(bot)
不适用
(1) 有关传统和新热指标的更多信息,请参阅应用报告《半导体和 IC 封装热指标》。
8.7 热性能信息:TLV9064
TLV9064
热指标(1)
PW (TSSOP)
D (SOIC)
单位
14 引脚
135.8
64
14 引脚
106.9
64
RθJA
RθJC(top)
RθJB
ψJT
结至环境热阻
°C/W
°C/W
°C/W
°C/W
°C/W
结至外壳(顶部)热阻
结至电路板热阻
79
63
结至顶部特征参数
结至电路板特征参数
15.7
78.4
25.9
62.7
ψJB
(1) 有关传统和新热指标的更多信息,请参阅应用报告《半导体和 IC 封装热指标》。
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8.8 电气特性:VS(总电源电压)= (V+) – (V–) = 1.8V 至 5.5V
TA = 25°C,RL = 10kΩ(连接至 VS / 2),VCM = VS / 2,且 VOUT = VS / 2(除非另有说明)
参数
测试条件
最小值
典型值
最大值
单位
失调电压
VS = 5V
±0.3
±1.6
±2
VOS
输入失调电压
mV
VS = 5V,TA = –40°C 至 +125°C
VS = 5V,TA = –40°C 至 +125°C
dVOS/d
T
漂移
±0.53
µV/°C
PSRR
电源抑制比
VS = 1.8V – 5.5V,VCM = (V–)
±7
±80
µV/V
dB
通道分离,直流
直流时
100
输入电压范围
VCM
共模电压范围
VS = 1.8V 至 5.5V
(V–) – 0.1
80
(V+)+0.1
V
VS = 5.5V,(V–) – 0.1 V < VCM < (V+) – 1.4V
TA = –40°C 至 +125°C
103
87
VS = 5.5V,VCM = –0.1V 至 5.6V
TA = –40°C 至 +125°C
57
CMRR 共模抑制比
输入偏置电流
dB
VS = 1.8V,(V–) – 0.1 V < VCM < (V+) – 1.4V,
TA = –40°C 至 +125°C
88
VS = 1.8V,VCM = –0.1V 至 1.9V
TA = –40°C 至 +125°C
81
IB
输入偏置电流
输入失调电流
±0.5
pA
pA
IOS
噪声
En
±0.05
输入电压噪声(峰峰值)
输入电压噪声密度
VS = 5V,f = 0.1Hz 至 10Hz
VS = 5V,f = 10kHz
VS = 5V,f = 1kHz
f = 1kHz
4.77
10
µVPP
nV/√Hz
nV/√Hz
fA/√Hz
en
16
in
输入电流噪声密度
23
输入电容
CID
差分
共模
2
4
pF
pF
CIC
开环增益
VS = 1.8V,(V–) + 0.04V < VO < (V+) – 0.04V,
RL = 10kΩ
100
130
100
130
VS = 5.5V,(V–) + 0.05V < VO < (V+) – 0.05V,
RL = 10kΩ
104
AOL
开环电压增益
dB
VS = 1.8V,(V–) + 0.06V < VO < (V+) – 0.06V,
RL = 2kΩ
VS = 5.5V,(V–) + 0.15V < VO < (V+) – 0.15V,
RL = 2kΩ
频率响应
GBP
φm
增益带宽积
相位裕度
压摆率
VS = 5V,G = +1
VS = 5V,G = +1
VS = 5V,G = +1
10
55
MHz
°
SR
6.5
V/µs
精度达到 0.1%,VS = 5V,2V 阶跃,G = +1,CL
100pF
=
0.5
tS
建立时间
µs
µs
精度达到 0.01%,VS = 5V,2V 阶跃,
G = +1,CL = 100pF
1
0.2
tOR
过载恢复时间
VS = 5V,VIN × 增益 > VS
THD +
N
VS = 5.5V,VCM = 2.5V,VO = 1VRMS,G = +1,f =
1kHz
总谐波失真 + 噪声(1)
0.0008%
输出
VS = 5.5V,RL = 10kΩ
VS=5.5V,RL=2kΩ
VS = 5V
20
60
VO
相对于电源轨的电压输出摆幅
mV
ISC
ZO
短路电流
±50
100
mA
开环输出阻抗
VS = 5V,f = 10MHz
Ω
(1) 三阶滤波器;–3dB 时的带宽 = 80kHz。
14
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电气特性:VS(总电源电压)= (V+) – (V–) = 1.8V 至 5.5V (continued)
TA = 25°C,RL = 10kΩ(连接至 VS / 2),VCM = VS / 2,且 VOUT = VS / 2(除非另有说明)
参数
测试条件
最小值
典型值
最大值
单位
电源
VS = 5.5V,IO = 0mA
538
750
800
IQ
每个放大器的静态电流
µA
VS = 5.5V,IO = 0mA,TA = –40°C 至 +125°C
关断
IQSD
VS = 1.8V 至 5.5V,所有放大器为禁用状态,SHDN =
VS–
静态电流(每个放大器)
关断时的输出阻抗
0.5
10 || 8
1.5
µA
GΩ || pF
V
ZSHDN
VS = 1.8V 至 5.5V,放大器为禁用状态
VS = 1.8V 至 5.5V
VSHDN_ 高电平电压关断阈值(放大器为启用
(V–) +
1.1V
(V–) + 0.9V
状态)
THR_HI
VSDHN_ 低电平电压关断阈值(放大器为禁用
(V–) +
0.2V
VS = 1.8V 至 5.5V
(V–) + 0.7V
V
状态)
THR_LO
VS = 1.8V 至 5.5V,完全关断;G = 1,VOUT = 0.9 ×
VS/2,RL 连接到 V–
放大器启用时间(完全关断)(2)(3)
tON
10
6
µs
µs
µs
VS = 1.8V 至 5.5V,部分关断;G = 1,VOUT = 0.9 ×
VS/2,RL 连接到 V–
放大器启用时间(部分关断)(2)(3)
VS = 1.8V 至 5.5V,G = 1,VOUT = 0.1 × VS/2,RL 连
接到 V–
tOFF
放大器禁用时间(2)
0.5
VS = 1.8V 至 5.5V,V+ ≥ SHDN ≥ (V+) - 0.8V
VS = 1.8V 至 5.5V,V- ≤ SHDN ≤ V- + 0.8V
130
40
SHDN 引脚输入偏置电流(每个引
脚)
pA
(2) 禁用时间 (tOFF) 和启用时间 (tON) 是指施加给 SHDN 引脚的信号为 50% 时到输出电压达到 10%(禁用)或 90%(启用)电平时之间的时
间间隔。
(3) 完全关断是指双通道 TLV9062S 将 A、B 两个通道都禁用 (SHDN_A = SHDN_B = V–) 以及四通道 TLV9064S 将 A、B、C、D 四个通道
都禁用 (SHDN_A/B = SHDN_C/D = V––)。部分关断是指仅使用一个 SHDN 引脚;在这种模式下,内部偏置电路仍然保持正常工作,并且
启用时间更短。
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8.9 典型特性
TA = 25°C,VS = 5.5V,RL = 10kΩ(连接至 VS / 2),VCM = VS / 2,且 VOUT = VS / 2(除非另有说明)
35
30
25
20
15
10
5
50
40
30
20
10
0
0
Offset Voltage Drift (µV/C)
C001
Offset Voltage (µV)
C002
TA = –40°C 至 +125°C
图 1. 失调电压产生分布
图 2. 失调电压漂移分布
500
400
2500
2000
1500
1000
500
300
200
100
0
0
œ100
œ200
œ300
œ400
œ500
œ500
œ1000
œ1500
œ2000
œ2500
0
25
50
75
100
125
150
-4
-3
-2
-1
0
1
2
3
4
œ50
œ25
Temperature (°C)
Input Common Mode Voltage (V)
C003
C005
V+ = 2.75V,V– = –2.75V
图 3. 失调电压与温度间的关系
图 4. 失调电压与共模电压间的关系
1000
120
100
80
180
135
90
Gain
Phase
500
0
60
40
20
œ500
œ1000
45
0
œ20
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
100
1k
10k
100k
1M
10M
Supply Voltage (V)
Frequency (Hz)
C004
C006
VS = 1.8V 至 5.5V
CL = 10pF
图 5. 失调电压与电源间的关系
图 6. 开环增益和相位与频率间的关系
16
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ZHCSGC0E –MARCH 2017–REVISED JULY 2018
典型特性 (接下页)
TA = 25°C,VS = 5.5V,RL = 10kΩ(连接至 VS / 2),VCM = VS / 2,且 VOUT = VS / 2(除非另有说明)
20
16
12
8
40
VS = 5.5 V
VS = 1.8 V
30
20
10
0
œ10
œ20
œ30
œ40
G=+1
G=-1
4
G=+10
0
0
25
50
75
100
125
1000
10k
100k
1M
10M
œ50
œ25
Temperature (°C)
RL = 2kΩ
Frequency (Hz)
C022
C007
图 7. 开环增益与温度间的关系
图 8. 闭环增益与频率间的关系
3
2
250
200
150
100
50
IBN
IBP
IOS
-40°C
125°C
85°C
1
25°C
0
25°C
85°C
-40°C
œ1
œ2
œ3
125°C
0
œ50
0
25
50
75
100
125
10
20
30
40
50
60
œ50
œ25
Temperature (°C)
Output Current (mA)
C008
C009
V+ = 2.75V,V– = –2.75V
图 9. 输入偏置电流与温度间的关系
图 10. 输出电压摆幅与输出电流间的关系
120
100
80
60
40
20
0
55
CMRR
PSRR-
PSRR+
50
45
40
35
30
1000
10k
100k
1M
10M
0
25
50
75
100
125
œ50
œ25
Frequency (Hz)
C011
Temperature (°C)
C012
VS = 5.5V,VCM = –0.1V 至 5.6V
TA= –40°C 至 +125°C,RL= 10kΩ
图 11. CMRR 和 PSRR 与频率间的关系
(以输入为基准)
图 12. CMRR 与温度间的关系
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典型特性 (接下页)
TA = 25°C,VS = 5.5V,RL = 10kΩ(连接至 VS / 2),VCM = VS / 2,且 VOUT = VS / 2(除非另有说明)
10
10
9
8
7
6
5
4
3
2
1
9
8
7
6
5
0
25
50
75
100
125
150
0
25
50
75
100
125
œ50
œ25
œ50
œ25
Temperature (°C)
Temperature (°C)
C016
C013
VS = 5.5V,VCM = (V–) – 0.1V 至 (V+) – 1.4V
TA= –40°C 至 +125°C,RL= 10kΩ
VS = 1.8V 至 5.5V
图 13. CMRR 与温度间的关系
图 14. PSRR 与温度间的关系
120
100
80
60
40
20
0
Time (1s/div)
10
100
1k
10k
100k
Frequency (Hz)
C014
C015
VS = 1.8V 至 5.5V
图 15. 0.1Hz 至 10Hz 输入电压噪声
图 16. 输入电压噪声频谱密度与频率间的关系
œ90
œ95
œ40
œ60
œ100
œ105
œ110
œ115
œ120
œ80
œ100
œ120
100
1k
10k
0.001
0.01
0.1
1
Frequency (Hz)
Output Voltage Amplitude (VRMS
)
C017
C018
VS = 5.5V,VCM = 2.5V,RL = 2kΩ,G = +1,BW = 80kHz
VS = 5.5V,VCM = 2.5V,RL = 2kΩ,G = +1
BW = 80kHz,f = 1kHz
VOUT = 0.5VRMS
图 17. THD + N 与频率间的关系
图 18. THD + N 与幅度间的关系
18
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典型特性 (接下页)
TA = 25°C,VS = 5.5V,RL = 10kΩ(连接至 VS / 2),VCM = VS / 2,且 VOUT = VS / 2(除非另有说明)
œ40
600
580
560
540
520
500
œ60
œ80
œ100
œ120
0.001
0.01
0.1
1
1.5
10k
0
2
2.5
3
3.5
4
4.5
5
5.5
Output Voltage Amplitude (VRMS
)
Supply Voltage (V)
C019
C020
VS = 5.5V,VCM = 2.5V,RL = 2kΩ,G = –1
BW = 80kHz,f = 1kHz
图 19. THD + N 与幅度间的关系
图 20. 静态电流与电源电压间的关系
800
700
600
500
400
300
200
100
0
200
160
120
80
40
0
0
25
50
75
100
125
œ50
œ25
100k
Frequency (Hz)
1M
10M
Temperature (°C)
C021
C024
图 21. 静态电流与温度间的关系
图 22. 开环输出阻抗与频率间的关系
60
50
40
30
20
10
0
60
50
40
30
20
10
0
Overshoot+
Overshoot-
Overshoot(+)
Overshoot(-)
0
50
100
150
200
250
300
50
100
150
200
250
300
Capacitive Load (pF)
Capacitive Load (pF)
C025
C026
V+ = 2.75V,V– = –2.75V,G = +1V/V,RL = 10kΩ
OUT 阶跃 = 100mVp-p
V+ = 2.75V,V– = –2.75V,G = -1V/V,RL = 10kΩ
OUT 阶跃 = 100mVp-p
V
V
图 23. 小信号过冲与负载电容间的关系
图 24. 小信号过冲与负载电容间的关系
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典型特性 (接下页)
TA = 25°C,VS = 5.5V,RL = 10kΩ(连接至 VS / 2),VCM = VS / 2,且 VOUT = VS / 2(除非另有说明)
INPUT
Input
OUTPUT
Output
Time (1 µs/div)
Time (200 µs/div)
C028
C036
V+ = 2.75V,V– = –2.75V,G = –10V/V
V+ = 2.75V,V– = –2.75V
图 26. 过载恢复
图 25. 无相位反转
Input
Output
Input
Output
Time (1 µs/div)
Time (0.1µs/div)
C031
C030
V+ = 2.75V,V– = –2.75V,CL = 100pF,G = 1V/V
V+ = 2.75V,V– = –2.75V,G = 1V/V
图 28. 大信号阶跃响应
图 27. 小信号阶跃响应
80
60
6
5
4
3
2
40
20
Sinking
0
Sourcing
œ20
œ40
œ60
œ80
1
0
VS = 5.5 V
VS = 1.8 V
0
25
50
75
100
125
1
10
100
1k
10k
100k
1M
10M
œ50
œ25
Temperature (°C)
Frequency (Hz)
C034
C035
RL = 10kΩ,CL = 10pF
图 29. 短路电流与温度间的关系
图 30. 最大输出电压与频率和电源电压间的关系
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典型特性 (接下页)
TA = 25°C,VS = 5.5V,RL = 10kΩ(连接至 VS / 2),VCM = VS / 2,且 VOUT = VS / 2(除非另有说明)
140
120
100
80
0
œ20
œ40
œ60
60
œ80
40
œ100
œ120
œ140
20
0
10M
100M
Frequency (Hz)
1G
100
1k
10k
100k
1M
10M
Frequency (Hz)
C041
C038
V+ = 2.75V,V– =
PRF = –10dBm
–2.75V
图 31. 以同相输入为基准的电磁干扰抑制比 (EMIRR+) 与频率间
图 32. 通道分离与频率间的关系
的关系
200
160
120
80
90
75
60
45
30
15
0
40
0
0
10
20
30
40
50
60
70
80
90 100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Capacitive Load (pF)
Output Voltage (V)
C037
C023
VS = 5.5V
VS = 5.5V
图 33. 相位裕度与容性负载间的关系
图 34. 开环电压增益与输出电压间的关系
100
75
100
75
50
50
25
25
0
0
-25
-50
-75
-100
-125
-150
œ25
œ50
œ75
œ100
0
0.3
0.6
0.9
0
0.3
0.6
0.9
1.2
1.5
Settling time (µs)
Settling time (µs)
C032
C033
图 35. 大信号建立时间(正)
图 36. 大信号建立时间(负)
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9 详细 说明
9.1 概要
TLV906x 是低功耗、轨至轨输入和输出运算放大器系列。这些器件的工作电压范围为 1.8V 至 5.5V,具有单位增益
稳定特性,并且适用于各种通用 应用。输入共模电压范围包括两个电源轨,并支持将 TLV906x 系列器件用于几乎
任何单电源应用。轨至轨输入和输出摆幅可大幅扩大动态范围(尤其在低电源 应用中),并且适用于驱动采样模数
转换器 (ADC)。
9.2 功能框图
V+
Reference
Current
VIN+
VINÛ
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
VÛ
(Ground)
22
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9.3 特性 描述
9.3.1 轨至轨输入
TLV906x 系列的输入共模电压范围相对于电源轨向外扩展了 100mV,从而支持 1.8V 至 5.5V 的完整电源电压范
围。此性能由一个互补输入级实现:一个 N 沟道输入差分对和一个 P 沟道差分对并联,如功能框图 所示。当输入
电压靠近正轨(通常在 (V+) – 1.4V 到高于正电源电压 200mV 之间)时,N 沟道对有效;而当输入在低于负电源
电压 200mV 到大约 (V+) – 1.4V 之间时,P 沟道对有效。在一个通常介于 (V+) – 1.2V 到 (V+) – 1V 之间的小转换
区域内,两个通道对都会打开。此 200mV 转换区域可能会随工艺不同而发生变化,最高可达 200mV。因此,此转
换区域(两个级都打开)在低端上的范围介于 (V+) – 1.4V 至 (V+) – 1.2V 之间,而在高端上的范围高达 (V+) – 1V
至 (V+) – 0.8V。在此转换区域内,与器件在该区域外运行相比,PSRR、CMRR、失调电压、温漂和 THD 等性能
可能会下降。
9.3.2 轨至轨输出
TLV906x 系列器件设计为一种低功耗、低电压运算放大器,可提供强大的输出驱动能力。一个具有共源晶体管的
AB 类输出级可实现完全的轨至轨输出摆幅功能。对于 10kΩ 的阻性负载,无论施加的电源电压是多少,输出摆幅
都在两个电源轨的 15mV 范围内。不同的负载情况会改变放大器在靠近电源轨范围内摆动的能力。
9.3.3 过载恢复
过载恢复定义为运算放大器输出从饱和状态恢复到线性状态所需的时间。当输出电压由于高输入电压或高增益而超
过额定工作电压时,运算放大器的输出器件进入饱和区。器件进入饱和区后,输出器件中的电荷载体需要时间回到
线性状态。当电荷载体回到线性状态时,器件开始以指定的压摆率进行转换。因此,传播延迟(过载情况下)等于
过载恢复时间与转换时间之和。TLV906x 系列器件的过载恢复时间大约为 200ns。
9.3.4 关断功能
TLV906xS 器件具有 SHDN 引脚,可禁用运算放大器,将其置于低功耗待机模式。在此模式下,运算放大器消耗
的电流通常低于 1uA。SHDN 引脚为低电平有效,这意味着当 SHDN 引脚的输入为有效逻辑低电平时启用关断模
式。
SHDN 引脚以运算放大器的负电源电压为基准。关断特性的阈值约为 800mV(典型值),且不随电源电压改变。
开关阈值中包含了迟滞,以确保顺畅的开关特性。为了确保最佳的关断行为,应通过有效逻辑信号驱动 SHDN 引
脚。有效逻辑低电平是指介于 V– 和 V– + 0.2V 之间的电压。有效逻辑高电平是指介于 V– + 1.2V 和 V+ 之间的电
压。关断引脚必须连接到有效的高电压或低电压或者被驱动,而不是处于开路状态。
SHDN 引脚为高阻抗 CMOS 输入。双通道运算放大器版本是独立控制的,而四通道运算放大器版本是采用逻辑输
入成对控制的。对于电池供电的 应用,这种特性可能用于大幅降低平均电流并延长电池使用寿命。所有通道全部关
闭时,启用时间为 10µs;禁用时间为 3μs。禁用时,输出呈现高阻抗状态。该架构允许将 TLV906xS 作为门控放
大器使用(或将器件输出复用到公共模拟输出总线上)。关断时间 (tOFF) 取决于负载条件,并随负载电阻的增加而
增加。为确保在特定的关断时间内关断(禁用),需要将 10kΩ 额定负载连接到中间电源 (VS/2)。如果在没有负载
的情况下使用 TLV906xS,则所需的关断时间会显著增加。
9.4 器件功能模式
TLV906x 系列可在 1.8V (±0.9V) 和 5.5V (±2.75V) 的电源电压范围内正常工作。TLV906xS 器件具有关断模式,当
在关断引脚上施加有效逻辑低电平时可将器件关断。
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10 应用和实现
注
以下应用部分中的 信息 不属于 TI 组件规格的范围,TI 不担保其准确性和完整性。TI 的客
户应负责确定组件是否适用于其应用。客户应验证并测试其设计实现,以确认系统功能。
10.1 应用信息
TLV906x 系列器件 具有 10MHz 带宽和 6.5V/µs 压摆率,且每个通道仅有 538µA 的电源电流,从而在功耗极低的
情况下提供良好的交流性能。在直流 应用 中也具有良好性能,其输入噪声电压极低(在 10kHz 时为 10nV/√
Hz),输入偏置电流低,且典型输入失调电压为 0.3mV。
10.2 典型 应用
10.2.1 典型的低侧电流检测应用
图 37 显示了低侧电流检测应用中配置的 TLV906x。
VBUS
ZLOAD
ILOAD
5V
+
TLV906x
VOUT
Rshunt
0.1ꢀ
VSHUNT
RF
165 kꢀ
RG
3.4 kꢀ
图 37. 低侧电流检测应用中的 TLV906x
10.2.1.1 设计要求
此设计的设计要求如下:
•
•
•
负载电流:0A 至 1A
输出电压:4.95V
最大分流电压:100mV
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典型 应用 (接下页)
10.2.1.2 详细设计流程
图 37 中的传递函数如公式 1 所示
VOUT = ILOAD ìRSHUNT ìGain
(1)
负载电流 (ILOAD) 在分流电阻器 (RSHUNT) 上产生压降。负载电流设置为 0A 至 1A。为了在最大负载电流下保持分流
电压低于 100mV,公式 2 中定义了最大分流电阻。
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
根据公式 2 可知,RSHUNT 等于 100mΩ。ILOAD 和 RSHUNT 产生的压降由 TLV906x 放大,从而产生大约 0V 至
4.95V 的输出电压。根据公式 3 可计算 TLV906x 产生所需输出电压需要的增益。
V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
根据公式 3 计算出的所需增益等于 49.5V/V,通过 RF 和 RG 电阻器进行设置。公式 4 可确定 RF 和 RG 电阻器的
大小,从而将 TLV906x 的增益设置为 49.5V/V。
R
(
)
F
Gain = 1+
R
G
(4)
当 RF 选定为 165kΩ 而 RG 选定为 3.4kΩ 时,可获得大约 49.5V/V 的增益。图 38 显示了图 37 所示电路的测量传
递函数。
10.2.1.3 应用曲线
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
ILOAD (A)
C219
图 38. 低侧电流检测传递函数
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典型 应用 (接下页)
10.2.2 比较器典型应用
比较器用于区分两种不同的信号电平。例如,比较器可用于区分过压情况和正常运行状态。TLV9062 可作为比较器
使用,方法是将待比较的两个电压施加到相应的每个输入,从输出到反相输入无任何反馈。
TLV9062 具有 一个轨至轨输入和输出级,其输入共模范围超出电源轨 100mV。TLV9062 适用于在整个输入共模
范围内防止相位反转。用作比较器的
TLV9062
的传播延迟等于过载恢复时间与压摆率之和。过驱动电压低于
100mV 将导致传播延迟延长,因为过载恢复时间将增加,而压摆率将降低。
V+
R1
100kꢀ
VTH
V+
R2
100kꢀ
+
TLV9062
VOUT
VIN
图 39. 比较器典型应用
10.2.2.1 设计要求
此设计的设计要求如下:
•
•
•
电源电压 (V+):5V
输入电压 (VIN):0 – 5V
阈值电压 (VTH) = 2.5V
10.2.2.2 详细设计流程
反相比较器电路在运算放大器的反相端施加输入电压 (VIN)。两个电阻器(R1 和 R2)分摊输入电压 (VCC) 以建立
中间阈值电压 (VTH)(根据公式 1 计算得出)。具体电路如图 39 所示。当 VIN 低于 VTH 时,输出电压将切换到正
电源,并等于高电平输出电压。当 VIN 高于 VTH 时,输出电压将切换为负电源,并等于低电平输出电压。VTH
。
R2
R1 + R2
VTH
=
ì V+ = 2.5V
(5)
26
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典型 应用 (接下页)
10.2.2.3 应用曲线
5.5
5
5.5
Input
Output
Input
Output
5
4.5
4.5
4
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
0
20
40
60
80 100 120 140 160 180 200
Time (us)
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Time (us)
D101
D102
图 40. 比较器对输入电压的响应(包括传播延迟)
图 41. 上升沿
5.5
5.5
5
Input
Output
20mV
50mV
100mV
200mV
500mV
5
4.5
4.5
4
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
5
10
15
20
25
30
35
40
Time (us)
Time (us)
D103
D104
图 42. 下降沿
图 43. 下降沿传播延迟与输入过驱电压间的关系
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11 电源建议
TLV906x 系列器件的额定工作电压范围是 1.8V 至 5.5V(±0.9V 至 ±2.75V);许多规格在 –40°C 至 +125°C 的温
度下适用。典型特性 部分提供的参数可能随工作电压或温度的变化而出现显著变化。
CAUTION
电源电压超过 6V 可能会对器件造成永久损坏;请参阅绝对最大额定值 表。
将 0.1µF 旁路电容器置于电源引脚附近,以减小从高噪声电源或高阻抗电源中耦合进来的误差。有关旁路电容器位
置的更多详细信息,请参阅 部分。
11.1 输入和 ESD 保护
TLV906x 系列器件在所有引脚上均整合了内部 ESD 保护电路。对于输入和输出引脚,这种保护主要包括输入和电
源引脚之间连接的导流二极管。如绝对最大额定值 表所示,只要电流不超过 10mA,这些 ESD 保护二极管就能提
供电路内输入过驱保护。图 44 显示了如何通过将串联输入电阻器添加到被驱动的输入端来限制输入电流。添加的
电阻器会增加放大器输入端的热噪声;在对噪声敏感的应用中,该值必须保持在最低 值中,该值必须保持在最低
值。
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
图 44. 输入电流保护
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ZHCSGC0E –MARCH 2017–REVISED JULY 2018
12 布局
12.1 布局指南
为了实现器件的最佳运行性能,应使用良好的印刷电路板 (PCB) 布局规范,包括:
•
噪声可以通过整个电路的电源引脚和运算放大器本身的电源引脚传入模拟电路。旁路电容为局部模拟电路提供
低阻抗电源,用于降低耦合噪声。
–
在每个电源引脚和接地端之间连接低 ESR 0.1µF 陶瓷旁路电容器,放置位置尽量靠近器件。从 V+ 到接地端
的单个旁路电容器适用于单通道电源 应用。
•
将电路的模拟和数字部分单独接地是最简单和最有效的噪声抑制方法之一。多层 PCB 中通常将一层或多层专门
作为接地层。接地层有助于散热和降低电磁干扰 (EMI) 噪声拾取。请小心地对数字接地和模拟接地进行物理隔
离,同时应注意接地电流。有关更多详细信息,请参阅《电路板布局技巧》。
•
•
为降低寄生耦合,输入迹线应尽量远离电源或输出迹线。如果这些走线不能保持分离,则敏感走线与有噪声走
线垂直相交比平行更好。
外部组件的位置应尽量靠近器件。如图 46 所示,使 RF 和 RG 接近反相输入可最大限度地减小反相输入端的寄
生电容。
•
•
•
•
尽可能缩短输入迹线。切记:输入走线是电路中最敏感的部分。
考虑在关键走线周围设定驱动型低阻抗保护环。这样可显著减少附近走线在不同电势下产生的泄漏电流。
为获得最佳性能,建议在组装 PCB 板后进行清洗。
任何精密集成电路都可能因湿气渗入塑料封装中而出现性能变化。请遵循所有的 PCB 水清洁流程,建议将
PCB 组装烘干,以去除清洗时渗入器件封装中的湿气。大多数情形下,清洗后在 85°C 下低温烘干 30 分钟即
可。
版权 © 2017–2018, Texas Instruments Incorporated
29
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
www.ti.com.cn
12.2 布局示例
VIN A
VIN B
+
+
VOUT A
VOUT B
RG
RG
RF
RF
图 45. 图 46 的原理图表示
Place components
close to device and to
each other to reduce
parasitic errors.
OUT A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
VS+
GND
OUT A
V+
RF
OUT B
GND
-IN A
+IN A
Vœ
OUT B
-IN B
RF
RG
GND
VIN B
VIN A
RG
+IN B
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor. Place as
close to the device
as possible.
VSœ
Ground (GND) plane on another layer
as possible.
图 46. 布局示例
30
版权 © 2017–2018, Texas Instruments Incorporated
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
www.ti.com.cn
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
德州仪器 (TI),《适用于成本敏感型系统的 TLVx313 低功耗、轨至轨输入/输出、500μV 典型失调电压、1MHz 运
算放大器》。
德州仪器 (TI),《TLVx314 3MHz、低功耗、内置 EMI 滤波器、RRIO 运算放大器》。
德州仪器 (TI),《运算放大器的 EMI 抑制比》。
德州仪器 (TI),《QFN/SON PCB 连接》。
Texas Instruments, 《四方扁平封装无引线逻辑封装》。
德州仪器 (TI),《电路板布局技巧》。
德州仪器 (TI),《单端输入至差分输出转换电路参考设计》。
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件,以及立即订购快速访问。
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
TLV9061
TLV9062S
TLV9062
TLV9064
TLV9064S
13.3 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
版权 © 2017–2018, Texas Instruments Incorporated
31
TLV9061, TLV9062S, TLV9062, TLV9064, TLV9064S
ZHCSGC0E –MARCH 2017–REVISED JULY 2018
www.ti.com.cn
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
32
版权 © 2017–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV9061IDBVR
TLV9061IDCKR
TLV9061IDPWR
TLV9061SIDBVR
TLV9062IDDFR
TLV9062IDGKR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DPW
DBV
DDF
DGK
5
5
5
6
8
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1OAF
1CA
Samples
Samples
Samples
Samples
Samples
Samples
SN
X2SON
SOT-23
NIPDAUAG
NIPDAU
NIPDAU
CG
1OEF
T062
T062
ACTIVE SOT-23-THIN
ACTIVE
ACTIVE
VSSOP
VSSOP
NIPDAU | SN
| NIPDAUAG
TLV9062IDGKT
DGK
8
250
RoHS & Green
NIPDAU | SN
| NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T062
Samples
TLV9062IDR
TLV9062IDSGR
TLV9062IDSGT
TLV9062IPWR
TLV9062SIDGSR
TLV9062SIRUGR
TLV9064IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
WSON
WSON
TSSOP
VSSOP
X2QFN
SOIC
D
8
2500 RoHS & Green
3000 RoHS & Green
NIPDAU | SN
NIPDAU
NIPDAU
NIPDAU | SN
NIPDAUAG
NIPDAUAG
NIPDAU
SN
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TL9062
T062
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
DSG
DSG
PW
8
8
250
RoHS & Green
T062
8
2000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
TL9062
1TDX
DGS
RUG
D
10
10
14
14
14
16
14
16
EOF
TLV9064D
TLV9064
TLV9064
T9064
1DD
TLV9064IPWR
TLV9064IPWT
TLV9064IRTER
TLV9064IRUCR
TLV9064SIRTER
TSSOP
TSSOP
WQFN
QFN
PW
PW
250
RoHS & Green
SN
RTE
RUC
RTE
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
WQFN
T9064S
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2023
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV9061, TLV9062, TLV9064 :
Automotive : TLV9061-Q1, TLV9062-Q1, TLV9064-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9061IDBVR
TLV9061IDBVR
TLV9061IDCKR
TLV9061IDPWR
TLV9061SIDBVR
TLV9062IDDFR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DPW
DBV
DDF
5
5
5
5
6
8
3000
3000
3000
3000
3000
3000
180.0
180.0
178.0
178.0
180.0
180.0
8.4
8.4
9.0
8.4
8.4
8.4
3.2
3.2
2.4
0.91
3.2
3.2
3.2
3.2
2.5
0.91
3.2
3.2
1.4
1.4
1.2
0.5
1.4
1.4
4.0
4.0
4.0
2.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q2
Q3
Q3
X2SON
SOT-23
SOT-23-
THIN
TLV9062IDGKR
TLV9062IDGKR
TLV9062IDGKT
TLV9062IDGKT
TLV9062IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
2500
2500
250
330.0
330.0
330.0
330.0
330.0
180.0
180.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
8.4
5.3
5.3
5.3
5.3
6.4
2.3
2.3
7.0
5.3
3.4
3.4
3.4
3.4
5.2
2.3
2.3
3.6
3.4
1.4
1.4
8.0
8.0
8.0
8.0
8.0
4.0
4.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
Q1
Q2
Q2
Q1
Q1
8
1.4
8
250
1.4
8
2500
3000
250
2.1
TLV9062IDSGR
TLV9062IDSGT
TLV9062IPWR
TLV9062SIDGSR
WSON
WSON
TSSOP
VSSOP
DSG
DSG
PW
8
1.15
1.15
1.6
8
8.4
8.0
8
2000
2500
12.4
12.4
12.0
12.0
DGS
10
1.4
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9062SIRUGR
TLV9064IDR
X2QFN
SOIC
RUG
D
10
14
14
14
16
14
16
3000
2500
2000
250
178.0
330.0
330.0
330.0
330.0
180.0
330.0
8.4
16.4
12.4
12.4
12.4
9.5
1.75
6.5
2.25
9.0
0.56
2.1
1.6
1.6
1.1
0.5
1.1
4.0
8.0
8.0
8.0
8.0
4.0
8.0
8.0
16.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
Q2
Q2
Q2
TLV9064IPWR
TLV9064IPWT
TLV9064IRTER
TLV9064IRUCR
TLV9064SIRTER
TSSOP
TSSOP
WQFN
QFN
PW
PW
RTE
RUC
RTE
6.9
5.6
6.9
5.6
3000
3000
3000
3.3
3.3
2.16
3.3
2.16
3.3
WQFN
12.4
12.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV9061IDBVR
TLV9061IDBVR
TLV9061IDCKR
TLV9061IDPWR
TLV9061SIDBVR
TLV9062IDDFR
TLV9062IDGKR
TLV9062IDGKR
TLV9062IDGKT
TLV9062IDGKT
TLV9062IDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DPW
DBV
DDF
DGK
DGK
DGK
DGK
D
5
5
3000
3000
3000
3000
3000
3000
2500
2500
250
210.0
210.0
190.0
205.0
210.0
210.0
366.0
366.0
366.0
366.0
356.0
210.0
210.0
356.0
366.0
205.0
356.0
366.0
185.0
185.0
190.0
200.0
185.0
185.0
364.0
364.0
364.0
364.0
356.0
185.0
185.0
356.0
364.0
200.0
356.0
364.0
35.0
35.0
30.0
33.0
35.0
35.0
50.0
50.0
50.0
50.0
35.0
35.0
35.0
35.0
50.0
33.0
35.0
50.0
5
X2SON
SOT-23
SOT-23-THIN
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
5
6
8
8
8
8
8
250
8
2500
3000
250
TLV9062IDSGR
TLV9062IDSGT
TLV9062IPWR
TLV9062SIDGSR
TLV9062SIRUGR
TLV9064IDR
WSON
DSG
DSG
PW
8
WSON
8
TSSOP
VSSOP
X2QFN
SOIC
8
2000
2500
3000
2500
2000
DGS
RUG
D
10
10
14
14
TLV9064IPWR
TSSOP
PW
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV9064IPWT
TLV9064IRTER
TLV9064IRUCR
TLV9064SIRTER
TSSOP
WQFN
QFN
PW
RTE
RUC
RTE
14
16
14
16
250
366.0
367.0
205.0
367.0
364.0
367.0
200.0
367.0
50.0
35.0
30.0
35.0
3000
3000
3000
WQFN
Pack Materials-Page 4
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.324)
4X (0.05)
0.25 0.1
2
1
4
5
NOTE 3
2X
3
2X (0.26)
0.48
0.27
0.17
4X
0.239
0.139
0.1
C A B
C
0.288
0.188
3X
0.05
4223102/D 03/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
(
0.1)
SYMM
4X (0.42)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
(0.21) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/D 03/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
5
1
4X (0.22)
SYMM
(
0.24)
4X (0.26)
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
3
2
4
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 3
92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:100X
4223102/D 03/2022
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RUC0014A
A
2.1
1.9
B
2.1
1.9
PIN 1 INDEX AREA
0.4 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
(0.15) TYP
2X 0.4
6
7
8X 0.4
5
8
SYMM
1.6
12
1
0.25
0.15
14
13
14X
0.5
PIN 1 ID
SYMM
(45oX0.1)
0.1
C A B
C
14X
0.3
0.05
4220584/A 05/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RUC0014A
SYMM
14X (0.6)
14X (0.2)
8X (0.4)
SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 23X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220584/A 05/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
X2QFN - 0.4 mm max height
RUC0014A
PLASTIC QUAD FLAT PACK- NO LEAD
SYMM
14X (0.6)
14X (0.2)
8X (0.4)
SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)
SOLDER PASTE EXAMPLE
BASED ON 0.100mm THICK STENCIL
SCALE: 23X
4220584/A 05/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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