TLV810EA29DPWR [TI]

具有高电平有效推挽复位功能的低功耗 3 引脚电压监控器（复位 IC） | DPW | 5 | -40 to 125;


型号：	TLV810EA29DPWR
厂家：	TEXAS INSTRUMENTS
描述：	具有高电平有效推挽复位功能的低功耗 3 引脚电压监控器（复位 IC） \| DPW \| 5 \| -40 to 125 监控
文件：	总49页 (文件大小：2289K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV803E, TLV809E, TLV810E

ZHCSJX8J –AUGUST 2018 –REVISED MAY 2021

TLV803E、TLV809E、TLV810E 低功耗250nA I_Q和小尺寸电源电压监控器

1 特性

3 说明

• 当VDD = 0.7-6V 时，确保执行RESET/RESET

• 固定延时时间：40µs、10ms、50ms、100ms、

200ms、400ms

• 电源电流(IDD)：250nA（典型值）

– 1µA（VDD = 3.3V 时的最大值）

• 输出拓扑：

– TLV809E：推挽，低电平有效

– TLV803E：开漏，低电平有效

– TLV810E：推挽，高电平有效

• 欠压检测：

TLV803E 、TLV809E 和 TLV810E 是 TLV803 、

TLV853、TLV809、LM809、TPS3809 和 TLV810 的

增强替代品。TLV80xE 和 TLV81xE 具有静态电流 I_Q

低、精度高、温度范围宽和上电复位 (V_POR) 低等优

势，能够提高系统可靠性。

TLV80xE 和 TLV81xE 系列是具有低 I_Q（250nA 典型

值、1µA 最大值）的电压监控电路（复位 IC），可监

控 VDD 电压电平。每当电源电压 VDD 下降到出厂编

程下降阈值电压 V_IT-以下时，这些器件都会启动一个

复位信号。VDD 电压升至上升电压阈值 (V_IT+)（等于

下降电压阈值(V_IT-) 与迟滞电压

– 高准确度：±0.5%（典型值）

– (V_IT–)：1.7V、1.8V、1.9V、2.25V、2.4V、

(V_HYS) 之和）以上后，在固定复位延时时间 t_D内，复

位输出都会保持低电平。

2.64V、

2.93V、3.08V、3.3V、4.2V、4.38V、4.55V、

4.63V

• 封装：

这些器件具有集成的毛刺抑制功能，可忽略 VDD 引脚

上的快速瞬变。这些电压监控器的 I_Q低，且精度高

（典型值为 ±0.5%），非常适合低功耗和便携式应

用。对于低至 V_POR= 0.7V 的电源电压，TLV80xE 和

TLV81xE 器件具有指定输出逻辑状态。TLV80xE 和

TLV81xE 器件可采用业界通用的 3 引脚 SOT23 (DBZ)

和 SC70 (DCK) 封装以及超紧凑 X2SON (DPW) 封

装。

– SOT23-3 (DBZ)（引脚1 = GND）

– SOT23-3 (DBZ)（带引脚1 = RESET/RESET）

– SOT23-3 (DBZ)（引脚3 = GND）

– SC-70 (DCK)

– X2SON-5 (DPW)

• 温度范围：–40°C 至+125°C

• 与MAX803/809/810、APX803/809/810 引脚对引

脚兼容

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

封装

SOT-23 (3)

SC-70 (3)

X2SON (5)

2.90mm × 1.30mm

2.00mm × 1.25mm

0.8mm x 0.8mm

2 应用

TLV803E、

TLV809E、TLV810E

• 电表

• 工厂自动化

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 便携式、电池供电类设备

• 机顶盒和电视

• 楼宇自动化

• 笔记本电脑/台式机、服务器

*R_pull-up

VDD

FPGA, ASIC, DSP

LDO

TLV803E

OUT

RESET

VDD

GND

*Pull-up resistor not required for TLV809E, TLV810E

典型应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSES2

TLV803E, TLV809E, TLV810E

ZHCSJX8J –AUGUST 2018 –REVISED MAY 2021

www.ti.com.cn

Table of Contents

8.4 Device Functional Modes..........................................19

9 Application and Implementation..................................20

9.1 Application Information............................................. 20

9.2 Typical Application - Voltage Rail Monitoring............20

9.3 Typical Application - Overvoltage Monitoring............22

10 Power Supply Recommendations..............................23

11 Layout...........................................................................24

11.1 Layout Guidelines................................................... 24

11.2 Layout Example...................................................... 24

12 Device and Documentation Support..........................26

12.1 Device Support....................................................... 26

12.2 Documentation Support.......................................... 27

12.3 接收文档更新通知................................................... 27

12.4 支持资源..................................................................27

12.5 Trademarks.............................................................27

12.6 Electrostatic Discharge Caution..............................27

12.7 术语表..................................................................... 27

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison.........................................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings ....................................... 6

7.2 ESD Ratings .............................................................. 6

7.3 Recommended Operating Conditions ........................6

7.4 Thermal Information ...................................................7

7.5 Electrical Characteristics ............................................8

7.6 Timing Requirements .................................................9

7.7 Timing Diagrams.......................................................10

7.8 Typical Characteristics.............................................. 11

8 Detailed Description......................................................16

8.1 Overview...................................................................16

8.2 Functional Block Diagram.........................................16

8.3 Feature Description...................................................16

Information.................................................................... 27

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision I (Feb 2021) to Revision J (May 2021)

Page

• Updated Device Naming Nomenclature figure by adding Pinout Indicator (DBZ Package Only) from Pinout

Indicator .............................................................................................................................................................3

• Updated pin numbering of Figure 6-5 (X2SON) package and updated Pin Functions Table............................. 4

• Updated X2SON (DPW) Layout Example........................................................................................................ 24

Changes from Revision H (December 2020) to Revision I (February 2021)

Page

• Remove duplicate package.............................................................................................................................. 27

Changes from Revision G (October 2020) to Revision H (December 2020)

Page

• Added Reset time delay variant F specification..................................................................................................9

Changes from Revision F (June 2020) to Revision G (October 2020)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1

• 添加了附加阈值电压(V_IT-) 和新封装的信息........................................................................................................ 1

• Updated Device Naming Nomenclature figure to include (DBZ) V pinout option .............................................. 3

• Added new (DBZ) package option (Pin 3 = GND, V pinout) and updated Pin Functions Table..........................4

• Added layout example for (DBZ) V pinout package..........................................................................................24

• Modified Device Naming Convention table to include additional threshold voltages (V_IT-), reset time delay

options and pinout indicator options................................................................................................................. 26

Changes from Revision E (April 2020) to Revision F (June 2020)

Page

• 将DPW 封装从“预告信息”更改为“量产数据”.............................................................................................1

• Changed DPW package Information ................................................................................................................. 4

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Changes from Revision D (February 2020) to Revision E (April 2020)

Page

• Added X2SON (DPW) package option ..............................................................................................................3

Changes from Revision C (November 2019) to Revision D (February 2020) Page

• Added device nomenclature figure .................................................................................................................... 3

• Added timing diagram for TLV810E .................................................................................................................10

• Added Figure 6, Figure 23, Figure 24 ..............................................................................................................11

• Added typical application for TLV810E ............................................................................................................22

Changes from Revision B (July 2019) to Revision C (November 2019)

Page

• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1

5 Device Comparison

图5-1 shows the device naming nomenclature to compare the difference device variants. See 表12-1 for a more

detailed explanation.

TLV XXXX X XX X XXX

OUTPUT TYPE

DELAY OPTIONS

THRESHOLD VOLTAGE

PINOUT INDICATOR (DBZ PACKAGE ONLY) Package

803E: Open-Drain Ac ve-Low A: 200 ms

17: 1.7 V

...

46: 4.63 V

R: Pin 1 = RESET, Pin 2 = GND

V: Pin 1 = RESET, Pin 3 = GND

DBZ: SOT23

DCK: SC70

DPW: X2SON

809E: Push-Pull Ac ve-Low

810E: Push-Pull Ac ve-High

B: 40 µs

C: 10 ms

D: 50 ms

E: 100 ms

F: 400 ms

图5-1. Device Naming Nomenclature

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6 Pin Configuration and Functions

GND

VDD

RESET

(TLV810E)

图6-2. DCK Package

3-Pin SC-70

图6-1. DBZ Package

(Pin 1 = GND)

3-Pin SOT-23

Top View

RESET

VDD

GND

图6-3. DBZ Package

(Pin 1 = RESET, R pinout)

3-Pin SOT-23

图6-4. DBZ Package

(Pin 3 = GND, V pinout)

3-Pin SOT-23

Top View

RESET

VDD

RESET

(TLV810E)

PAD

GND

Top View

图6-5. DPW Package

5-Pin X2SON

See 表6-1

Top View

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表6-1. Pin Functions

I/O

DESCRIPTION

DBZ

(V PINOUT)

DBZ

(R PINOUT)

NAME

DCK, DBZ

DPW

GND

Ground

—

Active-low output reset signal: This pin is driven

low logic when VDD voltage falls below the negative

voltage threshold (V_IT–). RESET remains low

(asserted) for the delay time period (t_D) after VDD

voltage rise above V_IT+.

RESET

Active-High output reset signal (TLV810E only):

This pin is driven high logic when VDD voltage falls

below the negative voltage threshold (V_IT–). RESET

remains high (asserted) for the delay time period (t_D)

after VDD voltage rise above V_IT+.

RESET

VDD

Input supply voltage. TLV803E, TLV809E,

TLV810E monitor VDD voltage.

Active-low manual reset input. Pull this pin to a

logic low (V_{MR_L}) to assert a reset signal in the output

pin. After the MR pin is left floating or pulled to V_{MR_H}

the output goes to the nominal state after the reset

delay time (t_D) expires. MR can be left floating when

not in use.

N/A

No Connection. Thermal pad helps with thermal

dissipation. PAD does not need to be soldered down.

PAD can be connected to GND.

PAD

—

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted⁽¹⁾

MIN

–0.3

-20

MAX

UNIT

VDD pin

6.5

V_DD+ 0.3 ⁽²⁾

6.5

Voltage

RESET (TLV809E), RESET (TLV810E)

RESET (TLV803E)

Voltage

Current

V_DD+ 0.3⁽²⁾

Output sink and source current

Operating ambient, T_A

Storage, T_stg

125

–40

–65

Temperature⁽³⁾

°C

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions (above the Recommended Operating

Conditions) for extended periods may affect device reliability.

(2) The absolute maximum rating is (V_DD+ 0.3) V or 6.5 V, whichever is smaller.

(3) As a result of the low dissipated power in this device, the junction temperature is assumed to be equal to the ambient temperature.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001⁽¹⁾

± 2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101⁽²⁾

± 500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.7

NOM

MAX

UNIT

V_DD

Input supply voltage

V_RESET, V_RESET

RESET pin and RESET pin voltage

RESET pin and RESET pin current

Junction temperature (free air temperature)

Manual reset pin voltage

I_RESET, I_RESET

±5

°C

T_J

125

V_DD

–40

V_MR

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7.4 Thermal Information

TLV803E, TLV809E, TLV810E

THERMAL METRIC⁽¹⁾

DPW (X2SON)

5 PINS

457.1

DCK (SC70-3)

3 PINS

300.5

DBZ (SOT23-3)

3 PINS

254.8

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

201.6

178.2

150.5

R_θJB

ψ_JT

Junction-to-board thermal resistance

320.4

166.5

140.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

22.8

48.1

318.8

165.2

139.1

ψ_JB

R_θJC(bot)Junction-to-case (bottom) thermal resistance

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.5 Electrical Characteristics

over operating range (T_A= –40℃to 125℃), 1.7 V ≤V_DD≤6 V, R_pull-up= 10 kΩto 6 V, 10 pF load at RESET pin, unless

otherwise noted. Typical values are at 25℃, V_DD= 3.3V and V_IT–= 2.93 V.

PARAMETER

COMMON PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_DD

Input supply voltage

1.7

–2

0.9

V_IT–

V_HYS

Input threshold voltage accuracy

Hysteresis voltage

0.5

1.2

T_A= –40℃to 125℃

Hysteresis from V_IT–

V_DD= 3.3 V; V_DD> V_IT+

V_DD= 6 V

1.5

(1)

0.25

0.4

µA

I_DD

Supply current into VDD pin

1.2

Manual reset pin internal pull-up

resistance

R_MR

100

kΩ

X2SON (DPW) package only

V_{MR_L}

V_{MR_H}

Manual reset pin logic low input

Manual reset pin logic high input

0.4

0.8V_DD

TLV809E (Push-Pull Active-Low)

V_POR

Power on reset voltage ⁽²⁾

700

300

V_OL≤300 mV, I_OUT(Sink)= 15 µA

V_DD= 1.7 V, V_DD< V_IT–, I_OUT(Sink)= 500 µA

V_DD= 3.3 V, V_DD< V_IT–, I_OUT(Sink)= 2 mA

V_DD= 6 V, V_DD> V_IT+, I_OUT(Source)= 4 mA

V_DD= 3.3 V, V_DD> V_IT+, I_OUT(Source)= 2 mA

Low level output voltage

V_OL

0.8V_DD

High level output voltage

V_OH

TLV803E (Open-Drain Active-Low)

V_POR

Power on reset voltage ⁽²⁾

700

300

350

V_OL≤300 mV, I_OUT(Sink)= 15 µA

V_DD= 1.7 V, V_DD< V_IT–, I_OUT(Sink)= 500 µA

V_DD= 3.3 V, V_DD< V_IT–, I_OUT(Sink)= 2 mA

V_DD= V_PULLUP= 6 V, V_DD> V_IT+

Low level output voltage

V_OL

I_lkg(OD)

Open drain output leakage current

100

TLV810E (Push-Pull Active-High)

V_DD= 3.3 V, V_DD< V_IT–, I_OUT(Source)= 2 mA

V_DD= 1.7 V, V_DD< V_IT–, I_OUT(Source)= 500 µA

0.8V_DD

High level output voltage

V_OH

V_POR

V_OL

Power on Reset Voltage

Low level output voltage

900

300

_OH≥720 mV, I_OUT(Source)= 15 µA

V_DD= 6 V, V_DD> V_IT+, I_OUT(Sink)= 2 mA

V_DD= 3.3 V, V_DD> V_IT+, I_OUT(Sink)= 500 µA

(1) V_IT+= V_IT–+ V_HYS

(2) Minimum V_DDvoltage for a controlled output state. Below V_POR, the output cannot be determined.

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7.6 Timing Requirements

over operating range (T_A= –40℃to 125℃), 1.7 V ≤V_DD≤6 V, R_pull-up= 10 kΩto 6 V (Open Drain only), 10 pF load at

RESET pin, Overdrive = 10%, unless otherwise noted. Typical values are at 25℃, V_DD= 3.3 V and V_IT–= 2.93 V.

PARAMETER

TEST CONDITIONS

5 % Overdrive⁽¹⁾

MIN

TYP

MAX

UNIT

t_GI

Glitch immunity

µs

Propagation delay from VDD falling below

V_IT–to RESET

V_DD= (V_IT++ 30%) to (V_IT–

10%)

–

t_{PD_HL}

µs

Reset time delay variant A ⁽²⁾

130

200

270

Reset time delay variant B ⁽²⁾

;

R_UP= 100 kΩ, C_L= 100 pF, 30%

µs

Overdrive ⁽³⁾

Reset time delay variant B ⁽²⁾

Reset time delay variant C ⁽²⁾

µs

t_D

Release time or reset timeout period

6.5

13.5

Reset time delay variant D ⁽²⁾

Reset time delay variant F ⁽²⁾

400

260

540

MR pin pulse duration to initiate RESET,

RESET

(4)

t_{MR_PW}

500

Propagation delay from MR low to RESET,

RESET

V_DD= 4.5 V, V_MR: V_{MR_H}to

V_{MR_L}

(4)

t_{MR_RES}

700

Delay from release MR to deasert RESET,

RESET

V_DD= 4.5 V, V_MR: V_{MR_L}to

V_{MR_H}

(4)

t_{MR_tD}

t_D__MIN

t_D__TYP

t_D__MAX

(1) Overdrive = [(V_DD/ V_IT–) - 1] × 100%. Refer to section on VDD glitch immunity

(2) Refer to Device nomenclature table. VDD: (V_IT--10%) to (V_IT++ 10%)

(3) Specified by design

(4) X2SON Package only

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7.7 Timing Diagrams

V_IT+

V_IT-

V_HYS

V_DD(MIN)

V_POR

VDD

t_{PD_HL}

t_D

RESET

Undefined output VDD < V_POR

Diagram not to scale

图7-1. TLV803E, TLV809E Timing Diagram

V_IT+

V_IT-

V_HYS

V_DD(MIN)

V_POR

VDD

t_{PD_HL}

t_D

RESET

Undefined output VDD < V_POR

Diagram not to scale

图7-2. TLV810E Timing Diagram

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7.8 Typical Characteristics

Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are

T_A= 25°C, VDD = 3.3 V, V_IT-= 2.93 V, R_pull-up= 10 kΩ to 6 V, C_Load= 50 pF, unless otherwise noted.

0.45

0.4

0.5

0.45

0.4

25°C

-40°C

125°C

25°C

-40°C

125°C

0.35

0.3

0.35

0.3

0.25

0.2

0.25

0.2

0.15

0.1

0.15

0.1

1.5

2.5

3.5 4

V_DD(V)

4.5

5.5

1.5

2.5

3.5 4

V_DD(V)

4.5

5.5

IDD_

图7-3. Supply Current Versus Supply Voltage for TLV803EA29

图7-4. Supply Current Versus Supply Voltage for TLV809EA29

0.45

0.32

25°C

-40°C

125°C

TLV803EA29

0.31

0.4

0.35

0.3

0.29

0.28

0.27

0.26

0.25

0.24

0.23

0.22

0.21

0.2

0.25

0.2

0.15

0.1

0.05

1.5

2.5

3.5 4

V_DD(V)

4.5

5.5

-40

-20

40 60

Temperature (°C)

100 120 140

IDDv

IDD_

图7-5. Supply Current Versus Supply Voltage for TLV810EA29

图7-6. Supply Current Verses Temperature for TLV803EA29,

VDD = 3.3 V

0.32

TLV803EA29

TLV809EA29

0.31

0.3

0.29

0.28

0.27

0.26

0.25

0.24

0.23

0.22

0.21

0.2

-40

-20

40 60

Temperature (°C)

100 120 140

-20

40 60

Temperature (°C)

100 120 140

IDD_

ILKG

图7-7. Supply Current Verses Temperature for TLV809EA29,

图7-8. Leakage Current Verses Temperature for TLV803EA29

VDD = 3.3 V

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7.8 Typical Characteristics (continued)

Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are

T_A= 25°C, VDD = 3.3 V, V_IT-= 2.93 V, R_pull-up= 10 kΩ to 6 V, C_Load= 50 pF, unless otherwise noted.

0.92

0.84

0.76

0.68

0.6

1.3

1.2

1.1

TLV803EA29

TLV809EA29

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.52

0.44

0.36

0.28

0.2

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

VIT-

图7-9. Voltage Threshold Accuracy Verses Temperature for

图7-10. Voltage Threshold Accuracy Verses Temperature for

TLV803EA29

TLV809EA29

0.8

0.55

-40°C

-20°C

-40°C

-20°C

0.5

0.72

85°C

105°C

125°C

85°C

105°C

125°C

0.45

0.4

0.64

0.56

0.48

0.4

0.35

0.3

0.25

0.2

0.32

0.24

0.16

0.08

0.15

0.1

0.05

0.002

0.004

0.006

0.008

0.01

0.002

0.004

0.006

0.008

0.01

I_RESET(A)

VOLx

图7-11. Low Voltage Output Versus Output Current for

图7-12. Low Voltage Output Versus Output Current for

TLV803EA29, VDD = 1.7 V

TLV809EA29, VDD = 1.7 V

TLV803EA29

24.5

TLV809EA29

24.5

23.5

22.5

21.5

-40

-20

100 120 140

-40

-20

100 120 140

Temperature (èC)

VOLx

图7-13. Low Voltage Output Verses Temperature for

图7-14. Low Voltage Output Verses Temperature for

TLV803EA29, VDD = 1.7 V

TLV809EA29, VDD = 1.7 V

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7.8 Typical Characteristics (continued)

Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are

T_A= 25°C, VDD = 3.3 V, V_IT-= 2.93 V, R_pull-up= 10 kΩ to 6 V, C_Load= 50 pF, unless otherwise noted.

5.9

5.8

5.7

5.6

5.5

5.4

5.3

5.2

5.1

3.12

3.115

3.11

-40°C

-20°C

25°C

85°C

105°C

125°C

TLV809EA29

3.105

3.1

3.095

3.09

3.085

3.08

3.075

3.07

3.065

-40

-20

100 120 140

0.002

0.004

0.006

0.008

0.01

Temperature (èC)

VOHx

I_RESET(A)

VOHx

图7-16. High Voltage Output Verses Temperature for

图7-15. High Voltage Output Versus Output Current for

TLV809EA29, VDD = 3.3 V

TLV809EA29, VDD = 6 V

0.12

TLV803EA29

25°C

5.5

4.5

0.1

0.08

0.06

0.04

0.02

3.5

2.5

1.5

0.5

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

V_DD(V)

0.5

1.5

2.5

V_DD(V)

3.5

4.5

5.5

Vpor

VCC_

图7-17. Reset Voltage Output Versus Voltage Input for

TLV803EA29, V_pull-up= VDD, R_pull-up= 10 kΩ

图7-18. Reset Voltage Output Versus Voltage Input for

TLV803EA29, R_pull-up= 10 kΩ

173

TLV803EA29

VDD

RESET

172

171

170

169

168

167

1.6

1.2

0.8

0.4

-40

-20

40 60

Temperature (°C)

100 120 140

Time (µs)

Rese

VRES

图7-20. Reset Delay Time Verses Temperature for TLV803EA29

图7-19. Transient Power-on-Reset Voltage for TLV809EA30,

I_RESET= 15 µA

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7.8 Typical Characteristics (continued)

Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are

T_A= 25°C, VDD = 3.3 V, V_IT-= 2.93 V, R_pull-up= 10 kΩ to 6 V, C_Load= 50 pF, unless otherwise noted.

16.25

171.5

TLV803EB29

TLV809EA29

16.2

16.15

16.1

171

170.5

170

16.05

169.5

169

15.95

15.9

168.5

168

15.85

15.8

167.5

167

15.75

15.7

166.5

15.65

15.6

166

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

tD__

Rese

图7-21. Reset Delay Time Verses Temperature for TLV809EA29

图7-22. Reset Delay Time Verses Temperature for TLV803EB29

TLV803EC29

TLV803EA29

24.75

8.8

8.6

8.4

8.2

24.5

24.25

23.75

23.5

23.25

22.75

22.5

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

tPHL

Rese

图7-24. High-to-Low Propagation Delay Verses Temperature for

图7-23. Reset Delay Time Verses Temperature for TLV803EC29

TLV803EA29

TLV809EA29

25°C

-40°C

125°C

25.5

24.5

23.5

22.5

-40

-20

40 60

Temperature (°C)

100 120 140

25 30

Overdrive (%)

tPHL

tGI_

图7-25. High-to-Low Propagation Delay Verses Temperature for

图7-26. Glitch Immunity Versus Overdrive for TLV803EA29

TLV809EA29

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7.8 Typical Characteristics (continued)

Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are

T_A= 25°C, VDD = 3.3 V, V_IT-= 2.93 V, R_pull-up= 10 kΩ to 6 V, C_Load= 50 pF, unless otherwise noted.

25°C

-40°C

125°C

25 30

Overdrive (%)

tGI_

图7-27. Glitch Immunity Versus Overdrive for TLV809EA29

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8 Detailed Description

8.1 Overview

The TLV803E, TLV809E, TLV810E is a family of easy to implement low power, small size voltage supervisors

(Reset ICs) with fixed threshold voltage and fixed reset delay. The TLV803E has open-drain active-low output

topology which requires an external pull-up resistor, TLV809E has push-pull active-low output topology and

TLV810E has push-pull active-high output topology. This family of devices features include integrated resistor

divider threshold with hysteresis and a glitch immunity filter.

These devices are available in SOT-23 (3) and SC70 (3) industry standard package and pinout as well as a very

small X2SON (5) package.

8.2 Functional Block Diagram

VDD

R_MR

Push-pull TLV809E,

TLV810E variants

DPW package only

VDD

RESET

LOGIC

TIMER

(TLV803E, TLV809E)

RESET (TLV810E)

RESET

Reference

Voltage

GND

8.3 Feature Description

8.3.1 Input Voltage (VDD)

VDD pin is monitored by the internal comparator with integrated reference to indicate when VDD falls below the

fixed threshold voltage. VDD also functions as the supply for the following:

• Internal bandgap (reference voltage)

• Internal regulator

• State machine

• Buffers

• Other control logic blocks

Good design practice involves placing a 0.1-µF to 1-µF bypass capacitor at VDD input for noisy applications and

to ensure enough charge is available for the device to power up correctly. The reset output is undefined when

VDD is below V_POR

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8.3.2 VDD Hysteresis

The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD

pin falls below the falling voltage threshold V_IT–, the output reset is asserted. When the voltage at the VDD pin

rises above the rising voltage threshold (V_IT+) equivalent to V_IT–plus hysteresis (V_HYS), the output reset is

deasserted after t_Dreset time delay.

8.3.3 VDD Glitch Immunity

These devices are immune to quick voltage transient or excursion on VDD. Sensitivity to transients depends on

both pulse duration (t_GI) found in 节7.6 and transient overdrive. Overdrive is defined by how much VDD exceeds

the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as shown in

方程式1.

Overdrive = | (VDD / (V_IT––1)) × 100% |

(1)

where

• V_IT–is the threshold voltage

• VDD is the input voltage crossing V_IT–

VDD

V_IT+

V_IT-

Overdrive

Pulse

Duration

图8-1. Overdrive Versus Pulse Duration

TLV803E, TLV809E, and TLV810E devices have built-in glitch immunity (t_GI) of 10 µs typical as shown in

节 7.6. 图 8-2 shows that VDD must fall below V_IT-for t_GI, otherwise the faling transistion is ignored. When VDD

falls below V_IT-for t_GI, RESET transitions low to indicate a fault condition after the propagation delay high-to-low

(t_PDHL). When VDD rises above V_IT+, RESET only deasserts to logic high indicating there is no more fault

condition only if VDD remains above V_IT+for longer than the reset delay (t_D).

VDD remains above VIT+ for only 199 ms

VDD

VIT+

VIT-

VDD drops below VIT- so

RESET transitions low after

Propagation Delay (t_PDHL

)

RESET

VDD transition to above VIT+ ignored when less than

Reset Delay (t_D) so RESET remains unchanged

图8-2. Glitch Immunity when VDD Rises Above V_IT+for Less than RESET Delay (TLV803EA29)

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8.3.4 Manual Reset (MR) Input for X2SON (DPW) Package Only

The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR

with pulse duration longer than t_{MR_RES}will cause reset output to assert. After MR returns to a logic high

(V_{MR_H}) and VDD is above V_IT+, reset is deasserted after the user programmed reset time delay (t_D) expires.

If MR is not controlled externally, then MR can be left disconnected. MR is internally connected to VDD through a

pull-up resistor R_MRshown in 节 8.2. If the logic signal controlling MR is less than VDD, then additional current

flows from VDD into MR internally. For minimum current consumption, drive MR to either VDD or GND.

V_MRshould not be higher than VDD voltage.

V_IT+

V_HYS

V_IT-

V_IT+

V_HYS

V_IT-

VDD

t_{P_HL}

t_D

t_{MR_tD}

RESET

(2)

t_{MR_RES}

V_{MR_H}

V_{MR_L}

(1)

t_{MR_PW}

Time

(1) MR pulse width too small to assert RESET

(2) MR voltage not low enough to assert RESET

图8-3. Timing Diagram MR and RESET for X2SON (DPW) Package

8.3.5 Output Logic

8.3.5.1 RESET Output, Active-Low

RESET remains high (deasserted) as long as VDD is above the negative threshold (V_IT–). If VDD falls below the

negative threshold (V_IT–), then reset is asserted and RESET transistions to logic low (V_OL).

When VDD rises above V_IT+, the delay circuit holds RESET active and logic low for the specified reset delay

period (t_D). When the reset delay has elapsed, the RESET pin transistions to high voltage (V_OH).

The open-drain version requires an external pull-up resistor to hold the RESET pin high because the internal

MOSFET turns off causing RESET output to pull-up to the pull-up voltage. Connect the pull-up resistor to the

desired interface voltage logic. RESET can be pulled up to any voltage up to maximum voltage independent of

the VDD voltage. To ensure proper voltage levels, take care when choosing the pull-up resistor values. The pull-

up resistor value is determined by V_OL, the output capacitive loading, and the output leakage current (I_lkg(OD)).

The push-pull variant does not require an external pull-up resistor.

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8.3.5.2 RESET Output, Active-High

RESET remains logic low (deasserted) as long as VDD is above the positive threshold (V_IT+). If VDD falls below

the negative threshold (V_IT–), then reset is asserted and RESET transistions to logic high (V_OH).

When VDD rises above V_IT+, the delay circuit holds RESET active and logic high for the specified reset delay

period (t_D). When the reset delay has elapsed the RESET pin transistions to low voltage (V_OL).

8.4 Device Functional Modes

表8-1 summarizes the various functional modes of the device.

表8-1. Truth Table

V_DD

V_DD< V_POR

MR (X2SON package only)

RESET (Active-High)

RESET(Active-Low)

N/A

Undefined

(1)

V_POR< V_DD< V_IT–

V_DD≥V_IT–

(1) When V_DDfalls below V_DD(MIN), output reset is held asserted until V_DDfalls below V_POR

8.4.1 Normal Operation (VDD > V_DD(min)

)

When VDD voltage is greater than V_DD(min), the reset signal is determined by the voltage on the VDD pin with

respect to the trip point (V_IT–) and the MR pin voltage (X2SON package only).

8.4.2 VDD Between VPOR and V_DD(min)

When the voltage on VDD is less than the V_DD(min)voltage and greater than the power-on-reset voltage (V_POR),

the reset signal is asserted.

8.4.3 Below Power-On-Reset (VDD < V_POR

)

When the voltage on VDD is lower than V_POR, the device does not have enough bias voltage to internally pull the

asserted output low or high and reset voltage level is undefined.

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The TLV803E, TLV809E, and TLV810E devices are used for voltage monitoring. These devices have only three

pins: VDD, GND, and RESET (or RESET for TLV810E). There are at the most two external components: a

capacitor on the VDD pin and a pull-up resistor on the RESET/RESET to VDD or another pull-up voltage for the

open-drain variants. The design involves choosing the device with the desired voltage threshold and output

topology and adding these components, if needed, as explained in the following sections.

9.2 Typical Application - Voltage Rail Monitoring

A typical application for TLV803E, TLV809E, and TLV810E devices is voltage rail monitoring. This rail can be the

input power supply or the output of an LDO or DC/DC converter. 图 9-1 shows the TLV803EA29 monitoring the

supply rail for a DSP, FPGA, or ASIC. This rail is at 3.3 V and generated by an LDO with an input power supply

of 5 V. The supervisor is needed to make sure that the supply to the MCU/ASIC/FPGA/DSP is above a certain

voltage threshold. If the supply voltage drops below a certain threshold, supervisor generates a reset output to

indicate to the MCU that the supply is going down so that the MCU can take actions to save register data before

supply enters brown-out conditions.

LDO

3.3 V

5 V

OUT

10 kΩ

VDD

FPGA, ASIC,

DSP

VDD

RESET

GND

TLV803E

GND

图9-1. The Output of LDO Powering the MCU is Monitored by the TLV803EA29

9.2.1 Design Requirements

This design monitors a 3.3-V rail and flags an undervoltage fault at the RESET output when supply rail falls

approximately 12% below the nominal rail voltage. The TLV803E device has an open-drain output topology so

an external pull-up resistor is required and is calculated to ensure that V_OLdoes not exceed max limit given the

I_RESET/RESETspec of ±5 mA is not violated at the expected supply voltage. 节 7.5 table provides 500 µA Isink for

1.7 V VDD, which is the closest voltage to this design example. Using 500 µA of Isink and 300 mV max V_OL

gives us 5.36kΩ for the external pull-up resistor. Any value greater than 5.36kΩ would ensure that V_OLwill not

exceed 300 mV max specification. If you are using the TLV809E device variant, no pull-up resistor is required

because TLV809E has push-pull output topology.

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9.2.2 Detailed Design Procedure

Select the TLV803EA29DBZR to satisfy the voltage threshold requirement for 3.3-V rail monitoring. As

mentioned in 表 12-1, the TLV803EA29DBZR triggers an undervoltage fault at the RESET output when VDD

falls below V_IT-which is 2.93 V for this device variant. Place a pull-up resistor on RESET to VDD to satisfy the

output logic requirement while not violating the I_RESETrecommended limit.

9.2.3 Application Curves

图 9-2 and 图 9-3 show the TLV803EA29 functionality. In 图 9-2, the VDD supply voltage drops from 30% above

V_IT-= 3.8 V to 10% below V_IT-= 2.6 V with a 0.1-µF capacitor on VDD. The RESET output is connected to VDD

through the pull-up resistor so when the VDD supply voltage drops. The RESET output discharges down to the

VDD supply voltage through the pull-up resistor and RESET pin capacitance. Once the high-to-low propagation

delay t_{PD_HL}expires, the internal MOSFET turns on and asserts RESET to logic low. Note that t_{PD_HL}varies with

VDD specifically on how much VDD drops and how quickly in addition to the VDD and RESET pin capacitances.

In 图 9-3, VDD rises from 2 V to 4 V and the RESET output deasserts to logic high after the reset delay time (t_D)

expires.

VDD

Propagation Delay from VDD falling below VIT- to Reset

(t_{PD_HL}) = 25 µs

Reset Delay (t_D) = 200 ms

RESET

图9-3. RESET Delay when Returning from Fault

图9-2. Propagation Delay when Fault Occurs after

VDD Falls Below V_IT-(TLV803EA29 No Load) ^{(1) (2)}

after VDD Rises Above V_IT+(TLV803EA29)

1. Typical t_{PD_HL}= 30 µs for VDD falling from (V_IT++ 30%) to (V_IT-- 10%).

2. VDD does not fall all the way to 0 V so RESET momentarily discharges to VDD until t_{PD_HL}expires.

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9.3 Typical Application - Overvoltage Monitoring

A typical use case for the push-pull active-high device variant TLV810E is overvoltage monitoring. The TLV810E

can monitor a power supply, a MCU power rail, or a battery during charging for example. The VDD pin monitors

the voltage rail and once VDD rises above VIT+, the RESET output deactivates to logic low after the reset delay

time t_D. If VDD falls below V_IT-, the RESET output activates to logic high after the propagation delay (t_{PD_HL}). The

voiltage thresholds and the reset delay time depends on the device variant. See 节 5 for device variant naming

nomenclature.

3 V

VDD

Battery Charger

VDD

RESET

ENABLE

GND

TLV810EA29

GND

图9-4. TLV810E Overvoltage Monitor Circuit for Battery Charger

9.3.1 Design Requirements

In this application design, the TLV810E device is monitoring a 3 V battery connected to a battery charger. The

battery charger turns on when the battery voltage is below 2.93 V and turns off once the battery charges to

2.96 V and remains above 2.96 V for at least 200 ms. The design must be low power and not consume more

than 500 nA typical.

9.3.2 Detailed Design Procedure

Select the TLV810EA29 to accomplish this design. The TLV810EA29 is a push-pull active-high device with a

V_IT-= 2.9 V and V_IT+= 2.9 + 1.2% = 2.93 V. Because the device is a push-pull output and the device threshold

meets the design requirements, no external resistors are needed. The TLV810EA29 device variant comes with

200 ms reset delay time meaning VDD must be above V_IT+for at least 200 ms for the RESET output to

transistion to logic low to turn off the battery charger. This device meets the low power requirement because the

TLV810E only consumes 250 nA typical.

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10 Power Supply Recommendations

These devices are designed to operate from an input supply range of 1.7 V to 6 V. An input supply capacitor is

recommended between the VDD pin and GND pin. If the voltage supply that provides power to VDD is

susceptible to any large voltage transient that can exceed VDD maximum, the user must take additional

precautions.

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11 Layout

11.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends

placing a minimum 0.1-µF ceramic capacitor as close to the VDD pin as possible. A pull-up resistor is required

for the open-drain output. Place the pull-up resistor on the RESET pin as close to the pin as possible.

11.2 Layout Example

GND

VDD

(TLV803E, TLV809E)

(TLV810E)

RESET

图11-1. TLV803E, TLV809E, and TLV810E SOT23 (DBZ) Layout Example

Pinout Option V

(TLV803E, TLV809E)

(TLV810E)

RESET

GND

R_pull-up

VDD

C_IN

Pull-up resistor required for Open-Drain output

图11-2. TLV803E, TLV809E, and TLV810E SOT23 (DBZ) V pinout Layout Example

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R_pull-up

RESET

VDD

PAD

C_IN

TI Gray

GND

Top View

Pull-up resistor required for Open-Drain output

Connection between PAD and GND is optional

图11-3. TLV803E, TLV809E, and TLV810E X2SON (DPW) Layout Example

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Device Nomenclature

表 12-1 shows how to decode the function of the device based on its part number. For example:

TLV803EA29DBZR is open-drain, active-low, 200 ms reset delay, 2.93 V threshold voltage, Pin 1 = GND,

SOT23-3 pin package, and large reel option.

表 12-1 shows all the possible variants of the TLV80xE and TLV81xE. Refer to the orderable device information

table for the options available to order. Contact Texas Instruments for the details and availability of devices not in

the orderable device information table.

表12-1. Device Naming Convention

DESCRIPTION

NOMENCLATURE

VALUE

Open-Drain, Active-Low

Part Number

TLV803E

TLV809E

Push-Pull, Active-Low

TLV810E

Push-Pull, Active-High

Reset Time Delay Option

Threshold Voltage Option

200 ms

40 µs

10 ms

50 ms

400 ms

1.7 V

1.8 V

1.9 V

2.25 V

2.4 V

2.64 V

2.93 V

3.08 V

3.3 V

4.2 V

4.38 V

4.55 V

4.63 V

Pinout Indicator (DBZ Package Only)

Package Option

Pin 1 = RESET, Pin 2 = GND, Pin 3 = VDD

Pin 1 = RESET, Pin 2 = VDD, Pin 3 = GND

DBZ

DCK

DPW

SOT23-3 pin

SC70-3 pin

X2SON-5 pin

Large reel

Reel

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12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, TLV803EA29EVM User Guide

• Texas Instruments, Voltage Supervisors (Reset ICs): Frequenctly Asked Questions (FAQs)

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: TLV803E TLV809E TLV810E

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

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提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

27-Aug-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TLV803EA17DPWR

TLV803EA18DPWR

TLV803EA22DBZR

TLV803EA22DCKR

TLV803EA24DCKR

TLV803EA26DBZR

TLV803EA26DCKR

TLV803EA26DPWR

TLV803EA26RDBZR

TLV803EA29DBZR

TLV803EA29DCKR

TLV803EA29DPWR

TLV803EA29RDBZR

TLV803EA29VDBZR

TLV803EA30DBZR

TLV803EA30DCKR

TLV803EA42RDBZR

TLV803EA43DBZR

TLV803EA43DCKR

TLV803EA43RDBZR

ACTIVE

X2SON

SOT-23

SC70

DPW

DBZ

DCK

DBZ

DCK

DPW

DBZ

DCK

DPW

DBZ

DCK

DBZ

DCK

DBZ

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

-40 to 125

Samples

NIPDAU

NIPDAU | SN

NIPDAU

NIPDAU | SN

NIPDAU

322A

3FA

34A

326A

32A

SC70

SOT-23

SC70

X2SON

SOT-23

SC70

36AR

329A

39A

NIPDAU | SN

NIPDAU

NIPDAU | SN

X2SON

SOT-23

SC70

39AR

39AV

330A

30A

3DAR

343A

33A

34AR

NIPDAU

SOT-23

SC70

NIPDAU

SOT-23

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

27-Aug-2022

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TLV803EA43VDBZR

TLV803EB22DCKR

TLV803EB26RDBZR

TLV803EB29DBZR

TLV803EB29RDBZR

TLV803EB33VDBZR

TLV803EB42VDBZR

TLV803EB46DCKR

TLV803EC29DBZR

TLV803EC29DCKR

TLV803EC30DBZR

TLV803EC43DBZR

TLV803ED17DPWR

TLV803ED18DPWR

TLV803ED29DBZR

TLV803EF26DBZR

TLV803EF29DBZR

TLV809EA17DBZR

TLV809EA22DBZR

TLV809EA26DBZR

TLV809EA26DCKR

ACTIVE

SOT-23

SC70

DBZ

DCK

DBZ

DCK

DBZ

DCK

DBZ

DPW

DBZ

DCK

3000 RoHS & Green

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

-40 to 125

34AV

32B

Samples

NIPDAU

SOT-23

SC70

36BR

329B

39BR

3CBV

3DBV

36B

NIPDAU | SN

NIPDAU

SOT-23

SC70

329C

39C

NIPDAU

SOT-23

X2SON

SOT-23

SC70

330C

343C

NIPDAU

329D

326F

329F

917A

922A

926A

92A

NIPDAU | SN

NIPDAU

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

27-Aug-2022

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TLV809EA26DPWR

TLV809EA29DBZR

TLV809EA29DCKR

TLV809EA29DPWR

TLV809EA30DBZR

TLV809EA30DCKR

TLV809EA43DBZR

TLV809EA45DBZR

TLV809EA45DCKR

TLV809EA46DBZR

TLV809EA46DCKR

TLV809EA46DPWR

TLV809EC26DBZR

TLV809EC46DBZR

TLV809ED29DBZR

TLV809EF30DBZR

TLV810EA29DBZR

TLV810EA29DPWR

ACTIVE

X2SON

SOT-23

SC70

DPW

DBZ

DCK

DPW

DBZ

DCK

DBZ

DCK

DBZ

DCK

DPW

DBZ

DPW

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

-40 to 125

Samples

NIPDAU | SN

NIPDAU

929A

99A

X2SON

SOT-23

SC70

930A

90A

943A

945A

95A

946A

96A

NIPDAU

SOT-23

SC70

NIPDAU

SOT-23

SC70

NIPDAU

X2SON

SOT-23

X2SON

926C

946C

929D

930F

029A

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

27-Aug-2022

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV803EA17DPWR

TLV803EA18DPWR

TLV803EA22DBZR

TLV803EA22DCKR

TLV803EA24DCKR

TLV803EA26DBZR

TLV803EA26DCKR

TLV803EA26DPWR

TLV803EA26RDBZR

TLV803EA29DBZR

TLV803EA29DCKR

TLV803EA29DPWR

TLV803EA29RDBZR

TLV803EA29VDBZR

TLV803EA30DBZR

X2SON

SOT-23

SC70

DPW

DBZ

DCK

DBZ

DCK

DPW

DBZ

DCK

DPW

DBZ

3000

178.0

180.0

178.0

180.0

178.0

180.0

178.0

8.4

9.0

8.4

9.0

8.4

9.0

8.4

9.0

8.4

9.0

0.91

3.15

2.4

0.91

2.77

2.5

0.5

2.0

4.0

2.0

4.0

2.0

4.0

8.0

1.22

1.2

SC70

2.4

2.5

1.2

SOT-23

SC70

2.9

3.35

2.77

2.5

1.35

1.22

1.2

3.15

2.4

X2SON

SOT-23

SC70

0.91

3.15

2.9

0.91

2.77

3.35

2.5

0.5

1.22

1.35

1.2

2.4

X2SON

SOT-23

0.91

2.9

0.91

3.35

2.77

0.5

1.35

1.22

3.15

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Jul-2023

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV803EA30DCKR

TLV803EA42RDBZR

TLV803EA43DBZR

TLV803EA43DCKR

TLV803EA43RDBZR

TLV803EA43VDBZR

TLV803EB22DCKR

TLV803EB26RDBZR

TLV803EB29DBZR

TLV803EB29RDBZR

TLV803EB33VDBZR

TLV803EB42VDBZR

TLV803EB46DCKR

TLV803EC29DBZR

TLV803EC29DCKR

TLV803EC30DBZR

TLV803EC43DBZR

TLV803ED17DPWR

TLV803ED18DPWR

TLV803ED29DBZR

TLV803EF26DBZR

TLV803EF29DBZR

TLV809EA17DBZR

TLV809EA22DBZR

TLV809EA26DBZR

TLV809EA26DCKR

TLV809EA26DPWR

TLV809EA29DBZR

TLV809EA29DCKR

TLV809EA29DPWR

TLV809EA30DBZR

TLV809EA30DCKR

TLV809EA43DBZR

TLV809EA45DBZR

TLV809EA45DCKR

TLV809EA46DBZR

SC70

SOT-23

SC70

DCK

DBZ

DCK

DBZ

DCK

DBZ

DCK

DBZ

DCK

DBZ

DPW

DBZ

DCK

DPW

DBZ

DCK

DPW

DBZ

DCK

DBZ

DCK

DBZ

3000

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

180.0

178.0

9.0

8.4

9.0

8.4

9.0

8.4

9.0

8.4

9.0

8.4

9.0

8.4

9.0

8.4

9.0

2.4

3.15

2.4

2.5

2.77

2.5

1.2

1.22

1.2

4.0

2.0

4.0

2.0

4.0

2.0

4.0

8.0

SOT-23

SC70

3.15

3.2

2.77

2.85

2.5

1.22

1.3

2.4

1.2

SOT-23

SC70

3.15

2.9

2.77

3.35

2.77

2.85

3.35

2.85

2.5

1.22

1.35

1.22

1.3

3.15

3.2

2.9

1.35

1.3

2.9

3.2

2.4

1.2

SOT-23

SC70

3.15

2.4

2.77

2.5

1.22

1.2

SOT-23

X2SON

SOT-23

SC70

3.15

0.91

3.15

2.9

2.77

0.91

2.77

3.35

2.5

1.22

0.5

1.22

1.35

1.2

2.4

X2SON

SOT-23

SC70

0.91

2.9

0.91

3.35

2.77

2.5

0.5

1.35

1.22

1.2

3.15

2.4

X2SON

SOT-23

SC70

0.91

3.15

2.4

0.91

2.77

2.5

0.5

1.22

1.2

SOT-23

SC70

3.15

2.4

2.77

2.5

1.22

1.2

SOT-23

3.15

2.77

1.22

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Jul-2023

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV809EA46DCKR

TLV809EA46DPWR

TLV809EC26DBZR

TLV809EC46DBZR

TLV809ED29DBZR

TLV809EF30DBZR

TLV810EA29DBZR

TLV810EA29DPWR

SC70

DCK

DPW

DBZ

DPW

3000

178.0

9.0

8.4

9.0

8.4

2.4

2.5

1.2

0.5

4.0

2.0

4.0

2.0

8.0

X2SON

SOT-23

X2SON

0.91

3.15

0.91

2.77

0.91

1.22

0.5

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV803EA17DPWR

TLV803EA18DPWR

TLV803EA22DBZR

TLV803EA22DCKR

TLV803EA24DCKR

TLV803EA26DBZR

TLV803EA26DCKR

TLV803EA26DPWR

TLV803EA26RDBZR

TLV803EA29DBZR

TLV803EA29DCKR

TLV803EA29DPWR

TLV803EA29RDBZR

TLV803EA29VDBZR

TLV803EA30DBZR

TLV803EA30DCKR

TLV803EA42RDBZR

X2SON

SOT-23

SC70

DPW

DBZ

DCK

DBZ

DCK

DPW

DBZ

DCK

DPW

DBZ

DCK

DBZ

3000

205.0

180.0

210.0

180.0

205.0

180.0

210.0

180.0

205.0

210.0

180.0

200.0

180.0

185.0

180.0

200.0

180.0

185.0

180.0

200.0

185.0

180.0

33.0

18.0

35.0

18.0

33.0

18.0

35.0

18.0

33.0

35.0

18.0

SC70

SOT-23

SC70

X2SON

SOT-23

SC70

X2SON

SOT-23

SC70

SOT-23

Pack Materials-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Jul-2023

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV803EA43DBZR

TLV803EA43DCKR

TLV803EA43RDBZR

TLV803EA43VDBZR

TLV803EB22DCKR

TLV803EB26RDBZR

TLV803EB29DBZR

TLV803EB29RDBZR

TLV803EB33VDBZR

TLV803EB42VDBZR

TLV803EB46DCKR

TLV803EC29DBZR

TLV803EC29DCKR

TLV803EC30DBZR

TLV803EC43DBZR

TLV803ED17DPWR

TLV803ED18DPWR

TLV803ED29DBZR

TLV803EF26DBZR

TLV803EF29DBZR

TLV809EA17DBZR

TLV809EA22DBZR

TLV809EA26DBZR

TLV809EA26DCKR

TLV809EA26DPWR

TLV809EA29DBZR

TLV809EA29DCKR

TLV809EA29DPWR

TLV809EA30DBZR

TLV809EA30DCKR

TLV809EA43DBZR

TLV809EA45DBZR

TLV809EA45DCKR

TLV809EA46DBZR

TLV809EA46DCKR

TLV809EA46DPWR

TLV809EC26DBZR

TLV809EC46DBZR

SOT-23

SC70

DBZ

DCK

DBZ

DCK

DBZ

DCK

DBZ

DCK

DBZ

DPW

DBZ

DCK

DPW

DBZ

DCK

DPW

DBZ

DCK

DBZ

DCK

DBZ

DCK

DPW

DBZ

3000

180.0

210.0

180.0

210.0

180.0

210.0

180.0

205.0

180.0

210.0

180.0

205.0

210.0

180.0

205.0

180.0

205.0

180.0

185.0

180.0

185.0

180.0

185.0

180.0

200.0

180.0

185.0

180.0

200.0

185.0

180.0

200.0

180.0

200.0

180.0

18.0

35.0

18.0

35.0

18.0

35.0

18.0

33.0

18.0

35.0

18.0

33.0

35.0

18.0

33.0

18.0

33.0

18.0

SOT-23

SC70

SOT-23

SC70

SOT-23

SC70

SOT-23

X2SON

SOT-23

SC70

X2SON

SOT-23

SC70

X2SON

SOT-23

SC70

SOT-23

SC70

SOT-23

SC70

X2SON

SOT-23

Pack Materials-Page 5

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Jul-2023

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV809ED29DBZR

TLV809EF30DBZR

TLV810EA29DBZR

TLV810EA29DPWR

SOT-23

X2SON

DBZ

DPW

3000

180.0

205.0

180.0

200.0

18.0

33.0

Pack Materials-Page 6

PACKAGE OUTLINE

DPW0005A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

0.85

0.75

PIN 1 INDEX AREA

0.85

0.75

0.4 MAX

SEATING PLANE

NOTE 3

(0.1)

0.05

0.00

(0.324)

4X (0.05)

0.25 0.1

NOTE 3

2X (0.26)

0.48

0.27

0.17

0.239

0.139

0.1

C A B

0.288

0.188

0.05

4223102/D 03/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The size and shape of this feature may vary.

www.ti.com

EXAMPLE BOARD LAYOUT

DPW0005A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.78)

(

0.1)

SYMM

4X (0.42)

VIA

0.05 MIN

ALL AROUND

TYP

4X (0.22)

SYMM

4X (0.26)

(0.48)

(R0.05) TYP

SOLDER MASK

OPENING, TYP

4X (0.06)

(

0.25)

(0.21) TYP

EXPOSED METAL

CLEARANCE

METAL UNDER

SOLDER MASK

TYP

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED

SCALE:60X

4223102/D 03/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note

in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

DPW0005A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

4X (0.42)

4X (0.06)

4X (0.22)

SYMM

(

0.24)

4X (0.26)

(0.21)

(0.48)

TYP

SOLDER MASK

EDGE

(R0.05) TYP

SYMM

(0.78)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 3

92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:100X

4223102/D 03/2022

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

DCK0003A

SOT-SC70 - 1.1 max height

SMALL OUTLINE TRANSISTOR SC70

2.4

1.8

0.1 C

1.4

1.1

1.1 MAX

PIN 1

INDEX AREA

0.65

1.3

2.15

1.85

0.30

0.15

C A B

0.1

0.0

0.1

(0.9)

TYP

0.15

0.22

0.08

GAGE PLANE

TYP

0.46

0.26

TYP

SEATING PLANE

4220745/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

DCK0003A

SOT-SC70 - 1.1 max height

SMALL OUTLINE TRANSISTOR SC70

PKG

3X (0.95)

3X (0.4)

SYMM

(1.3)

(0.65)

(R0.05) TYP

(2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4220745/C 06/2021

NOTES: (continued)

3. Publication IPC-7351 may have alternate designs.

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DCK0003A

SOT-SC70 - 1.1 max height

SMALL OUTLINE TRANSISTOR SC70

PKG

3X (0.95)

3X (0.4)

SYMM

(1.3)

(0.65)

(R0.05) TYP

(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL

SCALE:18X

4220745/C 06/2021

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

6. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DBZ0003A

SOT-23 - 1.12 mm max height

SMALL OUTLINE TRANSISTOR

2.64

2.10

1.12 MAX

1.4

1.2

0.1 C

PIN 1

INDEX AREA

0.95

(0.125)

3.04

2.80

1.9

(0.15)

NOTE 4

0.5

0.3

0.10

0.01

(0.95)

TYP

0.2

C A B

0.25

GAGE PLANE

0.20

0.08

TYP

0.6

0.2

TYP

SEATING PLANE

0 -8 TYP

4214838/D 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC registration TO-236, except minimum foot length.

4. Support pin may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DBZ0003A

SOT-23 - 1.12 mm max height

SMALL OUTLINE TRANSISTOR

PKG

3X (1.3)

3X (0.6)

SYMM

2X (0.95)

(R0.05) TYP

(2.1)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214838/D 03/2023

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBZ0003A

SOT-23 - 1.12 mm max height

SMALL OUTLINE TRANSISTOR

PKG

3X (1.3)

3X (0.6)

SYMM

2X(0.95)

(R0.05) TYP

(2.1)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL

SCALE:15X

4214838/D 03/2023

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TLV810EA29DPWR [TI]

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