TLV803EA42RDBZR [TI]
TLV803E, TLV809E, TLV810E Low Power 250-nA IQ and Small Size Supply Voltage Supervisors;
| 型号： | TLV803EA42RDBZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLV803E, TLV809E, TLV810E Low Power 250-nA IQ and Small Size Supply Voltage Supervisors |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV803E, TLV809E, TLV810E
SLVSES2G – AUGUST 2018 – REVISED OCTOBER 2020
TLV803E, TLV809E, TLV810E Low Power 250-nA IQ and Small Size Supply Voltage
Supervisors
1 Features
3 Description
•
•
Ensured RESET/RESET for VDD = 0.7 V to 6 V
Fixed time delay: 40 µs, 10 ms, 50 ms, 100 ms,
200 ms, 400 ms
Supply current (IDD): 250 nA (typical)
– 1 µA (maximum for VDD = 3.3 V)
Output topology:
The TLV803E, TLV809E, and TLV810E are enhanced
alternatives to the TLV803, TLV853, TLV809, LM809,
TPS3809 and TLV810. TLV80xE and TLV81xE offer
low quiescent current I Q, higher accuracy, wider
•
•
temperature range, and lower power-on-reset (VPOR
)
for increased system reliability.
The TLV80xE and TLV81xE family are low IQ (250 nA
typical, 1 µA max), voltage supervisory circuits (reset
IC) that monitor VDD voltage level. These devices
initiate a reset signal whenever supply voltage VDD
drops below the factory programmed falling threshold
voltage, VIT–. The reset output remains low for a fixed
reset time delay tD after the VDD voltage rises above
the rising voltage threshold (VIT+) which is equivalent
to the falling threshold voltage (VIT-) plus hysteresis
(VHYS).
– TLV809E: push-pull, active-low
– TLV803E: open-drain, active-low
– TLV810E: push-pull, active-high
Under voltage detection:
– High accuracy: ±0.5% (typical)
– (VIT–): 1.7 V, 1.8 V, 1.9 V, 2.25V, 2.4 V, 2.64 V,
2.93 V, 3.08ꢀV, 3.3V, 4.2V, 4.38 V, 4.55V, 4.63 V
Package:
– SOT23-3 (DBZ) (with pin 1 = GND)
– SOT23-3 (DBZ) (with pin 1 = RESET/RESET)
– SOT23-3 (DBZ) (with pin 3 = GND)
– SC-70 (DCK)
•
•
These devices have integrated glitch immunity to
ignore fast transients on the VDD pin. The low IQ and
high accuracy (±0.5% typical) makes these voltage
supervisors ideal for use in low-power and portable
applications. The TLV80xE and TLV81xE devices are
specified to have the defined output logic state for
supply voltages down to VPOR = 0.7 V. The TLV80xE
and TLV81xE devices are available in industry
standard 3-pin SOT23 (DBZ) and SC70 (DCK)
packages and very compact X2SON (DPW) package.
– X2SON-5 (DPW)
•
•
Temperature range: ꢀ–40°C to +125°C
Pin-to-pin compatible with MAX803/809/810,
APX803/809/810
2 Applications
•
•
•
•
•
•
Electricity meters
Factory Automation
Portable, battery-powered equipment
Set-top boxes and TVs
Building automation
Device Information (1)
PART NUMBER
PACKAGE
SOT-23 (3)
SC-70 (3)
BODY SIZE (NOM)
2.90 mm × 1.30 mm
2.00 mm × 1.25 mm
0.8 mm x 0.8 mm
TLV803E, TLV809E,
TLV810E
Notebook/desktop computers, servers
X2SON (5)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
*Rpull-up
VDD
FPGA, ASIC, DSP
LDO
TLV803E
IN
OUT
RESET
RESET
VDD
GND
GND
*Pull-up resistor not required for TLV809E, TLV810E
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV803E, TLV809E, TLV810E
SLVSES2G – AUGUST 2018 – REVISED OCTOBER 2020
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................7
7.6 Timing Requirements .................................................8
7.7 Timing Diagram...........................................................9
7.8 Typical Characteristics..............................................10
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application - Voltage Rail Monitoring............19
9.3 Typical Application - Overvoltage Monitoring............21
10 Power Supply Recommendations..............................22
11 Layout...........................................................................23
11.1 Layout Guidelines................................................... 23
11.2 Layout Example...................................................... 23
12 Device and Documentation Support..........................25
12.1 Device Support....................................................... 25
12.2 Documentation Support.......................................... 26
12.3 Receiving Notification of Documentation Updates..26
12.4 Support Resources................................................. 26
12.5 Trademarks.............................................................26
12.6 Electrostatic Discharge Caution..............................26
12.7 Glossary..................................................................26
13 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (June 2020) to Revision G (October 2020)
Page
•
•
•
•
•
•
•
Updated the numbering format for tables, figures and cross-references throughout the document...................1
Added additional threshold voltages (VIT-) and new package information .........................................................1
Updated Device Naming Nomenclature figure to include (DBZ) V pinout option .............................................. 3
Added new (DBZ) package option (Pin 3 = GND, V pinout) and updated Pin Functions Table..........................3
Added Reset time delay variant F specification .................................................................................................8
Added layout example for (DBZ) V pinout package..........................................................................................23
Modified Device Naming Convention table to include additional threshold voltages (VIT-), reset time delay
options and pinout indicator options................................................................................................................. 25
Changes from Revision E (April 2020) to Revision F (June 2020)
Page
Changed DPW package from Advanced Information to Production Data.......................................................... 1
Changed DPW package Information ................................................................................................................. 3
•
•
Changes from Revision D (February 2020) to Revision E (April 2020)
Page
•
Added X2SON (DPW) package option ..............................................................................................................3
Changes from Revision C (November 2019) to Revision D (February 2020)
Page
•
•
•
•
Added device nomenclature figure .................................................................................................................... 3
Added timing diagram for TLV810E ...................................................................................................................9
Added Figure 6, Figure 23, Figure 24 ..............................................................................................................10
Added typical application for TLV810E ............................................................................................................21
Changes from Revision B (July 2019) to Revision C (November 2019)
Page
•
Changed device status from Advance Information to Production Data.............................................................. 1
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5 Device Comparison
Figure 5-1 shows the device naming nomenclature to compare the difference device variants. See Table 12-1 for
a more detailed explanation.
TLV XXXX X XX X XXX
Output Type
Delay Op on
A: 200 ms
B: 40 µs
C: 10 ms
D: 50 ms
Threshold Voltage
17: 1.7 V
...
46: 4.63 V
Pinout Indicator
R: Pin 1 = RESET, Pin 2 = GND
V: Pin 1 = RESET, Pin 3 = GND
Package
803E: Open-Drain Ac ve-Low
809E: Push-Pull Ac ve-Low
810E: Push-Pull Ac ve-High
DBZ: SOT23
DCK: SC70
DPW: X2SON
E: 100 ms
F: 400 ms
Figure 5-1. Device Naming Nomenclature
6 Pin Configuration and Functions
GND
1
GND
1
2
VDD
VDD
3
3
RESET
2
RESET
RESET
(TLV810E)
Figure 6-2. DCK Package
3-Pin SC-70
Figure 6-1. DBZ Package
(Pin 1 = GND)
Top View
3-Pin SOT-23
Top View
RESET
1
2
RESET
VDD
1
2
VDD
GND
3
3
GND
Figure 6-3. DBZ Package
(Pin 1 = RESET, R pinout)
3-Pin SOT-23
Figure 6-4. DBZ Package
(Pin 3 = GND, V pinout)
3-Pin SOT-23
Top View
Top View
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RESET
VDD
GND
4
1
RESET
(TLV810E)
PAD
MR
2
3
Top View
Figure 6-5. DPW Package
4-Pin X2SON
Top View
Pin Functions
PIN
I/O
DESCRIPTION
DBZ
(V PINOUT)
DBZ
(R PINOUT)
NAME
DCK, DBZ
DPW
GND
1
3
2
3
—
Ground
Active-low output reset signal: This pin is driven
low logic when VDD voltage falls below the negative
voltage threshold (VIT–). RESET remains low
(asserted) for the delay time period (tD) after VDD
voltage rise above VIT+.
RESET
2
1
1
1
O
Active-High output reset signal (TLV810E only):
This pin is driven high logic when VDD voltage falls
below the negative voltage threshold (VIT–). RESET
remains high (asserted) for the delay time period (tD)
after VDD voltage rise above VIT+.
RESET
VDD
2
3
1
2
1
3
1
4
O
I
Input supply voltage. TLV803E, TLV809E,
TLV810E monitor VDD voltage.
Active-low manual reset input. Pull this pin to a
logic low (VMR_L) to assert a reset signal in the output
pin. After the MR pin is left floating or pulled to VMR_H
the output goes to the nominal state after the reset
delay time (tD) expires. MR can be left floating when
not in use.
MR
N/A
N/A
N/A
N/A
N/A
N/A
2
I
No Connection. Thermal pad helps with thermal
dissipation. Recommended connection to GND.
PAD
PAD
—
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted(1)
MIN
MAX
UNIT
V
VDD pin
–0.3
6.5
Voltage
RESET (TLV809E), RESET (TLV810E)
RESET (TLV803E)
–0.3 VDD + 0.3 (2)
V
–0.3
–0.3
-20
6.5
VDD + 0.3(2)
20
V
Voltage
Current
MR
V
Output sink and source current
Operating ambient, TA
Storage, Tstg
mA
–40
–65
125
Temperature(3)
°C
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions (above the Recommended Operating
Conditions) for extended periods may affect device reliability.
(2) The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller.
(3) As a result of the low dissipated power in this device, the junction temperature is assumed to be equal to the ambient temperature.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
± 2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
± 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.7
0
NOM
MAX
6
UNIT
V
VDD
Input supply voltage
VRESET, VRESET
RESET pin and RESET pin voltage
RESET pin and RESET pin current
Junction temperature (free air temperature)
Manual reset pin voltage
6
V
IRESET, IRESET
0
±5
mA
°C
V
TJ
–40
0
125
VDD
VMR
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UNIT
SLVSES2G – AUGUST 2018 – REVISED OCTOBER 2020
7.4 Thermal Information
TLV803E, TLV809E, TLV810E
THERMAL METRIC(1)
DPW (X2SON)
5 PINS
457.1
DCK (SC70-3)
3 PINS
300.5
DBZ (SOT23-3)
3 PINS
254.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
201.6
178.2
150.5
320.4
166.5
140.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
22.8
70
48.1
ψJB
318.8
165.2
139.1
RθJC(bot)
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
over operating range (TA = –40℃ to 125℃), 1.7 V ≤ VDD ≤ 6 V, Rpull-up = 10 kΩ to 6 V, 10 pF load at RESET pin, unless
otherwise noted. Typical values are at 25℃, VDD = 3.3V and VIT– = 2.93 V.
PARAMETER
COMMON PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDD
VIT–
VHYS
Input supply voltage
1.7
–2
6
2
V
%
Input threshold voltage accuracy
Hysteresis voltage
TA= –40℃ to 125℃
0.5
1.2
Hysteresis from VIT–
VDD = 3.3 V; VDD > VIT+
VDD = 6 V
0.9
1.5
1
%
(1)
0.25
0.4
µA
µA
IDD
Supply current into VDD pin
1.2
Manual reset pin internal pull-up
resistance
RMR
100
kΩ
X2SON (DPW) package only
VMR_L
VMR_H
Manual reset pin logic low input
Manual reset pin logic high input
0.4
V
V
0.8VDD
TLV809E (Push-Pull Active-Low)
VPOR
Power on reset voltage (2)
VOL ≤ 300 mV, IOUT(Sink) = 15 µA
700
300
300
mV
mV
mV
V
VDD = 1.7 V, VDD < VIT–, IOUT(Sink) = 500 µA
VDD = 3.3 V, VDD < VIT–, IOUT(Sink) = 2 mA
VDD = 6 V, VDD > VIT+, IOUT(Source) = 4 mA
VDD = 3.3 V, VDD > VIT+, IOUT(Source) = 2 mA
Low level output voltage
VOL
0.8VDD
0.8VDD
High level output voltage
VOH
V
TLV803E (Open-Drain Active-Low)
VPOR
Power on reset voltage (2)
VOL ≤ 300 mV, IOUT(Sink) = 15 µA
700
300
300
350
mV
mV
mV
nA
VDD = 1.7 V, VDD < VIT–, IOUT(Sink) = 500 µA
VDD = 3.3 V, VDD < VIT–, IOUT(Sink) = 2 mA
VDD = VPULLUP = 6 V, VDD > VIT+
Low level output voltage
VOL
Ilkg(OD)
Open drain output leakage current
100
TLV810E (Push-Pull Active-High)
VDD = 3.3 V, VDD < VIT–, IOUT(Source) = 2 mA
VDD = 1.7 V, VDD < VIT–, IOUT(Source) = 500 µA
VOH ≥ 720 mV, IOUT(Source) = 15 µA
0.8VDD
0.8VDD
V
High level output voltage
VOH
V
VPOR
VOL
Power on Reset Voltage
Low level output voltage
900
300
300
mV
mV
mV
VDD = 6 V, VDD > VIT+, IOUT(Sink) = 2 mA
VDD = 3.3 V, VDD > VIT+, IOUT(Sink) = 500 µA
(1) VIT+ = VIT– + VHYS
(2) Minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined.
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7.6 Timing Requirements
over operating range (TA = –40℃ to 125℃), 1.7 V ≤ VDD ≤ 6 V, Rpull-up = 10 kΩ to 6 V (Open Drain only), 10 pF load at
RESET pin, Overdrive = 10%, unless otherwise noted. Typical values are at 25℃, VDD = 3.3 V and VIT– = 2.93 V.
PARAMETER
Glitch immunity
Propagation delay from VDD falling below V VDD = (VIT+ + 30%) to (VIT–
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tGI
5 % Overdrive(1)
10
µs
–
tPD_HL
30
50
µs
IT– to RESET
10%)
Reset time delay variant A (2)
130
200
270
ms
Reset time delay variant B (2); R
UP = 100 kΩ, CL = 100 pF, 30%
Overdrive (3)
45
90
µs
Reset time delay variant B (2)
Reset time delay variant C (2)
40
10
80
µs
tD
Release time or reset timeout period
6.5
33
13.5
ms
Reset time delay variant D (2)
Reset time delay variant F (4)
50
400
67
ms
ms
ns
260
540
MR pin pulse duration to initiate RESET,
RESET
(5)
tMR_PW
500
Propagation delay from MR low to RESET,
RESET
VDD = 4.5 V, VMR : VMR_H to V
(5)
tMR_RES
700
ns
MR_L
Delay from release MR to deasert RESET,
RESET
VDD = 4.5 V, VMR : VMR_L to V
(5)
tMR_tD
tD_MIN
tD_TYP
tD_MAX
ms
MR_H
(1) Overdrive = [(VDD/ VIT–) - 1] × 100%. Refer to section on VDD glitch immunity
(2) Refer to Device nomenclature table. VDD: (VIT--10%) to (VIT+ + 10%)
(3) Specified by design
(4) Product Preview
(5) X2SON Package only
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7.7 Timing Diagram
VIT+
VIT-
VHYS
VDD(MIN)
VPOR
VDD
tPD_HL
tPD_HL
tD
RESET
Undefined output VDD < VPOR
Diagram not to scale
Figure 7-1. TLV803E, TLV809E Timing Diagram
VIT+
VIT-
VHYS
VDD(MIN)
VPOR
VDD
tPD_HL
tPD_HL
tD
tD
RESET
Undefined output VDD < VPOR
Diagram not to scale
Figure 7-2. TLV810E Timing Diagram
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7.8 Typical Characteristics
Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are
TA = 25°C, VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted.
0.45
0.4
0.5
0.45
0.4
25°C
-40°C
125°C
25°C
-40°C
125°C
0.35
0.3
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
1.5
2
2.5
3
3.5 4
VDD (V)
4.5
5
5.5
6
1.5
2
2.5
3
3.5 4
VDD (V)
4.5
5
5.5
6
IDD_
IDD_
Figure 7-3. Supply Current Versus Supply Voltage for
TLV803EA29
Figure 7-4. Supply Current Versus Supply Voltage for
TLV809EA29
0.45
0.32
25°C
-40°C
125°C
TLV803EA29
0.31
0.4
0.35
0.3
0.3
0.29
0.28
0.27
0.26
0.25
0.24
0.23
0.22
0.21
0.2
0.25
0.2
0.15
0.1
0.05
0
1.5
2
2.5
3
3.5 4
VDD (V)
4.5
5
5.5
6
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
IDDv
IDD_
Figure 7-5. Supply Current Versus Supply Voltage for
TLV810EA29
Figure 7-6. Supply Current Verses Temperature for
TLV803EA29, VDD = 3.3 V
0.32
30
TLV809EA29
TLV803EA29
0.31
27
24
21
18
15
12
9
0.3
0.29
0.28
0.27
0.26
0.25
0.24
0.23
0.22
0.21
0.2
6
3
0
-40
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-20
0
20
40 60
Temperature (°C)
80
100 120 140
IDD_
ILKG
Figure 7-7. Supply Current Verses Temperature for
TLV809EA29, VDD = 3.3 V
Figure 7-8. Leakage Current Verses Temperature for
TLV803EA29
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are
TA = 25°C, VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted.
1
0.92
0.84
0.76
0.68
0.6
1.3
1.2
1.1
1
TLV803EA29
TLV809EA29
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.52
0.44
0.36
0.28
0.2
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
VIT-
VIT-
Figure 7-9. Voltage Threshold Accuracy Verses Temperature for
TLV803EA29
Figure 7-10. Voltage Threshold Accuracy Verses Temperature
for TLV809EA29
0.8
0.55
-40°C
-20°C
-40°C
-20°C
0.5
0.72
85°C
105°C
125°C
85°C
105°C
125°C
0.45
0.4
0.64
0.56
0.48
0.4
0.35
0.3
0.25
0.2
0.32
0.24
0.16
0.08
0
0.15
0.1
0.05
0
0
0.002
0.004
0.006
0.008
0.01
0
0.002
0.004
0.006
0.008
0.01
IRESET (A)
IRESET (A)
VOLx
VOLx
Figure 7-11. Low Voltage Output Versus Output Current for
TLV803EA29, VDD = 1.7 V
Figure 7-12. Low Voltage Output Versus Output Current for
TLV809EA29, VDD = 1.7 V
25
TLV803EA29
24.5
25
TLV809EA29
24.5
24
23.5
23
24
23.5
23
22.5
22
22.5
22
21.5
21
21.5
21
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
VOLx
VOLx
Figure 7-13. Low Voltage Output Verses Temperature for
TLV803EA29, VDD = 1.7 V
Figure 7-14. Low Voltage Output Verses Temperature for
TLV809EA29, VDD = 1.7 V
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are
TA = 25°C, VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted.
6
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5
3.12
3.115
3.11
-40°C
-20°C
25°C
85°C
105°C
125°C
TLV809EA29
3.105
3.1
3.095
3.09
3.085
3.08
3.075
3.07
3.065
-40
-20
0
20
40
60
80
100 120 140
0
0.002
0.004
0.006
0.008
0.01
Temperature (èC)
VOHx
IRESET (A)
VOHx
Figure 7-16. High Voltage Output Verses Temperature for
TLV809EA29, VDD = 3.3 V
Figure 7-15. High Voltage Output Versus Output Current for
TLV809EA29, VDD = 6 V
6
0.12
TLV803EA29
25°C
5.5
5
4.5
4
0.1
0.08
0.06
0.04
0.02
0
3.5
3
2.5
2
1.5
1
0.5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VDD (V)
1
0
0.5
1
1.5
2
2.5
3
VDD (V)
3.5
4
4.5
5
5.5
6
Vpor
VCC_
Figure 7-17. Reset Voltage Output Versus Voltage Input for
TLV803EA29, Vpull-up = VDD, Rpull-up = 10 kΩ
Figure 7-18. Reset Voltage Output Versus Voltage Input for
TLV803EA29, Rpull-up = 10 kΩ
173
2
TLV803EA29
VDD
RESET
172
171
170
169
168
167
1.6
1.2
0.8
0.4
0
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
6
12
18
24
30
Time (µs)
Rese
VRES
Figure 7-20. Reset Delay Time Verses Temperature for
TLV803EA29
Figure 7-19. Transient Power-on-Reset Voltage for TLV809EA30,
IRESET = 15 µA
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are
TA = 25°C, VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted.
16.25
171.5
TLV803EB29
TLV809EA29
16.2
16.15
16.1
171
170.5
170
16.05
16
169.5
169
15.95
15.9
168.5
168
15.85
15.8
167.5
167
15.75
15.7
166.5
15.65
15.6
166
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
tD__
Rese
Figure 7-21. Reset Delay Time Verses Temperature for
TLV809EA29
Figure 7-22. Reset Delay Time Verses Temperature for
TLV803EB29
9
25
TLV803EC29
TLV803EA29
24.75
8.8
8.6
8.4
8.2
8
24.5
24.25
24
23.75
23.5
23.25
23
22.75
22.5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
tPHL
Rese
Figure 7-24. High-to-Low Propagation Delay Verses
Temperature for TLV803EA29
Figure 7-23. Reset Delay Time Verses Temperature for
TLV803EC29
26
13
TLV809EA29
25°C
-40°C
125°C
12
11
10
9
25.5
25
24.5
24
8
7
23.5
23
6
5
22.5
22
4
3
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
5
10
15
20
25 30
Overdrive (%)
35
40
45
50
tPHL
tGI_
Figure 7-25. High-to-Low Propagation Delay Verses
Temperature for TLV809EA29
Figure 7-26. Glitch Immunity Versus Overdrive for TLV803EA29
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7.8 Typical Characteristics (continued)
Typical characteristics show the typical performance of the TLV803E, TLV809E, and TLV810E devices. Test conditions are
TA = 25°C, VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted.
13
25°C
-40°C
125°C
12
11
10
9
8
7
6
5
4
3
5
10
15
20
25 30
Overdrive (%)
35
40
45
50
tGI_
Figure 7-27. Glitch Immunity Versus Overdrive for TLV809EA29
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8 Detailed Description
8.1 Overview
The TLV803E, TLV809E, TLV810E is a family of easy to implement low power, small size voltage supervisors
(Reset ICs) with fixed threshold voltage and fixed reset delay. The TLV803E has open-drain active-low output
topology which requires an external pull-up resistor, TLV809E has push-pull active-low output topology and
TLV810E has push-pull active-high output topology. This family of devices features include integrated resistor
divider threshold with hysteresis and a glitch immunity filter.
These devices are available in SOT-23 (3) and SC70 (3) industry standard package and pinout as well as a very
small X2SON (5) package.
8.2 Functional Block Diagram
VDD
RMR
MR
Push-pull TLV809E,
TLV810E variants
DPW package only
VDD
+
VDD
RESET
LOGIC
TIMER
(TLV803E, TLV809E)
RESET (TLV810E)
RESET
œ
Reference
Voltage
GND
GND
8.3 Feature Description
8.3.1 Input Voltage (VDD)
VDD pin is monitored by the internal comparator with integrated reference to indicate when VDD falls below the
fixed threshold voltage. VDD also functions as the supply for the following:
•
•
•
•
•
Internal bandgap (reference voltage)
Internal regulator
State machine
Buffers
Other control logic blocks
Good design practice involves placing a 0.1-µF to 1-µF bypass capacitor at VDD input for noisy applications and
to ensure enough charge is available for the device to power up correctly. The reset output is undefined when
VDD is below VPOR
.
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8.3.2 VDD Hysteresis
The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD
pin falls below the falling voltage threshold VIT–, the output reset is asserted. When the voltage at the VDD pin
rises above the rising voltage threshold (V IT+) equivalent to V IT– plus hysteresis (V HYS), the output reset is
deasserted after tD reset time delay.
8.3.3 VDD Glitch Immunity
These devices are immune to quick voltage transient or excursion on VDD. Sensitivity to transients depends on
both pulse duration (tGI) found in Section 7.6 and transient overdrive. Overdrive is defined by how much VDD
exceeds the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as
shown in Equation 1.
Overdrive = | (VDD / VIT– – 1) × 100% |
(1)
where
•
•
VIT– is the threshold voltage
VDD is the input voltage crossing VIT–
VDD
VIT+
VIT-
Overdrive
Pulse
Duration
Figure 8-1. Overdrive Versus Pulse Duration
TLV803E, TLV809E, and TLV810E devices have built-in glitch immunity (tGI) of 10 µs typical as shown in Section
7.6. Figure 8-2 shows that VDD must fall below VIT- for tGI, otherwise the faling transistion is ignored. When VDD
falls below VIT- for tGI, RESET transitions low to indicate a fault condition after the propagation delay high-to-low
(t PDHL). When VDD rises above V IT+, RESET only deasserts to logic high indicating there is no more fault
condition only if VDD remains above VIT+ for longer than the reset delay (tD).
VDD remains above VIT+ for only 199 ms
VDD
VIT+
VIT-
VDD drops below VIT- so
RESET transitions low after
Propagation Delay (tPDHL
)
RESET
VDD transition to above VIT+ ignored when less than
Reset Delay (tD) so RESET remains unchanged
Figure 8-2. Glitch Immunity when VDD Rises Above VIT+ for Less than RESET Delay (TLV803EA29)
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8.3.4 Manual Reset ( MR) Input for X2SON (DPW) Package Only
The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR
with pulse duration longer than tMR_RES will cause reset output to assert. After MR returns to a logic high
(VMR_H) and VDD is above VIT+, reset is deasserted after the user programmed reset time delay (tD) expires.
If MR is not controlled externally, then MR can be left disconnected. MR is internally connected to VDD through a
pull-up resistor RMR shown in Section 8.2. If the logic signal controlling MR is less than VDD, then additional
current flows from VDD into MR internally. For minimum current consumption, drive MR to either VDD or GND.
VMR should not be higher than VDD voltage.
VIT+
VHYS
VIT-
VIT+
VHYS
VIT-
VDD
tP_HL
tD
tMR_tD
RESET
(2)
tMR_RES
VMR_H
VMR_L
MR
(1)
tMR_PW
Time
(1) MR pulse width too small to assert RESET
(2) MR voltage not low enough to assert RESET
Figure 8-3. Timing Diagram MR and RESET for X2SON (DPW) Package
8.3.5 Output Logic
8.3.5.1 RESET Output, Active-Low
RESET remains high (deasserted) as long as VDD is above the negative threshold (VIT–). If VDD falls below the
negative threshold (VIT–), then reset is asserted and RESET transistions to logic low (VOL).
When VDD rises above VIT+, the delay circuit holds RESET active and logic low for the specified reset delay
period (tD). When the reset delay has elapsed, the RESET pin transistions to high voltage (VOH).
The open-drain version requires an external pull-up resistor to hold the RESET pin high because the internal
MOSFET turns off causing RESET output to pull-up to the pull-up voltage. Connect the pull-up resistor to the
desired interface voltage logic. RESET can be pulled up to any voltage up to maximum voltage independent of
the VDD voltage. To ensure proper voltage levels, take care when choosing the pull-up resistor values. The pull-
up resistor value is determined by VOL, the output capacitive loading, and the output leakage current (Ilkg(OD)).
The push-pull variant does not require an external pull-up resistor.
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8.3.5.2 RESET Output, Active-High
RESET remains logic low (deasserted) as long as VDD is above the positive threshold (VIT+). If VDD falls below
the negative threshold (VIT–), then reset is asserted and RESET transistions to logic high (VOH).
When VDD rises above VIT+, the delay circuit holds RESET active and logic high for the specified reset delay
period (tD). When the reset delay has elapsed the RESET pin transistions to low voltage (VOL).
8.4 Device Functional Modes
Table 8-1 summarizes the various functional modes of the device.
Table 8-1. Truth Table
VDD
VDD < VPOR
VPOR < VDD < VIT–
VDD ≥ VIT–
MR (X2SON package only)
RESET (Active-High)
RESET(Active-Low)
N/A
N/A
L
Undefined
Undefined
(1)
H
H
L
L
L
VDD ≥ VIT–
H
H
(1) When VDD falls below VDD(MIN), output reset is held asserted until VDD falls below VPOR
.
8.4.1 Normal Operation (VDD > VDD(min)
)
When VDD voltage is greater than VDD(min), the reset signal is determined by the voltage on the VDD pin with
respect to the trip point (VIT–) and the MR pin voltage (X2SON package only).
8.4.2 VDD Between VPOR and VDD(min)
When the voltage on VDD is less than the VDD(min) voltage and greater than the power-on-reset voltage (VPOR),
the reset signal is asserted.
8.4.3 Below Power-On-Reset (VDD < VPOR
)
When the voltage on VDD is lower than VPOR, the device does not have enough bias voltage to internally pull the
asserted output low or high and reset voltage level is undefined.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TLV803E, TLV809E, and TLV810E devices are used for voltage monitoring. These devices have only three
pins: VDD, GND, and RESET (or RESET for TLV810E). There are at the most two external components: a
capacitor on the VDD pin and a pull-up resistor on the RESET/RESET to VDD or another pull-up voltage for the
open-drain variants. The design involves choosing the device with the desired voltage threshold and output
topology and adding these components, if needed, as explained in the following sections.
9.2 Typical Application - Voltage Rail Monitoring
A typical application for TLV803E, TLV809E, and TLV810E devices is voltage rail monitoring. This rail can be the
input power supply or the output of an LDO or DC/DC converter. Figure 9-1 shows the TLV803EA29 monitoring
the supply rail for a DSP, FPGA, or ASIC. This rail is at 3.3 V and generated by an LDO with an input power
supply of 5 V. The supervisor is needed to make sure that the supply to the MCU/ASIC/FPGA/DSP is above a
certain voltage threshold. If the supply voltage drops below a certain threshold, supervisor generates a reset
output to indicate to the MCU that the supply is going down so that the MCU can take actions to save register
data before supply enters brown-out conditions.
LDO
3.3 V
5 V
IN
OUT
10 kΩ
VDD
FPGA, ASIC,
DSP
VDD
RESET
RESET
GND
TLV803E
GND
Figure 9-1. The Output of LDO Powering the MCU is Monitored by the TLV803EA29
9.2.1 Design Requirements
This design monitors a 3.3-V rail and flags an undervoltage fault at the RESET output when supply rail falls
approximately 12% below the nominal rail voltage. The TLV803E device has an open-drain output topology so
an external pull-up resistor is required and is calculated to ensure that VOL does not exceed max limit given the
IRESET/RESET spec of ±5 mA is not violated at the expected supply voltage. Section 7.5 table provides 500 µA
Isink for 1.7 V VDD, which is the closest voltage to this design example. Using 500 µA of Isink and 300 mV max
VOL, gives us 5.36kΩ for the external pull-up resistor. Any value greater than 5.36kΩ would ensure that VOL will
not exceed 300 mV max specification. If you are using the TLV809E device variant, no pull-up resistor is
required because TLV809E has push-pull output topology.
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9.2.2 Detailed Design Procedure
Select the TLV803EA29DBZR to satisfy the voltage threshold requirement for 3.3-V rail monitoring. As
mentioned in Table 12-1, the TLV803EA29DBZR triggers an undervoltage fault at the RESET output when VDD
falls below VIT- which is 2.93 V for this device variant. Place a pull-up resistor on RESET to VDD to satisfy the
output logic requirement while not violating the IRESET recommended limit.
9.2.3 Application Curves
Figure 9-2 and Figure 9-3 show the TLV803EA29 functionality. In Figure 9-2, the VDD supply voltage drops from
30% above VIT- = 3.8 V to 10% below VIT- = 2.6 V with a 0.1-µF capacitor on VDD. The RESET output is
connected to VDD through the pull-up resistor so when the VDD supply voltage drops. The RESET output
discharges down to the VDD supply voltage through the pull-up resistor and RESET pin capacitance. Once the
high-to-low propagation delay tPD_HL expires, the internal MOSFET turns on and asserts RESET to logic low.
Note that tPD_HL varies with VDD specifically on how much VDD drops and how quickly in addition to the VDD
and RESET pin capacitances. In Figure 9-3, VDD rises from 2 V to 4 V and the RESET output deasserts to logic
high after the reset delay time (tD) expires.
VDD
VDD
Propagation Delay from VDD falling below VIT- to Reset
(tPD_HL) = 25 µs
Reset Delay (tD) = 200 ms
RESET
RESET
Figure 9-3. RESET Delay when Returning from
Fault after VDD Rises Above VIT+ (TLV803EA29)
Figure 9-2. Propagation Delay when Fault Occurs
after VDD Falls Below VIT- (TLV803EA29 No Load)
(1) (2)
1. Typical tPD_HL= 30 µs for VDD falling from (VIT+ + 30%) to (VIT- - 10%).
2. VDD does not fall all the way to 0 V so RESET momentarily discharges to VDD until tPD_HL expires.
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9.3 Typical Application - Overvoltage Monitoring
A typical use case for the push-pull active-high device variant TLV810E is overvoltage monitoring. The TLV810E
can monitor a power supply, a MCU power rail, or a battery during charging for example. The VDD pin monitors
the voltage rail and once VDD rises above VIT+, the RESET output deactivates to logic low after the reset delay
time tD. If VDD falls below VIT-, the RESET output activates to logic high after the propagation delay (tPD_HL). The
voiltage thresholds and the reset delay time depends on the device variant. See Section 5 for device variant
naming nomenclature.
3 V
VDD
Battery Charger
VDD
RESET
ENABLE
GND
TLV810EA29
GND
Figure 9-4. TLV810E Overvoltage Monitor Circuit for Battery Charger
9.3.1 Design Requirements
In this application design, the TLV810E device is monitoring a 3 V battery connected to a battery charger. The
battery charger turns on when the battery voltage is below 2.93 V and turns off once the battery charges to 2.96
V and remains above 2.96 V for at least 200 ms. The design must be low power and not consume more than
500 nA typical.
9.3.2 Detailed Design Procedure
Select the TLV810EA29 to accomplish this design. The TLV810EA29 is a push-pull active-high device with a VIT-
= 2.9 V and VIT+ = 2.9 + 1.2% = 2.93 V. Because the device is a push-pull output and the device threshold meets
the design requirements, no external resistors are needed. The TLV810EA29 device variant comes with 200 ms
reset delay time meaning VDD must be above VIT+ for at least 200 ms for the RESET output to transistion to
logic low to turn off the battery charger. This device meets the low power requirement because the TLV810E only
consumes 250 nA typical.
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10 Power Supply Recommendations
These devices are designed to operate from an input supply range of 1.7 V to 6 V. An input supply capacitor is
recommended between the VDD pin and GND pin. If the voltage supply that provides power to VDD is
susceptible to any large voltage transient that can exceed VDD maximum, the user must take additional
precautions.
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11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends
placing a minimum 0.1-µF ceramic capacitor as close to the VDD pin as possible. A pull-up resistor is required
for the open-drain output. Place the pull-up resistor on the RESET pin as close to the pin as possible.
11.2 Layout Example
1
2
GND
3
VDD
(TLV803E, TLV809E)
(TLV810E)
RESET
RESET
RESET
RESET
Figure 11-1. TLV803E, TLV809E, and TLV810E SOT23 (DBZ) Layout Example
Pinout Option V
(TLV803E, TLV809E)
(TLV810E)
RESET
RESET
RESET
RESET
1
2
3
GND
Rpull-up
VDD
CIN
Pull-up resistor required for Open-Drain output
Figure 11-2. TLV803E, TLV809E, and TLV810E SOT23 (DBZ) V pinout Layout Example
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Rpull-up
RESET
1
4
VDD
PAD
CIN
GND
2
MR
3
Pull-up resistor required for Open-Drain output
Connection between PAD and GND is optional
Figure 11-3. TLV803E, TLV809E, and TLV810E X2SON (DPW) Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
Table 12-1 shows how to decode the function of the device based on its part number. For example:
TLV803EA29DBZR is open-drain, active-low, 200 ms reset delay, 2.93 V threshold voltage, Pin 1 = GND,
SOT23-3 pin package, and large reel option.
Table 12-1 shows all the possible variants of the TLV80xE and TLV81xE. Refer to the orderable device
information table for the options available to order. Contact Texas Instruments for the details and availability of
devices not in the orderable device information table.
Table 12-1. Device Naming Convention
DESCRIPTION
NOMENCLATURE
VALUE
Part Number
TLV803E
Open-Drain, Active-Low
TLV809E
Push-Pull, Active-Low
TLV810E
A
Push-Pull, Active-High
Reset Time Delay Option
Threshold Voltage Option
200 ms
B
40 µs
C
10 ms
D
50 ms
F
400 ms
17
18
19
22
24
26
29
30
33
42
43
45
46
R
1.7 V
1.8 V
1.9 V
2.25 V
2.4 V
2.64 V
2.93 V
3.08 V
3.3 V
4.2 V
4.38 V
4.55 V
4.63 V
Pinout Indicator
Package Option
Pin 1 = RESET, Pin 2 = GND, Pin 3 = VDD
V
Pin 1 = RESET, Pin 2 = VDD, Pin 3 = GND
DBZ
DCK
DPW
R
SOT23-3 pin
SC70-3 pin
X2SON-5 pin
Large reel
Reel
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Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
SLVSES2G – AUGUST 2018 – REVISED OCTOBER 2020
www.ti.com
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, TLV803EA29EVM User Guide
Texas Instruments, Voltage Supervisors (Reset ICs): Frequenctly Asked Questions (FAQs)
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
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TLV803E, TLV809E, TLV810E
SLVSES2G – AUGUST 2018 – REVISED OCTOBER 2020
www.ti.com
PACKAGE OUTLINE
DPW0004A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 4
(0.1)
0.25 0.1
0.05
0.00
THERMAL PAD
2
3
4
NOTE 4
5
2X
(45 ) TYP
0.48
1
0.27
4X
PIN 1 ID
(OPTIONAL)
NOTE 5
0.17
0.32
3X
0.1 C A
0.05 C
B
0.27
0.17
0.23
4218860/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. The size and shape of this feature may vary.
5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
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Product Folder Links: TLV803E TLV809E TLV810E
TLV803E, TLV809E, TLV810E
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www.ti.com
EXAMPLE BOARD LAYOUT
DPW0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
( 0.1)
VIA
SYMM
4X (0.42)
1
0.05 MIN
ALL AROUND
TYP
4
4X (0.22)
SYMM
5
4X (0.26)
(0.48)
2
3
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4218860/A 12/2015
NOTES: (continued)
6. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
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www.ti.com
EXAMPLE STENCIL DESIGN
DPW0004A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
4
1
4X (0.22)
(
0.24)
4X (0.26)
5
SYMM
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
2
3
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 5:
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4218860/A 12/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Product Folder Links: TLV803E TLV809E TLV810E
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTLV803ED29DBZR
PTLV803EF26DBZR
TLV803EA17DPWR
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
X2SON
DBZ
DBZ
DPW
3
3
5
3000
3000
3000
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
Call TI
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
IT
TLV803EA18DPWR
TLV803EA26DBZR
TLV803EA26DCKR
TLV803EA26DPWR
TLV803EA26RDBZR
TLV803EA29DBZR
TLV803EA29DCKR
TLV803EA29DPWR
TLV803EA29RDBZR
TLV803EA30DCKR
TLV803EA42RDBZR
TLV803EA43DBZR
TLV803EA43RDBZR
TLV803EB29DBZR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
X2SON
SOT-23
SC70
DPW
DBZ
DCK
DPW
DBZ
DBZ
DCK
DPW
DBZ
DCK
DBZ
DBZ
DBZ
DBZ
5
3
3
5
3
3
3
5
3
3
3
3
3
3
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
NIPDAU
SN
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
IV
Green (RoHS
& no Sb/Br)
326A
32A
IW
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
SN
X2SON
SOT-23
SOT-23
SC70
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
36AR
329A
39A
IX
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
SN
X2SON
SOT-23
SC70
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
39AR
30A
3DAR
343A
34AR
329B
Green (RoHS
& no Sb/Br)
NIPDAU
SN
SOT-23
SOT-23
SOT-23
SOT-23
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Green (RoHS
& no Sb/Br)
SN
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV803EB33VDBZR
TLV803EB42VDBZR
TLV803EB46DCKR
TLV803EC29DBZR
TLV803EC30DBZR
TLV803ED17DPWR
TLV803ED18DPWR
TLV809EA26DBZR
TLV809EA26DPWR
TLV809EA29DBZR
TLV809EA29DCKR
TLV809EA29DPWR
TLV809EA30DBZR
TLV809EA43DBZR
TLV809EA46DBZR
TLV809EA46DPWR
TLV809EC26DBZR
PREVIEW
SOT-23
SOT-23
SC70
DBZ
3
3
3
3
3
5
5
3
5
3
3
5
3
3
3
5
3
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
3CBV
3DBV
36B
329C
330C
IS
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBZ
Green (RoHS
& no Sb/Br)
SN
NIPDAU
SN
DCK
DBZ
Green (RoHS
& no Sb/Br)
SOT-23
SOT-23
X2SON
X2SON
SOT-23
X2SON
SOT-23
SC70
Green (RoHS
& no Sb/Br)
DBZ
Green (RoHS
& no Sb/Br)
SN
DPW
DPW
DBZ
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
SN
Green (RoHS
& no Sb/Br)
IU
Green (RoHS
& no Sb/Br)
926A
IZ
DPW
DBZ
Green (RoHS
& no Sb/Br)
NIPDAU
SN
Green (RoHS
& no Sb/Br)
929A
99A
J1
DCK
DPW
DBZ
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
SN
X2SON
SOT-23
SOT-23
SOT-23
X2SON
SOT-23
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
930A
943A
946A
J2
DBZ
Green (RoHS
& no Sb/Br)
SN
DBZ
Green (RoHS
& no Sb/Br)
SN
DPW
DBZ
Green (RoHS
& no Sb/Br)
NIPDAU
SN
Green (RoHS
& no Sb/Br)
926C
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV809EC46DBZR
TLV810EA29DBZR
TLV810EA29DPWR
ACTIVE
SOT-23
SOT-23
X2SON
DBZ
3
3
5
3000
3000
3000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
946C
029A
J3
ACTIVE
ACTIVE
DBZ
Green (RoHS
& no Sb/Br)
SN
DPW
Green (RoHS
& no Sb/Br)
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2020
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV803EA17DPWR
TLV803EA18DPWR
TLV803EA26DBZR
TLV803EA26DCKR
TLV803EA26DPWR
TLV803EA26RDBZR
TLV803EA29DBZR
TLV803EA29DCKR
TLV803EA29DPWR
TLV803EA29RDBZR
TLV803EA30DCKR
TLV803EA43DBZR
TLV803EA43RDBZR
TLV803EB29DBZR
TLV803EB46DCKR
TLV803EC29DBZR
TLV803EC30DBZR
TLV803ED17DPWR
X2SON
X2SON
SOT-23
SC70
DPW
DPW
DBZ
DCK
DPW
DBZ
DBZ
DCK
DPW
DBZ
DCK
DBZ
DBZ
DBZ
DCK
DBZ
DBZ
DPW
5
5
3
3
5
3
3
3
5
3
3
3
3
3
3
3
3
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
8.4
8.4
9.0
9.0
8.4
9.0
9.0
9.0
8.4
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
8.4
0.91
0.91
3.15
2.4
0.91
0.91
2.77
2.5
0.5
0.5
2.0
2.0
4.0
4.0
2.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q3
Q3
Q2
Q3
Q3
Q3
Q2
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q2
1.22
1.2
X2SON
SOT-23
SOT-23
SC70
0.91
3.15
3.15
2.4
0.91
2.77
2.77
2.5
0.5
1.22
1.22
1.2
X2SON
SOT-23
SC70
0.91
3.15
2.4
0.91
2.77
2.5
0.5
1.22
1.2
SOT-23
SOT-23
SOT-23
SC70
3.15
3.15
3.15
2.4
2.77
2.77
2.77
2.5
1.22
1.22
1.22
1.2
SOT-23
SOT-23
X2SON
3.15
3.15
0.91
2.77
2.77
0.91
1.22
1.22
0.5
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Sep-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV803ED18DPWR
TLV809EA26DBZR
TLV809EA26DPWR
TLV809EA29DBZR
TLV809EA29DCKR
TLV809EA29DPWR
TLV809EA30DBZR
TLV809EA43DBZR
TLV809EA46DBZR
TLV809EA46DPWR
TLV809EC26DBZR
TLV809EC46DBZR
TLV810EA29DBZR
TLV810EA29DPWR
X2SON
SOT-23
X2SON
SOT-23
SC70
DPW
DBZ
DPW
DBZ
DCK
DPW
DBZ
DBZ
DBZ
DPW
DBZ
DBZ
DBZ
DPW
5
3
5
3
3
5
3
3
3
5
3
3
3
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
8.4
9.0
8.4
9.0
9.0
8.4
9.0
9.0
9.0
8.4
9.0
9.0
9.0
8.4
0.91
3.15
0.91
3.15
2.4
0.91
2.77
0.91
2.77
2.5
0.5
1.22
0.5
2.0
4.0
2.0
4.0
4.0
2.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q3
Q2
Q3
Q3
Q2
Q3
Q3
Q3
Q2
Q3
Q3
Q3
Q2
1.22
1.2
X2SON
SOT-23
SOT-23
SOT-23
X2SON
SOT-23
SOT-23
SOT-23
X2SON
0.91
3.15
3.15
3.15
0.91
3.15
3.15
3.15
0.91
0.91
2.77
2.77
2.77
0.91
2.77
2.77
2.77
0.91
0.5
1.22
1.22
1.22
0.5
1.22
1.22
1.22
0.5
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV803EA17DPWR
TLV803EA18DPWR
TLV803EA26DBZR
X2SON
X2SON
SOT-23
DPW
DPW
DBZ
5
5
3
3000
3000
3000
205.0
205.0
180.0
200.0
200.0
180.0
33.0
33.0
18.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Sep-2020
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV803EA26DCKR
TLV803EA26DPWR
TLV803EA26RDBZR
TLV803EA29DBZR
TLV803EA29DCKR
TLV803EA29DPWR
TLV803EA29RDBZR
TLV803EA30DCKR
TLV803EA43DBZR
TLV803EA43RDBZR
TLV803EB29DBZR
TLV803EB46DCKR
TLV803EC29DBZR
TLV803EC30DBZR
TLV803ED17DPWR
TLV803ED18DPWR
TLV809EA26DBZR
TLV809EA26DPWR
TLV809EA29DBZR
TLV809EA29DCKR
TLV809EA29DPWR
TLV809EA30DBZR
TLV809EA43DBZR
TLV809EA46DBZR
TLV809EA46DPWR
TLV809EC26DBZR
TLV809EC46DBZR
TLV810EA29DBZR
TLV810EA29DPWR
SC70
DCK
DPW
DBZ
DBZ
DCK
DPW
DBZ
DCK
DBZ
DBZ
DBZ
DCK
DBZ
DBZ
DPW
DPW
DBZ
DPW
DBZ
DCK
DPW
DBZ
DBZ
DBZ
DPW
DBZ
DBZ
DBZ
DPW
3
5
3
3
3
5
3
3
3
3
3
3
3
3
5
5
3
5
3
3
5
3
3
3
5
3
3
3
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
205.0
180.0
180.0
180.0
205.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
205.0
205.0
180.0
205.0
180.0
180.0
205.0
180.0
180.0
180.0
205.0
180.0
180.0
180.0
205.0
180.0
200.0
180.0
180.0
180.0
200.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
200.0
200.0
180.0
200.0
180.0
180.0
200.0
180.0
180.0
180.0
200.0
180.0
180.0
180.0
200.0
18.0
33.0
18.0
18.0
18.0
33.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
33.0
33.0
18.0
33.0
18.0
18.0
33.0
18.0
18.0
18.0
33.0
18.0
18.0
18.0
33.0
X2SON
SOT-23
SOT-23
SC70
X2SON
SOT-23
SC70
SOT-23
SOT-23
SOT-23
SC70
SOT-23
SOT-23
X2SON
X2SON
SOT-23
X2SON
SOT-23
SC70
X2SON
SOT-23
SOT-23
SOT-23
X2SON
SOT-23
SOT-23
SOT-23
X2SON
Pack Materials-Page 3
4203227/C
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.12 MAX
1.4
1.2
B
A
0.1 C
PIN 1
INDEX AREA
1
0.95
3.04
2.80
1.9
3
2
0.5
0.3
3X
0.10
0.01
(0.95)
TYP
0.2
C A B
0.25
GAGE PLANE
0.20
0.08
TYP
0.6
0.2
TYP
SEATING PLANE
0 -8 TYP
4214838/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214838/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0003A
SOT-SC70 - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR SC70
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
0.65
1.3
2.15
1.85
3
0.30
3X
0.15
C A B
0.1
0.0
0.1
(0.9)
TYP
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
TYP
TYP
0
SEATING PLANE
4220745/B 06/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0003A
SOT-SC70 - 1.1 max height
SMALL OUTLINE TRANSISTOR SC70
PKG
3X (0.95)
3X (0.4)
1
SYMM
3
(1.3)
(0.65)
2
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220745/B 06/2020
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0003A
SOT-SC70 - 1.1 max height
SMALL OUTLINE TRANSISTOR SC70
PKG
3X (0.95)
3X (0.4)
1
SYMM
3
(1.3)
(0.65)
2
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4220745/B 06/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.25)
4X (0.05)
0.25 0.1
2
1
4
5
NOTE 3
2X
0.48
3
2X (0.26)
0.27
0.17
4X
0.27
0.17
0.1 C A B
0.05 C
(0.06)
3X
0.32
0.23
4223102/B 09/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
(
0.1)
SYMM
4X (0.42)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
(0.21) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/B 09/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
5
1
4X (0.22)
SYMM
(
0.24)
4X (0.26)
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
3
2
4
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4223102/B 09/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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