TLV75528PDQNT [TI]
具有使能功能的 500mA、高 PSRR、低 IQ、低压降 (LDO) 稳压器 | DQN | 4 | -40 to 125;型号: | TLV75528PDQNT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有使能功能的 500mA、高 PSRR、低 IQ、低压降 (LDO) 稳压器 | DQN | 4 | -40 to 125 稳压器 |
文件: | 总44页 (文件大小:2576K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
TLV755P 500mA、低 IQ、小型低压降稳压器
1 特性
3 说明
1
•
•
•
输入电压范围:1.45V 至 5.5V
TLV755P 是一款超小型低静态电流、低压差稳压器
(LDO),可提供 500mA 拉电流,具有良好的线路和负
载瞬态性能。TLV755P 经过优化,支持 1.45V 至
5.5V 的输入电压 范围, 因此适用于各种应用。为最大
程度地降低成本和解决方案尺寸,该器件可在 0.6V 至
5V 范围内提供固定输出电压,以支持现代微控制器
(MCU) 更低的内核电压。此外,TLV755P 具备带有使
能功能的低 IQ,从而可将待机功耗降至最低。该器件
具有 内部软启动功能,旨在降低浪涌电流,因此可为
负载提供受控电压并在启动过程中最大程度地降低输入
电压压降。关断时,该器件可主动降低输出以快速释放
输出并确保已知的启动状态。
低 IQ:25µA(典型值)
低压降:
–
在 500mA 下为 238mV(最大值)(VOUT 为
3.3V)
•
•
•
•
•
•
•
输出精度:1%(85°C 时达到最大)
内置软启动功能,具有单调 VOUT上升
折返电流限制
有源输出放电
高 PSRR:100kHz 时为 46dB
与 1µF 陶瓷输出电容器搭配使用时可保持稳定
封装:
–
–
–
2.9mm × 1.6mm SOT-23-5
1mm x 1mm X2SON-4
2mm × 2mm WSON-6
TLV755P 在与支持小尺寸总体解决方案的小型陶瓷输
出电容器搭配使用时,可保持稳定。高精度带隙与误差
放大器支持 1% 的典型精度。所有器件版本均具有集
成的热关断保护、电流限制和低压锁定 (UVLO) 功能。
TLV755P 具有内部折返电流限制,有助于在发生短路
时减少热耗散。
2 应用
•
•
•
•
•
•
•
机顶盒、电视和游戏机
便携式和电池供电类设备
台式机、笔记本和超级本
平板电脑和遥控器
器件信息(1)
器件型号
封装
X2SON (4)
封装尺寸(标称值)
1.00mm x 1.00mm
2.90mm × 1.60mm
2.00mm × 2.00mm
白色家电和电器
TLV755P
SOT-23 (5)
SON (6)
电网基础设施和保护继电器
摄像头模块和图像传感器
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
典型应用
启动波形
7
6
5
4
3
2
1
0
175
150
125
100
75
VOUT
VIN
VEN
IOUT
IN
OUT
TLV755P
COUT
CIN
EN
GND
ON
OFF
50
25
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Time (ms)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBVS320
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 19
Power Supply Recommendations...................... 20
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Examples................................................... 21
11 器件和文档支持 ..................................................... 22
11.1 器件支持................................................................ 22
11.2 接收文档更新通知 ................................................. 22
11.3 社区资源................................................................ 22
11.4 商标....................................................................... 22
11.5 静电放电警告......................................................... 22
11.6 术语表 ................................................................... 22
12 机械、封装和可订购信息....................................... 22
7
4 修订历史记录
Changes from Original (November 2017) to Revision A
Page
•
已发布至生产 .......................................................................................................................................................................... 1
2
Copyright © 2017–2018, Texas Instruments Incorporated
TLV755P
www.ti.com.cn
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
5 Pin Configuration and Functions
DQN Package
4-Pin X2SON
Top View
DBV Package
5-Pin SOT-23
Top View
OUT
GND
1
4
3
IN
IN
GND
EN
1
2
3
5
OUT
NC
5
4
2
EN
Not to scale
Not to scale
DRV Package
6-Pin WSON With Exposed Thermal Pad
Top View
OUT
NC
1
2
3
6
5
4
IN
Thermal
Pad
NC
EN
GND
Not to scale
NC = no internal connection.
Pin Functions
PIN
I/O
DESCRIPTION
NAME
EN
DQN
DBV
DRV
Enable pin. Drive EN greater than VHI to turn on the regulator.
Drive EN less than VLO to place the LDO into shutdown mode.
3
2
3
2
4
3
I
GND
—
Ground pin.
Input pin. A capacitor with a value of 1 µF or larger is required from
this pin to ground(1). See the Input and Output Capacitor Selection
section for more information.
IN
4
—
1
1
4
5
6
2, 5
1
I
NC
OUT
—
O
No internal connection.
Regulated output voltage pin. A capacitor with a value of 1 µF or larger
is required from this pin to ground(1). See the Input and Output
Capacitor Selection section for more information.
Connect the thermal pad to a large-area ground plane.
The thermal pad is internally connected to GND.
Thermal pad
Pad
—
Pad
—
(1) The nominal input and output capacitance must be greater than 0.47 µF; throughout this document the nominal derating on these
capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 0.47 µF.
Copyright © 2017–2018, Texas Instruments Incorporated
3
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
-40
MAX
6.0
UNIT
V
Supply voltage, VIN
Enable voltage, VEN
6.0
VIN + 0.3(2)
V
Output voltage, VOUT
V
Operating junction temperature range, TJ
Storage temperature, Tstg
150
°C
°C
-65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The absolute maximum rating is VIN + 0.3 V or 6.0 V, whichever is smaller
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.45
0.6
0
NOM
MAX
5.5
UNIT
V
VIN
Input voltage
VOUT
VEN
IOUT
CIN
Output voltage
5.0
V
Enable voltage
5.5
V
Output current
0
500
mA
μF
μF
kHz
°C
Input capacitor
1
COUT
fEN
Output capacitor
Enable toggle frequency
Junction temperature
1
200
10
TJ
–40
125
6.4 Thermal Information
TLV755
DQN (X2SON) DBV (SOT-23-
5)
DRV (SON)
THERMAL METRIC(1)
UNIT
4 PINS
168.4
139.1
101.4
5.6
5 PINS
231.1
118.4
64.4
6 PINS
100.2
108.5
64.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
28.4
10.4
ψJB
101.7
88.4
63.8
64.8
RθJC(bot)
N/A
34.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017–2018, Texas Instruments Incorporated
TLV755P
www.ti.com.cn
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
6.5 Electrical Characteristics
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 μF, unless otherwise noted. All typical values at TJ = 25°C.
PARAMETER
Input voltage
TEST CONDITIONS
MIN
1.45
0.6
TYP
MAX
5.5
UNIT
V
VIN
VOUT
Output voltage
5.0
V
-40°C ≤ TJ ≤ +85°C, DBV and DRV package
-1%
1%
V
OUT ≥ 1.0 V, DQN package
-40°C ≤ TJ ≤ +85°C; 0.6 V ≤ VOUT < 1.0 V
OUT ≥ 1 V
-1.2%
-10
1.2%
10
Output accuracy
mV
V
-1.5%
-15
1.5%
15
0.6 V ≤ VOUT < 1 V
mV
mV
(ΔVOUT)
ΔVIN
Line regulation
Load regulation
VOUT + 0.5 V ≤ VIN ≤ 5.5 V, VOUT > 1.5 V
2
DQN package
0.036
0.060
0.044
25
0.1 mA ≤
ΔVOUT/
ΔIOUT
IOUT ≤ 500 DBV package
V/A
mA
DRV package
TJ = 25°C, IOUT = 0 mA
14
31
33
40
IGND
Ground current
-40°C ≤ TJ ≤ +85°C, IOUT = 0 mA
-40°C ≤ TJ ≤ +125°C, IOUT = 0 mA
µA
µA
VEN ≤ 0.4 V, 1.4 V ≤ VIN ≤ 5.5 V, -40°C ≤ TJ ≤
ISHDN
Shutdown current
0.1
1
+125°C
VIN
VOUT
VDO(MAX)
0.25 V
=
+
VOUT = VOUT - 0.2 V, VOUT ≤ 1.5V
560
560
720
865
ICL
Output current limit
mA
mA
+
VOUT = 0.9 x VOUT, 1.5V < VOUT ≤ 4.5V
720
865
ISC
Short circuit current limit
VOUT = 0 V
355
675
600
550
500
350
325
250
150
0.6 V ≤ VOUT < 0.8 V
0.8 V ≤ VOUT < 1.0V
1.0 V ≤ VOUT < 1.2 V
1.2 V ≤ VOUT < 1.5 V
1.5 V ≤ VOUT < 1.8 V
1.8 V ≤ VOUT < 2.5 V
2.5 V ≤ VOUT < 3.3 V
3.3 V ≤ VOUT < 5.0 V
0.6 V ≤ VOUT < 0.8 V
0.8 V ≤ VOUT < 1.0 V
1.0 V ≤ VOUT < 1.2 V
1.2 V ≤ VOUT < 1.5 V
1.5 V ≤ VOUT < 1.8 V
1.8 V ≤ VOUT < 2.5 V
2.5 V ≤ VOUT < 3.3 V
3.3 V ≤ VOUT < 5.0 V
1080
930
780
630
400
380
300
215
1140
985
825
665
425
400
325
238
IOUT
=
500mA,
-40°C ≤ TJ
≤ +85°C
VDO
Dropout voltage
mV
IOUT
=
500mA,
-40°C ≤ TJ
≤ +125°C
f = 1 kHz, VIN = VOUT + 1 V, IOUT = 50 mA
f = 100 kHz, VIN = VOUT + 1 V, IOUT = 50 mA
f = 1 MHz, VIN = VOUT + 1 V, IOUT = 50 mA
52
46
52
PSRR
Power-supply rejection ratio
dB
BW = 10 Hz to 100 kHz; VOUT = 1.2 V, IOUT = 500
mA
VN
Output noise voltage
Undervoltage lockout
71.5
1.3
µVRMS
V
VUVLO
VIN rising
1.21
1.44
VUVLO,HY Undervoltage lockout
VIN falling
40
mV
hysteresis
ST
tSTR
VHI
Startup time
550
µs
V
EN pin high voltage (enabled)
1
Copyright © 2017–2018, Texas Instruments Incorporated
5
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
www.ti.com.cn
Electrical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 μF, unless otherwise noted. All typical values at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VLO
IEN
EN pin low voltage (enabled)
Enable pin current
0.3
EN = 5.5V
10
165
155
nA
Shutdown, temperature increasing
Reset, temperature decreasing
TSD
Thermal shutdown
Pulldown resistance
°C
RPULLDO
WN
VIN = 5.5V
120
Ω
6
版权 © 2017–2018, Texas Instruments Incorporated
TLV755P
www.ti.com.cn
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
6.6 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
100
80
60
40
20
0
100
80
60
40
20
0
VIN
3.8 V
4 V
4.3 V
4.5 V
5 V
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 500 mA
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
VIN = 4.3 V, VOUT = 3.3 V, COUT = 1 µF
VOUT = 3.3 V, COUT = 1 µF, IOUT = 500 mA
图 1. PSRR vs Frequency and IOUT
图 2. PSRR vs Frequency and VIN
10
100
80
60
40
20
0
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
COUT
COUT = 1 mF
1 mF, 143 mVRMS
10 mF, 150 mVRMS
22 mF, 149 mVRMS
100 mF, 146 mVRMS
COUT = 10 mF
COUT = 22 mF
COUT = 100 mF
0.005
0.002
0.001
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
VIN = 4.3 V, VOUT = 3.3 V, IOUT = 500 mA
VOUT = 3.3 V, VRMS BW = 10 Hz to 100 kHz
图 3. PSRR vs Frequency and COUT
图 4. Output Spectral Noise Density vs
Frequency and COUT
10
220
200
180
160
140
120
100
80
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
IOUT
10 mA, 140 mVRMS
50 mA, 142 mVRMS
100 mA, 142 mVRMS
500 mA, 143 mVRMS
0.005
60
0.002
0.001
40
10
100
1k
10k
100k
1M
10M
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Frequency (Hz)
Output Voltage (V)
VOUT = 3.3 V, IOUT = 500 mA, COUT = 1 µF, VRMS BW = 10 Hz to
100 kHz
IOUT = 500 mA, COUT = 1 µF, VRMS BW = 10 Hz to 100 kHz
图 5. Output Spectral Noise Density vs
图 6. Output Noise Voltage vs VOUT
Frequency and IOUT
版权 © 2017–2018, Texas Instruments Incorporated
7
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
www.ti.com.cn
Typical Characteristics (接下页)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
6
5
4
3
2
1
0
3.328
3.4
3.375
3.35
3.325
3.3
640
560
480
400
320
240
160
80
VIN
VOUT
VOUT
IOUT
3.32
3.312
3.304
3.296
3.288
3.28
3.275
3.25
3.225
3.2
0
0
40 80 120 160 200 240 280 320 360 400 440 480
Time (Ps)
0
20
Time (ms)
40
50
VOUT = 3.3 V, COUT = 1 µF, VIN slew rate = 1 V/µs
VIN = 5 V, VOUT = 3.3 V, COUT = 1 µF, IOUT slew rate = 1 A/µs
图 7. Line Transient
图 8. 3.3-V, 1-mA to 500-mA Load Transient
6
5
4
3
2
1
0
6
VIN
VOUT
VIN
VOUT
5
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
1
2
3
4
5
6
7
8
9
10
Time (ms)
Time (ms)
图 9. VIN = VEN Power-Up
图 10. VIN = VEN Shutdown
7
175
150
125
100
75
10
VOUT
VIN
VEN
IOUT
-40°C
0°C
25°C
85°C
125°C
5
0
6
5
4
3
2
1
0
-5
-10
-15
-20
-25
-30
50
25
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
Time (ms)
VIN = 5 V, IOUT = 100 mA, VEN slew rate = 1 V/µs, VOUT = 3.3 V
图 11. EN Startup
图 12. Load Regulation vs IOUT
8
版权 © 2017–2018, Texas Instruments Incorporated
TLV755P
www.ti.com.cn
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
Typical Characteristics (接下页)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
200
175
150
125
100
75
200
160
120
80
-40èC
0èC
25èC
85èC
125èC
-40èC
0èC
25èC
85èC
125èC
50
40
25
0
0
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
图 13. 3.3-V Dropout Voltage vs IOUT
图 14. 5.0-V Dropout Voltage vs IOUT
1
1
-40èC
0èC
25èC
85èC
125èC
-40èC
0èC
25èC
85èC
125èC
0.75
0.5
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
5
5.1
5.2
5.3
5.4
5.5
Input Voltage (V)
Input Voltage (V)
VOUT = 3.3 V, IOUT = 1 mA
IOUT = 1 mA, VOUT = 5 V
图 16. 5.0-V Accuracy vs VIN (Line Regulation)
图 15. 3.3-V Regulation vs VIN (Line Regulation)
800
700
600
500
400
300
200
100
0
650
600
550
500
450
400
350
300
250
200
150
100
50
-40èC
0èC
25èC
85èC
125èC
-40°C
0°C
25°C
85°C
125°C
0
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
0
1
2
3
4
5
6
Input Voltage (V)
VOUT = 3.3 V, IOUT = 1 mA
图 17. IGND vs IOUT
图 18. IGND vs VIN
版权 © 2017–2018, Texas Instruments Incorporated
9
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
www.ti.com.cn
Typical Characteristics (接下页)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
350
300
250
200
150
100
50
300
250
200
150
100
50
-40èC
0èC
25èC
85èC
125èC
-40èC
0èC
25èC
85èC
125èC
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Input Voltage (V)
Input Voltage (V)
VOUT = 3.3 V, IOUT = 0 mA
VEN = 0 V
图 19. IQ vs VIN
图 20. ISHDN vs VIN
180
160
140
120
100
80
800
750
700
650
600
550
500
60
40
20
EN Negative
EN Positive
0
-40
-20
0
20
40
60
80
100 120 140
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
VEN = 0 V
图 21. ISHDN vs Temperature
图 22. Enable Threshold vs Temperature
250
200
150
100
50
1.4
1.36
1.32
1.28
1.24
1.2
-40èC
0èC
25èC
85èC
125èC
UVLO Negative
-25
UVLO Positive
0
-50
0
25
50
75
100
125
0
1
2
3
4
5
6
Temperature (èC)
Input Voltage (V)
VEN = 5.5 V
图 24. UVLO Threshold vs Temperature
图 23. IEN vs VIN
10
版权 © 2017–2018, Texas Instruments Incorporated
TLV755P
www.ti.com.cn
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
Typical Characteristics (接下页)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
600
550
500
450
400
350
300
250
200
150
100
50
3.5
-40èC
0èC
85èC
125èC
3
25èC
2.5
2
1.5
1
-40°C
0°C
25°C
85°C
125°C
0.5
0
0
0
100
200
300
400
500
600
700
800
0
1
2
3
4
5
Output Current (mA)
Output Current (mA)
图 25. VOUT vs IOUT Pulldown Resistor
图 26. 3.3-V Foldback Current Limit, VOUT vs IOUT
版权 © 2017–2018, Texas Instruments Incorporated
11
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TLV755P belongs to a family of next-generation, low-dropout regulators (LDOs). This device consumes low
quiescent current and delivers excellent line and load transient performance. The TLV755P is optimized for a
wide variety of applications by supporting an input voltage range from 1.45 V to 5.5 V. To minimize cost and
solution size, the device is offered in fixed output voltages ranging from 0.6 V to 5 V to support the lower core
voltages of modern microcontrollers (MCUs).
This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature
is –40°C to +125°C.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
R1
Thermal
Shutdown
œ
+
UVLO
120 Ω
R2
EN
Bandgap
GND
Logic
NOTE: R2 = 550 kΩ, R1 = adjustable.
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) circuit disables the output until the input voltage is greater than the rising UVLO
voltage (VUVLO). This circuit ensures that the device does not exhibit any unpredictable behavior when the supply
voltage is lower than the operational range of the internal circuitry. When VIN is less than VUVLO, the output is
connected to ground with a 120-Ω pulldown resistor.
7.3.2 Enable (EN)
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VHI. Turn off the device by
forcing the EN pin below VLO. If shutdown capability is not required, connect EN to IN.
The device has an internal pulldown that connects a 120-Ω resistor to ground when the device is disabled. The
discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel
with the 120-Ω pulldown resistor. 公式 1 calculates the time constant τ:
120 · RL
t =
· COUT
120 + RL
(1)
12
版权 © 2017–2018, Texas Instruments Incorporated
TLV755P
www.ti.com.cn
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
Feature Description (接下页)
The EN pin is independent of the input pin (IN), but if the EN pin is driven to a higher voltage than VIN, the
current into the EN pin increases. This effect is illustrated in 图 23. When the EN voltage is higher than the input
voltage there is an increased current flow into the EN pin. If this increased flow causes problems in the
application, sequence the EN pin after VIN is high, or to tie EN to VIN to prevent this flow increase from
happening. If EN is driven to a higher voltage than VIN, limit the frequency on EN to below 10 kHz.
7.3.3 Internal Foldback Current Limit
The TLV755P has an internal current limit that protects the regulator during fault conditions. The current limit is a
hybrid scheme with brick wall until the output voltage is less than 0.4 V × VOUT(NOM). When the voltage drops
below 0.4 V × VOUT(NOM), a foldback current limit is implemented that scales back the current as the output
voltage approaches GND. When the output shorts, the LDO supplies a typical current of ISC. The output voltage
is not regulated when the device is in current limit. In this condition, the output voltage is the product of the
regulated current and the load resistance. When the device output shorts, the PMOS pass transistor dissipates
power [(VIN – VOUT) × ISC] until thermal shutdown is triggered and the device turns off. After the device cools
down, the internal thermal shutdown circuit turns the device back on. If the fault condition continues, the device
cycles between current limit and thermal shutdown.
The foldback current-limit circuit limits the current that is allowed through the device to current levels lower than
the minimum current limit at nominal VOUT current limit (ICL) during start up. See 图 26 for typical current limit
values. If the output is loaded by a constant-current load during start up, or if the output voltage is negative when
the device is enabled, then the load current demanded by the load may exceed the foldback current limit and the
device may not rise to the full output voltage. For constant-current loads, disable the output load until the output
has risen to the nominal voltage.
Excess inductance can cause the current limit to oscillate. Minimize the inductance to keep the current limit from
oscillating during a fault condition.
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 165°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the
junction temperature cools to approximately 155°C, the output circuitry is enabled again. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.
This cycling limits regulator dissipation that protects the circuit from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN – VOUT) voltage and the load current. For reliable operation, limit junction temperature to a maximum
of 125°C. To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
The internal protection circuitry protects against overload conditions but is not intended to be activated in normal
operation. Continuously running the device into thermal shutdown degrades device reliability.
版权 © 2017–2018, Texas Instruments Incorporated
13
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
www.ti.com.cn
7.4 Device Functional Modes
表 1 lists a comparison between the normal, dropout, and disabled modes of operation.
表 1. Device Functional Modes Comparison
PARAMETER
OPERATING MODE
VIN
EN
IOUT
IOUT < ICL
—
TJ
TJ < TSD
Normal(1)
Dropout(1)
Disabled(2)
VIN > VOUT(NOM) + VDO
VIN < VOUT(NOM) + VDO
VIN < VUVLO
VEN > VHI
VEN > VHI
VEN < VLO
TJ < TSD
TJ > TSD
—
(1) All table conditions must be met.
(2) The device is disabled when any condition is met.
7.4.1 Normal Operation
The device regulates to the nominal output voltage when all of the following conditions are met.
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO)
The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold
•
•
The output current is less than the current limit (IOUT < ICL
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD
)
)
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout. In this mode, the output voltage tracks
the input voltage. During this mode, the transient performance of the device degrades because the pass device
is in a triode state and no longer controls the output voltage of the LDO. Line or load transients in dropout can
result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
,
right after being in a normal regulation state, but not during startup), the pass-FET is driven as hard as possible
when the control loop is out of balance. During the normal time required for the device to regain regulation, VIN
VOUT(NOM) + VDO, VOUT can overshoot VOUT(NOM) during fast transients.
≥
7.4.3 Disabled
The output is shut down by forcing the enable pin below VLO. When disabled, the pass device is turned off,
internal circuits are shut down, and the output voltage is actively discharged to ground by an internal switch from
the output to ground. The active pulldown is on when sufficient input voltage is provided.
14
版权 © 2017–2018, Texas Instruments Incorporated
TLV755P
www.ti.com.cn
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TLV755P requires an output capacitance of 0.47 µF or larger for stability. Use X5R- and X7R-type ceramic
capacitors because these capacitors have minimal variation in capacitance value and equivalent series
resistance (ESR) over temperature. When selecting a capacitor for a specific application, consider the DC bias
characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. As a
general rule, ceramic capacitors must be derated by 50%. For best performance, TI recommends a maximum
output capacitance value of 200 µF.
Place a 1 µF or greater capacitor on the input pin of the LDO. Some input supplies have a high impedance.
Placing a capacitor on the input supply reduces the input impedance. The input capacitor counteracts reactive
input sources and improves transient response and PSRR. If the input supply has a high impedance over a large
range of frequencies, several input capacitors are used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are expected, or if the device is located several
inches from the input power source.
8.1.2 Dropout Voltage
The TLV755P uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales linearly with the output current because the PMOS device
functions like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as
(VIN – VOUT) approaches dropout operation. See 图 13 and 图 14 for typical dropout values.
8.1.3 Exiting Dropout
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up.
As with other LDOs, the output may overshoot on recovery from these conditions. A ramping input supply causes
an LDO to overshoot on start-up when the slew rate and voltage levels are in the correct range; see 图 27. Use
an enable signal to avoid this condition.
版权 © 2017–2018, Texas Instruments Incorporated
15
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
www.ti.com.cn
Application Information (接下页)
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VIN = VOUT(nom) + VDO
Output Voltage
Dropout
VOUT = VIN - VDO
Output Voltage in
normal regulation.
Time
图 27. Startup Into Dropout
Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are
caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to
the correct voltage for proper regulation. 图 28 illustrates what is happening internally with the gate voltage and
how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS) is
pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if a line
transient occurs while the device is in dropout, the loop is not in regulation and can cause the output to
overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If
these transients are not acceptable, then continue to add input capacitance in the system until the transient is
slow enough to reduce the overshoot.
16
版权 © 2017–2018, Texas Instruments Incorporated
TLV755P
www.ti.com.cn
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
Application Information (接下页)
Transient response
time of the LDO
Input Voltage
Load current
discharges
output
voltage
Output Voltage
VDO
Output Voltage in
normal regulation
Dropout
VOUT = VIN - VDO
VGS voltage
(pass device
fully off)
Input Voltage
VGS voltage for
normal operation
VGS voltage for
normal operation
Gate Voltage
VGS voltage in
dropout (pass device
fully on)
Time
图 28. Line Transients From Dropout
8.1.4 Reverse Current
As with most LDOs, excessive reverse current can damage this device.
Reverse current flows through the body diode on the pass element instead of the normal conducting channel. At
high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of the
following conditions:
•
•
•
Degradation caused by electromigration
Excessive heat dissipation
Potential for a latch-up condition
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT > VIN + 0.3 V:
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
版权 © 2017–2018, Texas Instruments Incorporated
17
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
www.ti.com.cn
Application Information (接下页)
If reverse current flow is expected in the application, external protection must be used to protect the device. 图
29 shows one approach of protecting the device.
Schottky Diode
Internal Body Diode
IN
OUT
Device
COUT
CIN
GND
图 29. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.5 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free of other heat-generating devices as possible that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use 公式 2 to approximate PD:
PD = (VIN – VOUT) × IOUT
(2)
Power dissipation must be minimized to achieve greater efficiency. This minimizing process is achieved by
selecting the correct system voltage rails. Proper selection helps obtain the minimum input-to-output voltage
differential. The low dropout of the device allows for maximum efficiency across a wide range of output voltages.
The main heat-conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to inner plane areas or to a bottom-side copper plane.
The maximum allowable junction temperature (TJ) determines the maximum power dissipation for the device.
According to 公式 3, power dissipation and junction temperature are most often related by the junction-to-
ambient thermal resistance (RθJA) of the combined PCB, device package, and the temperature of the ambient air
(TA).
TJ = TA + RθJA × PD
(3)
Unfortunately, this thermal resistance (RθJA) is dependent on the heat-spreading capability built into the particular
PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The RθJA value is only used as a relative measure of package thermal performance. RθJA is the sum of the
package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the
PCB copper.
18
版权 © 2017–2018, Texas Instruments Incorporated
TLV755P
www.ti.com.cn
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
Application Information (接下页)
8.1.5.1 Estimating Junction Temperature
The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of
the LDO when in-circuit on a typical PCB board application. These metrics are not thermal resistances, but offer
practical and relative means of estimating junction temperatures. These psi metrics are independent of the
copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are used in accordance with 公式 4 and are
described in the table.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as shown in 公式 2
TT is the temperature at the center-top of the device package
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(4)
8.2 Typical Application
IN
OUT
GND
1 …F
DC/DC
Converter
1 …F
TLV755P
Load
EN
ON
OFF
图 30. TLV755P Typical Application
8.2.1 Design Requirements
表 2 lists the design requirements for this application.
表 2. Design Parameters
PARAMETER
Input voltage
DESIGN REQUIREMENT
4.3 V
3.3 V
Output voltage
Input current
500 mA (maximum)
250-mA DC
70°C
Output load
Maximum ambient temperature
版权 © 2017–2018, Texas Instruments Incorporated
19
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Input Current
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.
During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use 公式
5 to calculate the current through the input.
C
OUT ´ dVOUT(t)
VOUT(t)
RLOAD
IOUT(t)
=
+
dt
where:
•
•
•
VOUT(t) is the instantaneous output voltage of the turn-on ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance
(5)
8.2.2.2 Thermal Dissipation
The junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total
power dissipation (PD). Use 公式 6 to calculate the power dissipation. Multiply PD by RθJA as 公式 7 shows and
add the ambient temperature (TA) to calculate the junction temperature (TJ).
PD = (IGND+ IOUT) × (VIN – VOUT
)
(6)
(7)
TJ = RθJA × PD + TA
Calculate the maximum ambient temperature as 公式 8 shows if the (TJ(MAX)) value does not exceed 125°C. 公式
9 calculates the maximum ambient temperature with a value of 99.95°C.
TA(MAX) = TJ(MAX) – RθJA × PD
(8)
(9)
TA(MAX) = 125°C – 100.2°C/W × (4.3 V – 3.3 V) × (0.25 A) = 99.95°C
8.2.3 Application Curve
100
80
60
40
IOUT = 10 mA
IOUT = 50 mA
20
IOUT = 100 mA
IOUT = 500 mA
0
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
VIN = 4.3 V, VOUT = 3.3 V
图 31. PSRR vs Frequency (4.3 V to 3.3 V)
9 Power Supply Recommendations
Connect a low output impedance power supply directly to the IN pin of the TLV755P. If the input source is
reactive, consider using multiple input capacitors in parallel with the 1-µF input capacitor to lower the input supply
impedance over frequency.
20
版权 © 2017–2018, Texas Instruments Incorporated
TLV755P
www.ti.com.cn
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
10 Layout
10.1 Layout Guidelines
•
•
•
Place input and output capacitors as close as possible to the device.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
10.2 Layout Examples
OUT
IN
1
4
COUT
CIN
EN
3
2
GND PLANE
Represents via used for application
specific connections
图 32. Layout Example for the DQN Package
VOUT
VIN
5
1
CIN
COUT
2
3
4
EN
GND PLANE
Represents via used for
application specific connections
图 33. Layout Example for the DBV Package
VIN
VOUT
1
6
5
COUT
CIN
2
3
4
EN
GND PLANE
Represents via used for
application specific connections
图 34. Layout Example for the DRV Package
版权 © 2017–2018, Texas Instruments Incorporated
21
TLV755P
ZHCSI89A –NOVEMBER 2017–REVISED MAY 2018
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
表 3. 器件命名规则(1)(2)
产品
VOUT
xx(x) 为标称输出电压。对于分辨率为 100mV 的输出电压,订货编号中使用两位数字;否则,使用三位数
字(例如,28 = 2.8V;125 = 1.25V)。
TLV755xx(x)Pyyyz
P 表示有源输出放电功能。TLV755P 系列的所有产品在器件处于禁用状态时都可以对输出进行主动放电。
yyy 为封装标识符。
z 为封装数量。R 表示卷(3000 片),T 表示带(250 片)。
(1) 要获得最新的封装和订货信息,请参阅本文档末尾的封装选项附录,或者访问器件产品文件夹(www.ti.com.cn)。
(2) 可提供 0.6V 至 5V 范围内的输出电压(以 50mV 为单位增加)。有关器件的详细信息和供货情况,请联系制造商。
11.2 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请参阅左侧的导航栏。
22
版权 © 2017–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV75507PDQNR
TLV75507PDQNT
TLV75509PDBVR
TLV75509PDQNR
TLV75509PDQNT
TLV75509PDRVR
TLV75510PDBVR
TLV75510PDQNR
TLV75510PDQNT
TLV75510PDRVR
TLV75511PDQNR
TLV75512PDBVR
TLV75512PDQNR
TLV75512PDQNT
TLV75512PDRVR
TLV75515PDBVR
TLV75515PDQNR
TLV75515PDQNT
TLV75515PDRVR
TLV755185PDQNR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
X2SON
X2SON
SOT-23
X2SON
X2SON
WSON
SOT-23
X2SON
X2SON
WSON
X2SON
SOT-23
X2SON
X2SON
WSON
SOT-23
X2SON
X2SON
WSON
X2SON
DQN
DQN
DBV
DQN
DQN
DRV
DBV
DQN
DQN
DRV
DQN
DBV
DQN
DQN
DRV
DBV
DQN
DQN
DRV
DQN
4
4
5
4
4
6
5
4
4
6
4
5
4
4
6
5
4
4
6
4
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
KD
KD
1HAF
AX
AX
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
1HDH
1FPF
KE
NIPDAU | SN
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
KE
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
1GUH
E8
NIPDAU | SN
1FQF
AG
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
AG
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
1GVH
1FRF
KF
NIPDAU | SN
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
KF
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
1GWH
EZ
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV75518PDBVR
TLV75518PDQNR
TLV75518PDQNT
TLV75518PDRVR
TLV75519PDBVR
TLV75519PDQNR
TLV75519PDQNT
TLV75519PDRVR
TLV75525PDBVR
TLV75525PDQNR
TLV75525PDQNT
TLV75525PDRVR
TLV75528PDBVR
TLV75528PDQNR
TLV75528PDQNT
TLV75528PDRVR
TLV75529PDBVR
TLV75529PDRVR
TLV75530PDBVR
TLV75530PDQNR
TLV75530PDQNT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
X2SON
X2SON
WSON
SOT-23
X2SON
X2SON
WSON
SOT-23
X2SON
X2SON
WSON
SOT-23
X2SON
X2SON
WSON
SOT-23
WSON
SOT-23
X2SON
X2SON
DBV
DQN
DQN
DRV
DBV
DQN
DQN
DRV
DBV
DQN
DQN
DRV
DBV
DQN
DQN
DRV
DBV
DRV
DBV
DQN
DQN
5
4
4
6
5
4
4
6
5
4
4
6
5
4
4
6
5
6
5
4
4
3000 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1FSF
AI
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
AI
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
1GXH
1HBF
B5
NIPDAU | SN
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
B5
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
1HEH
1FTF
AJ
NIPDAU | SN
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
AJ
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
1GZH
1FUF
KG
NIPDAU | SN
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
KG
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU | SN
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
1H1H
1HCF
1HFH
1FVF
KI
NIPDAU | SN
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250
RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
Addendum-Page 2
KI
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV75530PDRVR
TLV75533PDBVR
TLV75533PDQNR
TLV75533PDQNT
TLV75533PDRVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
SOT-23
X2SON
X2SON
WSON
DRV
DBV
DQN
DQN
DRV
6
5
4
4
6
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1H2H
1FWF
AN
NIPDAU | SN
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU Level-1-260C-UNLIM
AN
1H3H
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV75507PDQNR
TLV75507PDQNR
TLV75507PDQNT
TLV75507PDQNT
TLV75509PDBVR
TLV75509PDQNR
TLV75509PDQNR
TLV75509PDQNT
TLV75509PDQNT
TLV75509PDRVR
TLV75510PDBVR
TLV75510PDBVR
TLV75510PDQNR
TLV75510PDQNR
TLV75510PDQNT
TLV75510PDQNT
X2SON
X2SON
X2SON
X2SON
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
SOT-23
SOT-23
X2SON
X2SON
X2SON
X2SON
DQN
DQN
DQN
DQN
DBV
DQN
DQN
DQN
DQN
DRV
DBV
DBV
DQN
DQN
DQN
DQN
4
4
4
4
5
4
4
4
4
6
5
5
4
4
4
4
3000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
9.5
8.4
9.5
8.4
8.4
8.4
9.5
8.4
9.5
8.4
8.4
8.4
9.5
8.4
9.5
8.4
1.16
1.16
1.16
1.16
3.2
1.16
1.16
1.16
1.16
3.2
0.5
0.63
0.5
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q3
Q2
Q2
Q2
Q2
Q2
Q3
Q3
Q2
Q2
Q2
Q2
250
0.63
1.4
3000
3000
3000
250
1.16
1.16
1.16
1.16
2.3
1.16
1.16
1.16
1.16
2.3
0.63
0.5
0.63
0.5
250
3000
3000
3000
3000
3000
250
1.15
1.4
3.2
3.2
3.2
3.2
1.4
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
0.5
0.63
0.5
250
0.63
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV75510PDRVR
TLV75511PDQNR
TLV75512PDBVR
TLV75512PDBVR
TLV75512PDQNR
TLV75512PDQNT
TLV75512PDQNT
TLV75512PDRVR
TLV75515PDBVR
TLV75515PDBVR
TLV75515PDQNR
TLV75515PDQNR
TLV75515PDQNT
TLV75515PDQNT
TLV75515PDRVR
TLV755185PDQNR
TLV75518PDBVR
TLV75518PDQNR
TLV75518PDQNR
TLV75518PDQNT
TLV75518PDQNT
TLV75518PDRVR
TLV75519PDBVR
TLV75519PDBVR
TLV75519PDQNR
TLV75519PDQNR
TLV75519PDQNT
TLV75519PDQNT
TLV75519PDRVR
TLV75525PDBVR
TLV75525PDQNR
TLV75525PDQNR
TLV75525PDQNT
TLV75525PDQNT
TLV75525PDRVR
TLV75528PDBVR
TLV75528PDBVR
TLV75528PDQNR
TLV75528PDQNR
TLV75528PDQNT
TLV75528PDQNT
WSON
X2SON
SOT-23
SOT-23
X2SON
X2SON
X2SON
WSON
SOT-23
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
X2SON
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
SOT-23
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
SOT-23
SOT-23
X2SON
X2SON
X2SON
X2SON
DRV
DQN
DBV
DBV
DQN
DQN
DQN
DRV
DBV
DBV
DQN
DQN
DQN
DQN
DRV
DQN
DBV
DQN
DQN
DQN
DQN
DRV
DBV
DBV
DQN
DQN
DQN
DQN
DRV
DBV
DQN
DQN
DQN
DQN
DRV
DBV
DBV
DQN
DQN
DQN
DQN
6
4
5
5
4
4
4
6
5
5
4
4
4
4
6
4
5
4
4
4
4
6
5
5
4
4
4
4
6
5
4
4
4
4
6
5
5
4
4
4
4
3000
3000
3000
3000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
9.5
8.4
8.4
9.5
9.5
8.4
8.4
8.4
8.4
9.5
8.4
8.4
9.5
8.4
9.5
8.4
8.4
9.5
8.4
9.5
8.4
8.4
8.4
8.4
9.5
9.5
8.4
8.4
8.4
8.4
9.5
9.5
8.4
8.4
8.4
8.4
9.5
8.4
8.4
9.5
2.3
1.16
3.2
2.3
1.16
3.2
1.15
0.5
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q3
Q3
Q2
Q2
Q2
Q2
Q3
Q3
Q2
Q2
Q2
Q2
Q2
Q2
Q3
Q2
Q2
Q2
Q2
Q2
Q3
Q3
Q2
Q2
Q2
Q2
Q2
Q3
Q2
Q2
Q2
Q2
Q2
Q3
Q3
Q2
Q2
Q2
Q2
1.4
3.2
3.2
1.4
1.16
1.16
1.16
2.3
1.16
1.16
1.16
2.3
0.5
0.5
250
0.63
1.15
1.4
3000
3000
3000
3000
3000
250
3.2
3.2
3.2
3.2
1.4
1.16
1.16
1.16
1.16
2.3
1.16
1.16
1.16
1.16
2.3
0.5
0.63
0.63
0.5
250
3000
3000
3000
3000
3000
250
1.15
0.5
1.16
3.2
1.16
3.2
1.4
1.16
1.16
1.16
1.16
2.3
1.16
1.16
1.16
1.16
2.3
0.63
0.5
0.63
0.5
250
3000
3000
3000
3000
3000
250
1.15
1.4
3.2
3.2
3.2
3.2
1.4
1.16
1.16
1.16
1.16
2.3
1.16
1.16
1.16
1.16
2.3
0.63
0.5
0.5
250
0.63
1.15
1.4
3000
3000
3000
3000
250
3.2
3.2
1.16
1.16
1.16
1.16
2.3
1.16
1.16
1.16
1.16
2.3
0.63
0.5
0.5
250
0.63
1.15
1.4
3000
3000
3000
3000
3000
250
3.2
3.2
3.2
3.2
1.4
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
0.5
0.63
0.63
0.5
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV75528PDRVR
TLV75529PDBVR
TLV75529PDRVR
TLV75530PDBVR
TLV75530PDBVR
TLV75530PDQNR
TLV75530PDQNR
TLV75530PDQNT
TLV75530PDQNT
TLV75530PDRVR
TLV75533PDBVR
TLV75533PDQNR
TLV75533PDQNT
TLV75533PDQNT
TLV75533PDRVR
WSON
SOT-23
WSON
SOT-23
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
SOT-23
X2SON
X2SON
X2SON
WSON
DRV
DBV
DRV
DBV
DBV
DQN
DQN
DQN
DQN
DRV
DBV
DQN
DQN
DQN
DRV
6
5
6
5
5
4
4
4
4
6
5
4
4
4
6
3000
3000
3000
3000
3000
3000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
9.5
9.5
8.4
8.4
8.4
9.5
8.4
9.5
8.4
2.3
3.2
2.3
3.2
1.15
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q3
Q2
Q3
Q3
Q2
Q2
Q2
Q2
Q2
Q3
Q2
Q2
Q2
Q2
2.3
2.3
1.15
1.4
3.2
3.2
3.2
3.2
1.4
1.16
1.16
1.16
1.16
2.3
1.16
1.16
1.16
1.16
2.3
0.63
0.5
0.5
250
0.63
1.15
1.4
3000
3000
3000
250
3.2
3.2
1.16
1.16
1.16
2.3
1.16
1.16
1.16
2.3
0.5
0.63
0.5
250
3000
1.15
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV75507PDQNR
TLV75507PDQNR
TLV75507PDQNT
TLV75507PDQNT
TLV75509PDBVR
TLV75509PDQNR
TLV75509PDQNR
TLV75509PDQNT
TLV75509PDQNT
TLV75509PDRVR
TLV75510PDBVR
TLV75510PDBVR
TLV75510PDQNR
TLV75510PDQNR
TLV75510PDQNT
TLV75510PDQNT
TLV75510PDRVR
TLV75511PDQNR
X2SON
X2SON
X2SON
X2SON
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
SOT-23
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
X2SON
DQN
DQN
DQN
DQN
DBV
DQN
DQN
DQN
DQN
DRV
DBV
DBV
DQN
DQN
DQN
DQN
DRV
DQN
4
4
4
4
5
4
4
4
4
6
5
5
4
4
4
4
6
4
3000
3000
250
184.0
183.0
184.0
183.0
210.0
183.0
184.0
183.0
184.0
210.0
210.0
210.0
184.0
183.0
184.0
183.0
210.0
184.0
184.0
183.0
184.0
183.0
185.0
183.0
184.0
183.0
184.0
185.0
185.0
185.0
184.0
183.0
184.0
183.0
185.0
184.0
19.0
20.0
19.0
20.0
35.0
20.0
19.0
20.0
19.0
35.0
35.0
35.0
19.0
20.0
19.0
20.0
35.0
19.0
250
3000
3000
3000
250
250
3000
3000
3000
3000
3000
250
250
3000
3000
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV75512PDBVR
TLV75512PDBVR
TLV75512PDQNR
TLV75512PDQNT
TLV75512PDQNT
TLV75512PDRVR
TLV75515PDBVR
TLV75515PDBVR
TLV75515PDQNR
TLV75515PDQNR
TLV75515PDQNT
TLV75515PDQNT
TLV75515PDRVR
TLV755185PDQNR
TLV75518PDBVR
TLV75518PDQNR
TLV75518PDQNR
TLV75518PDQNT
TLV75518PDQNT
TLV75518PDRVR
TLV75519PDBVR
TLV75519PDBVR
TLV75519PDQNR
TLV75519PDQNR
TLV75519PDQNT
TLV75519PDQNT
TLV75519PDRVR
TLV75525PDBVR
TLV75525PDQNR
TLV75525PDQNR
TLV75525PDQNT
TLV75525PDQNT
TLV75525PDRVR
TLV75528PDBVR
TLV75528PDBVR
TLV75528PDQNR
TLV75528PDQNR
TLV75528PDQNT
TLV75528PDQNT
TLV75528PDRVR
TLV75529PDBVR
TLV75529PDRVR
TLV75530PDBVR
SOT-23
SOT-23
X2SON
X2SON
X2SON
WSON
SOT-23
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
X2SON
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
SOT-23
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
SOT-23
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
SOT-23
WSON
SOT-23
DBV
DBV
DQN
DQN
DQN
DRV
DBV
DBV
DQN
DQN
DQN
DQN
DRV
DQN
DBV
DQN
DQN
DQN
DQN
DRV
DBV
DBV
DQN
DQN
DQN
DQN
DRV
DBV
DQN
DQN
DQN
DQN
DRV
DBV
DBV
DQN
DQN
DQN
DQN
DRV
DBV
DRV
DBV
5
5
4
4
4
6
5
5
4
4
4
4
6
4
5
4
4
4
4
6
5
5
4
4
4
4
6
5
4
4
4
4
6
5
5
4
4
4
4
6
5
6
5
3000
3000
3000
250
210.0
210.0
184.0
184.0
183.0
210.0
210.0
210.0
184.0
183.0
183.0
184.0
210.0
184.0
210.0
183.0
184.0
183.0
184.0
210.0
210.0
210.0
183.0
184.0
184.0
183.0
210.0
210.0
183.0
184.0
184.0
183.0
210.0
210.0
210.0
184.0
183.0
183.0
184.0
210.0
210.0
210.0
210.0
185.0
185.0
184.0
184.0
183.0
185.0
185.0
185.0
184.0
183.0
183.0
184.0
185.0
184.0
185.0
183.0
184.0
183.0
184.0
185.0
185.0
185.0
183.0
184.0
184.0
183.0
185.0
185.0
183.0
184.0
184.0
183.0
185.0
185.0
185.0
184.0
183.0
183.0
184.0
185.0
185.0
185.0
185.0
35.0
35.0
19.0
19.0
20.0
35.0
35.0
35.0
19.0
20.0
20.0
19.0
35.0
19.0
35.0
20.0
19.0
20.0
19.0
35.0
35.0
35.0
20.0
19.0
19.0
20.0
35.0
35.0
20.0
19.0
19.0
20.0
35.0
35.0
35.0
19.0
20.0
20.0
19.0
35.0
35.0
35.0
35.0
250
3000
3000
3000
3000
3000
250
250
3000
3000
3000
3000
3000
250
250
3000
3000
3000
3000
3000
250
250
3000
3000
3000
3000
250
250
3000
3000
3000
3000
3000
250
250
3000
3000
3000
3000
Pack Materials-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV75530PDBVR
TLV75530PDQNR
TLV75530PDQNR
TLV75530PDQNT
TLV75530PDQNT
TLV75530PDRVR
TLV75533PDBVR
TLV75533PDQNR
TLV75533PDQNT
TLV75533PDQNT
TLV75533PDRVR
SOT-23
X2SON
X2SON
X2SON
X2SON
WSON
SOT-23
X2SON
X2SON
X2SON
WSON
DBV
DQN
DQN
DQN
DQN
DRV
DBV
DQN
DQN
DQN
DRV
5
4
4
4
4
6
5
4
4
4
6
3000
3000
3000
250
210.0
183.0
184.0
184.0
183.0
210.0
210.0
184.0
183.0
184.0
210.0
185.0
183.0
184.0
184.0
183.0
185.0
185.0
184.0
183.0
184.0
185.0
35.0
20.0
19.0
19.0
20.0
35.0
35.0
19.0
20.0
19.0
35.0
250
3000
3000
3000
250
250
3000
Pack Materials-Page 6
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
1
1.05
0.95
PIN 1
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
+0.12
-0.1
0.05
0.00
0.48
(0.05) TYP
NOTE 6
2
1
3
EXPOSED
THERMAL PAD
5
2X 0.65
(0.07) TYP
NOTE 5
4
0.28
PIN 1 ID
(OPTIONAL)
NOTE 4
4X
0.15
(0.11)
0.3
0.2
0.1
C A B
0.05
C
0.30
0.15
3X
4215302/E 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.86)
SYMM
SEE DETAIL
4X
4X (0.36)
(0.03)
4
4X (0.21)
1
5
SYMM
(0.65)
4X (0.18)
2
3
(
0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE
LAND PATTERN EXAMPLE
SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
1
4X (0.21)
5
SYMM
(0.65)
SOLDER MASK
EDGE
4X (0.22)
2
3
(
0.45)
4X (0.235)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
相关型号:
©2020 ICPDF网 联系我们和版权申明