TLV751180280PDSQR [TI]
500mA、低 IQ、高 PSRR、可调节、双通道低压降 (LDO) 稳压器 | DSQ | 10 | -40 to 125;型号: | TLV751180280PDSQR |
厂家: | TEXAS INSTRUMENTS |
描述: | 500mA、低 IQ、高 PSRR、可调节、双通道低压降 (LDO) 稳压器 | DSQ | 10 | -40 to 125 光电二极管 输出元件 稳压器 调节器 |
文件: | 总32页 (文件大小:3043K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TLV751
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
采用小尺寸封装的 TLV751 双通道 500mA 高精度可调节 LDO
1 特性
3 说明
1
•
•
输入电压范围:1.5V 至 6.0V
输出电压范围:
TLV751 是一款双通道、可调节的 500mA 低压降
(LDO) 稳压器。该器件采用小型 10 引脚 2mm × 2mm
WSON 封装,具有 25µA 的静态电流,同时提供快速
的线路和负载瞬态响应。TLV751 具有 130mV 的低压
降,有助于提高总功率效率。
–
–
可调节电压范围:0.55V 至 5.5V
固定电压范围:0.65V 至 5.0V
•
低压降:
–
500mA 时为 130mV(最大值)(3.3 VOUT)
TLV751 具有宽输入和输出电压范围以及出色的输出电
流能力,当用于小型印刷电路板 (PCB) 上时,可帮助
支持各类 应用 ,如传感器电源、辅助电源轨和具有更
低内核电压的现代微控制器。
•
•
•
•
高输出精度:1.5%(温度范围内最大值)
IQ:25µA(典型值)
内置软启动功能,具有单调 VOUT 上升
封装:
TLV751 可与小型陶瓷输出电容器搭配使用,从而减小
整体解决方案尺寸。精密带隙和误差放大器在整个温度
范围内具有高精度,最大值为 1.5%。该器件包括集成
的热关断、电流限制、有源输出放电和欠压锁定
(UVLO) 功能。TLV751 的内部过流保护限制功能可在
发生短路事件时减少热耗散。
–
2mm × 2mm WSON-10 (DSQ)
•
有源输出放电
2 应用
•
•
•
•
•
•
•
微服务器和塔式服务器
门窗传感器
便携式销售终端 (EPOS)
可穿戴健身和活动监测仪
扫描仪
器件信息(1)
器件型号
TLV751
封装
封装尺寸(标称值)
WSON (10)
2.00mm × 2.00mm
Wi-Fi 接入点
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
通信模块
(2) 预览器件。
典型应用
VIN
VOUT
INx
OUTx
½
CIN
R1
R2
COUT
TLV751P
GND
FBx
VEN
ENx
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBVS385
TLV751
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 21
Power Supply Recommendations...................... 23
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 8
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 器件和文档支持 ..................................................... 24
11.1 器件支持................................................................ 24
11.2 接收文档更新通知 ................................................. 24
11.3 社区资源................................................................ 24
11.4 商标....................................................................... 24
11.5 静电放电警告......................................................... 24
11.6 Glossary................................................................ 24
12 机械、封装和可订购信息....................................... 24
7
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Original (December 2019) to Revision A
Page
•
Changed pins 6, 8, 9, and 10 in Pin Configuration and Functions section ............................................................................ 3
2
Copyright © 2019–2020, Texas Instruments Incorporated
TLV751
www.ti.com.cn
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
5 Pin Configuration and Functions
DSQ Package
10-Pin Adjustable WSON
Top View
FB1
GND
EN1
GND
EN2
1
2
3
4
5
10
9
OUT1
IN1
Thermal
Pad
8
OUT2
FB2
7
6
IN2
Not to scale
DSQ Package
10-Pin Adjustable WSON
Top View
TOP View
N/C
OUT1
1
2
3
4
5
10
9
GND
EN1
GND
EN2
IN1
OUT2
N/C
Thermal
Pad
8
7
GND
IN2
6
Pin Functions
PIN
I/O
DESCRIPTION
NAME
DSQ
Enable pin. Drive EN1 greater than VEN1(HI) to turn on the regulator.
Drive EN1 less than VEN1(LO) to put the low-dropout (LDO) regulator into shutdown mode.
EN1
3
Input
Input
Enable pin. Drive EN2 greater than VEN2(HI) to turn on the regulator.
Drive EN2 less than VEN2(LO) to put the LDO into shutdown mode.
EN2
5
1
For the adjustable TLV75101, this pin is used as an input to the control loop error
amplifier and is used to set the output voltage of the LDO.
FB1/ NC
—
For the fixed TLV751xxxyyy, this is not connected internally.
For the adjustable TLV75101, this pin is used as an input to the control loop error
amplifier and is used to set the output voltage of the LDO.
For the fixed TLV751xxxyyy, this is not connected internally.
FB2 / NC
GND
7
—
—
2, 4
Ground pin
Input pin. For best transient response and to minimize input impedance, use the
recommended value or larger ceramic capacitor from IN to ground; see the
Recommended Operating Conditions table and the Input and Output Capacitor Selection
section. Place the input capacitor as close to the output of the device as possible.
IN1
9
Input
Copyright © 2019–2020, Texas Instruments Incorporated
3
TLV751
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
DSQ
Input pin. For best transient response and to minimize input impedance, use the
recommended value or larger ceramic capacitor from IN to ground; see the
Recommended Operating Conditions table and the Input and Output Capacitor Selection
section. Place the input capacitor as close to the output of the device as possible.
IN2
6
Input
Regulated output voltage pin. A capacitor is required from OUT to ground for stability.
For best transient response, use the nominal recommended value or larger ceramic
capacitor from OUT to ground; see the Recommended Operating Conditions table and
the Input and Output Capacitor Selection section. Place the output capacitor as close to
output of the device as possible.
OUT1
10
8
Output
Regulated output voltage pin. A capacitor is required from OUT to ground for stability.
For best transient response, use the nominal recommended value or larger ceramic
capacitor from OUT to ground; see the Recommended Operating Conditions table and
the Input and Output Capacitor Selection section. Place the output capacitor as close to
output of the device as possible.
OUT2
Output
—
Thermal pad
Connect the thermal pad to a large area GND plane for improved thermal performance.
4
Copyright © 2019–2020, Texas Instruments Incorporated
TLV751
www.ti.com.cn
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–40
MAX
UNIT
Supply, VIN
6.5
Voltage
Enable, VEN
6.5
V
Feedback, VFB
Output, VOUT
2
VIN + 0.3(2)
150
Voltage
Operating junction, TJ
Storage, Tstg
Temperature
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
(2) The absolute maximum rating is VIN + 0.3V or 6.5 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM ispossible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM ispossible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.5
0.55
0
NOM
MAX
6.0
UNIT
V
VIN
Input voltage
VOUT
IOUT
CIN
Output voltage
5.5
V
Output current
500
mA
µF
µF
V
Input capacitor
1
COUT
VEN
fEN
Output capacitor(1)
Enable voltage(2)
Enable toggle frequency
Junction temperature
1
220
6.0
10
0
kHz
°C
TJ
–40
125
(1) Minimum derated capacitance of 0.47 µF is required for stability
(2) If VEN > VIN, when VEN > VUVLO rising (min), the input pin (IN) must sink 1 mA of current to avoid the device being turn on with floating
input pin.
Copyright © 2019–2020, Texas Instruments Incorporated
5
TLV751
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
6.4 Thermal Information
TLV751P
DSQ (WSON)
10 PINS
74.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
90.5
39.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.8
ψJB
39.7
RθJC(bot)
17
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
6.5 Electrical Characteristics
At operating temperature range (TJ = –40°C to +125°C),VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever isgreater), IOUT = 1 mA,
VEN =VIN, and CIN = COUT = 1 uF(unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VFB
Feedback voltage
TJ = 25°C
TJ = 25°C
0.55
V
–0.5%
–1.5%
0.5%
1.5%
Output accuracy(1)
–40°C ≤ TJ ≤ +125°C; VOUT(NOM) + 0.5 V(2) ≤ VIN ≤ 6.0 V
VOUT(NOM) + 0.5 V(2) ≤ VIN ≤ 6.0 V
0.1 mA ≤ IOUT ≤ 500 mA, VIN = VOUT + 0.5 V(3)
Line regulation
Load regulation
2
0.030
25
mV
V/A
µA
µA
µA
µA
TJ = 25°C
10
31
35
1
IGND
Ground current
IOUT = 0 mA
–40°C ≤ TJ ≤ +125°C
ISHDN
IFB
Shutdown current
VEN ≤ 0.3 V, 1.5 V ≤ VIN ≤ 6.0 V
0.1
Feedback pin current
0.01
0.1
VOUT = VOUT(NOM) – 0.2 V,
VOUT < 1.5 V
530
530
720
720
310
865
865
400
VIN = 2 V with VOUT < 1 V;
otherwise VIN = VOUT(NOM) + 1.0 V
ICL
Output current limit
mA
mA
VOUT = 0.9 V × VOUT(NOM)
,
VOUT ≥ 1.5 V
VIN = 2 V with VOUT < 1 V;
otherwise VIN = VOUT(NOM) + 1.0 V
ISC
Short-circuit current limit
VOUT = 0 V
0.65 V ≤ VOUT < 0.8 V
0.8 V ≤ VOUT < 1.0 V
1.0 V ≤ VOUT < 1.2 V
1.2 V ≤ VOUT < 1.5 V
1.5 V ≤ VOUT < 1.8 V
1.8 V ≤ VOUT < 2.5 V
2.5 V ≤ VOUT < 3.3 V
3.3 V ≤ VOUT ≤ 5.5 V
f = 1 kHz
720
585
420
285
180
140
102
95
880
750
570
400
240
190
140
130
IOUT = 500 mA,
–40°C ≤ TJ ≤ +125°C,
VOUT = 0.95 × VOUT(NOM)
VDO
Dropout voltage
mV
50
VIN = VOUT(NOM) + 1.0 V,
IOUT = 50 mA
PSRR
Power-supply rejection ratio
f = 100 kHz
45
dB
f = 1 MHz
30
Vn
Output noise voltage
Undervoltage lockout
BW = 10 Hz to 100 kHz, VOUT = 0.9 V
53
µVRMS
VIN rising
VIN falling
1.21
1.17
1.33
1.29
1.47
1.42
V
V
VUVLO
VUVLO,
Undervoltage lockout hysteresis VIN hysteresis
45
mV
HYST
tSTR
Startup time
From EN low-to-high transition to VOUT = VOUT(NOM) × 95%
500
700
0.3
µs
V
VEN(HI)
VEN(LO)
IEN
EN pin high voltage
EN pin low voltage
Enable pin current
1.0
V
VIN = EN = 6.0 V
10
nA
(1) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
(2) VIN = 1.5 V for VOUT < 1.0 V.
(3) VIN = 2.0 V for VOUT < 1.5 V.
6
Copyright © 2019–2020, Texas Instruments Incorporated
TLV751
www.ti.com.cn
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
Electrical Characteristics (continued)
At operating temperature range (TJ = –40°C to +125°C),VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever isgreater), IOUT = 1 mA,
VEN =VIN, and CIN = COUT = 1 uF(unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RPULL
Pulldown resistance
VIN = 6.0 V
95
Ω
DOWN
Shutdown, temperature increasing
Reset, temperature decreasing
170
155
TSD
Thermal shutdown
°C
版权 © 2019–2020, Texas Instruments Incorporated
7
TLV751
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
6.6 Typical Characteristics
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
0.6
0.45
0.3
0.6
0.45
0.3
0.15
0
0.15
0
-0.15
-0.3
-0.45
-0.6
-0.15
-0.3
-0.45
-0.6
TJ
œ20èC
0èC
TJ
œ20èC
0èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
3.8
4
4.2 4.4 4.6 4.8
5
Input Voltage (V)
5.2 5.4 5.6 5.8
6
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Input Voltage (V)
VOUT = 0.55 V, IOUT = 1 mA
VOUT = 3.3 V, IOUT = 1 mA
图 1. 3.3-V Line Regulation vs VIN
图 2. 0.55-V Line Regulation vs VIN
0.3
0.2
0.1
0
160
140
120
100
80
TJ
œ20èC
0èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
60
-0.1
-0.2
-0.3
40
TJ
œ20èC
0èC
20
œ50èC
œ40èC
25èC
85èC
125èC
150èC
0
5.5
5.6
5.7
5.8
5.9
6
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
Input Voltage (V)
VOUT = 5.5 V, IOUT = 1 mA
图 3. 5.5-V Line Regulation vs VIN
图 4. 3.3-V Dropout Voltage vs IOUT
900
870
840
810
780
750
720
690
660
160
140
120
100
80
TJ
œ20èC
0èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
60
40
TJ
œ20èC
0èC
20
œ50èC
œ40èC
25èC
85èC
125èC
150èC
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
图 5. 0.55-V Dropout Voltage vs IOUT
图 6. 5.5-V Dropout Voltage vs IOUT
8
版权 © 2019–2020, Texas Instruments Incorporated
TLV751
www.ti.com.cn
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
Typical Characteristics (接下页)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
1,000
900
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
TJ
œ20èC
0èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
TJ
œ20èC
0èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
0.5
1
1.5
2
2.5
3
Output Voltage (V)
3.5
4
4.5
5
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
IOUT = 500 mA
图 7. VDO vs VOUT
图 8. IGND vs IOUT
2,100
1,800
1,500
1,200
900
560
480
400
320
240
160
80
TJ
œ20èC
0èC
TJ
œ20èC
0èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
600
300
0
0
-300
-80
0
0.6 1.2 1.8 2.4
3
Input Voltage (V)
3.6 4.2 4.8 5.4
6
0
0.6 1.2 1.8 2.4
3
Input Voltage (V)
3.6 4.2 4.8 5.4
6
VEN = 0 V
VOUT = 3.3 V, IOUT = 0 mA
图 9. ISHDN vs VIN
图 10. IGND vs VIN
1
0.75
0.5
0.6
0.45
0.3
TJ
œ20èC
0èC
TJ
œ20èC
0èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
0.25
0
0.15
0
-0.25
-0.5
-0.75
-1
-0.15
-0.3
-0.45
-0.6
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
VIN = 3.8 V, VOUT = 3.3 V
VIN = 2 V, VOUT = 0.55 V
图 11. 3.3-V Load Regulation vs IOUT
图 12. 0.55-V Load Regulation vs IOUT
版权 © 2019–2020, Texas Instruments Incorporated
9
TLV751
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
Typical Characteristics (接下页)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
640
560
480
400
320
240
160
80
1
0.75
0.5
TJ
œ20èC
0èC
TJ
œ20èC
0èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
œ50èC
œ40èC
25èC
85èC
125èC
150èC
0.25
0
-0.25
-0.5
-0.75
-1
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
0
0.5
1
1.5
2
2.5
3
Pulldown Current (mA)
3.5
4
4.5
5
VIN = 6 V, VOUT = 5.5 V
图 13. 5-V Load Regulation vs IOUT
图 14. VOUT vs IOUT Pulldown Resistor
840
800
760
720
680
640
600
560
520
480
440
300
250
200
150
100
50
VEN(LO)
VEN(HI)
TJ
œ20èC
0èC
œ50èC
œ40èC
125èC
85èC
125èC
150èC
0
-50
-50
-25
0
25
50
75
100
125
150
0
0.5
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
Temperature (èC)
VEN = 5.5 V
图 15. VEN(HI) and VEN(LO) vs Temperature
图 16. IEN vs VIN
14
13
12
11
10
9
25
5
TJ
-20èC
0èC
Vin
Vout
20
15
10
5
4.5
4
-50èC
-40èC
25èC
85èC
125èC
3.5
3
0
8
-5
2.5
2
7
-10
-15
-20
-25
-30
-35
-40
-45
6
5
1.5
1
4
3
2
0.5
0
1
0
0
100
200
300
400
Output Current (mA)
500
600
700
0
0.5
1
Time (ms)
1.5
2
VOUT = 0.55 V, IOUT = 1 mA, VIN slew rate = 1 V/µs
图 18. 0.55-V Line Transient
图 17. 3.3-V Foldback Current Limit vs IOUT
10
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Typical Characteristics (接下页)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
10
9.5
9
120
100
80
4
3.5
3
200
150
100
50
Iout
Vout
Vin
Vout
8.5
8
60
40
2.5
2
7.5
7
20
0
0
1.5
1
-50
6.5
6
-20
-40
-60
-80
-100
-120
-140
-160
-100
-150
-200
-250
-300
5.5
5
0.5
0
4.5
4
-0.5
-1
3.5
3
0
50 100 150 200 250 300 350 400 450 500
Time (us)
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Time (ms)
2
VIN = 3.8 V, VOUT = 3.3 V, IOUT slew rate = 1 A/µs
VOUT = 3.3 V, IOUT = 1 mA, VIN slew rate = 1 V/µs
图 20. 3.3-V, 1-mA to 500-mA Load Transient
图 19. 3.3-V Line Transient
4
200
150
100
50
4
3.5
3
200
Iout
Vout
Iout
Vout
3.5
3
150
100
50
2.5
2
2.5
2
0
0
1.5
1
-50
1.5
1
-50
-100
-150
-200
-250
-300
-100
-150
-200
-250
-300
0.5
0
0.5
0
-0.5
-1
-0.5
-1
0
50 100 150 200 250 300 350 400 450 500
Time (us)
0
50 100 150 200 250 300 350 400 450 500
Time (us)
VIN = 2 V, VOUT = 0.55 V, IOUT slew rate = 1 A/µs
VIN = 5.5 V, VOUT = 5 V, IOUT slew rate = 1 A/µs
图 21. 0.55-V, 1-mA to 500-mA Load Transient
图 22. 5-V, 1-mA to 500-mA Load Transient
5
5
4.5
4
4
3
3.5
3
2.5
2
2
1.5
1
1
0.5
0
Vout
Venable
Vin
0
Vout
Vin
-0.5
-1
-1
0
200
400
600
800
1,000
0
200
400
600
800
1,000
Time (us)
Time (us)
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 1 mA
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 1 mA
图 23. VIN Power-Up
图 24. Startup With EN
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Typical Characteristics (接下页)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
VIN = 3.5 V
VIN = 3.6 V
VIN = 3.7 V
VIN = 3.8 V
VIN = 3.9 V
VIN = 4.0 V
VIN = 4.1 V
VIN = 4.2 V
VIN = 4.3 V
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D001
VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF
VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF
图 26. PSRR vs Frequency and VIN
图 25. PSRR vs Frequency and VIN
90
90
80
70
60
50
40
30
20
10
0
VIN = 3.5 V
80
70
60
50
40
30
20
10
0
VIN = 3.6 V
VIN = 3.7 V
VIN = 3.8 V
VIN = 3.9 V
VIN = 4.0 V
VIN = 4.1 V
VIN = 4.2 V
VIN = 4.3 V
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
VOUT = 3.3 V, IOUT = 250 mA, COUT = 2.2 µF
VOUT = 3.3 V, IOUT = 250 mA, COUT = 2.2 µF
图 27. PSRR vs Frequency and VIN
图 28. PSRR vs Frequency and VIN
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
VIN = 1.9 V, VOUT = 0.9 V
VIN = 2.8 V, VOUT = 1.8 V
VIN = 4.3 V, VOUT = 3.3 V
COUT = 1 mF
COUT = 2.2 mF
COUT = 4.7 mF
COUT = 47 mF
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
IOUT = 500 mA, COUT = 2.2 µF
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA
图 29. PSRR vs Frequency
图 30. PSRR vs Frequency and COUT
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Typical Characteristics (接下页)
at operating temperature range TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and
CIN = COUT = 1 µF (unless otherwise noted)
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
CFF = 0 nF
CFF = 1 nF
CFF = 10 nF
CFF = 100 nF
ILOAD = 10 mA
ILOAD = 100 mA
ILOAD = 250 mA
ILOAD = 500 mA
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA
VIN = 3.8 V, VOUT = 3.3 V, COUT = 2.2 µF
图 31. PSRR vs Frequency and CFF
图 32. PSRR vs Frequency and ILOAD
20
20
IOUT= 10mA, 159mVRMS
IOUT= 100mA, 160mVRMS
IOUT= 500mA, 160mVRMS
CFF = 0 nF, 160 mVRMS
10
5
10
5
CFF = 1 nF, 108 mVRMS
CFF = 10 nF, 74 mVRMS
CFF = 100 nF, 44 mVRMS
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
VIN = 3.8 V, VOUT = 3.3 V, COUT = 2.2 µF,
VRMS BW = 10 Hz to 100 kHz
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 500 mA, COUT = 2.2 µF,
VRMS BW = 10 Hz to 100 kHz
图 33. Output Spectral Noise Density vs Frequency
图 34. Output Spectral Noise Density vs
Frequency and CFF
20
10
5
20
COUT = 2.2mF, 160 mVRMS
COUT = 4.7mF, 170 mVRMS
COUT = 47mF, 138 mVRMS
VIN=1.9V, VOUT=0.9V, 53mVRMS
10
VIN=2.8V, VOUT=1.8V, 96mVRMS
5
VIN=3.8V, VOUT=3.3V, 160mVRMS
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
0.02
0.01
0.02
0.01
0.005
0.005
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
VIN = 3.8 V, VOUT = 3.3 V, IOUT = 100 mA, CFF = 0 µF,
VRMS BW = 10 Hz to 100 kHz
IOUT = 500 mA, COUT = 2.2 µF, VRMS BW = 10 Hz to 100 kHz
图 35. Output Spectral Noise Density vs
图 36. Output Spectral Noise Density vs Frequency
Frequency and COUT
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7 Detailed Description
7.1 Overview
The TLV751 low-dropout regulator (LDO) consumes low quiescent current and delivers excellent line and load
transient performance. These characteristics, combined with low noise and good PSRR with low dropout voltage,
make this device ideal for portable consumer applications.
This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature
for this device is –40°C to +125°C.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
95
–
+
FB
UVLO
EN
Band Gap
GND
Logic
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TLV751 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is
greater than the rising UVLO voltage (VUVLO). This circuit ensures that the device does not exhibit any
unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. When
VIN is less than VUVLO, the output is connected to ground with a pulldown resistor (RPULLDOWN).
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI). Turn off the device
by forcing the EN pin to drop below VEN(LO). If shutdown capability is not required, connect EN to IN.
The TLV751 has an internal pulldown MOSFET that connects an RPULLDOWN resistor to ground when the device
is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the pulldown resistor (RPULLDOWN). 公式 1 calculates the time constant:
τ = ( RPULLDOWN × RL) / (RPULLDOWN + RL)
(1)
7.3.3 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a
brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the
output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the
voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output
voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-
circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
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Feature Description (continued)
For this device, VFOLDBACK = 0.4 V × VOUT(NOM)
.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the
device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If
the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
Figure 37 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
0 V
IOUT
IRATED
0 mA
ISC
ICL
Figure 37. Foldback Current Limit
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 170°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the
junction temperature cools to approximately 155°C, the output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.
This cycling limits regulator dissipation, protecting the LDO from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN – VOUT) voltage and the load current. For reliable operation, limit junction temperature to 125°C
maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
The TLV751 internal protection circuitry protects against overload conditions but is not intended to be activated in
normal operation. Continuously running the TLV751 into thermal shutdown degrades device reliability.
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
Dropout operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
TJ < TSD(shutdown)
Disabled
(any true condition
disables the device)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO
The output current is less than the current limit (IOUT < ICL
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to
less than the enable falling threshold
)
)
)
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned
off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
16
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Adjustable Device Feedback Resistors
图 38 shows that the output voltage of the TLV751 can be adjusted from 0.55 V to 5.5 V by using a resistor
divider network.
VIN
VOUT
COUT
IN
OUT
FB
½
CIN
R1
R2
TLV751P
GND
VEN
EN
图 38. Adjustable Operation
The adjustable-version device requires external feedback divider resistors to set the output voltage. VOUT is set
using the feedback divider resistors, R1 and R2, according to the following equation:
VOUT = VFB × (1 + R1 / R2)
(2)
For this device, VFB = 0.55 V.
To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100x the FB pin
current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series
resistance, as shown in the following equation:
R1 + R2 ≤ VOUT / (IFB × 100)
(3)
For this device, IFB = 10 nA.
8.1.2 Input and Output Capacitor Selection
The TLV751 requires an output capacitance of 0.47 µF or larger for stability. Use X5R- and X7R-type ceramic
capacitors because these capacitors have minimal variation in value and equivalent series resistance (ESR) over
temperature. When choosing a capacitor for a specific application, pay attention to the dc bias characteristics for
the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the
maximum recommended output capacitance is 220 µF.
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input
supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of
frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several
inches from the input power source.
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Application Information (接下页)
8.1.3 Dropout Voltage
The TLV751 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as
(VIN – VOUT) approaches dropout operation.
8.1.4 Exiting Dropout
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up.
As with other LDOs, the output may overshoot on recovery from these conditions. A ramping input supply causes
an LDO to overshoot on start-up, as shown in 图 39, when the slew rate and voltage levels are in the correct
range. Use an enable signal to avoid this condition.
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VIN = VOUT(nom) + VDO
Output Voltage
Dropout
VOUT = VIN - VDO
Output Voltage in
normal regulation.
Time
图 39. Startup Into Dropout
Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are
caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to
the correct voltage for proper regulation. 图 40 illustrates what is happening internally with the gate voltage and
how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS) is
pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if a line
transient occurs when the device is in dropout, the loop is not in regulation and can cause the output to
overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If
these transients are not acceptable, then continue to add input capacitance in the system until the transient is
slow enough to reduce the overshoot.
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Application Information (接下页)
Transient response
time of the LDO
Input Voltage
Load current
discharges
output
voltage
Output Voltage
VDO
Output Voltage in
normal regulation
Dropout
VOUT = VIN - VDO
VGS voltage
(pass device
fully off)
Input Voltage
VGS voltage for
normal operation
VGS voltage for
normal operation
Gate Voltage
VGS voltage in
dropout (pass device
fully on)
Time
图 40. Line Transients From Dropout
8.1.5 Reverse Current
As with most LDOs, excessive reverse current can damage this device.
Reverse current flows through the body diode on the pass element instead of the normal conducting channel. At
high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of the
following conditions:
•
•
•
Degradation caused by electromigration
Excessive heat dissipation
Potential for a latch-up condition
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT > VIN + 0.3 V:
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
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Application Information (接下页)
If reverse current flow is expected in the application, external protection must be used to protect the device. 图
41 shows one approach of protecting the device.
Schottky Diode
Internal Body Diode
IN
OUT
Device
COUT
CIN
GND
图 41. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.6 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit
board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no
other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. Equation 4 calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(4)
NOTE
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by
correct selection of the system voltage rails. For the lowest power dissipation use the
minimum input voltage required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to Equation 5, power dissipation and junction temperature are most often related by the junction-to-
ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA).
TJ = TA + (RθJA × PD)
(5)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes. The
junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.7 Feed-Forward Capacitor (CFF)
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to
the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance CFF
can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros and
Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.
20
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8.2 Typical Application
图 42 shows the typical application circuit for the TLV751. Input and output capacitances must be at least 1 µF.
VIN
VOUT
COUT
IN
OUT
FB
½
CIN
R1
R2
TLV751P
GND
VEN
EN
图 42. TLV751 Typical Application
8.2.1 Design Requirements
Use the parameters listed in 表 2 for typical linear regulator applications.
表 2. Design Parameters
PARAMETER
Input voltage
DESIGN REQUIREMENT
3.8 V
Output voltage
3.3 V, ±1%
Input current
500 mA (maximum)
500-mA dc
Output load
Maximum ambient temperature
70°C
8.2.2 Detailed Design Procedure
Input and output capacitors are required to achieve the output voltage transient requirements. Capacitance
values of 2.2 µF are selected to give the maximum output capacitance in a small, low-cost package; see the
Input and Output Capacitor Selection section for details.
图 38 illustrates the output voltage of the TLV751; set the output voltage using the resistor divider.
8.2.2.1 Input Current
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.
During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use 公式
6 to calculate the current through the input.
C
OUT ´ dVOUT(t)
VOUT(t)
RLOAD
IOUT(t)
=
+
dt
where:
•
•
•
VOUT(t) is the instantaneous output voltage of the turn-on ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance
(6)
版权 © 2019–2020, Texas Instruments Incorporated
21
TLV751
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
8.2.2.2 Thermal Dissipation
The junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total
power dissipation (PD). Use 公式 7 to calculate the power dissipation. Multiply PD by RθJA as 公式 8 shows and
add the ambient temperature (TA) to calculate the junction temperature (TJ).
PD = (IGND+ IOUT) × (VIN – VOUT
)
(7)
(8)
TJ = RθJA × PD + TA
Calculate the maximum ambient temperature as 公式 9 shows if the (TJ(MAX)) value does not exceed 125°C. 公式
10 calculates the maximum ambient temperature with a value of 104.93°C.
TA(MAX) = TJ(MAX) – RθJA × PD
(9)
TA(MAX) = 125°C – 80.3°C/W × (3.8 V – 3.3 V) × (0.5 A) = 104.93°C
(10)
8.2.3 Application Curve
90
80
70
60
50
40
30
ILOAD = 10 mA
20
ILOAD = 100 mA
ILOAD = 250 mA
ILOAD = 500 mA
10
0
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
VIN = 3.8 V, VOUT = 3.3 V, COUT = 2.2 µF
图 43. PSRR vs Frequency and ILOAD
22
版权 © 2019–2020, Texas Instruments Incorporated
TLV751
www.ti.com.cn
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
9 Power Supply Recommendations
Connect a low output impedance power supply directly to the IN pin of the TLV751.
10 Layout
10.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device as possible.
Use copper planes for device connections, in order to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
Do not place a thermal via directly beneath the thermal pad of the DSQ package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
10.2 Layout Example
Cff1
R1
C2
R2
OUT1
IN1
FB1
C1
GND
EN1
GND
EN2
C4
OUT2
R3
CFF2
FB2
IN2
R4
C3
GND
图 44. DSQ Package Layout Example
版权 © 2019–2020, Texas Instruments Incorporated
23
TLV751
ZHCSKJ1A –DECEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
表 3. 器件命名规则(1)(2)
产品
VOUT
yyy 为封装标识符。
TLV75101Pyyyz
z 为封装数量。R 表示卷(3000 片),T 表示带(250 片)。
aaa 为通道 1 的标称输出电压
bbb 为通道 2 的标称输出电压
yyy 为封装标识符。
TLV751aaabbbPyyyz
z 为封装数量。R 表示卷(3000 片)。
(1) 要获得最新的封装和订货信息,请参阅本文档末尾的封装选项附录,或者访问器件产品文件夹(www.ti.com.cn)。
(2) 可提供 0.6V 至 5.0V 范围内的输出电压(以 50mV 为单位增量)。有关器件的详细信息和供货情况,请联系制造商。
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
24
版权 © 2019–2020, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTLV75101PDSQR
TLV75101PDSQR
OBSOLETE
ACTIVE
WSON
WSON
DSQ
DSQ
10
10
TBD
Call TI
NIPDAU
Call TI
3000 RoHS & Green
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1XUH
1XUH
2AOH
2ALH
2A1H
2AMH
2ANH
Samples
Samples
Samples
Samples
Samples
Samples
Samples
TLV75101PDSQT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
DSQ
DSQ
DSQ
DSQ
DSQ
DSQ
10
10
10
10
10
10
250 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TLV751120280PDSQR
TLV751180280PDSQR
TLV751180300PDSQR
TLV751180330PDSQR
TLV751330500PDSQR
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV75101PDSQR
TLV75101PDSQT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSQ
DSQ
DSQ
DSQ
DSQ
DSQ
DSQ
10
10
10
10
10
10
10
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
TLV751120280PDSQR
TLV751180280PDSQR
TLV751180300PDSQR
TLV751180330PDSQR
TLV751330500PDSQR
3000
3000
3000
3000
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV75101PDSQR
TLV75101PDSQT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSQ
DSQ
DSQ
DSQ
DSQ
DSQ
DSQ
10
10
10
10
10
10
10
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
TLV751120280PDSQR
TLV751180280PDSQR
TLV751180300PDSQR
TLV751180330PDSQR
TLV751330500PDSQR
3000
3000
3000
3000
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DSQ0010A
WSON - 0.8 mm max height
S
C
A
L
E
5
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
0.9 0.1
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
5
6
SYMM
1.5 0.1
11
2X 1.6
8X 0.4
1
PIN 1 ID
10
0.25
0.15
10X
0.4
0.2
10X
0.1
C A B
0.05
4218906/A 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSQ0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SEE SOLDER MASK
DETAIL
10X (0.5)
10X (0.2)
SYMM
10
1
(1.5)
8X (0.4)
11
SYMM
(0.5)
(R0.05) TYP
5
6
(
0.2) TYP
VIA
(1.9)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218906/A 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSQ0010A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.5)
10X (0.2)
(0.85)
10
1
8X (0.4)
11
SYMM
(1.38)
(R0.05) TYP
5
6
SYMM
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 11
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4218906/A 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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