TLV5510INS [TI]
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER; 2.7 V至3.6 V的8位高速模拟数字转换器
| 型号： | TLV5510INS |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总19页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
†
PW OR NS PACKAGE
(TOP VIEW)
8-Bit Resolution
Integral Linearity Error
±0.75 LSB Max (25°C)
OE
DGND
D1(LSB)
D2
DGND
1
24
23
22
21
20
19
18
17
16
15
14
13
±1 LSB Max (–35°C to 85°C)
REFB
2
Differential Linearity Error
± 0.5 LSB (25°C)
REFBS
AGND
3
4
±0.75 LSB Max (–35°C to 85°C)
D3
AGND
5
D4
ANALOG IN
6
Maximum Conversion Rate
10 Mega-Samples per Second
(MSPS) Min
D5
V
7
DDA
REFT
D6
8
D7
REFTS
9
2.7-V to 3.6-V Single-Supply Operation
D8(MSB)
V
10
11
DDA
Low Power Consumption . . . 42 mW Typ at
3 V
V
V
DDD
CLK 12
DDA
V
DDD
Low Voltage Replacement for CXD1175
†
Also available in tape and reel and
ordered as the TLV5510INSR.
Applications
Communications
AVAILABLE OPTIONS
PACKAGE
Digital Imaging
T
A
Video Conferencing
High-Speed Data Conversion
TSSOP (PW)
SOP (NS)
TLV5510INS
TLV5510IPW
–35°C to 85°C
description
The TLV5510isaCMOS8-bitresolutionsemiflashanalog-to-digitalconverter(ADC)witha2.7-Vto3.6-Vsingle
power supply and an internal reference voltage source. It converts a wide band analog signal (such as a video
signal) to a digital signal at a sampling rate of dc to 10 MHz.
functional block diagram
Resistor
Reference
Divider
OE
REFB
200 Ω
NOM
Lower Sampling
Comparators
(4 Bit)
REFT
Lower Encoder
(4 Bit)
D1(LSB)
D2
REFBS
Lower Data
Latch
60 Ω
NOM
D3
AGND
AGND
D4
Lower Sampling
Comparators
(4 Bit)
Lower Encoder
(4 Bit)
V
DDA
D5
D6
40 Ω
NOM
Upper Data
Latch
D7
REFTS
ANALOG IN
Upper Sampling
Comparators
(4 Bit)
Upper Encoder
(4 Bit)
D8(MSB)
Clock
Generator
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT
EQUIVALENT OF EACH DIGITAL INPUT
EQUIVALENT OF EACH DIGITAL OUTPUT
V
DDA
V
DDD
V
DDD
D1–D8
OE, CLK
ANALOG IN
AGND
DGND
DGND
Terminal Functions
TERMINAL
NAME NO.
AGND
I/O
DESCRIPTION
20, 21
19
Analog ground
Analog input
Clock input
ANALOG IN
CLK
I
I
12
DGND
D1–D8
OE
2, 24
3–10
1
Digital ground
O
I
Digital data out. D1:LSB, D8:MSB
Output enable. When OE = low, data is enabled. When OE = high, D1 – D8 is high impedance.
V
V
14, 15, 18
11, 13
23
Analog supply voltage
DDA
Digital supply voltage
DDD
REFB
I
I
Reference voltage in (bottom)
REFBS
22
Reference voltage (bottom). When using the internal voltage divider to generate a nominal 2-V reference,
this terminal is shorted to the REFB terminal and the REFTS terminal is shorted to the REFT terminal (see
Figure 21).
REFT
17
16
Reference voltage in (top)
REFTS
Reference voltage (top). When using the internal voltage divider to generate a nominal 2-V reference, this
terminal is shorted to the REFT terminal and the REFBS terminal is shorted to the REFB terminal (see
Figure 21).
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DDA DDD
Reference voltage input range, REFT, REFB, REFBS, REFTS . . . . . . . . . . . . . . . . . . . . . . . . . AGND to V
Analog input voltage range, V
Digital input voltage range, V
Digital output voltage range, V
Operating free-air temperature range, T
Storage temperature range, T
DDA
DDA
DDD
DDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to V
I(ANLG)
I(DGTL)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to V
O(DGTL)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –35°C to 85°C
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
recommended operating conditions
MIN
2.7
NOM
MAX
3.6
UNIT
V
V
–AGND
–DGND
3
3
0
DDA
V
Supply voltage
2.7
3.6
DDD
AGND–DGND
–100
REFB+2
0
100
mV
V
Reference input voltage (top), REFT
VDDA–0.3
REFT–2
REFT
Reference input voltage (bottom), REFB
0.6
V
Analog input voltage range, V
I(ANLG)
(see Note 1)
V
REFB
2.5
High-level input voltage, V
IH
V
Low-level input voltage, V
0.5
V
IL
Pulse duration, clock high, t
10
10
ns
ns
MHz
w(H)
Pulse duration, clock low, t
w(L)
Clock frequency, f
(CLK)
10
Sampling frequency, f
10 MSPS
s
NOTE 1: REFT – REFB ≤ 2.4 V maximum
electrical characteristics at V
A
= V
= 3 V, REFT = 2.5 V, REFB = 0.5 V, f
= 10 MHz,
DDD
DDA
(CLK)
T = 25°C (unless otherwise noted)
digital I/O
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
High-level input current
Low-level input current
High-level output current
Low-level output current
V
V
= MAX,
= MAX,
V
V
V
V
= V
= 0
5
5
IH
DDD
IH
DDD
µA
IL
DDD
IL
OE = GND,
OE = GND,
= MIN,
= MIN,
V
V
= V
DDD
= 0.4 V
–0.5 V
–1.6
2.6
OH
OL
DDD
DDD
OH
mA
OL
High-level high-impedance-state
output leakage current
I
OE = V
OE = V
,
,
V
= MAX
= MIN
V
= V
= 0
15
15
OZH
DDD
DDD
OH
DDD
µA
Low-level high-impedance-state
output leakage current
I
V
DDD
V
OL
OZL
DDD
†
Conditions marked MIN or MAX are as stated in recommended operating conditions.
power
†
PARAMETER
TEST CONDITIONS
MIN
TYP
4
MAX
10
UNIT
mA
I
I
Supply current
f
sin
= 1 MHz sine wave, reference resistor dissipation is separate
DD
Reference voltage current ∆REF = REFT – REFB = 2 V
6
10
14
mA
ref
†
Conditions marked MIN or MAX are as stated in recommended operating conditions.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
electrical characteristics at V
= V
= 3 V, REFT = 2.5 V, REFB = 0.5 V, f
= 10 MHz,
DDD
DDA
(CLK)
T = 25°C (unless otherwise noted) (continued)
A
static performance
PARAMETER
†
TEST CONDITIONS
MIN
TYP
MAX
0.72
2.4
UNIT
Self-bias (1), at REFB
0.54
1.8
0.60
2
Short REFB to REFBS, Short REFT to REFTS
Self-bias (1), REFT – REFB
Self-bias (2), at REFT
V
Short REFB to AGND,
Short REFT to REFTS
rms
2.25
140
2.5
200
16
3
R
C
Reference voltage resistor
Analog input capacitance
Between REFT and REFB
260
Ω
ref
i
V
= 1.5 V + 0.07 V
pF
I(ANLG)
T
= 25°C
±0.3 ±0.75
±1
f
= 10 MHz,
A
(CLK)
V = 0.5 V to 2.5 V
Integral nonlinearity (INL)
T
= –35°C to 85°C
T = 25°C
A
I
A
LSB
±0.2
±0.5
±0.75
–68
f
= 10 MHz,
(CLK)
V = 0.5 V to 2.5 V
Differential nonlinearity (DNL)
T
A
= –35°C to 85°C
I
E
E
Zero-scale error
Full-scale error
∆REF = REFT – REFB = 2 V
∆REF = REFT – REFB = 2 V
–18
–20
–43
0
mV
mV
ZS
20
FS
†
Conditions marked MIN or MAX are as stated in recommended operating conditions.
operating characteristics at V
A
= V
= 3 V, REFT = 2.5 V, REFB = 0.5 V, f
= 10 MHz,
DDD
DDA
(CLK)
T = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
f = 1-kHz ramp wave form,
MIN
TYP
MAX
UNIT
I
f
Maximum conversion rate
Analog input bandwidth
0.2
10 MSPS
conv
V
= 0.5 V – 2.5 V
I(ANLG)
At – 1 dB
At – 3 dB
17
36
18
30
4
MHz
MHz
ns
BW
t
t
t
Digital output delay time
Aperture jitter time
C
≤ 10 pF (see Note 1 and Figure 1)
30
d(D)
L
ps
AJ
Sampling delay time
ns
d(s)
t
Enable time, OE↓ to valid data
C
C
= 10 pF
= 10 pF
15
10
ns
ns
en
L
L
t
Disable time, OE↑ to high impedance
dis
T
= 25°C
41
41
38
38
38
37
A
Input tone = 1 MHz
Input tone = 1.4 MHz
Input tone = 1.4 MHz
Full range
= 25°C
Spurious free dynamic range (SFDR)
dB
dB
T
A
Full range
= 25°C
T
A
SNR
Signal-to-noise ratio
Full range
NOTE 2:
C includes probe and jig capacitance.
L
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
t
t
w(L)
w(H)
CLK (Clock)
ANALOG IN
(Input Signal)
N+2
N+1
N–2
N+4
N
N+3
D1–D8
(Output Data)
N–3
N–1
N
N+1
t
pd
Figure 1. I/O Timing Diagram
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
ANALOG INPUT BANDWIDTH
SAMPLING FREQUENCY
0
12
T
V
V
V
= 25°C
A
–1
= 2.7 V,
DDA
10
8
= 0.5 V,
= 2.5 V,
REFB
REFT
–2
Fclk = 10 MHz
–3
–4
–5
6
4
T
= 25°C
A
–6
–7
–8
V
V
V
= 2.7 V,
DDA
= 0.5 V,
= 2.5 V,
REFB
REFT
2
0
Fclk = 10 MHz
0
1
10
2
10
0
2
4
6
8
10
12
10
f – Input Frequency – MHz
I
Sampling Frequency – MHz
Figure 2
Figure 3
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
60
T
= 25°C
A
V
V
V
= 3 V,
DDA
50
= 0.5 V,
= 2.5 V,
REFB
REFT
Fclk = 10 MHz
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
Input Frequency – MHz
Figure 4
DIFFERENTIAL NONLINEARITY
vs
SAMPLES
(Under Recommended Operating Conditions)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
20
40
60
80
100
120
140
160
180
200
220
240 253
Samples
Figure 5
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
TEMPERATURE
6.5
V
V
V
= 3 V,
DDA
= 0.5 V,
= 2.5 V,
REFB
REFT
6.45
6.4
Fclk = 10 MHz,
f
= 1 MHz
sin
6.35
6.3
6.25
–40
–20
0
20
40
60
80
Ambient Temperature – °C
Figure 6
INTEGRAL NONLINEARITY
vs
SAMPLES
(Under Recommended Operating Conditions)
0.75
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.75
0
20
40
60
80
100
120
140
160
180
200
220
240 254
Samples
Figure 7
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORMER
vs
FREQUENCY
(Under Recommended Operating Conditions)
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
f – Frequency – MHz
Figure 8
INTEGRAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
FREQUENCY
FREQUENCY
1.8
1.6
1.8
V
V
V
V
= 2.7 V,
V
= 2.7 V,
= 2.7 V,
= 2.5 V,
DDD
DDA
DDD
1.6
= 2.7 V,
= 2.5 V,
V
V
V
DDA
REFT
REFB
T
A
= 25°C
REFT
REFB
1.4
1.2
1
= 0.5 V
1.4
1.2
1
= 0.5 V
T
A
= 25°C
T
A
= –35°C
0.8
0.6
T
A
= 85°C
0.8
0.6
T
A
= –35°C
T
A
= 85°C
0.4
0.4
0.2
0
0.2
0
5
7
9
11
13
15
17
19
21
5
7
9
11
13
15
17
19
21
f
– Frequency – MHz
f
– Frequency – MHz
CLK
CLK
Figure 9
Figure 10
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS
INTEGRAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
FREQUENCY
FREQUENCY
1.8
1.6
1.8
1.6
V
V
V
V
= 3 V,
= 3 V,
DDD
DDA
V
V
V
V
= 3 V,
= 3 V,
DDD
DDA
= 2.5 V,
= 0.5 V
REFT
REFB
= 2.5 V,
= 0.5 V
REFT
REFB
1.4
1.2
1
1.4
1.2
1
T
A
= 25°C
T
A
= 25°C
0.8
0.6
0.8
0.6
T
A
= 85°C
T
A
= 85°C
0.4
T
A
= –35°C
0.4
T
= –35°C
A
0.2
0
0.2
0
5
7
9
11
13
15
17
19
21
5
7
9
f
11
13
15
17
19
21
f
– Frequency – MHz
CLK
– Frequency – MHz
CLK
Figure 11
Figure 12
INTEGRAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
FREQUENCY
FREQUENCY
1.8
1.6
1.8
1.6
V
V
V
V
= 3.3 V,
= 3.3 V,
DDD
DDA
V
V
V
V
= 3.3 V,
= 3.3 V,
DDD
DDA
= 2.5 V,
= 0.5 V
REFT
REFB
= 2.5 V,
= 0.5 V
REFT
REFB
1.4
1.2
1
1.4
1.2
1
T
A
= 25°C
T
A
= 25°C
0.8
0.6
0.8
0.6
T
A
= 85°C
T
A
= 85°C
0.4
0.4
T
A
= –35°C
0.2
0
0.2
0
T
A
= –35°C
5
7
9
11
13
15
17
19
21
5
7
9
11
13
15
17
19
21
f
– Frequency – MHz
CLK
f
CLK
– Frequency – MHz
Figure 13
Figure 14
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
INPUT SINEWAVE FREQUENCY
EFFECTIVE NUMBER OF BITS
vs
INPUT SINEWAVE FREQUENCY
8
7.5
7
8
7.5
7
V
DDD
V
DDA
= 2.7 V,
= 2.7 V
V
DDD
V
DDA
= 3 V,
= 3 V
T
= –35°C
A
T
= –35°C
= 85°C
A
6.5
6
6.5
6
T
A
= 25°C
T
A
= 25°C
T
A
5.5
5
5.5
5
T
= 85°C
A
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
0.2
0.4
0.6
0.8
1
1.2
1.4
f – Input Sinewave Frequency – MHz
f – Input Sinewave Frequency – MHz
Figure 15
Figure 16
EFFECTIVE NUMBER OF BITS
vs
INPUT SINEWAVE FREQUENCY
8
7.5
7
V
V
= 3.3 V,
= 3.3 V
DDD
DDA
T
= –35°C
A
T
A
= 25°C
T
A
= 85°C
6.5
6
5.5
5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
f – Input Sinewave Frequency – MHz
Figure 17
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
APPLICATION INFORMATION
The following notes are design recommendations that should be used with the TLV5510.
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
RF breadboarding or printed-circuit-board (PCB) techniques should be used throughout the evaluation and
production process. Breadboards should be copper clad for bench evaluation.
Since AGND and DGND are connected internally, the ground lead in must be kept as noise free as possible.
A good method to use is twisted-pair cables for the supply lines to minimize noise pickup. An analog and
digital ground plane should be used on PCB layouts when additional logic devices are used. The AGND
and DGND terminals of the device should be tied to the analog ground plane.
V
to AGND and V
to DGND should be decoupled with 1-µF and 0.01-µF capacitors, respectively,
DDA
DDD
placed as close as possible to the appropriate device terminals. A ceramic chip capacitor is recommended
for the 0.01-µF capacitor. Care should be exercised to assure a solid noise-free ground connection for the
analog and digital grounds.
V
, AGND, and ANALOG IN terminals should be shielded from the higher frequency terminals, CLK and
DDA
D0–D7. If possible, AGND traces should be placed on both sides of the ANALOG IN traces on the PCB for
shielding.
In testing or application of the device, the resistance of the driving source connected to the analog input
should be 10 Ω or less within the analog frequency range of interest.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
APPLICATION INFORMATION
V
DDA
3.3 V
V
DDD
3.3 V
FB2
+
C10
FB3
FB1
14
C3
C8
C9
13
11
V
DV
DV
DDA
DDD
DDD
C4
C5
15
18
V
DDA
V
DDA
16
17
10
9
REFTS
REFT
D8
D7
D6
D5
D4
D3
D2
D1
C6
8
7
From Clamp
Output
6
5
4
3
C1
R1
19
Video Input
Buffer
ANALOG IN
(2V
)
PP
C2
A
22
23
20
21
12
REFBS
REFB
CLK
OE
C7
1
2
AGND
AGND
DGND
DGND
24
D
Output Enable
Clock
LOCATION
C1, C3, C4 –C9
C2
DESCRIPTION
0.1 µF Capacitor
10 pF Capacitor
47 µF Capacitor
Ferrite bead
C10
FB1, FB2, FB3
R1
75 Ω Resistor
Figure 18. Application and Test Schematic Using Internal Reference
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
PRINCIPLES OF OPERATION
functional description
The TLV5510 is a semiflash ADC featuring two lower comparator blocks of four bits each.
As shown in Figure 19, input voltage V (1) is sampled with the falling edge of CLK1 to the upper comparators
I
block and the lower comparators block(A), S(1). The upper comparators block finalizes the upper data UD(1)
with the rising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1)
corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the rising
edge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. According
to the above internal operation described, output data is delayed 2.5 clocks from the analog input voltage
sampling point.
Input voltage V (2) is sampled with the falling edge of CLK2. UD(2) is finalized with the rising edge of CLK3, and
I
LD(2) is finalized with the rising edge of CLK4 at the lower comparators block(B). OUT(2) is output with the rising
edge of CLK5.
V (1)
I
V (2)
I
V (3)
I
V (4)
I
ANALOG IN
(Sampling Points)
CLK1
CLK2
S(2)
CLK3
S(3)
CLK4
S(4)
CLK (Clock)
S(1)
C(1)
C(2)
C(3)
C(4)
Upper Comparators Block
Upper Data
UD(0)
UD(1)
RV(1)
UD(2)
RV(2)
UD(3)
RV(3)
RV(0)
Lower Reference Voltage
S(1)
H(1)
C(1)
S(3)
H(3)
C(3)
Lower Comparators Block (A)
Lower Data (A)
LD(–1)
LD(1)
H(0)
C(0)
S(2)
H(2)
C(2)
S(4)
H(4)
Lower Comparators Block (B)
Lower Data (B)
LD(–2)
LD(0)
LD(2)
OUT(–2)
OUT(–1)
OUT(0)
OUT(1)
D1–D8 (Data Output)
Figure 19. Internal Functional Timing Diagram
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
PRINCIPLES OF OPERATION
functional description (continued)
TheMSBcomparatorblockconvertsonthefallingedgeofeachappliedclockcycle. TheLSBcomparatorblocks
CB-A and CB-B convert on the falling edges of the first and second following clock cycles, respectively. The
timing diagram of the conversion algorithm is shown in Figure 19.
analog input operation
The analog input stage to the TLV5510 is a chopper-stabilized comparator and is equivalently shown below:
φ2
S2
φ1
To Encoder Logic
To Encoder Logic
V
DDA
C
C
s
s
φ2
φ2
S3
φ1
φ1
φ1
φ2
ANALOG IN
S1
ref(N)
V
S(N)
To Encoder Logic
C
s
Figure 20. External Connections for Using the Internal Reference Resistor Divider
Figure 20 depicts the analog input for the TLV5510. The switches shown are controlled by two internal clocks,
φ1 and φ2. These are nonoverlapping clocks that are generated from the CLK input. During the sampling period,
φ1, S1isclosedandtheinputsignalisappliedtoonesideofthesamplingcapacitor, C . Alsoduringthesampling
s
period, S2 through S(N) are closed. This sets the comparator input to approximately 2.5 V. The delta voltage
is developed across C . During the comparison phase, φ2, S1 is switched to the appropriate reference voltage
s
for the bit value N, i.e., V
. S2 is opened and V
– VC toggles the comparator output to the appropriate
ref(N)
ref(N) s
digital 1 or 0. The small resistance values for the switch, S1, and small value of the sampling capacitor combine
to produce the wide analog input bandwidth of the TLV5510. The source impedance driving the analog input
of the TLV5510 should be less than 100 Ω across the range of input frequency spectrum.
reference inputs – REFB, REFT, REFBS, REFTS
The range of analog inputs that can be converted are determined by REFB and REFT, REFT being the
maximum reference voltage and REFB being the minimum reference voltage. The TLV5510 is tested with
REFT = 2.5 V or 2 V and REFB = 0.5 V or 0 V producing a 2-V full-scale range. The TLV5510 can operate with
REFT –REFB = 2.4 V, but the power dissipation in the reference resistor increases significantly (49 mW at 3.3 V
nominally). It is recommended that a 0.1 µF capacitor be attached to REFB and REFT whether using externally
or internally generated voltages.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
PRINCIPLES OF OPERATION
internal reference voltage conversion
Three internal resistors allow the device to generate an internal reference voltage. These resistors are brought
out on terminals V , REFTS, REFT, REFB, REFBS, and AGND. Two different bias voltages are possible
DDA
without the use of external resistors.
The internal resistors are provided to develop REFT and REFB as listed in Table 1 (bias option 1) with only two
external connections. This is developed with a 3-resistor network connected to V
. When using this feature,
DDA
connect REFT to REFTS and connect REFB to REFBS. For applications where the variance associated with
is acceptable, this internal voltage reference saves space and cost (see Figure 21).
V
DDA
A second internal bias option (bias two option) is shown in Figure 22. Using this scheme REFB = AGND and
REFT is as shown in Table 1 (bias option 2). These bias voltage options can be used to provide the values listed
in the following table.
Table 1. Bias Voltage Options for Different V
DDA
BIAS VOLTAGE
BIAS OPTION
V
DDA
V
V
REFT
V
– V
REFB
REFT REFB
2.7 V
3 V
0.54
2.34
1.8
2
0.6
2.60
2.86
3.12
2.25
2.5
1
3.3 V
3.6 V
2.7 V
3 V
0.66
0.72
2.2
2.4
2.25
2.5
2.75
3
AGND
AGND
AGND
AGND
2
3.3 V
3.6 V
2.75
3
To use the internally-generated reference voltage, terminal connections should be made as shown in
Figure 21 or Figure 22.
TLV5510
18
V
DDA
R1
40 Ω NOM
REFTS
16
17
2.63 V dc
0.1 µF
0.1 µF
REFT
REFB
R
ref
200 Ω NOM
23
22
REFBS
AGND
R2
60 Ω NOM
21
Figure 21. External Connections Using the Internal Bias One Option
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
PRINCIPLES OF OPERATION
TLV5510
18
V
DDA
(Analog Supply)
R1
40 Ω NOM
REFTS
16
17
0.1 µF
REFT
REFB
R
ref
200 Ω NOM
23
22
REFBS
AGND
R2
60 Ω NOM
21
Figure 22. External Connections for Using the Internal Reference Resistor Divider
functional operation
The TLV5510 functions as shown in the Table 2.
Table 2. Functional Operation
DIGITAL OUTPUT CODE
INPUT SIGNAL
VOLTAGE
STEP
MSB
LSB
REFT
255
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
•
•
•
•
128
127
•
•
•
•
•
•
•
•
•
•
1
0
•
0
1
•
0
1
•
0
1
•
0
1
•
0
1
•
0
1
•
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
REFB
0
0
0
0
0
0
0
0
0
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
M
0,10
0,65
0,19
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
MECHANICAL DATA
NS (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
14
16
20
24
DIM
10,50
10,50
12,90
15,30
A MAX
0,51
0,35
1,27
14
M
0,25
8
9,90
9,90
12,30
14,70
A MIN
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
7
0,25
0°–10°
A
1,05
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
4040062/B 2/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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