TLV320AIC1106_14_技术文档

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SLAS357 − DECEMBER 2001

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FEATURES

APPLICATIONS

D

Designed for Analog and Digital Wireless

Handsets, Voice-Enabled Terminals, and

Telecommunications Applications

D

Digital Handset

Digital Headset

Cordless Phones

Digital PABX

D

2.7-V to 3.3-V Operation

Selectable 13-Bit Linear or 8-Bit µ-Law

Companded Conversion

Digital Voice Recording

Differential Microphone Input With External

Gain Setting

DESCRIPTION

The TLV320AIC1106 PCM codec is designed to

perform transmit encoding analog-to-digital (A/D)

conversion, receive decoding digital-to-analog (D/A)

conversion, and transmit and receive filtering for

Differential Earphone Output Capable of

Driving a 32-Ω to 8-Ω Load

Programmable Volume Control in Linear Mode

D

voice-band

communications

systems.

The

D

Microphone (MIC) and Earphone (EAR) Mute

Functions

TLV320AIC1106 device operates in either the 13-bit

linear or 8-bit companded (µ-law) mode. The PCM

codec generates its own internal clocks from a

2.048-MHz master clock input.

PW PACKAGE

D

Typical Power Dissipation of 0.03 mW in

Power-Down Mode

2.048-MHz Master Clock Rate

(TOP VIEW)

300-Hz to 3.4-kHz Passband

Low Profile 20-Terminal TSSOP Packaging

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

MICMUTE

RESET

EARMUTE

MCLK

PCMSYNC

PCMO

PCMI

DVSS

VSS

EARVSS

EAROUT+

EARVDD

EAROUT−

EARVSS

MICGAIN+

MICIN−

DVDD

LINSEL

MICGAIN−

MICIN+

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These

circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,

Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated

voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device

should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,

preferably either V

or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for

CC

Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2001, Texas Instruments Incorporated

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SLAS357 − DECEMBER 2001

functional block diagram

(16)

PCMI

(18)

PCMSYNC

(17)

PCMO

(19)

RX

Volume

Control

MCLK

PLL

TX

Filter

PCM

Interface

(12)

MICGAIN −

MIC Amp 1

(5)

(11)

Digital

Modulator

and Filter

EAROUT+

EAROUT−

MICIN +

MICIN −

+

−

Analog

Modulator

RX

Filter

EAR

AMP

MIC

Amp 2

(7)

(10)

(9)

MICGAIN +

(20)

(1)

EARMUTE

MICMUTE

(2)

RESET

LINSEL

(13)

(6)

EARVDD

Power

and

Reset

(8) (4)

EARVSS

VSS

(3)

(15)

(14)

DVSS

DVDD

RX = Receive

TX = Transmit

2

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SLAS357 − DECEMBER 2001

detailed description

power up/reset

An external reset must be applied to the active-low RESET terminal while MCLK is active to ensure reset at

power up.

reference

A precision band-gap reference voltage is generated internally and supplies all required references to operate

the transmit and receive channels.

phase-locked loop

The phase-locked loop generates the internal clock frequency required for internal digital filters and modulators

by phase-locking to 2.048-MHz master clock input.

PCM interface

The PCM interface transmits and receives data at the PCMO and PCMI terminals, respectively. The data is

transmitted or received at the MCLK speed once on each PCMSYN cycle. The PCMSYN can be driven by an

external source that is derived from the master clock and used as an interrupt to the host controller.

microphone input

The microphone input circuit consists of two differential input/differential output amplifiers (MIC Amp 1 and

MIC Amp 2). MIC Amp 1 is a low-noise differential amplifier capable of an externally set gain. MIC Amp 2 is a

differential amplifier with a fixed gain of 6 dB.

analog modulator

The transmit channel modulator is a third-order sigma-delta design.

transmit filter

The transmit filter is a digital filter designed to meet Consultive Committee on International Telegraphy and

Telephony (CCITT) G.714 requirements. The TLV320AIC1106 device operates in either the 13-bit linear or 8-bit

companded µ-law mode.

receive filter

The receive (RX) filter is a digital filter that meets CCITT G.714 requirements. The TLV320AIC1106 device

operates in either the 13-bit linear or 8-bit µ-law companded mode, which is selected at the LINSEL input.

receive volume control

In linear mode, the three least significant bits of the 16-bit PCMI data sample is used to control volume. The

volume range is −18 dB to 3 dB in 3-dB steps.

digital modulator and filter

The second-order digital modulator and filter convert the received digital PCM data to the analog output required

by the earphone interface.

earphone amplifiers

EAROUT is recommended for use as a differential output; however, it can be connected in single-ended

topology as well. Clicks and pops are suppressed from the differential output.

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SLAS357 − DECEMBER 2001

Terminal Functions

TERMINAL

I/O

DESCRIPTION

TERMINAL

EARVSS

NO.

4

I

Analog ground for EAROUT+

DVDD

14

15

20

7

Digital positive power supply

Digital negative power supply

Earphone mute

DVSS

I

EARMUTE

EAROUT−

EAROUT+

EARVDD

EARVSS

LINSEL

MCLK

I

O

I

Earphone amplifier negative output

Earphone amplifier positive output

5

6

Analog positive power supply for the earphone amplifiers

Analog ground for EAROUT−

Companding enable

8

I

13

19

9

I

Master system clock input (2.048 MHz) (digital)

Microphone gain positive feedback

Microphone gain negative feedback

Microphone mute

MICGAIN+

MICGAIN−

MICMUTE

MICIN−

MICIN+

PCMI

I

12

1

I

10

11

16

17

18

2

I

Microphone negative input (−)

Microphone positive input (+)

Receive PCM input

I

PCMO

O

I

Transmit PCM output

PCMSYNC

RESET

PCM frame synchronization

I

Active-low reset

VSS

3

I

Ground return for band-gap internal reference

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, DVDD, EARVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V

Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V

O

Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V

I

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

A

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature 1,6 mm from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

T

≤ 25°C

DERATING FACTOR

T = 85°C

A

POWER RATING

A

PACKAGE

POWER RATING

ABOVE T = 25°C

A

PW

680 W

6.8 W/°C

270 W

4

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SLAS357 − DECEMBER 2001

recommended operating conditions (see Note 2)

MIN

NOM

MAX

UNIT

V

Supply voltage, DVDD, EARVDD

2.7

3.3

High-level input voltage, V

IH

0.7xV

V

DD

Low-level input voltage, V

IL

0.3xV

V

DD

Load impedance between EAROUT+ and EAROUT−, R

Input voltage, MICIN

8 to 32

Ω

L

0.9xV

85

V

Operating free-air temperature, T

A

−40

_C

NOTES: 1. To avoid possible damage and resulting reliability problems to these CMOS devices, follow the power-on initialization paragraph,

described in the Principles of Operations.

2. Voltages are with respect to DVSS, and EARVSS.

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature

(unless otherwise noted)

supply current

PARAMETER

TEST CONDITIONS

MIN

TYP

5

MAX

7

UNIT

mA

µA

Operating

I

t

Supply current from V

DD

Power down, MCLK not present

10

30

Power-up time from power down

10

ms

pu

digital interface

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

High-level output voltage, PCMO

Low-level output voltage, PCMO

High-level input current, any digital input

Low-level input current, any digital input

Input capacitance

I

= −3.2 mA,

= 3.2 mA,

V

= 3 V

DVDD−0.25

OH

DD

V

0.2

10

20

V

OL

I

V = 2.2 V to V

DD

µA

pF

IH

I

V = 0 to 0.8 V

IL

I

C

I

Output capacitance

o

microphone interface

PARAMETER

Input offset voltage

TEST CONDITIONS

See Note 3

MIN

−5

TYP

MAX

5

UNIT

mV

nA

V

IO

I

IB

Input bias current

Input capacitance

−250

250

C

5

pF

i

MIC Amp 1 gain = 23.5 dB,

See Note 4

V

n

Microphone input referred noise, psophometric weighted

2.9

4

µV

rms

MICMUTE

−80

dB

NOTES: 3. Measured while MICIN+ and MICIN− are connected together. Less than a 0.5-mV offset results in 0 value code on PCMOUT.

4. Configured as shown in Figure 3.

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SLAS357 − DECEMBER 2001

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature

(unless otherwise noted) (continued)

speaker interface

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

DD

= 2.7 V, fully differential, 8-Ω load,

3-dBm0 output, volume control = −3 dB,

PCMI data input to −4 dB level

161

200

V

= 2.7 V, fully differential, 16-Ω load,

DD

3-dBm0 output, volume control = −3 dB,

PCMI data input to −2 dB level

128

81

160

100

Earphone AMP output power (see Note 5)

mW

V

= 2.7 V, fully differential, 32-Ω load,

DD

3-dBm0 output, volume control = −3 dB,

PCMI data input to −1 dB level

3-dBm0 input, 8-Ω load

3-dBm0 input, 16-Ω load

3-dBm0 input, 32-Ω load

141

90

178

112

63

I

O

max

Maximum output current for EAROUT (rms)

EARMUTE

mA

dB

50

−80

NOTE 5: Maximum power is with a load impedance of −20%, at 25°C.

transmit gain and dynamic range, companded mode (µ-law) or linear mode selected (see Notes 6 and 7)

PARAMETER

Transmit reference-signal level (0dB)

Overload-signal level (3 dBm0)

Absolute gain error

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Differential, MIC Amp 1 configured for 23.5 dB gain

88 mV

pp

124 mV

0 dBm0 input signal, 2.7 V ≤ V

DD

≤ 3.3 V

−1

−0.5

−1

1

0.5

1

dB

MICIN−, MICIN+ to PCMO at 3 dBm0 to −30 dBm0

MICIN−, MICIN+ to PCMO at −31 dBm0 to −45 dBm0

MICIN−, MICIN+ to PCMO at −46 dBm0 to −55 dBm0

Gain error with input level relative to gain at

−10 dBm0 MICIN, MICIN+ to PCMO

dB

−1.2

1.2

NOTES: 6. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel

under test.

7. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 124-mV

.

pp

transmit filter transfer, companded mode (µ-law) or linear mode selected

PARAMETER

TEST CONDITIONS

< 100 Hz

MIN

−0.5

−1.5

TYP

MAX

0.5

UNIT

f

MIC

= 200 Hz

0.5

= 300 Hz to 3 kHz

= 3.4 kHz

0.5

0

Gain relative to input signal gain at 1.02 kHz

dB

= 4 kHz

−14

−35

−47

= 4.6 kHz

= 8 kHz

6

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SLAS357 − DECEMBER 2001

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature

(unless otherwise noted) (continued)

transmit idle channel noise and distortion, companded mode (µ-law) selected

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MIC Amp 1 configured for 23.5-dB gain

(see Note 8)

Transmit idle channel noise, psophometrically weighted

−80

−70 dBm0

p

MICIN−, MICIN+ to PCMO at 3 dBm0

MICIN−, MICIN+ to PCMO at 0 dBm0

MICIN−, MICIN+ to PCMO at −5 dBm0

MICIN−, MICIN+ to PCMO at −10 dBm0

MICIN−, MICIN+ to PCMO at −20 dBm0

MICIN−, MICIN+ to PCMO at −30 dBm0

MICIN−, MICIN+ to PCMO at −40 dBm0

MICIN−, MICIN+ to PCMO at −45 dBm0

CCITT G.712 (7.1), R2

27

30

33

36

35

26

24

19

49

51

Transmit signal-to-distortion ratio with 1.02-kHz sine-wave

input

dBm0

Intermodulation distortion, 2-tone CCITT method, composite

power level, −13 dBm0

dB

CCITT G.712 (7.2), R2

NOTE 8: With recommended impedances and resistor tolerance of 1%

transmit idle channel noise and distortion, linear mode selected

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MIC Amp 1 configured for 23.5-dB gain

(see Note 8)

Transmit idle channel noise, psophometrically weighted

−80

−74 dBm0

p

MICIN−, MICIN+ to PCMO at 3 dBm0

MICIN−, MICIN+ to PCMO at 0 dBm0

MICIN−, MICIN+ to PCMO at −5 dBm0

MICIN−, MICIN+ to PCMO at −10 dBm0

MICIN−, MICIN+ to PCMO at −20 dBm0

MICIN−, MICIN+ to PCMO at −30 dBm0

MICIN−, MICIN+ to PCMO at −40 dBm0

MICIN−, MICIN+ to PCMO at −45 dBm0

40

50

52

56

52

51

43

38

55

61

62

66

68

61

59

55

Transmit signal-to-total distortion ratio with 1.02-kHz

sine-wave input

dB

NOTE 8: With recommended impedances and resistor tolerance of 1%

receive gain and dynamic range, linear or companded (µ-law) mode selected (see Note 9)

PARAMETER

TEST CONDITIONS

MIN

TYP

3.2

MAX

UNIT

Load = 8 Ω, volume control = −3 dB, PCMI data input to −4 dB level

Load = 16 Ω, volume control = −3 dB, PCMI data input to −2 dB level

Load = 32 Ω, volume control = −3 dB, PCMI data input to −1 dB level

4.05

4.54

Overload-signal level (3 dB)

Absolute gain error

V

pp

0 dBm0 input signal, 2.7 V ≤ V

DD

≤ 3.3 V

−1

−0.5

−1

1

0.5

1

dB

PCMI to EAROUT−, EAROUT+ at 3 dBm0 to −40 dBm0

PCMI to EAROUT−, EAROUT+ at −41 dBm0 to −50 dBm0

PCMI to EAROUT−, EAROUT+ at −51 dBm0 to −55 dBm0

Gain error with output level

relative to gain at −10 dBm0

−1.2

1.2

NOTE 9: 1020-Hz input signal at PCMI, output measured differentially between EAROUT− and EAROUT+

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SLAS357 − DECEMBER 2001

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature

(unless otherwise noted) (continued)

receive filter transfer, companded mode (µ-law) or linear mode selected (MCLK = 2.048 MHz) (see Note 10)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

−15

−5

UNIT

f

< 100 Hz

EAROUT

= 200 Hz

= 300 Hz to 3 kHz

= 3.4 kHz

= 4 kHz

−0.5

−1.5

0.5

0

Gain relative to input signal gain at 1.02-kHz

dB

−14

−35

−47

= 4.6 kHz

= 8 kHz

NOTE 10: Volume control = −3 dB, PCMI data input to −1 dB level (32-Ω load)

receive idle channel noise and distortion, companded mode (µ-law) selected (see Note 10)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Receive noise, C-message weighted

PCMI = 11111111 (µ-law)

−90

−88 dBm0

PCMI to EAROUT−, EAROUT+ at 3 dBm0

PCMI to EAROUT−, EAROUT+ at 0 dBm0

PCMI to EAROUT−, EAROUT+ at −5 dBm0

PCMI to EAROUT−, EAROUT+ at −10 dBm0

PCMI to EAROUT−, EAROUT+ at −20 dBm0

PCMI to EAROUT−, EAROUT+ at −30 dBm0

PCMI to EAROUT−, EAROUT+ at −40 dBm0

PCMI to EAROUT−, EAROUT+ at −45 dBm0

21

25

36

43

40

38

28

23

Receive signal-to-distortion ratio with 1.02-kHz

sine-wave input

dB

NOTE 10: Volume control = −3 dB, PCMI data input to −1 dB level (32-Ω load)

receive idle channel noise and distortion, linear mode selected (see Note 10)

PARAMETER

TEST CONDITIONS

PCMI = 0000000000000

MIN

TYP

−83

52

MAX

UNIT

Receive noise, (20-Hz to 20-kHz brickwall window)

−78 dBm0

PCMI to EAROUT−, EAROUT+ at 3 dBm0

PCMI to EAROUT−, EAROUT+ at 0 dBm0

PCMI to EAROUT−, EAROUT+ at −5 dBm0

PCMI to EAROUT−, EAROUT+ at −10 dBm0

PCMI to EAROUT−, EAROUT+ at −20 dBm0

PCMI to EAROUT−, EAROUT+ at −30 dBm0

PCMI to EAROUT−, EAROUT+ at −40 dBm0

PCMI to EAROUT−, EAROUT+ at −45 dBm0

CCITT G.712 (7.1), R2

48

51

57

55

51

45

42

35

50

54

56

59

62

Receive signal-to-distortion ratio with 1.02-kHz

sine-wave input (0−4 kHz)

dB

53

47

45

Intermodulation distortion, 2-tone CCITT method,

composite power level, −13 dBm0

dB

CCITT G.712 (7.2), R2

NOTE 10: Volume control = −3 dB, PCMI data input to −1 dB level (32-Ω load)

8

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SLAS357 − DECEMBER 2001

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature

(unless otherwise noted) (continued)

power supply rejection

PARAMETER

TEST CONDITIONS

MICIN−, MICIN+ = 0 V, = 2.7 V + 100 mV

MIN

TYP

MAX

UNIT

V

DD

pp,

Supply voltage rejection, transmit channel

−74

−50

dB

f = 1 kHz, Resistor tolerance of 1%

Supply voltage rejection, receive channel

(differential)

PCM code = positive zero, V

f = 1 kHz, Resistor tolerance of 1%

= 2.7 V + 100 mV

,

DD pp

−80

−65

dB

crosstalk attenuation, linear mode selected

PARAMETER

TEST CONDITIONS

MIN

70

TYP

MAX

UNIT

dB

Crosstalk attenuation, transmit-to-receive

(differential)

MICIN−, MICIN+ = 0 dB, f = 300 Hz to 3400 Hz measured

differentially between EAROUT− and EAROUT+

Crosstalk attenuation, receive-to-transmit

PCMI = 0 dBm0, f = 300 Hz to 3400 Hz measured at PCMO

70

dB

timing requirements

clock

MIN NOM

2.048

MAX

UNIT

ns

t

f

Transition time, MCLK

MCLK frequency

MCLK jitter

10

t

MHz

mclk

37%

MCLK clock cycles per PCMSYN frame

256

256 cycles

transmit (see Figure 1)

MIN

MAX

UNIT

t

Setup time, PCMSYN high before MCLK ↓

Hold time, PCMSYN high after MCLK ↓

20

t

−20

ns

su(PCMSYN)

c(MCLK)

20

h(PCMSYN)

c(MCLK)

receive (see Figure 2)

MIN

20

MAX

UNIT

ns

t

Setup time, PCMSYN high before MCLK ↓

Hold time, PCMSYN high after MCLK ↓

Setup time, PCMI high or low before MCLK ↓

Hold time, PCMI high or low after MCLK ↓

t

−20

su(PCSYN)

h(PCSYN)

su(PCMI)

h(PCMI)

c(MCLK)

20

ns

c(MCLK)

20

ns

20

ns

switching characteristics over recommended operating conditions, C max = 10 pF (see Figure 1)

L

MIN

MAX

35

UNIT

ns

t

Propagation delay time, MCLK bit 1 high to PCMO bit 1 valid

Propagation delay time, MCLK high to PCMO valid, bits 2 to n

Propagation delay time, MCLK bit n low to PCMO bit n Hi-Z

pd1

pd2

pd3

35

ns

30

ns

9

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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢉ ꢅꢊ

SLAS357 − DECEMBER 2001

PARAMETER MEASUREMENT INFORMATION

Transmit Time Slot

0

1

2

3

4

N−2

N−1

N

N+1

80%

MCLK

20%

t

su(PCMSYN)

t

h(PCMSYN)

PCMSYN

See Note B

t

See Note A

PCMO

pd2

t

pd3

1

2

3

4

N−2

N−1

N

See Note C

t

pd1

t

See Note D

su(PCMO)

NOTES: A. This window is allowed for PCMSYN high.

B. This window is allowed for PCMSYN low (t

C. Transitions are measured at 50%.

max determined by data collision considerations).

h(PCMSYN)

D. Bit 1 = Most significant bit (MSB), Bit N = Least significant bit (LSB)

Figure 1. Transmit Timing Diagram

Receive Time Slot

4

0

1

2

3

N −2

20%

N −1

N

N +1

80%

MCLK

t

20%

t

su(PCMSYN)

h(PCMSYN)

PCMSYN

See Note B

4

See Note A

See Note D

2

t

h(PCMI)

1

3

N −2

N −1

N

PCMI

See Note C

t

su(PCMI)

NOTES: A. This window is allowed for PCMSYN high.

B. This window is allowed for PCMSYN low.

C. Transitions are measured at 50%.

D. Bit 1 = Most significant bit (MSB), Bit N = Least significant bit (LSB)

Figure 2. Receive Timing Diagram

10

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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢉꢉꢅ ꢊ

SLAS357 − DECEMBER 2001

PRINCIPLES OF OPERATION

power-up initialization

An external reset with a minimum pulse width of 500 ns must be applied to the active-low RESET terminal with

MCLK active to ensure reset upon power up.

Table 1. Power-Up and Power-Down Power Consumption

(V

= 2.7 V, Earphone Amplifier Loaded)

DD

DEVICE STATUS

Power up

MAXIMUM POWER CONSUMPTION

16.2 mW

Power down

81 µW

The loss of MCLK (no transition detected) automatically enters the device into a power-down state with PCMO

in the high-impedance state. If an asynchronous power down occurs during a pulse code modulation (PCM)

data transmit cycle, the PCM interface remains powered up until the PCM data is completely transferred.

conversion laws

The device can be programmed either for a 13-bit linear or 8-bit (µ-law) companding mode. The companding

operation approximates the CCITT G.711 recommendation. The linear mode operation uses a 13-bit twos

complement format. Linear mode is selected with LINSEL low. LINSEL is high for companding.

transmit operation

microphone input

The microphone input stage is a low-noise differential amplifier. The microphone must be capacitively coupled

to the MICIN− and MICIN+ terminals. Preamplifier (MIC Amp 1) gain is determined by selection of external

resistors R2 and R3. To achieve the recommended gain setting of 23.5 dB for MIC Amp 1, resistor values of

R2 = 34 kΩ and R3 = 510 kΩ are suggested. A 1% tolerance is recommended for all resistors to meet the

specification. The recommended range for R2 is 34−100 kΩ. For values above 100 kΩ, the noise performance

of the channel is degraded.

+V

R3

MICGAIN−

MICIN+

R1

C1

R2

+

_

MIC Amp 1

MICIN−

R1

MICGAIN+

R3

R1 = 2 kΩ

C1 = 0.22 µF

R3

_{MIC Amp 1 Gain in dB + 20 log}ǒ Ǔ

R2

Figure 3. Typical Microphone Interface

11

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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢉ ꢅꢊ

SLAS357 − DECEMBER 2001

PRINCIPLES OF OPERATION

microphone mute function

Transmit channel muting can be selected by setting MICMUTE high. Muting provides 80-dB attenuation of the

input microphone signal.

receive operation

earphone amplifier

The analog signal is routed to the earphone amplifier differential output (EAROUT− or EAROUT+), which is

capable of driving a load as low as 8 Ω. EAROUT is recommended for use as a differential output.

earphone mute function

Receive channel muting can be selected by setting the EARMUTE terminal to high.

receive PCM data format

D

Companded mode: 8 bits are received, the MSB first

Linear mode: 13 bits are received, the MSB first

Table 2. Receive Data Bit Definitions

BIT NO.

COMPANDED

MODE

LINEAR

MODE

1

2

CD7

CD6

CD5

CD4

CD3

CD2

CD1

CD0

−

LD12

LD11

LD10

LD9

3

4

5

LD8

6

LD7

7

LD6

8

LD5

9

LD4

10

11

12

13

14

15

16

−

LD3

−

LD2

−

LD1

−

LD0

−

RXVOL2

RXVOL1

RXVOL0

−

12

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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢉꢉꢅ ꢊ

SLAS357 − DECEMBER 2001

PRINCIPLES OF OPERATION

receive volume control

In linear mode, RXVOL [2:0] PCM data bits are used for volume control according to Table 3. Volume control

bits must be sent on PCMI for each 13-bit receive word. In companded mode, volume control is fixed at 0 dB.

Table 3. Volume Control Bit Definition in Linear Mode

RXVOL [2:0]

000

GAIN SETTING

3 dB

001

0 dB

010

−3 dB

011

−6 dB

100

−9 dB

101

−12 dB

−15 dB

−18 dB

110

111

support section

The clock generator and control circuit uses the master clock input (MCLK) to generate internal clocks to drive

internal counters, filters, and converters.

clock frequencies and sample rates

A fixed PCMSYN rate of 8 kHz determines the sampling rate. The PCMSYN signal must be derived from the

master clock. The divide ratio must be set to 256 for the device to work properly.

13

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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢉ ꢅꢊ

SLAS357 − DECEMBER 2001

TYPICAL CHARACTERISTICS

RELATIVE GAIN

vs

RELATIVE GAIN

vs

FREQUENCY

20

0

10

0

−20

−40

−10

−20

−30

See Note B

See Note A

−60

−80

−40

−100

−120

−50

−60

0

1

2

3

4

5

6

0

1

2

3

4

5

6

f − Frequency − kHz

Figure 4

Figure 5

NOTES: A. Transmit channel frequency response shown relative to the gain at a 1.02-kHz input signal in linear mode.

B. Receive channel frequency response shown relative to the gain at a 1.02-kHz input signal in linear mode.

RELATIVE GAIN

vs

RELATIVE GAIN

vs

FREQUENCY

20

0

10

0

−20

−40

−60

−10

−20

−30

See Note A

See Note B

−80

−40

−100

−120

−50

−60

0

1

2

3

4

5

6

0

1

2

3

4

5

6

f − Frequency − kHz

Figure 6

Figure 7

NOTES: A. Transmit channel frequency response shown relative to the gain at a 1.02-kHz input signal in µ-Law mode.

B. Receive channel frequency response shown relative to the gain at a 1.02-kHz input signal in µ-Law mode.

14

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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇ ꢈꢉꢉꢅ ꢊ

SLAS357 − DECEMBER 2001

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

10

8

20

16

See Note A

See Note B

6

12

8

4

2

0

4

0

2.5

3

3.5

2.5

3

3.5

Supply Voltage − V

Figure 8

Figure 9

NOTES: A. Supply current as a function of supply voltage in power-up mode.

B. Supply current as a function of supply voltage in power-down mode.

15

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PACKAGE OPTION ADDENDUM

www.ti.com

27-Feb-2006

PACKAGING INFORMATION

Orderable Device

TLV320AIC1106PW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

PW

20

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLV320AIC1106PWG4

TLV320AIC1106PWR

TLV320AIC1106PWRG4

TSSOP

PW

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV320AIC1106PWR

TSSOP

PW

20

2000

330.0

16.4

6.95

7.1

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 20

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

TLV320AIC1106PWR

2000

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

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semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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型号：	TLV320AIC1106_14
厂家：	TEXAS INSTRUMENTS
描述：	PCM CODEC PC
文件：	总19页 (文件大小：538K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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