TLV2470IDBVTG3 [TI]
OP-AMP, 2400uV OFFSET-MAX, 2.8MHz BAND WIDTH, PDSO6;型号: | TLV2470IDBVTG3 |
厂家: | TEXAS INSTRUMENTS |
描述: | OP-AMP, 2400uV OFFSET-MAX, 2.8MHz BAND WIDTH, PDSO6 放大器 光电二极管 |
文件: | 总63页 (文件大小:2734K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLV2470, TLV2471
TLV2472, TLV2473
®
®
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E–JUNE 1999–REVISED JULY 2007
FAMILY OF 600μA/Ch 2.8MHz RAIL-TO-RAIL INPUT/OUTPUT
HIGH-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN
FEATURES
DESCRIPTION
•
•
•
•
CMOS Rail-To-Rail Input/Output
The TLV247x is a family of CMOS rail-to-rail input/
output operational amplifiers that establishes a new
performance point for supply current versus ac
Input Bias Current: 2.5pA
Low Supply Current: 600μA/Channel
performance.
600μA/channel
These
while
devices
offering
consume
2.8MHz
just
of
Ultra-Low Power Shutdown Mode:
IDD(SHDN): 350nA/ch at 3V
IDD(SHDN): 1000nA/ch at 5V
gain-bandwidth product. Along with increased ac
performance, the amplifier provides high output drive
capability, solving a major shortcoming of older
micropower operational amplifiers. The TLV247x can
swing to within 180mV of each supply rail while
driving a 10mA load. For non-RRO applications, the
TLV247x can supply ±35mA at 500mV off the rail.
Both the inputs and outputs swing rail-to-rail for
increased dynamic range in low-voltage applications.
This performance makes the TLV247x family ideal
for sensor interface, portable medical equipment,
and other data acquisition circuits.
•
•
Gain-Bandwidth Product: 2.8MHz
High Output Drive Capability:
–
–
±10mA at 180mV
±35mA at 500mV
•
•
•
Input Offset Voltage: 250μV (typ)
Supply Voltage Range: 2.7V to 6V
Ultra-Small Packaging
–
–
SOT23-5 or -6 (TLV2470/1)
MSOP-8 or -10 (TLV2472/3)
FAMILY PACKAGE TABLE
PACKAGE TYPES
NUMBER OF
CHANNELS
DEVICE
SHUTDOWN
UNIVERSAL EVM BOARD
PDIP
8
SOIC
8
SOT23
TSSOP
MSOP
—
TLV2470
TLV2471
TLV2472
TLV2473
TLV2474
TLV2475
1
1
2
2
4
4
6
—
—
—
—
14
16
Yes
—
8
8
5
—
8
8
—
—
—
—
8
—
Refer to the EVM Selection
Guide (SLOU060)
14
14
16
14
14
16
10
Yes
—
—
—
Yes
A SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS(1)
VDD
(V)
VIO
(μV)
BW
(MHz)
SLEW RATE
IDD (per channel)
DEVICE
OUTPUT DRIVE
RAIL-TO-RAIL
(V/μs)
(μA)
TLV247X
TLV245X
TLV246X
TLV277X
2.7 – 6.0
2.7 – 6.0
2.7 – 6.0
2.5 – 6.0
250
20
2.8
0.22
6.4
1.5
0.11
1.6
600
23
±35mA
±10mA
±90mA
±10mA
I/O
I/O
I/O
O
150
360
550
1000
5.1
10.5
(1) All specifications measured at 5V.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Microsim PARTS is a trademark of MicroSim Corporation.
Microsim PSpice is a registered trademark of MicroSim Corporation.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV2470, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E–JUNE 1999–REVISED JULY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
TLV2470 and TLV2471 AVAILABLE OPTIONS(1)
PACKAGED DEVICES
TA
SOT23
SMALL OUTLINE (D)(2)
PLASTIC DIP (P)
(DBV)(2)
SYMBOL
TLV2470CD
TLV2471CD
TLV2470CDBV
TLV2471CDBV
VAUC
VAVC
TLV2470CP
TLV2471CP
0°C to +70°C
TLV2470ID
TLV2471ID
TLV2470IDBV
TLV2471IDBV
VAUI
VAVI
TLV2470IP
TLV2471IP
–40°C to +125°C
TLV2470AID
TLV2471AID
TLV2470AIP
TLV2471AIP
——
——
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (for example,
TLV2470CDR).
TLV2472 AND TLV2473 AVAILABLE OPTIONS(1)
PACKAGED DEVICES
SMALL
OUTLINE
(D)(2)
MSOP
MSOP
TA
PLASTIC DIP PLASTIC DIP
(DGN)(2)
SYMBOL(3)
(DGQ)(2)
SYMBOL(3)
(N)
(P)
TLV2472CD
TLV2473CD
TLV2472CDGN
—
xxTIABU
—
—
—
—
TLV2472CP
—
0°C to +70°C
–40°C to +125°C
TLV2473CDGQ
xxTIABW
TLV2473CN
TLV2472ID
TLV2473ID
TLV2472IDGN
—
xxTIABV
—
—
—
xxTIABX
—
TLV2472IP
—
TLV2473IDGQ
TLV2473IN
TLV2472AID
TLV2473AID
—
TLV2472AIP
—
——
——
——
——
TLV2473AIN
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (for example,
TLV2472CDR).
(3) xx represents the device date code.
TLV2474 and TLV2475 AVAILABLE OPTIONS(1)
PACKAGED DEVICES
TA
SMALL OUTLINE (D)(2)
PLASTIC DIP (N)
TSSOP (PWP)(2)
TLV2474CD
TLV2475CD
TLV2474CN
TLV2475CN
TLV2474CPWP
TLV2475CPWP
0°C to +70°C
TLV2474ID
TLV2475ID
TLV2474IN
TLV2475IN
TLV2474IPWP
TLV2475IPWP
–40°C to +125°C
TLV2474AID
TLV2475AID
TLV2474AIN
TLV2475AIN
TLV2474AIPWP
TLV2475AIPWP
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (for example,
TLV2474CDR).
2
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TLV2470, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E–JUNE 1999–REVISED JULY 2007
TLV247X PACKAGE PINOUTS
TLV2470
D OR P PACKAGE
(TOP VIEW)
TLV2470
DBV PACKAGE
(TOP VIEW)
TLV2471
DBV PACKAGE
(TOP VIEW)
1
2
3
V
5
V
DD
OUT
GND
IN+
OUT
GND
IN+
1
2
6
5
NC
IN−
IN+
SHDN
DD
1
2
3
4
8
7
6
5
V
DD
SHDN
IN−
OUT
NC
GND
4
IN−
3
4
TLV2473
DGQ PACKAGE
(TOP VIEW)
TLV2471
D OR P PACKAGE
(TOP VIEW)
TLV2472
D, DGN, OR P PACKAGE
(TOP VIEW)
1
1OUT
1IN−
1IN+
GND
1SHDN
V
2OUT
2IN−
2IN+
2SHDN
10
DD
NC
IN−
IN+
NC
1OUT
1IN−
1IN+
GND
V
DD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
2
3
4
5
9
8
7
6
V
DD
2OUT
2IN−
2IN+
OUT
NC
GND
TLV2474
TLV2475
TLV2473
D, N, OR PWP PACKAGE
D, N, OR PWP PACKAGE
D OR N PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1OUT
1IN−
1IN+
4OUT
4IN−
4IN+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
GND
NC
V
1OUT
1IN−
1IN+
1
2
3
4
5
6
7
14
13
12
11
10
9
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
DD
2OUT
2IN−
2IN+
NC
V
DD
GND
3IN+
V
DD
2IN+
2IN−
2IN+
2IN−
3IN−
1SHDN
NC
2SHDN
NC
2OUT
1/2SHDN
3OUT
3/4SHDN
8
8
2OUT
NC − No internal connection
TYPICAL PIN 1 INDICATORS
Pin 1
Printed or
Molded Dot
Pin 1
Pin 1
Pin 1
Stripe
Beveled Edges
Molded U Shape
3
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TLV2470, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E–JUNE 1999–REVISED JULY 2007
DESCRIPTION (CONTINUED)
Three members of the family (TLV2470/3/5) offer a shutdown terminal for conserving battery life in portable
applications. During shutdown, the outputs are placed in a high-impedance state and the amplifier consumes
only 350nA/channel. The family is fully specified at 3V and 5V across an expanded industrial temperature range
(–40°C to +125°C). The singles and duals are available in the SOT23 and MSOP packages, while the quads are
available in TSSOP. The TLV2470 offers an amplifier with shutdown functionality all in a SOT23-6 package,
making it perfect for high-density power-sensitive circuits.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
UNIT
(2)
Supply voltage, VDD
7V
±VDD
Differential input voltage, VID
Continuous total power dissipation
See Dissipation Rating table
0°C to +70°C
–40°C to +125°C
+150°C
C-suffix
I-suffix
Operating free-air temperature range, TA
Maximum junction temperature, TJ
Storage temperature range, Tstg
–65°C to +150°C
+260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated underrecommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ +25°C
POWER RATING
PACKAGE
D (8)
D (14)
38.3
26.9
25.7
55
176
122.3
114.7
324.1
294.3
52.7
52.3
78
710mW
1022mW
1090mW
385mW
D (16)
DBV (5)
DBV (6)
DGN (8)
DGQ (10)
N (14, 16)
P (8)
55
425mW
4.7
2.37W
4.7
2.39W
32
1600mW
1200mW
4.07W
41
104
PWP (14)
PWP (16)
2.07
2.07
30.7
29.7
4.21W
RECOMMENDED OPERATING CONDITIONS
MIN
2.7
±1.35
0
MAX
6
UNIT
V
Single supply
Supply voltage, VDD
Split supply
±3
Common-mode input voltage range, VICR
Operating free-air temperature, TA
VDD
+70
+125
V
C-suffix
I-suffix
VIH
0
°C
–40
2
Shutdown on/off voltage level(1)
(1) Relative to GND.
V
VIL
0.8
4
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TLV2470, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E–JUNE 1999–REVISED JULY 2007
ELECTRICAL CHARACTERISTICS
At specified free-air temperature, VDD = 3V, unless otherwise noted.
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
2200
2400
1600
1800
UNIT
+25°C
250
TLV247x
Full range
+25°C
VIO
Input offset voltage
μV
250
TLV247xA
Full range
Temperature coefficient of
input offset voltage
αVIO
0.4
1.5
μV/°C
VIC = VDD/2,
VO = VDD/2, RS = 50Ω
25°C
Full range
Full range
+25°C
50
100
300
50
IIO
Input offset current
Input bias current
TLV247xC
TLV247xI
pA
2
IIB
TLV247xC
TLV247xI
Full range
Full range
+25°C
100
300
2.85
2.8
2.6
2.5
2.94
2.74
0.07
0.2
IOH = –2.5mA
IOH = –10mA
IOL = 2.5mA
IOL = 10mA
Full range
+25°C
VOH
High-level output voltage
Low-level output voltage
VIC = VDD/2
V
V
Full range
+25°C
0.15
0.2
Full range
+25°C
VOL
VIC = VDD/2
Sourcing
0.35
0.5
Full range
+25°C
30
20
30
20
Full range
+25°C
IOS
Short-circuit output current
Output current
mA
Sinking
Full range
+25°C
IO
VO = 0.5V from rail
VO(PP) = 1V, RL = 10kΩ
±22
mA
dB
+25°C
90
88
116
Large-signal differential
voltage amplification
AVD
Full range
+25°C
ri(d)
CIC
Differential input resistance
1012
19.3
Ω
Common-mode input
capacitance
f = 10kHz
+25°C
+25°C
pF
Closed-loop output
impedance
zo
f = 10kHz, AV = 10
2
Ω
+25°C
61
59
58
78
CMRR
Common-mode rejection ratio
TLV247xC
TLV247xI
Full range
Full range
dB
VIC = 0V to 3V,
RS = 50Ω
(1) Full range is 0°C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C.
5
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TLV2470, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E–JUNE 1999–REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
At specified free-air temperature, VDD = 3V, unless otherwise noted.
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
74
TYP
MAX
UNIT
+25°C
Full range
+25°C
90
VDD = 2.7V to 6V, VIC = VDD/2, No load
66
Supply voltage rejection ratio
kSVR
dB
(ΔVDD/ΔVIO
)
77
92
550
350
VDD = 3V to 5V, VIC = VDD/2, No load
Full range
+25°C
68
750
800
IDD
Supply current (per channel) VO = 1.5V, No load
μA
Full range
+25°C
1500
2000
4000
Supply current in shutdown
mode (TLV2470, TLV2473,
TLV2475) (per channel)
IDD(SHDN)
TLV247xC
TLV247xI
Full range
Full range
nA
SHDN = 0V
(1) Full range is 0°C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C.
OPERATING CHARACTERISTICS
At specified free-air temperature, VDD = 3V, unless otherwise noted.
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
1.1
TYP
MAX
UNIT
+25°C
Full range
+25°C
+25°C
1.4
SR
Slew rate at unity gain VO(PP) = 0.8V, CL = 150pF, RL= 10kΩ
V/μs
0.6
f = 100Hz
f = 1kHz
28
15
Equivalent input noise
voltage
Vn
In
nV/√Hz
pA/√Hz
Equivalent input noise
current
f = 1kHz
+25°C
0.405
AV = 1
0.02%
0.1%
0.5%
5
VO(PP) = 2V,
RL= 10kΩ,
f = 1kHz
Total harmonic
distortion plus noise
THD+N
AV = 10
AV = 100
+25°C
t(on)
t(off)
Amplifier turn-on time
Amplifier turn-off time
+25°C
+25°C
μs
RL= OPEN(2)
250
ns
Gain-bandwidth
product
f = 10kHz, RL = 600Ω
+25°C
2.8
MHz
V(STEP)PP = 2V,
AV = –1, CL = 10pF,
RL = 10kΩ
0.1%
1.5
3.9
1.6
4
0.01%
0.1%
ts
Settling time
+25°C
μs
V(STEP)PP = 2V,
AV = –1, CL = 56pF,
RL = 10kΩ
0.01%
Φm
Phase margin
Gain margin
RL = 10kΩ, CL = 1000pF
RL = 10kΩ, CL = 1000pF
+25°C
+25°C
61
15
°
dB
(1) Full range is 0°C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C.
(2) Disable and enable time are defined as the interval between application of logic signal to SHDN and the point at which the supply
current has reached half its final value.
6
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TLV2470, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E–JUNE 1999–REVISED JULY 2007
ELECTRICAL CHARACTERISTICS
At specified free-air temperature, VDD = 5V, unless otherwise noted.
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP MAX UNIT
+25°C
250 2200
TLV247x
Full range
+25°C
2400
μV
VIO
Input offset voltage
250 1600
TLV247xA
Full range
2000
Temperature coefficient of input
offset voltage
VIC = VDD/2,
VO = VDD/2,
RS = 50Ω
αVIO
0.4
1.7
μV/°C
+25°C
Full range
Full range
+25°C
50
100
300
50
IIO
Input offset current
Input bias current
TLV247xC
TLV247xI
pA
2.5
IIB
TLV247xC
TLV247xI
Full range
Full range
+25°C
100
300
4.85
4.8
4.96
4.82
IOH = –2.5mA
IOH = –10mA
IOL = 2.5mA
IOL = 10mA
Full range
+25°C
VOH
High-level output voltage
Low-level output voltage
VIC = VDD/2
V
V
4.72
4.65
Full range
+25°C
0.07 0.15
0.2
Full range
+25°C
VOL
VIC = VDD/2
Sourcing
0.178 0.28
0.35
Full range
+25°C
110
60
Full range
+25°C
IOS
Short-circuit output current
Output current
mA
90
Sinking
Full range
+25°C
60
IO
VO = 0.5V from rail
VO(PP) = 3V, RL = 10kΩ
±35
mA
dB
+25°C
92
91
120
Large-signal differential voltage
amplification
AVD
Full range
+25°C
ri(d)
CIC
zo
Differential input resistance
1012
18.9
1.8
Ω
pF
Ω
Common-mode input capacitance f = 10kHz
+25°C
Closed-loop output impedance
Common-mode rejection ratio
f = 10kHz, AV = 10
+25°C
+25°C
64
63
58
74
66
77
66
84
CMRR
TLV247xC
TLV247xI
Full range
Full range
+25°C
dB
VIC = 0V to 5V,
RS = 50Ω
90
92
VDD = 2.7V to 6V, VIC = VDD/2,
No load
Full range
+25°C
Supply voltage rejection ratio
kSVR
dB
(ΔVDD/ΔVIO
)
VDD = 3V to 5V, VIC = VDD/2,
No load
Full range
+25°C
600 900
1000
IDD
Supply current (per channel)
VO = 2.5V, No load
μA
Full range
(1) Full range is 0°C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C.
7
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TLV2470, TLV2471
TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
www.ti.com
SLOS232E–JUNE 1999–REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)
At specified free-air temperature, VDD = 5V, unless otherwise noted.
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP MAX UNIT
+25°C
1000 2500
nA
Supply current in shutdown mode
IDD(SHDN) (TLV2470, TLV2473, TLV2475)
(per channel)
SHDN = 0V
TLV247xC
TLV247xI
Full range
Full range
3000
6000
nA
(1) Full range is 0°C to +70°C for C-suffix and –40°C to +125°C for I-suffix. If not specified, full range is –40°C to +125°C.
OPERATING CHARACTERISTICS
At specified free-air temperature, VDD = 5V, unless otherwise noted.
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
1.1
TYP
MAX
UNIT
+25°C
Full range
+25°C
+25°C
1.5
SR
Slew rate at unity gain VO(PP) = 2V, CL = 150pF, RL= 10kΩ
V/μs
0.7
f = 100Hz
f = 1kHz
28
15
Equivalent input noise
voltage
Vn
In
nV/√Hz
pA/√Hz
Equivalent input noise
current
f = 1kHz
+25°C
0.39
AV = 1
0.01%
0.05%
0.3%
5
VO(PP) = 4V,
RL= 10kΩ,
f = 1kHz
Total harmonic
distortion plus noise
THD + N
AV = 10
AV = 100
+25°C
t(on)
t(off)
Amplifier turn-on time
Amplifier turn-off time
+25°C
+25°C
μs
RL= OPEN(2)
250
ns
Gain-bandwidth
product
f = 10kHz, RL = 600Ω
+25°C
2.8
MHz
V(STEP)PP = 2V,
AV = –1, CL = 10pF,
RL = 10kΩ
0.1%
1.8
3.3
1.7
3
0.01%
0.1%
ts
Settling time
+25°C
μs
V(STEP)PP = 2V,
AV = –1, CL = 56pF,
RL = 10kΩ
0.01%
Φm
Phase margin
Gain margin
RL = 10kΩ, CL = 1000pF
RL = 10kΩ, CL = 1000pF
+25°C
+25°C
68
23
°C
dB
(1) Full range is 0°C to +70°C for C suffix and –40°C to +125°C for I suffix. If not specified, full range is –40°C to +125°C.
(2) Disable and enable time are defined as the interval between application of logic signal to SHDN and the point at which the supply
current has reached half its final value.
8
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
vs Common-mode input voltage
vs Free-air temperature
Figure 1, Figure 2
IIB
Input bias current
Figure 3, Figure 4
IIO
Input offset current
VOH
VOL
Zo
High-level output voltage
Low-level output voltage
Output impedance
vs High-level output current
vs Low-level output current
vs Frequency
Figure 5, Figure 7
Figure 6, Figure 8
Figure 9
IDD
Supply current
vs Supply voltage
Figure 10
PSRR
CMRR
Vn
Power-supply rejection ratio
vs Frequency
Figure 11
Common-mode rejection ratio
Equivalent input noise voltage
Maximum peak-to-peak output voltage
Differential voltage gain and phase
Phase margin
vs Frequency
Figure 12
vs Frequency
Figure 13
VO(PP)
AVD
Φm
vs Frequency
Figure 14, Figure 15
Figure 16, Figure 17
Figure 18, Figure 19
Figure 20, Figure 21
Figure 22
vs Frequency
vs Load capacitance
vs Load capacitance
vs Supply voltage
vs Supply voltage
vs Free-air temperature
vs Frequency
Gain margin
Gain-bandwidth product
Figure 23
SR
Slew rate
Figure 24, Figure 25
Figure 26
Crosstalk
THD+N
VO
Total harmonic distortion + noise
Large and small signal follower
Shutdown pulse response
Shutdown forward and reverse isolation
Shutdown supply current
Shutdown supply current
Shutdown pulse current
vs Frequency
Figure 27, Figure 28
Figure 29–Figure 32
Figure 33, Figure 34
Figure 35, Figure 36
Figure 37
vs Time
vs Time
vs Frequency
IDD(SHDN)
IDD(SHDN)
IDD(SHDN)
vs Supply voltage
vs Free-air temperature
vs Time
Figure 38
Figure 39, Figure 40
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TYPICAL CHARACTERISTICS
INPUT BIAS AND INPUT OFFSET
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
CURRENTS
vs
FREE-AIR TEMPERATURE
50
40
30
20
10
0
600
600
V
= 3V
V
= 3V
DD
DD
V
= 5V
DD
400
200
400
200
T
A
= +25° C
T
A
= +25 °C
I
IB
0
0
−200
−400
−600
−800
−200
−400
−600
−800
I
IO
−10
−55 −35 −15
5
25 45 65 85 105 125
−0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
−0.5
0.5
1.5
2.5
3.5
4.5
5.5
T
A
− Free-Air Temperature − °C
V
− Common-Mode Input Voltage − V
V
− Common-Mode Input Voltage − V
ICR
ICR
Figure 1.
Figure 2.
Figure 3.
INPUT BIAS AND INPUT OFFSET
CURRENTS
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
50
40
30
20
10
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
= 5V
V
= 3V
DD
DD
V
= 3V
DD
T
A
= +125°C
T
A
= +85°C
T
= +25°C
= −40°C
A
T
T
= +125°C
A
I
A
IB
T
= +85°C
A
T
T
= +25°C
= −40°C
A
I
IO
A
−10
−55 −35 −15
5
25 45 65 85 105 125
0
10
20
30
40
50
60
0
10
20
30
40
50
T
A
− Free-Air Temperature − °C
I
− High-Level Output Current − mA
I
− Low-Level Output Current − mA
OL
OH
Figure 4.
Figure 5.
Figure 6.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
OUTPUT IMPEDANCE
vs
FREQUENCY
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1000
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
= 3V, 5V
= +25°C
DD
T
= +125°C
A
V
= 5V
T
A
DD
T
= +85°C
A
100
AV = 100
T
T
= +25°C
= −40°C
A
10
1
A
AV = 10
T
= +125°C
A
T
= +85°C
A
AV = 1
0.1
T
A
= +25°C
A
T
= −40°C
V
= 5V
DD
0.01
0
20
40
60
80 100 120 140
0
20 40 60 80 100 120 140 160
100
1k
10k
100k
1M
10M
I
− Low-Level Output Current − mA
I
− High-Level Output Current − mA
f − Frequency − Hz
OL
OH
Figure 7.
Figure 8.
Figure 9.
10
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SLOS232E–JUNE 1999–REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
POWER-SUPPLY REJECTION
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
RATIO
vs
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
FREQUENCY
1.0
0.9
100
90
80
70
60
50
40
30
130
V
R
= 3V, 5V
= 5kΩ
DD
F
I
T
= +125°C
PSRR+
A
120
110
100
90
T
= +85°C
A
R = 50Ω
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
T
A
= +25°C
PSRR−
T
A
= +25°C
V
V
= 5V
DD
= 2.5V
IC
T
= −40°C
A
80
V
V
= 3V
DD
70
A
= 1
= 1.5V
V
IC
SHDN = V
Per Channel
60
DD
50
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
V
− Supply Voltage − V
f − Frequency − Hz
DD
f − Frequency − Hz
Figure 10.
Figure 11.
Figure 12.
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
EQUIVALENT NOISE VOLTAGE
vs
FREQUENCY
FREQUENCY
FREQUENCY
80
70
60
50
40
30
20
10
0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.5
V
A
V
= 3V, 5V
= 10
DD
V
IN
THD+N ≤ 2.0%
THD+N ≤ 2.0%
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
R
L
= 10kΩ
= +25°C
R
L
= 600Ω
= +25°C
= V /2
DD
T
A
T
A
V
= 5V
O(PP)
T
A
= +25°C
V
= 5V
O(PP)
V
= 3V
O(PP)
V
= 3V
O(PP)
10
100
1k
10k
100k
10k
100k
1M
10k
100k
1M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 13.
Figure 14.
Figure 15.
DIFFERENTIAL VOLTAGE GAIN
DIFFERENTIAL VOLTAGE GAIN
AND PHASE
vs
AND PHASE
vs
FREQUENCY
FREQUENCY
100
45
100
45
V
= ±3
= 600Ω
= 0
V
= ±5
= 600Ω
= 0
DD
L
L
DD
L
L
R
C
T
R
C
T
80
60
40
20
0
80
60
40
20
0
= +25°C
= +25°C
A
A
−45
−90
−135
−45
−90
−135
0
−180
−225
0
−180
−225
−20
−20
−40
100
−270
100M
−40
100
−270
100M
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
Frequency − Hz
Frequency − Hz
Figure 16.
Figure 17.
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SLOS232E–JUNE 1999–REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
PHASE MARGIN
vs
LOAD CAPACITANCE
PHASE MARGIN
vs
LOAD CAPACITANCE
GAIN MARGIN
vs
LOAD CAPACITANCE
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
0
V
R
= 3V
= 10kΩ
= +25°C
DD
L
V
R
= 5V
= 10kΩ
= +25°C
V
R
T
= 3V
= 10kΩ
= +25°C
DD
L
DD
L
A
RNULL = 50
RNULL = 50
T
A
T
A
5
See Figure 42
See Figure 42
RNULL = 0
RNULL = 100
10
15
RNULL = 100
RNULL = 20
RNULL = 100
RNULL = 20
20
RNULL = 20
25
30
RNULL = 50
RNULL = 0
RNULL = 0
100
1k
10k
100k
100
1k
10k
100k
100
1k
10k
100k
C
L
− Load Capacitance − pF
C
L
− Load Capacitance − pF
C − Load Capacitance − pF
L
Figure 18.
Figure 19.
Figure 20.
GAIN MARGIN
vs
LOAD CAPACITANCE
GAIN-BANDWIDTH PRODUCT
SLEW RATE
vs
SUPPLY VOLTAGE
vs
SUPPLY VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
5
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
SR−
SR+
R
= 10kΩ
L
RNULL = 0
10
15
R
L
= 600Ω
RNULL = 20
20
25
C
= 11pF
f = 10kHz
= +25°C
RNULL = 100
L
RNULL = 50
T
A
V
A
R
C
= 1.5V
= −1
= 10kΩ
= 150pF
O(PP)
V
L
L
V
R
= 5V
= 10kΩ
= +25°C
DD
L
30
35
T
A
100
1k
10k
100k
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
C
L
− Load Capacitance − pF
V
− Supply Voltage − V
V − Supply Voltage − V
DD
DD
Figure 21.
Figure 22.
Figure 23.
SLEW RATE
vs
FREE-AIR TEMPERATURE
SLEW RATE
vs
FREE-AIR TEMPERATURE
2.00
1.75
1.50
1.25
1.00
0.75
0.50
2.00
1.75
1.50
1.25
1.00
0.75
0.50
SR−
SR+
SR+
SR−
V
R
C
A
= 5V
= 10kΩ
= 150pF
= −1
DD
V
R
C
A
= 3V
= 10kΩ
= 150pF
= −1
DD
L
L
V
L
L
V
0.25
0.00
0.25
0.00
−55 −35 −15
5
25 45 65 85 105 125
−55 −35 −15
5
25 45 65 85 105 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 24.
Figure 25.
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SLOS232E–JUNE 1999–REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC
DISTORTION PLUS NOISE
vs
TOTAL HARMONIC
DISTORTION PLUS NOISE
vs
CROSSTALK
vs
FREQUENCY
FREQUENCY
FREQUENCY
0
1
0.1
V
A
R
= 3V, 5V
DD
= 1
1
0.1
A
= 100
A
= 100
V
V
−20
V
=
600Ω
L
V
= 2V
I(PP)
−40
−60
All Channels
A
A
= 10
= 1
V
V
A
A
= 10
= 1
V
V
−80
−100
−120
−140
0.01
0.001
0.01
0.001
V
R
V
= 5V
= 10kΩ
DD
V
R
V
= 3V
= 10kΩ
DD
L
0
L
0
=
4V
PP
=
2V
PP
T
A
= +25°C
T
A
= +25°C
−160
10
100
1k
10k
100k
10
100
1 k
10 k
100 k
10
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 26.
Figure 27.
Figure 28.
LARGE-SIGNAL FOLLOWER
LARGE-SIGNAL FOLLOWER
SMALL-SIGNAL FOLLOWER
PULSE RESPONSE
PULSE RESPONSE
PULSE RESPONSE
vs
TIME
vs
TIME
vs
TIME
V (2V/DIV)
I
V (50mV/DIV)
I
V (2V/DIV)
I
V
R
C
= 3V
= 10kΩ
= 8pF
DD
L
L
f = 1MHz
= +25°C
V
(1V/DIV)
T
O
A
V
(1V/DIV)
O
V
R
C
= 5V
DD
V
R
C
= 3V
= 10kΩ
= 8pF
DD
= 10kΩ
L
L
L
L
V
(50mV/DIV)
200
O
= 8pF
f = 85kHz
= +25°C
f = 85kHz
= +25°C
T
T
A
A
0
100
300
400
500
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
t − Time − µs
t − Time − µs
t − Time − µs
Figure 29.
Figure 30.
Figure 31.
SMALL-SIGNAL FOLLOWER
SHUTDOWN (ON AND OFF)
SHUTDOWN (ON AND OFF)
PULSE RESPONSE
PULSE RESPONSE
PULSE RESPONSE
vs
TIME
vs
TIME
vs
TIME
V
(2V/DIV)
SHDN
V (50mV/DIV)
I
V
R
C
= 5V
= 10kΩ
= 8pF
V
(2V/DIV)
SHDN
DD
L
R
L
= 600Ω
R
L
= 600Ω
L
f = 1MHz
= +25°C
R
L
= 10kΩ
R
L
= 10kΩ
T
A
V
(500mV/DIV)
V
(1V/DIV)
O
O
V
(50mV/DIV)
200
O
V
C
T
A
= 3V
= 8pF
= +25°C
DD
V
C
= 5V
= 8pF
DD
L
L
T
A
= +25°C
0
2
4
6
8
10 12 14 16
0
2
4
6
8
10 12 14 16 18
0
100
300
400
500
t − Time − µs
t − Time − µs
t − Time − µs
Figure 32.
Figure 33.
Figure 34.
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SLOS232E–JUNE 1999–REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
SHUTDOWN FORWARD
ISOLATION
SHUTDOWN REVERSE ISOLATION
SHUTDOWN SUPPLY CURRENT
vs
vs
vs
FREQUENCY
FREQUENCY
SUPPLY VOLTAGE
120
100
120
100
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
C
= 3V, 5V
DD
= 0pF
L
A
= 1
V
V
= 0.1V, 1.5V, 3V
I(PP)
T
= +125°C
= +85°C
A
80
60
80
60
T
A
R
L
= 600Ω
R
L
= 600Ω
R
= 10kΩ
L
T
= +25°C
= −40°C
A
R
= 10kΩ
L
T
A
40
20
40
20
V
= 3V, 5V
= 10kΩ
= 0pF
DD
R
L
C
L
Shutdown On
= OPEN
R
L
A
= 1
V
V = V
I DD/2
V
= 0.1VPP, 1.5VPP, 3VPP
IN
0
0
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
f − Frequency − Hz
f − Frequency − Hz
V
− Supply Voltage − V
DD
Figure 35.
Figure 36.
Figure 37.
SHUTDOWN SUPPLY CURRENT
vs
SHUTDOWN PULSE CURRENT
SHUTDOWN PULSE CURRENT
vs
vs
FREE-AIR TEMPERATURE
TIME
TIME
2.00
1.75
1.50
4
2.00
6
1.6
Shutdown Pulse
3
SD MODE Channel 1 and 2
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
4
A
V
= 1
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Shutdown Pulse
2
1
0
R
L
= OPEN
2
0
V
= V
DD/2
IN
1.25
1.00
0.75
0.50
0.25
0
I
R
L
= 10kΩ
DD
−1
−2
−3
−4
−5
−6
−7
−8
I
R
R
= 10kΩ
= 600Ω
DD
L
−2
V
= 5V
DD
−4
I
I
R
L
= 600Ω
DD
L
DD
−6
−8
V
= 5V
V
= 3V
DD
DD
V
= 3V
DD
C
T
= 8pF
= +25°C
C
T
= 8pF
= +25°C
L
L
−10
−12
−0.25
−0.50
−0.25
−0.50
A
A
0
4
8
12 16 20 24 28 30
0
4
8
12 16 20 24 28 30
−55 −35 −15
5
25 45 65 85 105 125
t − Time − µs
t − Time − µs
T
A
− Free-Air Temperature − °C
Figure 38.
Figure 39.
Figure 40.
14
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PARAMETER MEASUREMENT INFORMATION
RNULL
_
+
R
L
C
L
Figure 41.
APPLICATION INFORMATION
DRIVING A CAPACITIVE LOAD
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10pF, it is recommended that a resistor (RNULL) be placed in series with the output of the amplifier, as
shown in Figure 42. A minimum value of 20Ω should work well for most applications.
R
F
R
G
R
NULL
_
+
Input
Output
C
LOAD
Figure 42. Driving a Capacitive Load
OFFSET VOLTAGE
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
R
F
I
IB−
R
G
+
−
+
V
I
V
O
R
S
I
IB+
RF
RG
RF
RG
ǒ Ǔ
ǒ Ǔ
ǒ1 ) Ǔ" I ǒ1 ) Ǔ" I
VOO + VIO
IB) RS
IB* RF
Figure 43. Output Offset Voltage Model
15
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TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
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SLOS232E–JUNE 1999–REVISED JULY 2007
APPLICATION INFORMATION (continued)
GENERAL CONFIGURATIONS
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 44).
R
G
R
F
–
+
V
1
O
V
I
R1
V
C1
f
+
–3dB
2pR1C1
R
O
F
1
ǒ
Ǔ
+
ǒ
1 )
Ǔ
V
R
1 ) sR1C1
I
G
Figure 44. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is eight to ten times the filter frequency
bandwidth. Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
F
R
G
=
1
R
F
2 –
)
(
R
G
Q
Figure 45. 2-Pole Low-Pass Sallen-Key Filter
SHUTDOWN FUNCTION
Three members of the TLV247x family (TLV2470/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 350nA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2.
Therefore, when operating the device with split supply voltages (e.g., ±2.5V), the shutdown terminal needs to be
pulled to VDD– (not GND) to disable the operational amplifier.
The amplifier output with a shutdown pulse is shown in Figure 33 and Figure 34. The amplifier is powered with a
single 5V supply and configured as a noninverting configuration with a gain of 5. The amplifier turn-on and
turn-off times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform.
The times for the single, dual, and quad versions are listed in the data tables.
16
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SLOS232E–JUNE 1999–REVISED JULY 2007
APPLICATION INFORMATION (continued)
Figure 35 and Figure 36 show the amplifier forward and reverse isolation in shutdown. The operational amplifier
is powered by ±1.35V supplies and configured as a voltage follower (AV= 1). The isolation performance is plotted
across frequency using 0.1VPP, 1.5VPP, and 2.5VPP input signals. During normal operation, the amplifier would
not be able to handle a 2.5VPP input signal with a supply voltage of ±1.35V since it exceeds the common-mode
input voltage range (VICR). However, this curve illustrates that the amplifier remains in shutdown even under a
worst case scenario.
CIRCUIT LAYOUT CONSIDERATIONS
To achieve the levels of high performance of the TLV247x, follow proper printed circuit board (PCB) design
techniques. A general set of guidelines is given below:
•
Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
•
Proper power supply decoupling—Use a 6.8μF tantalum capacitor in parallel with a 0.1μF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1μF ceramic capacitor should always be used on the supply terminal of every amplifier. In
addition, the 0.1μF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
•
•
Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is
the best implementation.
Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the
input of the amplifier.
•
Surface-mount passive components—Using surface-mount passive components is recommended for
high-performance amplifier circuits for several reasons. First, because of the extremely low lead inductance
of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
GENERAL PowerPAD™ DESIGN CONSIDERATIONS
The TLV247x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted (see Figure 46a and Figure 46b). This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package (see
Figure 46c). Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
Soldering the PowerPAD to the PCB is always recommended, even with applications that have low power
dissipation. It provides the necessary mechanical and thermal connection between the lead frame die pad and
the PCB.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with previously awkward mechanical methods of heatsinking.
17
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TLV2474, TLV2475, TLV247xA
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SLOS232E–JUNE 1999–REVISED JULY 2007
APPLICATION INFORMATION (continued)
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
The thermal pad is electrically isolated from all terminals in the package.
Figure 46. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
1. The thermal pad must be connected to the most negative supply voltage on the device (GND pin).
2. Prepare the PCB with a top side etch pattern as illustrated in the thermal land pattern mechanical drawing
at the end of this document. There should be etch for the leads as well as etch for the thermal pad.
3. Place holes in the area of the thermal pad as illustrated in the land pattern mechanical drawing at the end
of this document. These holes should be 13mils (0.013 inches or 0.3302mm) in diameter. Keep them
small so that solder wicking through the holes is not a problem during reflow.
4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the TLV247x IC. These additional vias may be larger than the 13mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
5. Connect all holes to the internal ground plane that is at the same voltage potential as the device GND pin.
6. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes the soldering of vias that have plane connections
easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer.
Therefore, the holes under the TLV247x PowerPAD package should make their connection to the internal
ground plane with a complete connection around the entire circumference of the plated-through hole.
7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its
holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
8. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
9. With these preparatory steps in place, the TLV247x IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
For a given θJA, the maximum power dissipation is shown in Figure 47 and is calculated by Equation 1:
TMAX * TA
qJA
P + ǒ Ǔ
D
(1)
Where:
•
•
•
•
PD = Maximum power dissipation of TLV247x IC (watts)
TMAX = Absolute maximum junction temperature (+150°C)
TA = Free-ambient air temperature (°C)
θJA = θJC + θCA
–
–
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
18
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TLV2474, TLV2475, TLV247xA
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SLOS232E–JUNE 1999–REVISED JULY 2007
APPLICATION INFORMATION (continued)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
7
6
5
4
3
2
PWP Package
Low-K Test PCB
T
= +150°C
J
θ
= 29.7°C/W
JA
SOT-23 Package
Low-K Test PCB
= 324°C/W
θ
JA
DGN Package
Low-K Test PCB
θ
= 52.3°C/W
JA
SOIC Package
Low-K Test PCB
θ
= 176°C/W
JA
PDIP Package
Low-K Test PCB
θ
= 104°C/W
JA
1
0
−55 −40 −25 −10
5
20 35 50 65 80 95 110 125
T
A
− Free-Air Temperature − °C
Results are obtained with no air flow and using JEDEC Standard Low-K test PCB.
Figure 47. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of
the heat dissipation is at low output voltages with high output currents. Figure 48 to Figure 53 show this effect,
along with the quiescent heat, with an ambient air temperature of +70°C and +125°C. When using VDD = 3V,
there is generally not a heat problem with an ambient air temperature of +70°C. But, when using VDD = 5V, the
package is severely limited in the amount of heat it can dissipate. The other key factor when looking at these
graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat
dissipation. But the device should always be soldered to a copper plane to fully use the heat dissipation
properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted
on the PCB. As more trace and copper area is placed around the device,θJA decreases and the heat dissipation
capability increases. The currents and voltages shown in these graphs are for the total package. For the dual or
quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the proper
package.
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SLOS232E–JUNE 1999–REVISED JULY 2007
APPLICATION INFORMATION (continued)
TLV2470, TLV2471(1)
MAXIMUM RMS OUTPUT CURRENT
vs
TLV2470, TLV2471(1)
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
180
Maximum Output
Current Limit Line
Maximum Output
Current Limit Line
160
140
120
100
160
140
120
100
Packages With
≤ 110°C/W
C
B
G
C
θ
JA
B
at T = +125°C
A
or
A
θ
≤ 355°C/W
JA
A
80
60
40
80
60
40
at T = +70°C
A
Packages With
≤ 210°C/W
Safe Operating Area
θ
JA
at T = +70°C
A
V
T
T
A
= ±3V
= +150°C
= +125°C
DD
V
= ± 5V
= +150°C
= +125°C
DD
20
0
20
0
J
T
J
Safe Operating Area
T
A
0
0.25
0.50
0.75
1.00
1.25
1.50
0
0.5
1.0
1.5
2.0
2.5
| V | − RMS Output Voltage − V
O
| V | − RMS Output Voltage − V
O
Figure 48.
Figure 49.
TLV2472, TLV2473(1)
TLV2472, TLV2473(1)
MAXIMUM RMS OUTPUT CURRENT
vs
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
180
Maximum Output
Current Limit Line
Maximum Output
Current Limit Line
160
140
120
100
160
140
120
100
G
D
C
H
F
Packages With
≤ 55°C/W
G
θ
JA
at T = +125°C
A
H
or
D
80
60
40
80
60
40
θ
≤ 178°C/W
JA
C
at T = +70°C
A
Packages With
θ
≤ 105°C/W
JA
at T = +70°C
A
Safe Operating Area
V
T
T
A
= ± 3V
= +150°C
= +125°C
DD
V
= ± 5V
= +150°C
= +125°C
DD
20
0
20
0
J
T
J
Safe Operating Area
1.5 2.0 2.5
T
A
0
0.25
0.50
0.75
1.00
1.25
1.50
0
0.5
1.0
| V | − RMS Output Voltage − V
O
| V | − RMS Output Voltage − V
O
Figure 50.
Figure 51.
Note: (1) A - SOT23 (5); B - SOT23 (6); C - SOIC (8); D - SOIC (14); E - SOIC (16); F - MSOP PP (8); G - PDIP
(8); H - PDIP (14): I - PDIP (16); J - TSSOP PP (14/16)
20
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TLV2472, TLV2473
TLV2474, TLV2475, TLV247xA
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SLOS232E–JUNE 1999–REVISED JULY 2007
APPLICATION INFORMATION (continued)
TLV2474, TLV2475(1)
MAXIMUM RMS OUTPUT CURRENT
vs
TLV2474, TLV2475(1)
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
180
Maximum Output
Current Limit Line
Maximum Output
Current Limit Line
160
140
120
100
160
140
120
100
J
J
H and I
E
H and I
Packages With
≤ 88°C/W
80
60
40
80
60
40
E
θ
V
= ±5V
= +150°C
= +125°C
JA
DD
D
D
T
J
at T = +70°C
A
T
A
Packages With
≤ 52°C/W
V
= ±3V
= +150°C
= +125°C
DD
θ
20
0
20
0
JA
T
T
J
Safe Operating Area
0.75 1.00 1.25
at T = +70°C
Safe Operating Area
A
A
0
0.25
0.50
1.50
0
0.5
1.0
1.5
2.0
2.5
| V | − RMS Output Voltage − V
O
| V | − RMS Output Voltage − V
O
Figure 52.
Figure 53.
NOTE: (1) A - SOT23 (5); B - SOT23 (6); C - SOIC (8); D - SOIC (14); E - SOIC (16); F - MSOP PP (8); G -
PDIP (8); H - PDIP (14): I - PDIP (16); J - TSSOP PP (14/16)
21
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SLOS232E–JUNE 1999–REVISED JULY 2007
APPLICATION INFORMATION (continued)
MACROMODEL INFORMATION
Macromodel information provided was derived using Microsim PARTS™, the model generation software used
with Microsim PSpice®. The Boyle macromodel and subcircuit in Figure 54 are generated using the TLV247x
typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the
following key parameters can be generated to a tolerance of 20% (in most cases):
•
•
•
•
•
•
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
•
•
•
•
•
•
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
Open-loop voltage amplification
3
99
V
DD
+
egnd
rd1
11
rd2
12
rss
ro2
css
fb
rp
–
c1
7
+
c2
vlim
1
2
+
–
r2
9
6
IN+
IN–
–
8
vc
D
S
D
S
+
vb
ga
G
G
–
ro1
OUT
gcm
ioff
53
dp
5
dlp
dln
91
90
92
10
–
+
–
+
–
iss
dc
vlp
hlim
vln
–
+
GND
+ 54
4
de
ve
* TLV247x operational amplifier ”macromodel” subcircuit
* created using Parts release 8.0 on 4/27/99 at 14:31
* Parts is a MicroSim product.
iss
hlim
ioff
j1
10
90
0
4
dc
10.714E–6
75E–9
0
vlim 1K
dc
6
*
11
12
6
2
10 jx1
10 jx2
* connections: non–inverting input
j2
1
*
*
*
*
*
| inverting input
r2
9
100.00E3
12.527E3
12.527E3
10
| | positive power supply
| | | negative power supply
| | | | output
rd1
rd2
ro1
ro2
rp
3
11
12
5
3
8
| | | | |
7
99
4
10
.subckt TLV247x 1 2 3 4 5
*
3
3.8023E3
18.667E6
dc 0
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
*$
10
9
99
0
c1
11
6
12
7
99
53
5
91
90
3
0
99
1.1094E–12
c2
5.5000E–12
3
53
4
dc .842
dc .842
dc 0
dc 110
dc 110
css
dc
de
dlp
dln
dp
egnd
fb
10
5
556.53E–15
54
7
dy
dy
dx
dx
dx
8
54
90
92
4
91
0
0
92
dx
dy
jx1
jx2
D(Is=800.00E–18)
D(Is=800.00E–18 Rs=1m Cjo=10p)
99
7
poly(2) (3,0) (4,0) 0 .5 .5
poly(5) vb vc ve vlp vln 0
NJF(Is=1.0825E–12 Beta=594.78E–06 + Vto=–1)
NJF(Is=1.0825E–12 Beta=594.78E–06 + Vto=–1)
+ 39.614E6 –1E3 1E3 40E6 –40E6
ga
gcm
6
0
0
6
11
10
12 79.828E–6
99 32.483E–9
G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational
Amplifiers, ”IEEE Journal of Solid-State Circuits, SC-9, 353 (1974).
Figure 54. Boyle Macromodel and Subcircuit
22
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
TLV2470AID
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
6
6
8
8
8
8
6
6
6
6
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
2470AI
TLV2470AIDG4
TLV2470AIDR
TLV2470AIP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
2500
50
Green (RoHS
& no Sb/Br)
2470AI
2470AI
TLV2470AI
TLV2470AI
2470C
VAUC
SOIC
Green (RoHS
& no Sb/Br)
PDIP
P
Pb-Free
(RoHS)
TLV2470AIPE4
TLV2470CD
PDIP
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
SOIC
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLV2470CDBVR
TLV2470CDBVT
TLV2470CDR
TLV2470CDRG4
TLV2470CP
SOT-23
SOT-23
SOIC
DBV
DBV
D
3000
250
2500
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
VAUC
Green (RoHS
& no Sb/Br)
0 to 70
2470C
2470C
TLV2470C
2470I
SOIC
D
Green (RoHS
& no Sb/Br)
0 to 70
PDIP
P
Pb-Free
(RoHS)
0 to 70
TLV2470ID
SOIC
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TLV2470IDBVR
TLV2470IDBVRG4
TLV2470IDBVT
TLV2470IDBVTG4
TLV2470IDR
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
3000
3000
250
250
2500
Green (RoHS
& no Sb/Br)
VAUI
Green (RoHS
& no Sb/Br)
VAUI
Green (RoHS
& no Sb/Br)
VAUI
Green (RoHS
& no Sb/Br)
VAUI
Green (RoHS
& no Sb/Br)
2470I
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TLV2471AID
TLV2471AIDR
TLV2471AIP
ACTIVE
SOIC
SOIC
D
8
8
8
8
5
5
5
5
8
8
8
8
5
5
5
5
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
2471AI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
P
2500
50
Green (RoHS
& no Sb/Br)
2471AI
TLV2471AI
2471C
VAVC
PDIP
Pb-Free
(RoHS)
TLV2471CD
SOIC
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLV2471CDBVR
TLV2471CDBVRG4
TLV2471CDBVT
TLV2471CDBVTG4
TLV2471CDG4
TLV2471CDR
TLV2471CP
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
3000
3000
250
250
75
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
VAVC
Green (RoHS
& no Sb/Br)
0 to 70
VAVC
Green (RoHS
& no Sb/Br)
0 to 70
VAVC
Green (RoHS
& no Sb/Br)
0 to 70
2471C
2471C
TLV2471C
2471I
SOIC
D
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
PDIP
P
Pb-Free
(RoHS)
0 to 70
TLV2471ID
SOIC
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TLV2471IDBVR
TLV2471IDBVRG4
TLV2471IDBVT
TLV2471IDBVTG4
TLV2471IDR
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
3000
3000
250
250
2500
50
Green (RoHS
& no Sb/Br)
VAVI
Green (RoHS
& no Sb/Br)
VAVI
Green (RoHS
& no Sb/Br)
VAVI
Green (RoHS
& no Sb/Br)
VAVI
Green (RoHS
& no Sb/Br)
2471I
TLV2471IP
PDIP
P
Pb-Free
(RoHS)
TLV2471I
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TLV2472AID
TLV2472AIDG4
TLV2472AIDR
TLV2472AIDRG4
TLV2472AIP
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
2472AI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
2500
2500
50
Green (RoHS
& no Sb/Br)
2472AI
2472AI
2472AI
TLV2472AI
2472C
2472C
ABU
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
P
Pb-Free
(RoHS)
TLV2472CD
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLV2472CDG4
TLV2472CDGN
TLV2472CDGNR
TLV2472CDGNRG4
TLV2472CDR
TLV2472CDRG4
TLV2472CP
D
75
Green (RoHS
& no Sb/Br)
0 to 70
MSOP-
PowerPAD
DGN
DGN
DGN
D
80
Green (RoHS
& no Sb/Br)
0 to 70
MSOP-
PowerPAD
2500
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
ABU
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
0 to 70
ABU
SOIC
SOIC
PDIP
SOIC
SOIC
Green (RoHS
& no Sb/Br)
0 to 70
2472C
2472C
TLV2472CP
2472I
D
Green (RoHS
& no Sb/Br)
0 to 70
P
Pb-Free
(RoHS)
0 to 70
TLV2472ID
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TLV2472IDG4
TLV2472IDGN
TLV2472IDGNG4
TLV2472IDGNR
D
75
Green (RoHS
& no Sb/Br)
2472I
MSOP-
PowerPAD
DGN
DGN
DGN
80
Green (RoHS
& no Sb/Br)
ABV
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
ABV
MSOP-
2500
Green (RoHS
& no Sb/Br)
ABV
PowerPAD
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TLV2472IDGNRG4
TLV2472IDR
ACTIVE
MSOP-
DGN
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
ABV
PowerPAD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
SOIC
SOIC
PDIP
SOIC
D
D
8
2500
2500
50
Green (RoHS
& no Sb/Br)
2472I
2472I
TLV2472IDRG4
TLV2472IP
8
Green (RoHS
& no Sb/Br)
P
8
Pb-Free
(RoHS)
TLV2472IP
TLV2473AI
TLV2473AI
TLV2473AIN
TLV2473C
ABW
TLV2473AID
D
14
14
14
14
10
14
10
10
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLV2473AIDR
TLV2473AIN
D
2500
25
Green (RoHS
& no Sb/Br)
N
Pb-Free
(RoHS)
TLV2473CD
D
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLV2473CDGQR
TLV2473CDR
TLV2473IDGQR
TLV2473IDGQRG4
TLV2473IN
MSOP-
PowerPAD
DGQ
D
2500
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
0 to 70
SOIC
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
0 to 70
TLV2473C
ABX
MSOP-
PowerPAD
DGQ
DGQ
N
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
ABX
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
Pb-Free
(RoHS)
TLV2473IN
2474AI
TLV2474AID
D
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLV2474AIDG4
TLV2474AIDR
TLV2474AIDRG4
TLV2474AIN
D
50
Green (RoHS
& no Sb/Br)
2474AI
D
2500
2500
25
Green (RoHS
& no Sb/Br)
2474AI
D
Green (RoHS
& no Sb/Br)
2474AI
N
Pb-Free
(RoHS)
TLV2474AI
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TLV2474AINE4
TLV2474AIPWP
TLV2474AIPWPG4
TLV2474AIPWPR
TLV2474AIPWR
TLV2474AIPWRG4
TLV2474CD
ACTIVE
PDIP
HTSSOP
HTSSOP
HTSSOP
TSSOP
TSSOP
SOIC
N
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
25
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLV2474AI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PWP
PWP
PWP
PW
PW
D
90
90
Green (RoHS
& no Sb/Br)
2474AI
2474AI
2474AI
2474AI
2474AI
2474C
2474C
2474C
2474C
TLV2474C
2474C
2474C
2474I
Green (RoHS
& no Sb/Br)
2000
2000
2000
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TLV2474CDG4
TLV2474CDR
SOIC
D
50
Green (RoHS
& no Sb/Br)
0 to 70
SOIC
D
2500
2500
25
Green (RoHS
& no Sb/Br)
0 to 70
TLV2474CDRG4
TLV2474CN
SOIC
D
Green (RoHS
& no Sb/Br)
0 to 70
PDIP
N
Pb-Free
(RoHS)
0 to 70
TLV2474CPWP
TLV2474CPWPR
TLV2474ID
HTSSOP
HTSSOP
SOIC
PWP
PWP
D
90
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
2000
50
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TLV2474IDG4
TLV2474IDR
SOIC
D
50
Green (RoHS
& no Sb/Br)
2474I
SOIC
D
2500
2500
25
Green (RoHS
& no Sb/Br)
2474I
TLV2474IDRG4
TLV2474IN
SOIC
D
Green (RoHS
& no Sb/Br)
2474I
PDIP
N
Pb-Free
(RoHS)
TLV2474I
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TLV2474IPWP
TLV2474IPWPR
TLV2474IPWPRG4
TLV2475AIDR
TLV2475AIN
ACTIVE
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
14
14
14
16
16
16
16
16
16
16
16
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
N / A for Pkg Type
2474I
2474I
2474I
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PWP
PWP
D
2000
2000
2500
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TLV2475AI
TLV2475AI
TLV2475AI
2475AI
PDIP
N
Pb-Free
(RoHS)
TLV2475AINE4
TLV2475AIPWP
TLV2475AIPWPR
TLV2475CD
PDIP
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
HTSSOP
HTSSOP
SOIC
PWP
PWP
D
90
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
2000
40
Green (RoHS
& no Sb/Br)
2475AI
Green (RoHS
& no Sb/Br)
TLV2475C
TLV2475C
TLV2475C
2475C
TLV2475CDR
SOIC
D
2500
25
Green (RoHS
& no Sb/Br)
0 to 70
TLV2475CN
PDIP
N
Pb-Free
(RoHS)
0 to 70
TLV2475CPWPR
HTSSOP
PWP
2000
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
0 to 70
TLV2475IDR
TLV2475IDRG4
TLV2475IPWPR
OBSOLETE
OBSOLETE
ACTIVE
SOIC
SOIC
D
D
16
16
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
TLV2475I
HTSSOP
PWP
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2475I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2471, TLV2471A, TLV2472, TLV2472A, TLV2474, TLV2474A :
Automotive: TLV2471-Q1, TLV2471A-Q1, TLV2472-Q1, TLV2472A-Q1, TLV2474-Q1, TLV2474A-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 7
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV2470AIDR
TLV2470CDBVR
TLV2470CDBVT
TLV2470CDR
TLV2470IDBVR
TLV2470IDBVT
TLV2470IDR
SOIC
SOT-23
SOT-23
SOIC
D
DBV
DBV
D
8
6
6
8
6
6
8
8
8
5
5
8
5
5
8
8
8
2500
3000
250
330.0
178.0
178.0
330.0
178.0
178.0
330.0
330.0
330.0
180.0
180.0
330.0
180.0
180.0
330.0
330.0
330.0
12.4
9.0
6.4
3.23
3.23
6.4
5.2
3.17
3.17
5.2
2.1
1.37
1.37
2.1
8.0
4.0
4.0
8.0
4.0
4.0
8.0
8.0
8.0
4.0
4.0
8.0
4.0
4.0
8.0
8.0
8.0
12.0
8.0
Q1
Q3
Q3
Q1
Q3
Q3
Q1
Q1
Q1
Q3
Q3
Q1
Q3
Q3
Q1
Q1
Q1
9.0
8.0
2500
3000
250
12.4
9.0
12.0
8.0
SOT-23
SOT-23
SOIC
DBV
DBV
D
3.23
3.23
6.4
3.17
3.17
5.2
1.37
1.37
2.1
9.0
8.0
2500
2500
2500
3000
250
12.4
12.4
12.4
9.0
12.0
12.0
12.0
8.0
TLV2470IDR
SOIC
D
6.4
5.2
2.1
TLV2471AIDR
TLV2471CDBVR
TLV2471CDBVT
TLV2471CDR
TLV2471IDBVR
TLV2471IDBVT
TLV2471IDR
SOIC
D
6.4
5.2
2.1
SOT-23
SOT-23
SOIC
DBV
DBV
D
3.15
3.15
6.4
3.2
1.4
9.0
3.2
1.4
8.0
2500
3000
250
12.4
9.0
5.2
2.1
12.0
8.0
SOT-23
SOT-23
SOIC
DBV
DBV
D
3.15
3.15
6.4
3.2
1.4
9.0
3.2
1.4
8.0
2500
2500
2500
12.4
12.4
12.4
5.2
2.1
12.0
12.0
12.0
TLV2472AIDR
TLV2472CDGNR
SOIC
D
6.4
5.2
2.1
MSOP-
Power
DGN
5.3
3.4
1.4
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2012
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PAD
TLV2472CDR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
TLV2472IDGNR
MSOP-
Power
PAD
DGN
TLV2472IDR
TLV2473AIDR
TLV2473CDGQR
SOIC
SOIC
D
D
8
2500
2500
2500
330.0
330.0
330.0
12.4
16.4
12.4
6.4
6.5
5.3
5.2
9.0
3.4
2.1
2.1
1.4
8.0
8.0
8.0
12.0
16.0
12.0
Q1
Q1
Q1
14
10
MSOP-
Power
PAD
DGQ
TLV2473CDGQR
MSOP-
Power
PAD
DGQ
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TLV2473CDR
SOIC
D
14
10
2500
2500
330.0
330.0
16.4
12.4
6.5
5.3
9.0
3.4
2.1
1.4
8.0
8.0
16.0
12.0
Q1
Q1
TLV2473IDGQR
MSOP-
Power
PAD
DGQ
TLV2474AIDR
TLV2474AIPWPR
TLV2474AIPWR
TLV2474CDR
SOIC
D
14
14
14
14
14
14
14
16
16
16
16
16
2500
2000
2000
2500
2000
2500
2000
2500
2000
2500
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
12.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
12.4
6.5
6.9
6.9
6.5
6.9
6.5
6.9
6.5
6.9
6.5
6.9
6.9
9.0
5.6
5.6
9.0
5.6
9.0
5.6
10.3
5.6
10.3
5.6
5.6
2.1
1.6
1.6
2.1
1.6
2.1
1.6
2.1
1.6
2.1
1.6
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
16.0
12.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
HTSSOP PWP
TSSOP
SOIC
PW
D
TLV2474CPWPR
TLV2474IDR
HTSSOP PWP
SOIC
HTSSOP PWP
SOIC
HTSSOP PWP
SOIC
D
TLV2474IPWPR
TLV2475AIDR
D
TLV2475AIPWPR
TLV2475CDR
D
TLV2475CPWPR
TLV2475IPWPR
HTSSOP PWP
HTSSOP PWP
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV2470AIDR
TLV2470CDBVR
TLV2470CDBVT
TLV2470CDR
TLV2470IDBVR
TLV2470IDBVT
TLV2470IDR
SOIC
SOT-23
SOT-23
SOIC
D
DBV
DBV
D
8
6
6
8
6
6
8
8
8
5
5
8
5
5
8
8
8
8
8
8
2500
3000
250
340.5
180.0
180.0
340.5
180.0
180.0
340.5
367.0
340.5
182.0
182.0
340.5
182.0
182.0
340.5
340.5
358.0
340.5
358.0
340.5
338.1
180.0
180.0
338.1
180.0
180.0
338.1
367.0
338.1
182.0
182.0
338.1
182.0
182.0
338.1
338.1
335.0
338.1
335.0
338.1
20.6
18.0
18.0
20.6
18.0
18.0
20.6
35.0
20.6
20.0
20.0
20.6
20.0
20.0
20.6
20.6
35.0
20.6
35.0
20.6
2500
3000
250
SOT-23
SOT-23
SOIC
DBV
DBV
D
2500
2500
2500
3000
250
TLV2470IDR
SOIC
D
TLV2471AIDR
TLV2471CDBVR
TLV2471CDBVT
TLV2471CDR
TLV2471IDBVR
TLV2471IDBVT
TLV2471IDR
SOIC
D
SOT-23
SOT-23
SOIC
DBV
DBV
D
2500
3000
250
SOT-23
SOT-23
SOIC
DBV
DBV
D
2500
2500
2500
2500
2500
2500
TLV2472AIDR
TLV2472CDGNR
TLV2472CDR
TLV2472IDGNR
TLV2472IDR
SOIC
D
MSOP-PowerPAD
SOIC
DGN
D
MSOP-PowerPAD
SOIC
DGN
D
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2012
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV2473AIDR
TLV2473CDGQR
TLV2473CDGQR
TLV2473CDR
SOIC
MSOP-PowerPAD
MSOP-PowerPAD
SOIC
D
DGQ
DGQ
D
14
10
10
14
10
14
14
14
14
14
14
14
16
16
16
16
16
2500
2500
2500
2500
2500
2500
2000
2000
2500
2000
2500
2000
2500
2000
2500
2000
2000
367.0
358.0
364.0
367.0
358.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
335.0
364.0
367.0
335.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
35.0
27.0
38.0
35.0
38.0
35.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
35.0
TLV2473IDGQR
TLV2474AIDR
MSOP-PowerPAD
SOIC
DGQ
D
TLV2474AIPWPR
TLV2474AIPWR
TLV2474CDR
HTSSOP
TSSOP
PWP
PW
D
SOIC
TLV2474CPWPR
TLV2474IDR
HTSSOP
SOIC
PWP
D
TLV2474IPWPR
TLV2475AIDR
HTSSOP
SOIC
PWP
D
TLV2475AIPWPR
TLV2475CDR
HTSSOP
SOIC
PWP
D
TLV2475CPWPR
TLV2475IPWPR
HTSSOP
HTSSOP
PWP
PWP
Pack Materials-Page 4
IMPORTANT NOTICE
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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