TLV2334IDR [TI]
LinCMOSE LOW-VOLTAGE MEDIUM-POWER OPERATIONAL AMPLIFIERS; LinCMOSE低压中等功率运算放大器
| 型号： | TLV2334IDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LinCMOSE LOW-VOLTAGE MEDIUM-POWER OPERATIONAL AMPLIFIERS |
| 文件： | 总33页 (文件大小：499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2332
D OR P PACKAGE
(TOP VIEW)
Wide Range of Supply Voltages Over
Specified Temperature Range:
T = –40°C to 85°C . . . 2 V to 8 V
A
Fully Characterized at 3 V and 5 V
Single-Supply Operation
1OUT
1IN–
1IN+
/GND
V
DD
1
2
3
4
8
7
6
5
2OUT
2IN–
2IN+
Common-Mode Input-Voltage Range
Extends Below the Negative Rail and up to
V
DD–
V
–1 V at T = 25°C
DD
A
TLV2332
PW PACKAGE
(TOP VIEW)
Output Voltage Range Includes Negative
Rail
12
High Input Impedance . . . 10 Ω Typ
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
/GND
V
DD+
ESD-Protection Circuitry
2OUT
2IN–
2IN+
Designed-In Latch-Up Immunity
V
DD –
description
TLV2334
D OR N PACKAGE
(TOP VIEW)
The TLV233x operational amplifiers are in a family
of devices that has been specifically designed for
use in low-voltage single-supply applications.
Unlike the TLV2322 which is optimized for
ultra-low power, the TLV233x is designed to
provide a combination of low power and good ac
performance. Each amplifier is fully functional
down to a minimum supply voltage of 2 V, is fully
characterized, tested, and specified at both 3-V
and 5-V power supplies. The common-mode
input-voltage range includes the negative rail and
extends to within 1 V of the positive rail.
1OUT
4OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
1IN–
1IN+
4IN–
4IN+
V
V
DD+
DD–/GND
2IN+
3IN+
3IN–
3OUT
2N–
2OUT
8
TLV2334
PW PACKAGE
(TOP VIEW)
Having a maximum supply current of only 310 µA
per amplifier over full temperature range, the
TLV233x devices offer a combination of good ac
performance and microampere supply currents.
From a 3-V power supply, the amplifier’s typical
slew rate is 0.38 V/µs and its bandwidth is
300 kHz.
1
14
1OUT
1IN–
1IN+
4OUT
4IN–
4IN+
V
2IN+
V
DD+
DD–/GND
3IN+
3IN–
3OUT
2IN–
2OUT
7
8
AVAILABLE OPTIONS
PACKAGED DEVICES
§
V
max
CHIP FORM
(Y)
IO
†
‡
T
A
SMALL OUTLINE
(D)
PLASTIC DIP PLASTIC DIP
TSSOP
(PW)
AT 25°C
(N)
(P)
TLV2332IP
—
9 mV
TLV2332ID
TLV2334ID
—
TLV2332IPWLE
TLV2334IPWLE
TLV2332Y
TLV2334Y
–40°C to 85°C
10 mV
TLV2334IN
†
‡
§
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLV2332IDR).
The PW package is only available left-end taped and reeled (e.g., TLV2332IPWLE).
Chip forms are tested at 25°C only.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
description (continued)
These amplifiers offer a level of ac performance greater than that of many other devices operating at
comparable power levels. The TLV233x operational amplifiers are especially well suited for use in low-current
or battery-powered applications.
Low-voltage and low-power operation has been made possible by using the Texas Instruments silicon-gate
LinCMOS technology. TheLinCMOSprocessalsofeaturesextremelyhighinputimpedanceandultra-lowbias
currents making these amplifiers ideal for interfacing to high-impedance sources such as sensor circuits or filter
applications.
To facilitate the design of small portable equipment, the TLV233x is made available in a wide range of package
options, including the small-outline and thin-shrink small-outline package (TSSOP). The TSSOP package has
significantly reduced dimensions compared to a standard surface-mount package. Its maximum height of only
1.1 mm makes it particularly attractive when space is critical.
The device inputs and outputs are designed to withstand –100-mA currents without sustaining latch-up. The
TLV233x incorporates internal ESD-protection circuits that prevents functional failures at voltages up to
2000 V as tested under MIL-STD 883C, Method 3015.2; however, care should be exercised in handling these
devices as exposure to ESD may result in the degradation of the device parametric performance.
TLV2332Y chip information
This chip, when properly assembled, display characteristics similar to the TLV2332. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(4)
(3)
(2)
(5)
(6)
V
DD
(8)
(3)
(2)
1IN+
1IN–
+
(1)
1OUT
–
(5)
(6)
2IN+
2IN–
59
+
(7)
2OUT
–
(4)
V
DD–
/GND
CHIP THICKNESS: 15 MILS TYPICAL
(1)
(7)
BONDING PADS: 4 × 4 MILS MINIMUM
(8)
72
T max = 150°C
J
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2334Y chip information
This chip, when properly assembled, displays characteristics similar to the TLV2334. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
V
DD
(4)
BONDING PAD ASSIGNMENTS
(3)
(2)
1IN+
1IN–
+
–
+
–
+
–
(14)
(13)
(12) (11)
(10)
(9)
(8)
(1)
(7)
(8)
1OUT
2OUT
3OUT
(5)
(6)
2IN+
2IN–
68
(10)
(9)
3IN+
3IN–
(12)
(13)
+
–
4IN+
4IN–
(14)
4OUT
(1)
(2)
(3)
(4) (5)
108
(6)
(7)
(11)
V
/GND
DD–
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
T max = 150°C
J
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
equivalent schematic (each amplifier)
V
DD
P3
P4
R6
P2
P1
N5
IN–
IN+
R2
R1
P6
P5
C1
R5
N3
OUT
N4
N2
N1
N6
N7
D2
D1
R4
R3
R7
GND
ACTUAL DEVICE COMPONENT COUNT
†
COMPONENT
TLV2332
TLV2334
Transistors
Resistors
Diodes
54
14
4
108
28
8
Capacitors
2
4
†
Includes both amplifiers and all ESD, bias, and trim
circuitry.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
ID
DD±
I
DD
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA
O
Duration of short-circuit current at (or below) T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
A
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at the noninverting input with respect to the inverting input.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D–8
D–14
N
725 mW
5.8 mW/°C
7.6 mW/°C
12.6 mW/°C
8.0 mW/°C
4.2 mW/°C
5.6 mW/°C
377 mW
950 mW
494 mW
1575 mW
1000 mW
525 mW
819 mW
P
520 mW
PW–8
PW–14
273 mW
700 mW
364 mW
recommended operating conditions
MIN
2
MAX
8
UNIT
Supply voltage, V
V
DD
V
V
= 3 V
= 5 V
–0.2
–0.2
–40
1.8
3.8
85
DD
Common-mode input voltage, V
V
IC
Operating free-air temperature, T
DD
°C
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2332I electrical characteristics at specified free-air temperature
TLV2332I
TEST
CONDITIONS
†
PARAMETER
V
= 3 V
DD
TYP
V
= 5 V
DD
TYP
UNIT
T
A
MIN
MAX
MIN
MAX
V
V
R
R
= 1 V,
= 1 V,
= 50 Ω,
= 100 kΩ
O
S
L
25°C
0.6
9
1.1
9
V
IO
Input offset voltage
mV
Full range
11
11
Average temperature coefficient of
input offset voltage
25°C to
85°C
α
1
1.7
µV/°C
VIO
25°C
85°C
25°C
85°C
0.1
22
0.1
24
V
V
= 1 V,
= 1 V
O
IC
I
Input offset current (see Note 4)
Input bias current (see Note 4)
pA
IO
1000
2000
1000
2000
0.6
175
0.6
200
V
V
= 1 V,
= 1 V
O
IC
I
IB
pA
–0.2
to
–0.3
to
2.3
–0.2
to
4
–0.3
to
4.2
25°C
2
Common-mode input
voltage range (see Note 5)
V
ICR
V
–0.2
to
–0.2
to
Full range
1.8
3.8
V
V
= 1 V,
= 100 mV,
= –1 mA
25°C
Full range
25°C
1.75
1.7
1.9
115
83
3.2
3
3.9
95
IC
ID
V
V
A
High-level output voltage
Low-level output voltage
V
mV
V/mV
dB
OH
I
OH
V
V
= 1 V,
= –100 mV,
= 1 mA
150
190
150
190
IC
ID
OL
Full range
25°C
I
OL
V
R
= 1 V,
= 100 kΩ,
25
15
65
60
70
65
25
15
65
60
70
65
170
91
IC
Large-signal differential
voltage amplification
VD
L
Full range
25°C
See Note 6
V
V
R
= 1 V,
92
O
IC
CMRR Common-mode rejection ratio
= V
= 50 Ω
min,
ICR
Full range
25°C
S
V
V
R
= 1 V,
= 1 V,
= 50 Ω
94
94
IC
O
Supply-voltage rejection ratio
k
dB
SVR
(∆V
DD
/∆V )
IO
Full range
25°C
S
V
= 1 V,
= 1 V,
160
500
620
210
560
800
O
I
Supply current
µA
V
IC
DD
Full range
No load
†
Full range is –40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At V
= 5 V, V = 0.25 V to 2 V; at V = 3 V, V = 0.5 V to 1.5 V.
DD O
DD
O
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2332I operating characteristics at specified free-air temperature, V
= 3 V
DD
TLV2332I
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
MAX
V
= 1 V,
= 20 pF,
V
R
= 1 V,
= 100 kΩ,
I(PP)
25°C
85°C
0.38
IC
L
C
R
C
SR
Slew rate at unity gain
V/µs
L
S
L
0.29
32
See Figure 34
f =1 kHz,
See Figure 35
= 20 Ω,
V
n
Equivalent input noise voltage
25°C
nV/√Hz
25°C
85°C
25°C
85°C
–40°C
25°C
85°C
34
32
V
R
= V
OH
= 100 kΩ,
,
= 20 pF,
O
B
Maximum output-swing bandwidth
kHz
OM
1
See Figure 34
C = 20 pF,
L
L
300
235
42°
39°
36°
V = 10 mV,
I
B
Unity-gain bandwidth
Phase margin
kHz
R
= 100 kΩ,
See Figure 36
L
V = 10 mV,
f = B ,
R = 100 kΩ,
I
1
C
= 20 pF,
φ
m
L
L
See Figure 36
TLV2332I operating characteristics at specified free-air temperature, V
= 5 V
DD
TLV2332I
TYP
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
MAX
25°C
85°C
25°C
85°C
0.43
V
R
C
= 1 V,
= 100 kΩ,
= 20 pF,
IC
L
L
V
= 1 V
I(PP)
I(PP)
0.35
SR
Slew rate at unity gain
V/µs
0.40
V
= 2.5 V
See Figure 34
0.32
f =1 kHz,
See Figure 35
R
= 20 Ω,
S
V
n
Equivalent input noise voltage
25°C
32
nV/√Hz
25°C
85°C
25°C
85°C
–40°C
25°C
85°C
55
45
V
R
= V
,
C
= 20 pF,
O
L
OH
= 100 kΩ,
L
B
Maximum output-swing bandwidth
kHz
OM
1
See Figure 34
C = 20 pF,
L
525
370
43°
40°
38°
V = 10 mV,
I
B
Unity-gain bandwidth
Phase margin
kHz
R
= 100 kΩ,
See Figure 36
L
V = 10 mV,
f = B ,
R = 100 kΩ,
I
1
C
= 20 pF,
φ
m
L
L
See Figure 36
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2334I electrical characteristics at specified free-air temperature
TLV2334I
†
PARAMETER
TEST CONDITIONS
V
= 3 V
DD
TYP
V
= 5 V
DD
TYP
UNIT
T
A
MIN
MAX
MIN
MAX
V
R
R
= 1 V,
= 50 Ω,
= 100 kΩ
V
= 1 V,
25°C
0.6
10
1.1
10
O
S
L
IC
V
IO
Input offset voltage
mV
Full range
12
12
Average temperature coefficient
of input offset voltage
25°C to
85°C
α
1
1.7
µV/°C
VIO
25°C
85°C
25°C
85°C
0.1
22
0.1
24
I
Input offset current (see Note 4)
Input bias current (see Note 4)
V
V
= 1 V,
= 1 V,
V
V
= 1 V
= 1 V
pA
IO
O
IC
IC
1000
2000
1000
2000
0.6
175
0.6
200
I
IB
pA
V
O
–0.2
to
–0.3
to
2.3
–0.2
to
4
–0.3
to
4.2
25°C
2
Common-mode input voltage
range (see Note 5)
V
ICR
–0.2
to
1.8
–0.2
to
3.8
Full range
V
V
V
V
= 1 V,
= 100 mV,
= –1 mA
25°C
Full range
25°C
1.75
1.7
1.9
115
83
3.2
3
3.9
95
IC
ID
V
V
A
High-level output voltage
Low-level output voltage
OH
I
OH
V
V
= 1 V,
= –100 mV,
= 1 mA
150
190
150
190
IC
ID
mV
V/mV
dB
OL
Full range
25°C
I
OL
V
R
= 1 V,
= 100 kΩ,
25
15
65
60
70
65
25
15
65
60
70
65
170
91
IC
Large-signal differential
voltage amplification
VD
L
Full range
25°C
See Note 6
V
V
R
= 1 V,
= V
ICR
= 50 Ω
92
O
IC
CMRR Common-mode rejection ratio
min,
Full range
25°C
S
V
= 3 V to 5 V,
= 1 V, V = 1 V,
= 50 Ω
94
94
DD
Supply-voltage rejection ratio
k
dB
V
IC
SVR
O
(∆V
DD
/∆V )
IO
Full range
R
S
25°C
320
1000
1200
420
1120
1600
V
= 1 V,
V
= 1 V,
IC
O
I
Supply current
µA
DD
No load
Full range
†
Full range is –40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At V
= 5 V, V = 0.25 V to 2 V; at V = 3 V, V = 0.5 V to 1.5 V.
DD O
DD
O
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2334I operating characteristics at specified free-air temperature, V
= 3 V
DD
TLV2334I
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
MAX
V
= 1 V,
= 20 pF,
V
R
= 1 V,
= 100 kΩ,
I(PP)
25°C
85°C
0.38
IC
L
C
R
C
SR
Slew rate at unity gain
V/µs
L
S
L
0.29
32
See Figure 34
f = 1 kHz,
See Figure 35
= 20 Ω,
V
n
Equivalent input noise voltage
25°C
nV/√Hz
25°C
85°C
25°C
85°C
–40°C
25°C
85°C
34
32
V
R
= V
OH
= 100 kΩ,
,
= 20 pF,
O
B
Maximum output-swing bandwidth
kHz
OM
1
See Figure 34
C = 20 pF,
L
L
300
235
42°
39°
36°
V = 10 mV,
I
B
Unity-gain bandwidth
Phase margin
kHz
R
= 100 kΩ,
See Figure 36
L
V = 10 mV,
I
f = B ,
R
1
C
= 20 pF,
φ
m
L
= 100 kΩ,
L
See Figure 36
TLV2334I operating characteristics at specified free-air temperature, V
= 5 V
DD
TLV2334I
TYP
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
MAX
25°C
85°C
25°C
85°C
0.43
V
R
C
= 1 V,
= 100 kΩ,
= 20 pF,
IC
L
L
V
= 1 V
I(PP)
I(PP)
0.35
SR
Slew rate at unity gain
V/µs
0.40
V
= 2.5 V
See Figure 34
0.32
f = 1 kHz,
See Figure 35
R
= 20 Ω,
S
V
n
Equivalent input noise voltage
25°C
32
nV/√Hz
25°C
85°C
25°C
85°C
–40°C
25°C
85°C
55
45
V
R
= V
,
C
= 20 pF,
O
L
OH
= 100 kΩ,
L
B
Maximum output-swing bandwidth
kHz
OM
1
See Figure 34
C = 20 pF,
L
525
370
43°
40°
38°
V = 10 mV,
I
B
Unity-gain bandwidth
Phase margin
kHz
R
= 100 kΩ,
See Figure 36
L
V = 10 mV,
f = B ,
R = 100 kΩ,
I
1
C
= 20 pF,
φ
m
L
L
See Figure 36
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2332Y electrical characteristics, T = 25°C
A
TLV2332Y
V
= 3 V
DD
TYP
V
= 5 V
DD
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
V
= 1 V,
= 50 Ω,
V
R
= 1 V,
= 100 kΩ
O
IC
L
V
Input offset voltage
0.6
1.1
mV
IO
R
S
O
O
I
I
Input offset current (see Note 4)
Input bias current (see Note 4)
V
V
= 1 V,
= 1 V,
V
V
= 1 V
= 1 V
0.1
0.6
0.1
0.6
pA
pA
IO
IC
IB
IC
–0.3
to
2.3
–0.3
to
4.2
Common-mode input voltage
range (see Note 5)
V
ICR
V
V
= 1 V,
= –1 mA
V
V
= 100 mV,
= 100 mV,
= 100 kΩ,
IC
ID
V
V
High-level output voltage
Low-level output voltage
1.9
115
83
3.9
95
V
mV
V/mV
dB
OH
I
OH
V
= 1 V,
= 1 mA
IC
ID
OL
I
OL
Large-signal differential voltage
amplification
V
IC
= 1 V,
R
L
A
VD
170
91
See Note 6
V
R
= 1 V,
= 50 Ω
V
IC
V
IC
V
IC
= V
min,
ICR
O
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
92
S
V
R
= 1 V,
= 50 Ω
= 1 V,
= 1 V,
O
k
94
94
dB
SVR
(∆V
DD
/∆V
ID
)
S
V
O
= 1 V,
I
Supply current
160
210
µA
DD
No load
NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At V
= 5 V, V = 0.25 V to 2 V; at V = 3 V, V = 0.5 V to 1.5 V.
DD O
DD
O
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TLV2334Y electrical characteristics, T = 25°C
A
TLV2334Y
V
= 3 V
DD
TYP
V
= 5 V
DD
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
V
= 1 V,
= 50 Ω,
V
R
= 1 V
= 100 kΩ
O
IC
L
V
Input offset voltage
0.6
1.1
mV
IO
R
S
O
O
I
I
Input offset current (see Note 4)
Input bias current (see Note 4)
V
V
= 1 V,
= 1 V,
V
V
= 1 V
= 1 V
0.1
0.6
0.1
0.6
pA
pA
IO
IC
IB
IC
–0.3
to
2.3
–0.3
to
4.2
Common-mode input voltage
range (see Note 5)
V
ICR
V
V
= 1 V,
= –1 mA
V
V
= 100 mV,
= –100 mV,
= 100 kΩ,
IC
ID
V
V
High-level output voltage
Low-level output voltage
1.9
115
83
3.9
95
V
mV
V/mV
dB
OH
I
OH
V
= 1 V,
= 1 mA
IC
ID
OL
I
OL
Large-signal differential voltage
amplification
V
IC
= 1 V,
R
L
A
VD
170
91
See Note 6
V
R
= 1 V,
= 50 Ω
V
IC
V
O
V
IC
= V
min,
ICR
O
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
92
S
V
R
= 1 V,
= 50 Ω
= 1 V,
= 1 V,
IC
k
94
94
dB
SVR
(∆V
DD
/∆V
ID
)
S
V
O
= 1 V,
I
Supply current
320
420
µA
DD
No load
NOTES: 4. The typical values of input bias current offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At V
= 5 V, V = 0.25 V to 2 V; at V = 3 V, V = 0.5 V to 1.5 V.
DD O
DD
O
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
V
Input offset voltage
Distribution
1 – 4
5 – 8
9
IO
α
Input offset voltage temperature coefficient
Input bias current
Distribution
VIO
I
IB
I
IO
vs Free-air temperature
vs Free-air temperature
vs Supply voltage
Input offset current
9
V
IC
Common-mode input voltage
10
vs High-level output current
vs Supply voltage
vs Free-air temperature
11
12
13
V
High-level output voltage
Low-level output voltage
OH
vs Common-mode input voltage
vs Free-air temperature
vs Differential input voltage
vs Low-level output current
14
15, 16
17
V
OL
18
vs Supply voltage
vs Free-air temperature
vs Frequency
19
20
21, 22
A
Large-signal differential voltage amplification
Supply current
VD
vs Supply voltage
vs Free-air temperature
23
24
I
DD
vs Supply voltage
vs Free-air temperature
25
26
SR
Slew rate
V
Maximum peak-to-peak output voltage
Unity-gain bandwidth
vs Frequency
27
O(PP)
1
vs Supply voltage
vs Free-air temperature
28
29
B
vs Supply voltage
vs Free-air temperature
vs Load capacitance
30
31
32
φ
m
Phase margin
Phase shift
vs Frequency
vs Frequency
21, 22
33
V
n
Equivalent input noise voltage
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2332
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2332
INPUT OFFSET VOLTAGE
50
60
50
40
30
20
10
0
V
= 3 V
DD
= 25°C
V
= 5 V
DD
= 25°C
T
A
P Package
T
A
P Package
40
30
20
10
0
– 5 – 4 – 3 – 2 – 1
0
1
2
3
4
5
– 5 – 4 – 3 – 2 – 1
0
1
2
3
4
5
V
IO
– Input Offset Voltage – mV
V
IO
– Input Offset Voltage – mV
Figure 1
Figure 2
DISTRIBUTION OF TLV2334
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2334
INPUT OFFSET VOLTAGE
60
50
50
V
T
= 3 V
V
T
= 5 V
DD
= 25°C
DD
= 25°C
A
A
N Package
N Package
40
30
40
30
20
20
10
0
10
0
–1
0
1
2
3
4
5
–5 –4 –3 –2
–1
0
1
2
3
4
5
–5 –4 –3 –2
V
IO
– Input Offset Voltage – mV
V
IO
– Input Offset Voltage – mV
Figure 3
Figure 4
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2332
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2332
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
60
50
40
30
20
10
0
50
V
= 3 V
DD
= 25°C to 85°C
V
= 5 V
DD
= 25°C to 85°C
T
A
P Package
T
A
P Package
40
30
Outliers:
(1) 33 mV/°C
20
10
0
– 10 – 8 – 6 – 4 – 2
0
2
4
6
8
10
– 10 – 8 – 6 – 4 – 2
0
2
4
6
8
10
α
– Temperature Coefficient – µV/°C
α
– Temperature Coefficient – µV/°C
VIO
VIO
Figure 5
Figure 6
DISTRIBUTION OF TLV2334
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2334
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
TEMPERATURE COEFFICIENT
50
60
50
V
T
= 3 V
V
T
= 5 V
= 25°C to 85°C
DD
= 25°C to 85°C
DD
A
A
N Package
N Package
Outliers:
(1) 33 mV/°C
40
30
40
30
20
10
0
20
10
0
–10 –8 –6 –4 –2
0
2
4
6
8
10
–8 –6 –4
–10
–2
0
2
4
6
8
10
α
– Temperature Coefficient – µV/°C
α
– Temperature Coefficient – µV/°C
VIO
VIO
Figure 7
Figure 8
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
COMMON-MODE INPUT VOLTAGE
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
4
10
3
10
2
10
8
6
4
T
= 25°C
V
V
= 3 V
A
DD
= 1 V
Positive Limit
IC
See Note A
I
IB
1
1
10
I
IO
2
0
0.1
25
45
65
85
105
125
0
2
4
6
8
T
A
– Free-Air Temperature – °C
V
DD
– Supply Voltage – V
NOTE: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
Figure 9
Figure 10
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
SUPPLY VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
8
6
4
5
V
V
R
= 1 V
V
V
T
= 1 V
IC
IC
= 100 mV
= 100 mV
ID
ID
= 100 kΩ
= 25°C
= 25°C
L
A
4
3
2
1
0
T
A
V
DD
= 5 V
V
DD
= 3 V
2
0
0
–2
–4
–6
–8
0
2
4
6
8
V
DD
– Supply Voltage – V
I
– High-Level Output Current – mA
OH
Figure 11
Figure 12
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
COMMON-MODE INPUT VOLTAGE
700
650
600
550
3
2.4
1.8
1.2
0.6
0
V
V
V
= 3 V
DD
V
I
= 5 V
DD
= 1 V
IC
ID
= 5 mA
OL
= 100 mV
T
A
= 25°C
V
= –100 mV
ID
500
450
I
I
I
I
I
= –500 µA
= –1 mA
= –2 mA
= –3 mA
= –4 mA
OH
OH
OH
OH
OH
400
350
V
= –1 V
ID
300
–75 –50 –25
0
25
50
75 100 125
0
0.5
V
1
1.5
2
2.5
3
3.5
4
T
A
– Free-Air Temperature – °C
– Common-Mode Input Voltage – V
IC
Figure 13
Figure 14
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
200
185
170
155
140
125
110
95
900
800
700
600
500
V
V
V
I
= 3 V
DD
V
= 5 V
DD
= 1 V
IC
ID
V
IC
V
ID
I
= 0.5 V
= –1 V
= 5 mA
= –100 mV
= 1 mA
OL
OL
400
300
200
100
80
65
50
0
–75 –50 –25
0
25
50
75 100 125
–75 –50 –25
0
25
50
75 100 125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 15
Figure 16
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
800
700
600
500
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
V
V
= 5 V
DD
V
V
= 1 V
IC
= |V /2|
IC
ID
= –100 mV
ID
I
= 5 mA
OL
T
A
= 25°C
T
A
= 25°C
V
DD
= 5 V
400
300
V
DD
= 3 V
200
100
0.2
0.1
0
0
0
–1
–2
–3
–4
–5
–6
–7
–8
0
1
2
3
4
5
6
7
8
V
ID
– Differential Input Voltage – V
I
– Low-Level Output Current – mA
OL
Figure 17
Figure 18
LARGE-SIGNAL
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
500
500
R
= 100 kΩ
R
= 100 kΩ
L
L
450
450
400
350
400
350
T
A
= –40°C
300
300
250
200
150
100
50
250
200
150
100
50
T
A
= 25°C
V
DD
= 5 V
T
= 85°C
V
DD
= 3 V
A
0
0
0
2
4
6
8
–75 –50 –25
0
25
50
75 100 125
V
DD
– Supply Voltage – V
T
A
– Free-Air Temperature – °C
Figure 19
Figure 20
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
7
6
–60°
–30°
0°
10
V
= 3 V
= 100 kΩ
= 20 pF
= 25°C
DD
R
L
L
10
C
T
A
5
4
10
10
30°
A
VD
3
2
60°
10
10
90°
Phase Shift
1
10
120°
150°
1
0.1
180°
1 M
1
10
100
1 k
10 k
100 k
f – Frequency – Hz
Figure 21
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
7
6
10
–60°
–30°
0°
V
= 5 V
= 100 kΩ
= 20 pF
= 25°C
DD
R
L
L
10
C
T
A
5
10
4
10
10
30°
A
VD
3
60°
2
10
10
90°
Phase Shift
1
120°
150°
180°
1
0.1
1
10
100
1 k
10 k
100 k
1 M
f – Frequency – Hz
Figure 22
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
400
350
300
250
450
V
V
= 1 V
IC
V
V
= 1 V
= 1 V
IC
= 1 V
O
400
350
O
T
= –40°C
No Load
A
No Load
300
V
DD
= 5 V
T
= 25°C
A
250
200
150
100
50
V
DD
= 3 V
200
150
T
A
= 85°C
100
50
0
0
0
2
4
6
8
–75 –50 –25
0
25
50
75 100 125
V
DD
– Supply Voltage – V
T
A
– Free-Air Temperature – °C
Figure 23
Figure 24
SLEW RATE
vs
SUPPLY VOLTAGE
SLEW RATE
vs
FREE-AIR TEMPERATURE
0.9
0.9
0.8
0.7
V
V
= 1 V
IC
V
V
= 1 V
IC
I(PP)
= 1
= 1 V
I(PP)
= 1
= 1 V
A
V
A
0.8
0.7
0.6
0.5
0.4
0.3
V
R
C
= 100 kΩ
= 20 pF
= 25°C
L
L
R
C
= 100 kΩ
= 20 pF
L
L
T
A
0.6
0.5
0.4
0.3
V
DD
= 5 V
V
DD
= 3 V
0.2
0
2
4
6
8
–75 –50 –25
0
25
50
75
100 125
V
DD
– Supply Voltage – V
T
– Free-Air Temperature – °C
A
Figure 25
Figure 26
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
UNITY-GAIN BANDWIDTH
vs
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
FREQUENCY
1000
900
800
700
600
500
400
300
200
5
4
3
V = 10 mV
R
= 100 kΩ
I
L
R
= 100 kΩ
= 20 pF
= 25°C
L
L
C
T
V
= 5 V
DD
A
T
= – 40°C
A
V
= 3 V
T
DD
2
1
0
= 85°C
A
T
= 25°C
A
0
1
2
3
4
5
6
7
8
1
10
100
1000
V
DD
– Supply Voltage – V
f – Frequency – kHz
Figure 27
Figure 28
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
1000
900
800
700
600
500
400
300
200
V = 10 mV
I
R
L
C
L
= 100 kΩ
= 20 pF
V
= 5 V
DD
V
= 3 V
DD
–75 –50 –25
0
25
50
75 100 125
T
A
– Free-Air Temperature – °C
Figure 29
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS
SLOS189 – FEBRUARY 1997
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
PHASE MARGIN
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
50°
45°
V = 10 mV
V = 10 mV
I
I
48°
46°
44°
42°
40°
38°
36°
R
L
L
= 100 kΩ
= 20 pF
= 25°C
R
L
L
= 100 kΩ
C
C
= 20 pF
43°
43°
T
A
V
= 5 V
DD
39°
37°
35°
V
DD
= 3 V
34°
32°
30°
0
1
2
3
4
5
6
7
8
– 75 – 50 – 25
0
25
50
75 100 125
V
DD
– Supply Voltage – V
T
A
– Free-Air Temperature – °C
Figure 30
Figure 31
PHASE MARGIN
vs
LOAD CAPACITANCE
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
44°
300
250
V = 10 mV
I
R
T
= 20 Ω
= 25°C
S
A
R
= 100 KΩ
= 25°C
L
42°
40°
T
A
V
DD
= 5 V
200
150
38°
36°
34°
32°
30°
28°
V
DD
= 3 V
100
50
0
V
= 5 V
DD
V
= 3 V
DD
0
20
40
60
80
100
1
10
100
1000
C
– Load Capacitance – pF
f – Frequency – Hz
L
Figure 32
Figure 33
21
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PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLV233x is optimized for single-supply operation, circuit configurations used for the various tests
often present some inconvenience since the input signal, in many cases, must be offset from ground. This
inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative
rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives
the same result.
V
DD
V
DD+
–
+
–
+
V
O
V
O
V
I
V
I
R
C
C
L
R
L
L
L
V
DD–
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 34. Unity-Gain Amplifier
2 kΩ
2 kΩ
V
DD
V
DD+
20 Ω
20 Ω
–
+
–
+
V
O
1/2 V
V
O
DD
20 Ω
20 Ω
V
DD–
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 35. Noise-Test Circuit
10 kΩ
10 kΩ
V
DD
V
DD+
100 Ω
100 Ω
V
I
V
I
–
+
–
+
V
V
O
O
1/2 V
DD
C
L
C
L
V
DD–
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 36. Gain-of-100 Inverting Amplifier
22
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PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLV233x operational amplifier, attempts to measure the input bias
current can result in erroneous readings. The bias current at normal ambient temperature is typically less than
1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid
erroneous measurements:
•
•
Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 37). Leakages that would otherwise flow to the inputs are shunted away.
Compensate for the leakage of the test socket by actually performing an input bias current test (using a
picoammeter) with no device in the test socket. The actual input bias current can then be calculated by
subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
Many automatic testers as well as some bench-top operational amplifier testers use the servo-loop
technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires
thatadevicebeinsertedintoatestsockettoobtainacorrectreading;therefore, anopen-socketreading
is not feasible using this method.
8
5
V = V
IC
1
4
Figure 37. Isolation Metal Around Device Inputs (P package)
low-level output voltage
To obtain low-level supply-voltage operation, some compromise is necessary in the input stage. This
compromise results in the device low-level output voltage being dependent on both the common-mode input
voltage level as well as the differential input voltage level. When attempting to correlate low-level output
readings with those quoted in the electrical specifications, these two conditions should be observed. If
conditions other than these are to be used, please refer to the Typical Characteristics section of this data sheet.
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. These measurements should be
performed at temperatures above freezing to minimize error.
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
23
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generallymeasuredbymonitoringthedistortionleveloftheoutputwhileincreasingthefrequencyofasinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 34. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. Thefrequencyisthenincreaseduntilthemaximumpeak-to-peakoutputcannolongerbemaintained
(Figure 38). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 100 Hz
(b) B
OM
> f > 100 Hz
(c) f = B
OM
(d) f > B
OM
Figure 38. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
APPLICATION INFORMATION
single-supply operation
While the TLV233x performs well using dual-
power supplies (also called balanced or split
supplies), the design is optimized for single-
supply operation. This includes an input common-
mode voltage range that encompasses ground as
well as an output voltage range that pulls down to
ground. The supply voltage range extends down
to 2 V, thus allowing operation with supply levels
commonly available for TTL and HCMOS.
V
DD
R2
R1
V
I
–
+
V
I
O
TLE2426
Many single-supply applications require that a
voltage be applied to one input to establish a
reference level that is above ground. This virtual
ground can be generated using two large
resistors, but a preferred technique is to use a
virtual-ground generator such as the TLE2426
(see Figure 39).
V
–V
V
DD
2
R2
R1
DD
2
V
O
Figure 39. Inverting Amplifier With Voltage
Reference
24
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APPLICATION INFORMATION
single-supply operation (continued)
The TLE2426 supplies an accurate voltage equal to V /2, while consuming very little power and is suitable
DD
for supply voltages of greater than 4 V. The TLV233x works well in conjunction with digital logic; however, when
powering both linear devices and digital logic from the same power supply, the following precautions are
recommended:
•
Power the linear devices from separate bypassed supply lines (see Figure 40); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
•
Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, RC decoupling may be necessary in high-frequency
applications.
–
Power
Supply
Logic
Logic
Logic
+
(a) COMMON-SUPPLY RAILS
–
+
Power
Supply
Logic
Logic
Logic
(b) SEPARATE-BYPASSED SUPPLY RAILS (preferred)
Figure 40. Common Versus Separate Supply Rails
input characteristics
The TLV233x is specified with a minimum and a maximum input voltage that, if exceeded at either input, could
cause the device to malfunction. Exceeding this specified range is a common problem, especially in
single-supply operation. The lower the range limit includes the negative rail, while the upper range limit is
specified at V
– 1 V at T = 25°C and at V
– 1.2 V at all other temperatures.
DD
A
DD
The use of the polysilicon-gate process and the careful input circuit design gives the TLV233x very good input
offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS
devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant
implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the
polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset
voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of operation.
Because of the extremely high input impedance and resulting low bias-current requirements, the TLV233x is
well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can
easily exceed bias-current requirements and cause a degradation in device performance.
25
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APPLICATION INFORMATION
input characteristics (continued)
It is good practice to include guard rings around inputs (similar to those of Figure 37 in the Parameter
Measurement Information section). These guards should be driven from a low-impedance source at the same
voltage level as the common-mode input (see Figure 41).
The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.
V
I
–
+
–
+
–
+
V
O
V
O
V
O
V
I
V
I
(a) NONINVERTING AMPLIFIER
(b) INVERTING AMPLIFIER
(c) UNITY-GAIN AMPLIFIER
Figure 41. Guard-Ring Schemes
noise performance
The noise specifications in operational amplifiers circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias-current requirements of the TLV233x results in a very low noise current,
which is insignificant in most applications. This feature makes the device especially favorable over bipolar
devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noise
currents.
feedback
Operational amplifiers circuits nearly always
employ feedback, and since feedback is the first
prerequisite for oscillation, caution is appropriate.
Most oscillation problems result from driving
capacitive loads and ignoring stray input
capacitance. A small-value capacitor connected
in parallel with the feedback resistor is an effective
remedy (see Figure 42). The value of this
capacitor is optimized empirically.
–
+
Figure 42. Compensation for Input Capacitance
electrostatic-discharge protection
The TLV233x incorporates an internal electrostatic-discharge (ESD)-protection circuit that prevents functional
failures at voltages up to 2000 V as tested under MIL-PRF-38535. Method 3015.2. Care should be exercised,
however, when handling these devices as exposure to ESD may result in the degradation of the device
parametric performance. The protection circuit also causes the input bias currents to be temperature dependent
and have the characteristics of a reverse-biased diode.
26
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APPLICATION INFORMATION
latch-up
BecauseCMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLV233xinputs
and outputs are designed to withstand –100-mA surge currents without sustaining latch-up; however,
techniques should be used to reduce the chance of latch-up whenever possible. Internal-protection diodes
should not by design be forward biased. Applied input and output voltage should not exceed the supply voltage
by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply
transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails
as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
output characteristics
V
DD
The output stage of the TLV233x is designed to
sink and source relatively high amounts of current
(see Typical Characteristics). If the output is
subjected to a short-circuit condition, this high-
current capability can cause device damage
undercertainconditions. Outputcurrentcapability
increases with supply voltage.
R
P
V
F
V
I
I
P
DD
O
I
V
I
–
+
R
P
I
I
L
P
V
O
I
P
= Pullup Current
Required by the
F
Operational Amplifier
(typically 500 µA)
R2
Although the TLV233x possesses excellent
high-level output voltage and current capability,
methods are available for boosting this capability
if needed. The simplest method involves the use
I
L
R
R1
L
Figure 43. Resistive Pullup to Increase V
OH
of a pullup resistor (R )connectedfromtheoutput
P
to the positive supply rail (see Figure 43). There
are two disadvantages to the use of this circuit.
First, the NMOS pulldown transistor N4 (see
equivalent schematic) must sink a comparatively
largeamountofcurrent. Inthiscircuit, N4behaves
likealinearresistorwithanonresistancebetween
approximately 60 Ω and 180 Ω, depending on
how hard the operational amplifier input is driven.
2.5 V
–
V
O
+
V
I
C
L
With very low values of R , a voltage offset from
0 V at the output occurs. Secondly, pullup resistor
P
T
= 25°C
A
f = 1 kHz
= 1 V
R acts as a drain load to N4 and the gain of the
V
P
I(PP)
operational amplifier is reduced at output voltage
levels where N5 is not supplying the output
current.
–2.5 V
Figure 44. Test Circuit for Output Characteristics
All operating characteristics of the TLV233x are measured using a 20-pF load. The device drives higher
capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower
frequencies thereby causing ringing, peaking, or even oscillation (see Figure 44 and Figure 45). In many cases,
adding some compensation in the form of a series resistor in the feedback loop alleviates the problem.
27
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APPLICATION INFORMATION
output characteristics (continued)
(a) C = 20 pF, R = NO LOAD
(b) C = 170 pF, R = NO LOAD
(c) C = 190 pF, R = NO LOAD
L L
L
L
L
L
Figure 45. Effect of Capacitive Loads
28
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MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Four center pins are connected to die mount pad.
E. Falls within JEDEC MS-012
29
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MECHANICAL INFORMATION
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
30
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MECHANICAL INFORMATION
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
4040082/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
31
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MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,32
0,19
0,65
M
0,13
14
8
0,15 NOM
4,50
4,30
6,70
6,10
Gage Plane
0,25
1
7
0°–8°
0,75
A
0,50
Seating Plane
0,10
1,20 MAX
0,10 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/D 10/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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