TLIN1028-Q1 [TI]
具有集成稳压器的汽车本地互联网络 (LIN) 收发器;型号: | TLIN1028-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有集成稳压器的汽车本地互联网络 (LIN) 收发器 稳压器 |
文件: | 总54页 (文件大小:3174K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLIN1028-Q1
ZHCSK68B –AUGUST 2019 –REVISED JUNE 2022
TLIN1028-Q1 汽车LIN 125mA 系统基础芯片(SBC)
1 特性
2 应用
• AEC-Q100(1 级):符合汽车应用要求
• 符合本地互连网络(LIN) 物理层规范ISO/DIS
17987-4,并符合适用于LIN 的SAE J2602 推荐实
践要求
• 车身电子装置和照明
• 混合动力、电动和动力总成系统
• 汽车信息娱乐系统和仪表组
• 电器
• 提供功能安全
3 说明
– 有助于进行功能安全系统设计的文档
• 支持12V 应用
• 宽工作范围
TLIN1028-Q1 是一款本地互连网络 (LIN) 物理层收发
器,符合 LIN 2.2AISO/DIS 17987–4 标准,具有集成
的低压降(LDO) 稳压器。
– ±58V LIN 总线故障保护
– 支持3.3V 或5V 的LDO 输出
– 睡眠模式:超低电流消耗
允许以下类型的唤醒事件:
• LIN 总线或通过EN 引脚的本地唤醒
– 上电和断电无干扰运行
此 LIN 系统基础芯片 (SBC) 通过为功率微处理器、传
感器或其他器件提供电流高达 70mA (D) 或 125mA
(DRB 和 DDA)的 3.3V 或 5V 电压轨,来降低系统
的复杂性。TLIN1028-Q1 具有经过优化的限流波形整
形驱动器,可降低电磁辐射 (EME)。 TLIN1028-Q1 将
TXD 输入上的 LIN 协议数据流转化为 LIN 总线信号。
接收器将数据流转化为逻辑电平信号,此信号通过开漏
RXD 引脚发送到微处理器。
• 保护特性:
– ESD 保护、VSUP 欠压保护
– TXD 显性超时(DTO) 保护、热关断
– 系统级未供电节点或接地断开失效防护
• VCC 电源高达125mA,采用DRB 和DDA 封装
• 采用SOIC (8) 和HSOIC (8) 封装以及无引线
VSON (8) 封装,具有改善的自动光学检测(AOI) 功
能
器件信息
封装(1)
封装尺寸(标称值)
4.90mm x 3.91mm
4.90mm x 3.91mm
3.00mm x 3.00mm
器件型号
TLIN1028D-Q1
SOIC (8)
TLIN1028DDA-Q1
TLIN1028DRB-Q1
HSOIC (8)
VSON (8)
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
Commander
Node
VBAT
VBAT
Responder
Node
10 µF
10 µF
VSUP
VSUP
Vcc
Vcc
EN
100 nF
EN
1
1
8
2
8
2
VDD
VDD
Commander
Node
100 nF
I/O
I/O
MCU w/o
pullup
MCU w/o
pullup
Pull-up
1 k
V
DD I/O
V
DD I/O
Low
Power
MCU
Low
Power
MCU
LIN
LIN
LIN Bus
LIN Bus
4
4
LIN Controller
Or
SCI/UART
LIN Controller
Or
SCI/UART
5
5
220 pF
220 pF
RXD
TXD
RXD
TXD
6
7
6
7
GND
3,PAD
GND
3,PAD
nRST
nRST
简化版原理图,指挥官节点(1)
简化版原理图,响应者节点(2)
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLLSEX4
TLIN1028-Q1
ZHCSK68B –AUGUST 2019 –REVISED JUNE 2022
www.ti.com.cn
Table of Contents
9.2 Functional Block Diagram.........................................21
9.3 Feature Description...................................................21
9.4 Device Functional Modes..........................................25
10 Application and Implementation................................29
10.1 Application Information........................................... 29
10.2 Typical Application.................................................. 29
11 Power Supply Recommendations..............................34
12 Layout...........................................................................35
12.1 Layout Guidelines................................................... 35
12.2 Layout Example...................................................... 36
13 Device and Documentation Support..........................37
13.1 Documentation Support.......................................... 37
13.2 Related Links.......................................................... 37
13.3 接收文档更新通知................................................... 37
13.4 支持资源..................................................................37
13.5 Trademarks.............................................................37
13.6 Electrostatic Discharge Caution..............................38
13.7 术语表..................................................................... 38
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明(续).........................................................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 ESD Ratings, IEC Specification..................................4
7.4 Recommended Operating Conditions.........................5
7.5 Thermal Information....................................................5
7.6 Power Supply Characteristics.....................................5
7.7 Electrical Charateristics.............................................. 6
7.8 AC Switching Characteristics......................................8
7.9 Typical Characteristics..............................................10
8 Parameter Measurement Information..........................12
8.1 Test Circuit: Diagrams and Waveforms.....................12
9 Detailed Description......................................................21
9.1 Overview...................................................................21
Information.................................................................... 38
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (July 2020) to Revision B (June 2022)
Page
• 将提到的所有旧术语实例更改为“指挥官”和“响应者”。.............................................................................. 1
• Changed nRST is only dependent.. statement to: nRST is dependent in the nRST (Reset Output) section... 23
• Changed nRST: Float to nRST: GND in the sleep mode section of 图9-5 ......................................................25
Changes from Revision * (August 2019) to Revision A (July 2020)
Page
• 将文档状态从预告信息更改为量产数据.............................................................................................................1
• 添加了特性:提供功能安全.................................................................................................................................1
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5 说明(续)
休眠模式可实现超低电流消耗,该模式允许通过 LIN 总线或 EN 引脚实现唤醒。LIN 总线有两种状态:显性状态
(电压接近接地)和隐性状态(电压接近电池)。在受支配状态下,LIN 总线被内部上拉电阻器 (45kΩ) 和串联二
极管拉高,所以响应者节点应用无需外部上拉组件。按照 LIN 规范,指挥官节点应用需要一个外部上拉电阻器
(1kΩ) 加上一个串联二极管。
6 Pin Configuration and Functions
1
2
3
4
8
7
6
5
VSUP
EN
VCC
1
2
3
4
8
7
6
5
VSUP
EN
VCC
nRST
TXD
RXD
nRST
TXD
RXD
Thermal
Pad
GND
LIN
GND
LIN
Not to scale
Not to scale
图6-1. D Package, 8-Pin (SOIC), Top View
图6-2. DRB Package, 8-Pin (VSON), Top View
1
2
3
4
8
7
6
5
VSUP
EN
VCC
nRST
TXD
RXD
Thermal
Pad
GND
LIN
Not to scale
图6-3. DDA Package, 8-Pin (HSOIC), Top View
表6-1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
1
VSUP
EN
HV Supply In Device supply voltage (connected to battery in series with external reverse-blocking diode)
2
D I
GND
HV I/O
D O
Enable input
3
GND
LIN
Ground (2) (3)
4
LIN bus single-wire transmitter and receiver
RXD output (open-drain) interface reporting state of LIN bus voltage
TXD input interface to control state of LIN output
Reset output (active low)
5
RXD
TXD
nRST
VCC
6
D I
7
D O
8
Supply Out Output voltage from integrated LDO
(1) HV - High Voltage, DI - Digital Input, DO - Digital Output, HV I/O - High Voltage Input/Output
(2) When the thermal pad is present, it must be soldered to ground plane.
(3) If the DDA package is placed onto a D package footprint without the thermal pad soldered down, expect the performance to match the
D package and not the DDA package.
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7 Specifications
7.1 Absolute Maximum Ratings
(1)
MIN
–0.3
–58
MAX
UNIT
V
VSUP
Supply voltage range
42
VLIN
LIN Bus input voltage
58
V
VCC50
Regulated 5 V Output Supply
Regulated 3.3 V Output Supply
Reset output voltage
6
V
–0.3
–0.3
–0.3
–0.3
–0.3
VCC33
4.5
V
VnRST
VCC + 0.3
V
VLOGIC_INPUT
VLOGIC_OUTPUT
IVCC
Logic input voltage
6
6
V
Logic output voltage
V
VCC supply current(2)
300
8
mA
mA
mA
°C
°C
IO
Digital pin output current
Reset and RXD open-drain output current
Junction temperature
–8
–5
IO(nRST_RXD)
TJ
5
165
150
–40
–65
Tstg
Storage temperature range
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Device will enter thermal shutdown prior to hitting this limit. If the limit is reached the device may sustain permanent damage.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM) classification level H2: VSUP, LIN, and WAKE with
respect to ground
±8000
Human body model (HBM) classification level 3A: all other pins, per AEC
Q100-002(1)
V(ESD)
Electrostatic discharge
±4000
±750
V
Charged device model (CDM) classification level
All pins
C5, per AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings, IEC Specification
VALUE
UNIT
V
Electrostatic discharge per IEC 62228-2 (1), LIN, VSUP
terminal to GND
Contact discharge
Indirect ESD discharge
Contact discharge
Air discharge
Pulse 1
±15000
±15000
±8000
±25000
-100
V(ESD)
V
V(ESD)
Powered electrostatic discharge per SAE J2962-1(3)
V
Pulse 2a
75
ISO 7637-2 and IEC 62215-3 transients per IEC
62228-1(2)
Transient
Transient
V
V
Pulse 3a
-150
Pulse 3b
100
ISO 7637 slow transients pulse
Per SAE J2962-1(4)
30
(1) IEC 62228-2 ESD testing performed at third party. Different system-level configurations may lead to different results.
(2) ISO 7637 is a system-level transient test. Different system-level configurations may lead to different results.
(3) SAE J2962-1 Testing performed at third party US3 approved EMC test facility.
(4) ISO 7637 is a system-level transient test. Results given here are specific to the SAE J2962-1 Test specification conditions. Different
system-level configurations may lead to different results.
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7.4 Recommended Operating Conditions
MIN
5.5
0
NOM
MAX
28
UNIT
V
VSUP
Supply voltage
VLIN
LIN bus input voltage
28
V
VLOGIC5
VLOGIC33
IOH(DO)
IOL(DO)
C(VSUP)
C(VCC)
C(VCC)
ESRCO
Logic pin voltage
0
5.25
3.465
V
Logic pin voltage
0
V
Digital terminal HIGH level output current
Digital terminal LOW level output current
VSUP supply capacitance
-2
mA
mA
nF
µF
µF
Ω
2
100
1.5
VCC supply capacitance; 20 µA to full load
VCC supply capacitance; no load to full load
Output ESR requirements
10
0.001
2
7.5 Thermal Information
TLIN1028
DRB
8 PINS
45.7
THERMAL METRIC(1)
D
8 PINS
119.4
51.5
64.9
9.6
DDA
8 PINS
40.9
60.5
15.6
4.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
49.2
18.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
ψJT
63.7
n/a
18.8
15.8
4.6
ψJB
RθJC(bot)
2.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Power Supply Characteristics
parameters valid over –40℃≤TJ ≤150 ℃range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
36
UNIT
V
SUPPLY VOLTAGE AND CURRENT
Device is operational beyond the LIN
defined nominal supply voltage range. See
图8-1 and 图8-2
Operational supply voltage (ISO/DIS 17987
Param 10)(2)
VSUP
5.5
Normal and Standby Modes: Ramp VSUP
while LIN signal is a 10 kHz square wave
with 50 % duty cycle and swing between 5.5
V ≤VLIN ≤28 V. See 图8-1 and 图8-2
5.5
5.5
1.8
28
V
Nominal supply voltage (ISO/DIS 17987
Param 10)(2)
VSUP
Sleep Mode
Ramp Up
28
4.2
2.7
V
V
V
UVSUPR
UVSUPF
Under voltage VSUP threshold
Under voltage VSUP threshold
3.5
2.1
Ramp Down
Delta hysteresis voltage for VSUP under
voltage threshold
UVHYS
ISUP
1.5
V
Transceiver and LDO supply current (D
Package)
Transceiver normal mode dominant plus
LDO output
80
mA
mA
Transceiver and LDO supply current (DRB
and DDA Packages)
Transceiver normal mode dominant plus
LDO output
ISUP
135
Normal Mode: EN = VCC, bus dominant:
total bus load where RLIN ≥500 Ω and CLIN
≤10 nF
1.2
1
5
mA
mA
ISUPTRXDOM
Supply current transceiver only
Standby Mode: EN = 0 V, bus dominant:
total bus load where RLIN ≥500 Ω and CLIN
≤10 nF
2.1
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7.6 Power Supply Characteristics (continued)
parameters valid over –40℃≤TJ ≤150 ℃range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Normal Mode: EN = VCC
Bus recessive: LIN = VSUP
,
450
775
µA
,
Standby Mode: EN = 0 V, LIN = recessive =
SUP, IOH from processor ≤1 µA
38
55
55
33
V
ISUPTRXREC
Supply current transceiver only(3)
Added Standby Mode current through the
RXD pull-up resistor with a value of 100 kΩ:
EN = 0 V, LIN = recessive = VSUP, RXD =
GND(1)
µA
µA
5.5 V < VSUP ≤28 V, LIN = VSUP, EN = 0 V,
TXD and RXD floating
ISUPTRXSLP
Sleep mode supply current transceiver only
17
REGULATED OUTPUT VCC
VCC
Regulated output (D package)
VSUP = 5.5 to 28 V, ICC = 1 to 70 mA
2
2
%
–2
–2
VCC
Regulated output (DRB and DDA package) VSUP = 5.5 to 28 V, ICC = 1 to 125 mA
%
Line regulation
50
50
50
mV
mV
mV
∆VCC(∆VSUP)
∆VCC(∆VSUPL)
∆VCC(∆VSUPL)
VSUP = 5.5 to 28 V, ΔVCC, ICC = 10 mA
ICC = 1 to 125 mA, VSUP = 14 V, ΔVCC
ICC = 1 to 70 mA, VSUP = 14 V, ΔVCC
Load regulation (DRB and DDA package)
Load regulation (D package)
Dropout voltage (5 V LDO) (DRB and DDA
package)
VDROP
VDROP
VDROP
300
300
350
600
600
700
mV
mV
mV
V
V
V
V
SUP –VCC, ICC = 125 mA;
SUP –VCC, ICC = 70 mA;
SUP –VCC, ICC = 125 mA;
SUP –VCC, ICC = 70 mA;
Dropout voltage (5 V LDO) (D package)
Dropout voltage (3.3 V LDO) (DRB and DDA
package)
VDROP
Dropout voltage (3.3 V LDO) (D package)
Under voltage 5 V VCC threshold
350
4.7
700
mV
V
UVCC5R
UVCC5F
UVCC33R
UVCC33F
Ramp Up
4.86
Under voltage 5 V VCC threshold
Ramp Down
Ramp Up
4.2
4.45
2.9
V
Under voltage 3.3 V VCC threshold (3)
Under voltage 3.3 V VCC threshold(3)
3.1
15
V
Ramp Down
2.5
1
2.75
V
VCC undervoltage deglitch time. An UVCC
event will not be recognized unless the
duration is longer than this.(3)
tDET(UVCC)
CnRST = 20pF
µs
ICCOUT
ICCOUT
ICCOUTL
Output current (D Package)
Output current (DRB and DDA package)
Output current limit
VCC in regulation with 12 V VSUP
VCC in regulation with 12 V VSUP
VCC short to ground
0
0
70
125
275
mA
mA
mA
VRIP = 0.5 VPP, Load = 10 mA, ƒ= 100 Hz,
CO = 10 μF
PSRR
Power supply rejection ratio(3)
60
10
dB
TSDR
Thermal shutdown temperature
Thermal shutdown temperature
Thermal shutdown hysteresis
Internal junction temperature - rising
Internal junction temperature - falling
165
°C
°C
°C
TSDF
150
TSDHYS
(1) RXD pin is an open-drain output. In standby mode RXD is pulled low which has the device pulling current through VSUP through the
pull-up resisitor to VCC. The value of the pull-up resistor impacts the standby mode current. A 10 kΩ resistor value can add as much
as 500 µA of current.
(2) Operational supply voltage and nominal supply voltage are in relationship to the LIN transceiver. A VSUP above 28 V means the
device will function but may not meet the rest of the parametric data while the nominal range means the device will meet the
parametric data minus any differences provided in the test conditions.
(3) Specified by design
7.7 Electrical Charateristics
parameters valid over –40℃≤TJ ≤150 ℃range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RXD OUTPUT TERMINAL (OPEN-DRAIN)
Based upon a 2 kΩto 10 kΩexternal pull-
up to VCC
VOL
IOL
Output low voltage
0.2
VCC
mA
Low-level output current, open-drain
LIN = 0 V, RXD = 0.4 V
1.5
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7.7 Electrical Charateristics (continued)
parameters valid over –40℃≤TJ ≤150 ℃range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ILKG
Leakage current, high-level
LIN = VSUP, RXD = VCC
0
5
µA
–5
TXD INPUT TERMINAL
VIL
Low-level input voltage
0.8
5.5
5
V
V
–0.3
2
VIH
IIH
High-level input voltage
High-level input leakage current
Internal pull-up resistor value
TXD = high
0
µA
kΩ
–5
125
RTXD
350
800
LIN TERMINAL (REFERENCED TO VSUP
)
LIN recessive, TXD = high, IO = 0 mA, VSUP
= 5.5 V to 36 V
VOH
High-level output voltage(1)
0.85
VSUP
VSUP
VSUP
VSUP
V
LIN dominant, TXD = low, VSUP = 5.5 V to
36 V
VOL
Low-level output voltage(1)
High-level input voltage(1)
Low-level input voltage(1)
0.2
0.6
LIN recessive, TXD = high, IO = 0 mA, VSUP
= 5.5 V to 36 V
VIH
0.47
0.4
LIN dominant, TXD = low, VSUP = 5.5 V to
36 V
VIL
0.53
42
TXD & RXD open, VLIN = 5.5 V to 42 V, Bus
Load = 60 kΩ+ diode and 1.1 kΩ+ diode
VSUP where impact of recessive LIN bus < 5%
(ISO/DIS 17987 Param 11)
VSUP_NON_OP
–0.3
TXD = 0 V, VLIN = 36 V, RMEAS = 440 Ω,
VSUP = 36 V,
I BUS_LIM
Limiting current (ISO/DIS 17987 Param 12)
40
90
200
mA
VBUSdom < 4.518 V; 图8-6
VLIN = 0 V, VSUP = 12 V Driver off/recessive,
Receiver leakage current, dominant (ISO/DIS
17987 Param 13)
I BUS_PAS_dom
I BUS_PAS_rec1
I BUS_PAS_rec2
I BUS_NO_GND
mA
µA
–1
R
MEAS = 499 Ω; 图8-7
Receiver leakage current, recessive (ISO/DIS
17987 Param 14)
VLIN ≥VSUP, 5.5 V ≤VSUP ≤36 V Driver
off, RMEAS = 1 kΩ; 图8-8
20
8
Receiver leakage current, recessive (ISO/DIS
17987 Param 14)
µA
VLIN = VSUP, Driver off, RMEAS = 1 kΩ; 图8-8
–8
–1
Leakage current, loss of ground (ISO/DIS 17987 GND = VSUP, VSUP = 12 V, 0 V ≤VLIN ≤28
1
mA
Param 15)
V, RMEAS = 1 kΩ; 图8-9
Leakage current, loss of supply (ISO/DIS 17987
Param 16)
0 V ≤VLIN ≤28 V, VSUP = GND, RMEAS
10 kΩ; 图8-10
=
IBUS_NO_BAT
VBUSdom
VBUSrec
8
µA
LIN dominant (including LIN dominant for
wake up); 图8-3, 图8-4
Low-level input voltage (ISO/DIS 17987 Param
17)
0.4
VSUP
VSUP
High-level input voltage (ISO/DIS 17987 Param
18)
0.6
LIN recessive; 图8-3, 图8-4
Receiver center threshold (ISO/DIS 17987 Param
19)
VBUS_CNT
VHYS
0.475
0.07
0.4
0.5
0.525
0.175
1.0
VSUP
VSUP
V
VBUS_CNT = (VIL + VIH)/2; 图8-3, 图8-4
VHYS = (VIL - VIH); 图8-3, 图8-4
By design and characterization
Hysteresis voltage (ISO/DIS 17987 Param 20)(2)
Serial diode LIN term pull-up path (ISO/DIS 17987
Param 21)
VSERIAL_DIODE
0.7
45
Internal Pull-up resistor to VSUP (ISO/DIS 17987
Param 26)
RPU
Normal and Standby modes
20
60
kΩ
IRSLEEP
CLINPIN
Pull-up current source to VSUP
Capacitance of the LIN pin (6)
Sleep mode, VSUP = 12 V, LIN = GND
µA
pF
–20
–2
25
EN INPUT TERMINAL
VIH
VIL
High-level input voltage
2
–0.3
30
5.5
0.8
500
6
V
V
Low-level input voltage
Hysteresis voltage
VHYS
IIL
By design and characterization
EN = Low
mV
µA
kΩ
Low-level input current
Internal pull-down resistor
0
–6
REN
125
350
800
nRST TERMINAL (OPEN DRAIN OUTPUT)
ILKG
VOL
IOL
Leakage current, high-level
Low-level output voltage
LIN = VSUP, nRST = VCC
6
µA
VCC
mA
–6
Based upon external pull up to VCC
LIN = 0 V, nRST = 0.4 V
0.2
Low-level output current, open-drain
1.5
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7.7 Electrical Charateristics (continued)
parameters valid over –40℃≤TJ ≤150 ℃range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DUTY CYCLE CHARACTERISTICS
THREC(MAX) = 0.744 x VSUP
,
THDOM(MAX) = 0.581 x VSUP
,
Duty Cycle 1 (ISO/DIS 17987 Param 27 and
J2602 Normal battery)(3) (4)
VSUP = 7 V to 18 V, tBIT = 50/52 µs,
D1 = tBUS_rec(min)/(2 x tBIT) (See 图8-11, 图
8-12)
D1
D2
D3
0.396
THREC(MIN) = 0.422 x VSUP
THDOM(MIN) = 0.284 x VSUP, VSUP = 7.6 V to
18 V,
,
Duty Cycle 2 (ISO/DIS 17987 Param 28 and
J2602 Normal battery)(3) (4)
0.581
tBIT = 50/52 µs (20 kbps), D2 =
t
BUS_rec(MAX)/(2 x tBIT) (See 图8-11, 图8-12)
THREC(MAX) = 0.778 x VSUP, THDOM(MAX)
=
0.616 x VSUP
,
Duty Cycle 3 (ISO/DIS 17987 Param 29 and
J2602 Normal battery)(3) (4)
VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps),
D3 = tBUS_rec(min)/(2 x tBIT) (See 图8-11, 图
8-12)
0.417
THREC(MIN) = 0.389 x VSUP
,
THDOM(MIN) = 0.251 x VSUP
,
VSUP = 7.6 V to 18 V, tBIT = 96 µs (10.4
kbps),
Duty Cycle 4 (ISO/DIS 17987 Param 30 and
J2602 Normal battery)(3) (4)
D4
0.59
D4 = tBUS_rec(MAX)/(2 x tBIT) (See 图8-11, 图
8-12)
THREC(MAX) = 0.665 x VSUP, THDOM(MAX)
0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT
50/52 µs, D1LB = tBUS_rec(min)/(2 x tBIT) (See 图
8-11, 图8-12)
=
=
Duty Cycle 1
D1LB
D2LB
D3LB
D4LB
0.396
J2602 Low battery (4) (5)
T THREC(MIN) = 0.496 x VSUP, THDOM(MIN)
0.361 x VSUP, VSUP = 6.1 V to 7.6 V, tBIT
50/52 µs, D2LB = tBUS_rec(MAX)/(2 x tBIT) (See
=
=
Duty Cycle 2
0.581
J2602 Low battery (4) (5)
图8-11, 图8-12)
THREC(MAX) = 0.665 x VSUP, THDOM(MAX)
=
0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 96
µs, D3LB = tBUS_rec(min)/(2 x tBIT) (See 图8-11,
图8-12)
Duty Cycle 3
0.417
J2602 Low battery (4) (5)
T THREC(MIN) = 0.496 x VSUP, THDOM(MIN)
0.361 x VSUP, VSUP = 6.1 V to 7.6 V, tBIT
96 µs, D4LB = tBUS_rec(MAX)/(2 x tBIT) (See 图
8-11, 图8-12)
=
=
Duty Cycle 4
0.59
J2602 Low battery (4) (5)
(1) SAE J2602 loads include: commander node: 5.5 nF; 4 kΩ and for a commander node: 5.5 nF; 875 Ω
(2) VHYS is defined for both ISO 17987 and SAE J2602-1.
(3) ISO 17987 loads include 1 nF; 1 kΩ/ 6.8nF; 660 Ω/ 10 nF; 500 Ω; with tBIT values of 50 µs and 96 µs
(4) SAE J2602 loads include: commander node: 5.5 nF; 4 kΩ/ 899 pF; 20 kΩ and for a responder node: 5.5 nF; 875 Ω/ 899 pF; 900 Ω;
with tBIT values of 52 µs and 96 µs
(5) ISO 17987 does not have a low battery specification. Using the ISO 17987 loads these low battery duty cycle parameters are covered
for tBIT values of 50 µs and 96 µs
(6) Specified by design
7.8 AC Switching Characteristics
parameters valid over –40℃≤TJ ≤150 ℃range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6
UNIT
µs
DEVICE SWITCHING CHARACTERISTICS
trx_pdr
trx_pdf
Receiver rising/falling propagation delay time
(ISO/DIS 17987 Param 31)
RRXD = 2.4 kΩ, CRXD = 20 pF
(See 图8-13, 图8-14 and 图8-18)
Rising edge with respect to falling edge,
(trx_sym = trx_pdf –trx_pdr), RRXD = 2.4 kΩ,
CRXD = 20 pF (图8-13, 图8-14 and 图
8-18)
Symmetry of receiver propagation delay time
Receiver rising propagation delay time (ISO/DIS
17987 Param 32)
trs_sym
2
µs
–2
LIN wakeup time (minimum dominant time on
LIN bus for wakeup)
tLINBUS
25
100
150
µs
See 图8-17, 图9-3 and 图9-4
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7.8 AC Switching Characteristics (continued)
parameters valid over –40℃≤TJ ≤150 ℃range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
17
MAX
UNIT
Time to clear false wake-up prevention logic if
LIN bus had a bus stuck dominant fault
(recessive time on LIN bus to clear bus stuck
dominant fault)
tCLEAR
8
50
µs
See 图9-4
tTXD_DTO
tEN
Dominant state time out
20
3
34
80
12
ms
µs
Time of enable pin state change before
initiating mode change or sampling TXD
pin: See 图8-15
Enable pin deglitch time(1)
Time to change from normal mode to sleep
or standby after TXD pin sampling after
EN pin set low: See 图8-15
Mode change delay time from normal mode to
sleep or standby modes
tMODE_CHANGE
20
µs
µs
Time to change from sleep mode to normal
mode through EN pin and not due to a
wake event; RXD pulled up to VCC: See 图
8-15
Mode change delay time from sleep mode to
normal mode
tMODE_CHANGE
400
Time for normal mode to initialize and data
on RXD pin to be valid after tEN: See 图
8-15
tNOMINT
Normal mode initialization time
Power-up time
35
2
µs
Upon power up, time it takes for nRST to
go high
tPWR
ms
(1) Specified by design
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7.9 Typical Characteristics
80
75
70
65
60
55
50
45
130
125
120
115
110
105
100
95
40
-40°C
25°C
85°C
105°C
115°C
125°C
90
35
30
25
20
-40°C
25°C
85°C
105°C
125°C
85
80
75
0
3
6
9
12
15
VSUP (V)
18
21
24
27
30
D001
5
7.5
10
12.5
15
17.5
VSUP (V)
20
22.5
25
27.5
30
Package = DRB
VCC = 3.3 V
Temp = Ambient
Package = D
VCC = 3.3 V
Temp = Ambient
图7-2. ICC vs VSUP vs Temperature
图7-1. ICC vs VSUP vs Temperature
130
128
126
124
122
120
118
116
114
112
110
108
106
104
102
100
80
75
70
65
60
55
50
45
40
35
30
25
-40°C
25°C
85°C
105°C
115°C
125°C
-40°C
25°C
85°C
105°C
125°C
20
3
6
9
12
15
18
VSUP (V)
21
24
27
30
33
D006
4
6
8
10
12
14
16
18
20
22
24
26
28
30
VSUP (V)
Package = DDA
VCC = 3.3 V
Temp = Ambient
Package = D
VCC = 5 V
Temp = Ambient
图7-3. ICC vs VSUP vs Temperature
图7-4. ICC vs VSUP vs Temperature
130
120
110
100
90
130
120
110
100
90
80
80
70
70
60
60
50
-40°C
25°C
85°C
105°C
125°C
-40°C
25°C
85°C
105°C
125°C
50
40
40
30
30
20
5
7.5
10
12.5
15
17.5
VSUP (V)
20
22.5
25
27.5
30
4
6
8
10
12
14
16
VSUP (V)
18
20
22
24
26
28
30
Package = DRB
VCC = 5 V
Temp = Ambient
Package = DDA
VCC = 5 V
Temp = Ambient
图7-5. ICC vs VSUP vs Temperature
图7-6. ICC vs VSUP vs Temperature
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20
19
18
17
16
15
14
13
12
11
10
9
22
20
18
16
14
12
10
8
-40°C
25°C
85°C
105°C
115°C
125°C
-40°C
25°C
85°C
105°C
115°C
125°C
5
5
5
7.5
10
12.5
15
17.5
VSUP (V)
20
22.5
25
27.5
30
D003
5
5
5
7.5
10
12.5
15
17.5
VSUP (V)
20
22.5
25
27.5
30
D013
Package = D
VCC = 3.3 V
Temp = Ambient
Package = DRB
VCC = 3.3 V
Temp = Ambient
图7-7. Sleep Mode Current Across VSUP and
图7-8. Sleep Mode Current Across VSUP and
Temperature
Temperature
22
20
18
16
14
12
10
8
20
19
18
17
16
15
14
13
12
11
10
9
-40°C
25°C
85°C
105°C
115°C
125°C
-40°C
25°C
85°C
105°C
115°C
125°C
8
7.5
10
12.5
15
17.5
VSUP (V)
20
22.5
25
27.5
30
D023
7.5
10
12.5
15
17.5
VSUP (V)
20
22.5
25
27.5
30
D008
Package = DDA
VCC = 3.3 V
Temp = Ambient
Package = D
VCC = 5 V
Temp = Ambient
图7-9. Sleep Mode Current Across VSUP and
图7-10. Sleep Mode Current Across VSUP and
Temperature
Temperature
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
-40°C
25°C
85°C
-40°C
25°C
85°C
105°C
115°C
125°C
105°C
115°C
125°C
7.5
10
12.5
15
17.5
VSUP (V)
20
22.5
25
27.5
30
D018
7.5
10
12.5
15
17.5
VSUP (V)
20
22.5
25
27.5
30
D028
Package = DRB
VCC = 5 V
Temp = Ambient
Package = DDA
VCC = 5 V
Temp = Ambient
图7-11. Sleep Mode Current Across VSUP and
图7-12. Sleep Mode Current Across VSUP and
Temperature
Temperature
备注
For the LDO ICC vs VSUP vs Temperature typical curves the data was collected on a high-k EVM board
using a forced air system. The curves show performance based upon thermal resistance RθJB
.
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8 Parameter Measurement Information
8.1 Test Circuit: Diagrams and Waveforms
5
8
1
VCC
RXD
VCC
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
2
VSUP
EN
VPS
7
6
4
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
LIN
3
Jitter: < 25 ns
GND
Measurement Tools
O-scope:
DMM
图8-1. Test System: Operating Voltage Range with RX and TX Access
Delta t = + 5 µs (tBIT
= 50 µs)
Trigger Point
RX
2 * tBIT = 100 µs (20 kBaud)
图8-2. RX Response: Operating Voltage Range
Period T = 1/f
Amplitude
(signal range)
LIN Bus Input
Frequency: f = 20 Hz
Symmetry: 50%
图8-3. LIN Bus Input Signal
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5
2
VCC
8
1
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
RXD
EN
VCC
VSUP
VPS
7
6
4
LIN
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
3
GND
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
图8-4. LIN Receiver Test with RX access
5
2
8
1
VCC
VCC
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VSUP
EN
VPS1
D
4
3
6
LIN
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
3
VPS2
RBUS
GND
Measurement Tools
O-scope:
DMM
图8-5. VSUP_NON_OP Test Circuit
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5
2
1
7
VCC
VCC
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VSUP
EN
VPS
RMEAS
=
440 ꢀ
7
6
4
LIN
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
3
TXD
GND
T = 10 ms
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
图8-6. Test Circuit for IBUS_LIM at Dominant State (Driver on)
5
8
VCC
VCC
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
2
1
VSUP
EN
VPS
RMEAS = 499 Ω
4
7
6
LIN
3
GND
Measurement Tools
O-scope:
DMM
图8-7. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V
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Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
5
2
8
1
VCC
VCC
VPS1
VSUP
EN
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
RMEAS
=1 kΩ
4
7
6
LIN
VPS2
VPS2 2 V/s ramp
[8 V ‰ 36 V]
3
GND
V Drop across resistor
< 20 mV
Measurement Tools
O-scope:
DMM
图8-8. Test Circuit for IBUS_PAS_rec
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
5
2
8
1
VCC
VCC
VPS1
VSUP
EN
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
RMEAS
= 1 kΩ
4
3
7
6
LIN
VPS2
VPS2 2 V/s ramp
[0 V ‰ 36 V]
GND
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
图8-9. Test Circuit for IBUS_NO_GND Loss of GND
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8
1
5
VCC
VCC
2
VSUP
EN
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
RMEAS
10 kΩ
=
4
7
6
LIN
VPS 2 V/s ramp
[0 V ‰ 36 V]
3
GND
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
图8-10. Test Circuit for IBUS_NO_BAT Loss of Battery
5
2
8
1
VCC
VCC
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VSUP
EN
VPS1
RMEAS
4
7
6
LIN
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
3
VPS2
TXD
GND
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
图8-11. Test Circuit Slope Control and Duty Cycle
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tBIT
tBIT
RECESSIVE
TXD (Input)
DOMINANT
THREC(MAX)
THDOM(MAX)
THREC(MIN)
THDOM(MIN)
Thresholds
RX Node 1
LIN Bus
Signal
VSUP
Thresholds
RX Node 2
tBUS_REC(MIN)
tBUS_DOM(MAX)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
D = tBUS_REC(MIN)/(2 x tBIT
)
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
D = tBUS_REC(MAX)/(2 x tBIT
)
图8-12. Definition of Bus Timing
VCC
2.4 kΩ
5
2
VCC
8
1
RXD
VCC
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
20 pF
VSUP
EN
VPS
4
7
6
LIN
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
3
GND
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
图8-13. Propagation Delay Test Circuit
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THREC(MAX)
Thresholds
RX Node 1
THDOM(MAX)
LIN Bus
Signal
VSUP
THREC(MIN)
Thresholds
RX Node 2
THDOM(MIN)
RXD: Node 1
D1 (20 kbps)
trx_pdr(1)
trx_pdf(1)
D3 (10.4 kbps)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
trx_pdr(2)
trx_pdf(2)
Copyright © 2017, Texas Instruments Incorporated
图8-14. Propagation Delay
Wake Event
tMODE_CHANGE
tMODE_CHANGE
tNOMINT
tEN
EN
tEN
Can be high or low
TXD
EN
Filter/TXD
Sampling
Window
Enable
Filter
Transition
Sleep
Standby
Transition
Normal
Normal
MODE
Mirrors
Bus
Wake Request
RXD = Low
RXD
Indeterminate Ignore
‹
Floating for sleep
Indeterminate Ignore
Mirrors Bus
Can be high or low
TXD
EN
Filter/TXD
Sampling
Window
Enable
Filter
Transition
Standby
Transition
Normal
Normal
MODE
Wake Request
RXD = Low
Mirrors
Bus
RXD
Indeterminate Ignore
Indeterminate Ignore
Mirrors Bus
图8-15. Mode Transitions
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EN
tEN
Weak Internal Pullup
TXD
Weak Internal Pullup
VSUP
LIN
RXD
Floating
tMODE_CHANGE
+
Sleep
MODE
Normal
tNOMINIT
图8-16. Wakeup Through EN
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0.6 x VSUP
LIN
0.6 x VSUP
VSUP
0.4 x VSUP
0.4 x VSUP
t < tLINBUS
tLINBUS
TXD
Weak Internal Pullup
EN
Floating
RXD
MODE
Sleep
Standby
Normal
图8-17. Wakeup through LIN
VSUP
VCC
100 nF
10 µF
10 µF
nRST
EN
RLIN
TXD
GND
RRXD
LIN
RXD
CLIN
CRXD
图8-18. Test Circuit for AC Characteristics
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9 Detailed Description
9.1 Overview
The TLIN1028-Q1 LIN transceiver is a Local Interconnect Network (LIN) physical layer transceiver, compliant to
LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4 with integrated wake-up and protection features. The
LIN bus is a single-wire, bidirectional bus that typically is used in low-speed in-vehicle networks with data rates
that range up to 20 kbps. The LIN receiver works up to 100 kbps supporting in-line programming. The device
converts the LIN protocol data stream on the TXD input into a LIN bus signal using a current-limited wave-
shaping driver which reduces electromagnetic emissions (EME). The receiver converts the data stream to logic-
level signals that are sent to the microprocessor through the open-drain RXD pin. The LIN bus has two states:
dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive state, the LIN
bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode.
Ultra-low current consumption is possible using the sleep mode. The TLIN1028-Q1 provides two methods to
wake up from sleep mode: EN pin and LIN bus. The device integrates a low dropout voltage regulator with a
wide input from VSUP providing 5 V ±2% or 3.3 V ±2% with up to 125 mA of current depending upon system
implementation. nRST is asserted high when VCC increases above UVCC and stays high as long as VCC is above
this threshold.
9.2 Functional Block Diagram
VSUP
VCC
5.0-V or 3.3-V LDO
POR
UV
DET
CNTL
VSUP
RXD
VSUP/2
Filter
VCC
Comp
250 kΩ
nRST
45 kꢀ
Control
EN
Fault
Detection
& Protection
350 kΩ
350 kΩ
LIN
VCC
GND
Dominant
State
Timeout
DR/
Slope
CTL
TXD
图9-1. Functional Block Diagram
9.3 Feature Description
9.3.1 LIN Pin
This high-voltage input or output pin is a single-wire LIN bus transmitter and receiver. The LIN pin can survive
transient voltages up to 58 V. Reverse currents from the LIN to supply (VSUP) are minimized with blocking
diodes, even in the event of a ground shift or loss of supply (VSUP).
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9.3.1.1 LIN Transmitter Characteristics
The transmitter meets thresholds and AC parameters according to the LIN specification. The transmitter is a low-
side transistor with internal current limitation and thermal shutdown. During a thermal shutdown condition, the
transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to
VSUP, so no external pull-up components are required for the LIN responder node applications. An external pull-
up resistor and series diode to VSUP must be added when the device is used for a commander node application.
9.3.1.2 LIN Receiver Characteristics
The receiver characteristic thresholds are ratio-metric with the device supply pin according to the LIN
specification.
The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAEJ2602
specifications. This allows the TLIN1028-Q1 to be used for high-speed downloads at the end-of-line production
or other applications. The actual data rate achievable depends on system time constants (bus capacitance and
pull-up resistance) and driver characteristics used in the system.
9.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to VSUP, so no external pull-up components are
required for the LIN responder node applications. An external pull-up resistor (1 kΩ) and a series diode to VSUP
must be added when the device is used for commander node applications as per the LIN specification.
图9-2 shows a commander node configuration and how the voltage levels are defined
Voltage drop across the
Simplified Transceiver
VLIN_Bus
diodes in the pullup path
VSUP
VSUP/2
RXD
VBAT
VBattery
VSUP
VLIN_Recessive
Receiver
Filter
1 kꢀ
LIN Bus
45 kΩ
LIN
VCC
350 kꢀ
TXD
GND
Transmitter
with slope control
VLIN_Dominant
t
图9-2. Commander Node Configuration with Voltage Levels
9.3.2 TXD (Transmit Input)
TXD is the interface to the node processor’s LIN protocol controller that is used to control the state of the LIN
output. When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is
recessive (near VSUP). See 图9-2. The TXD input structure is compatible with processors that use 3.3 V and 5 V
VI and VO. TXD has an internal pull-up resistor. The LIN bus is protected from being stuck dominant through a
system failure driving TXD low through the dominant state time-out timer.
9.3.3 RXD (Receive Output)
RXD is the interface to the processor's LIN protocol controller, which reports the state of the LIN bus voltage. LIN
recessive (near VSUP) is represented by a high level on the RXD and LIN dominant (near ground) is represented
by a low level on the RXD pin. The RXD output structure is an open-drain output stage. This allows the device to
be used with 3.3 V and 5 VI/O processors. If the processor's RXD pin does not have an integrated pull-up, an
external pull-up resistor to the processors I and O supply voltage is required. In standby mode, the RXD pin is
driven low to indicate a wake-up request from the LIN bus from sleep mode. When going from normal mode to
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standby mode, the RXD pin is released and pulled-up to the voltage rail that the external pull-up resistor is
connected. A LIN bus wake event will cause the RXD pin to be pulled low indicating a wake request.
9.3.4 VSUP (Supply Voltage)
VSUP is the power supply pin. VSUP is connected to the battery through an external reverse-battery blocking
diode.
The VSUP pin is a high-voltage-tolerant pin. A decoupling capacitor with a value of 100 nF is recommended to be
connected close to this pin to improve the transient performance. If there is a loss of power at the ECU level, the
device has ultra low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems
in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered
(battery supplied). When VSUP drops low enough the regulated output drops out of regulation. The LIN bus works
with a VSUP as low as 5.5 V, but at a lower voltage, the performance is indeterminate and not ensured. If VSUP
voltage level drops enough, it triggers the UVSUP, and if it keeps dropping, at some point it passes the POR
threshold.
9.3.5 GND (Ground)
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce the VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the
device has ultra low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems
in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered
(battery supplied).
9.3.6 EN (Enable Input)
EN controls the operational modes of the device. When EN is high, the device is in normal operating mode
allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low, the device is put into sleep
or standby mode and there are no transmission paths available. EN has an internal pull-down resistor to ensure
the device remains in low power mode even if EN is left floating. EN should be held low until VSUP reaches the
expected system voltage level.
9.3.7 nRST (Reset Output)
The VCC pin is monitored for under voltage events. This pin is internally pulled up to VCC and when an
undervoltage event takes place, this pin is pulled low. The pin returns to VCC once the voltage on VCC exceeds
the under-voltage threshold. nRST is dependent on the value VCC and not the operational mode. If UVCC takes
place for longer than tDET(UVCC) nRST is pulled to ground. If a thermal shutdown event takes place, this pin is
pulled to ground.
9.3.8 VCC (Supply Output)
The VCC terminal can provide 5 V or 3.3 V with up to 125 mA to power up external devices when using high-k
boards and thermal management best practices in order to keep the virtual junction temperature below 165 °C
and avoid thermal shutdown.
9.3.9 Protection Features
The device has several protection features that are described as follows.
9.3.9.1 TXD Dominant Time Out (DTO)
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application
failure, the LIN bus is protected by the dominant state time-out timer. This timer is triggered by a falling edge on
the TXD pin. If the low signal remains on TXD for longer than tTXD_DTO, the transmitter is disabled, thus allowing
the LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and
the tTXD_DTO timer is reset by a rising edge on TXD. The TXD pin has an internal pull-up to ensure the device
fails to a known recessive state if TXD is disconnected. During this fault, the transceiver remains in normal mode
(assuming no change of state request on EN), the RXD pin reflects the LIN bus and the LIN bus pull-up
termination remains on.
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9.3.9.2 Bus Stuck Dominant System Fault: False Wake Up Lockout
The device contains logic to detect bus stuck dominant system faults and prevents the device from waking up
falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus. If the bus
is dominant, the wake-up logic is locked out until a valid recessive on the bus “clears”the bus stuck dominant,
preventing excessive current use. 图9-3 and 图9-4 show the behavior of this protection.
RXD
EN
LIN Bus
tLINBUS
< tLINBUS
< tLINBUS
图9-3. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup
RXD
EN
tLINBUS
tLINBUS
tLINBUS
LIN Bus
tCLEAR
< tCLEAR
图9-4. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup
9.3.9.3 Thermal Shutdown
The LIN transmitter is protected by current-limiting circuit; however, if the junction temperature of the device
exceeds the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state and turns
off the VCC regulator. The nRST pin is pulled to ground during a TSD event. Once the over-temperature fault
condition has been removed and the virtual junction temperature has cooled beyond the hysteresis temperature,
the transmitter is re-enabled. During this fault the device enters a TSD off mode. Once the junction temperature
cools, the device enters standby mode as per the state diagram.
9.3.9.4 Under Voltage on VSUP
The device contains a power-on reset circuit to avoid false bus messages during under voltage conditions when
VSUP is less than UVSUP
.
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9.3.9.5 Unpowered Device and LIN Bus
In automotive applications, some LIN nodes in a system can be unpowered (ignition supplied) while others in the
network remain powered by the battery. The device has extremely low unpowered leakage current from the bus,
so an unpowered node does not affect the network nor load it down.
9.4 Device Functional Modes
nRST: Float
The TLIN1028-Q1 has three functional modes of operation: normal, sleep, and standby. The next sections
describes these modes as well as how the device moves between the different modes. 图 9-5 graphically shows
the relationship while 表9-1 shows the state of pins.
表9-1. Operating Modes
LIN BUS
Termination
Mode
EN
RXD
Transmitter
nRST
Comment
nRST is internally connected to the LDO output which
is pulled to ground in sleep mode.
Sleep
Low
Floating Weak Current pull-up
Off
Ground
nRST is internally connected to the LDO output which
in standby init mode is pulled low until VCC raises
beyond UVCC threshold.
Standby
Init
Low
Low
Low
Floating
Low
Off
Off
Off
Ramping
VCC
45 kΩ (typical)
45 kΩ (typical)
45 kΩ (typical)
Standby
from
SLP
Wake-up event detected, waiting on processors to set
EN
nRST comes on to VCC once thresholds are met.
Standby
from
Norm
LDO is on and RXD is high but if a LIN bus wake
event takes place RXD is pulled low.
High
VCC
LIN Bus
Data
Normal
High
NA
On
Off
VCC
LIN transmission up to 20 kbps
45 kΩ (typical)
45 kΩ (typical)
nRST is pulled low as the LDO is turned off which
means UVCC threshold has been met.
TSD Off
Floating
Ground
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Unpowered System
VSUP < UVSUP
VSUP < UVSUP
VSUP ≥ UVSUP
Standby Init Mode
VCC > UVCC
EN = High
Transceiver: Off
WUP Receiver: Off
RXD: Floating
Termination: 45 k
LDO: Ramping up
Any State
VCC > UVCC
EN = Low
Tj > TSD
TSD Off Mode
Standby Mode
Transceiver: Off
WUP Receiver: On
RXD: Floating
Termination: 45 k
LDO: Off
Tj < TSD
Transceiver: Off
WUP Receiver: On
RXD: Signals wake event
Termination: 45 k
LDO: On
nRST: Low (Fault Condition)
nRST: High
EN = Low > tEN
AND TXD = High
AND nRST = High
VSUP < UVSUP
LIN Bus Wake up
Unpowered State
EN = High > tEN
nRST = High
VSUP < UVSUP
VSUP < UVSUP
Normal Mode
Sleep Mode
EN = Low > tEN
AND TXD = Low
AND nRST = High
Transceiver: On
WUP Receiver: Off
RXD: LIN Bus Data
Termination: 45 k
LDO: On
Transceiver: Off
WUP Receiver: On
RXD: Floating
Termination: Weak pullup
LDO: Off
EN = High > tEN
nRST: High
nRST: Low
图9-5. Operating State Diagram
9.4.1 Normal Mode
If the EN pin is high after the device enters standby init mode, the device enters normal mode. If EN is low, it
enters standby mode. In normal operational mode, the receiver and transmitter are active and the LIN
transmission up to the LIN specified maximum of 20 kbps is supported. If TXD pin is dominant at the time of
entering normal mode the LIN transmitter is kept off until a recessive is applied to TXD. The receiver detects the
data stream on the LIN bus and outputs it on RXD for the LIN controller. A recessive signal on the LIN bus is a
digital high and a dominant signal on the LIN bus is a digital low. The driver transmits input data from TXD to the
LIN bus. Normal mode is entered as EN transitions high while the device is in sleep or standby mode for > tEN
.
Once EN has been high for tEN the device enters normal mode after tMODE_CHANGE and tNOMINIT
.
9.4.2 Sleep Mode
Sleep Mode is the power saving mode for the TLIN1028-Q1. Even with extremely low current consumption in
this mode, the device can still wake up from the LIN bus through a wake-up signal or if EN is set high for > tEN
.
The wake-up events must be active for the respective time periods (tLINBUS).
While the device is in sleep mode, the following conditions exist:
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• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short-circuited to ground). However, the weak current pull-up is active to prevent false wake-up events
in case an external connection to the LIN bus is lost.
• The normal receiver is disabled.
• EN input and LIN wake-up receiver are active.
9.4.3 Standby Mode
Standby mode is entered either by a wake-up event through LIN bus while the device is in sleep mode or by the
EN pin from normal or standby init modes. From normal mode EN must be low for > tEN and TXD and nRST are
high. RXD pin in standby mode is dependent upon how standby mode was entered. If entered from normal
mode or power up, RXD is high. If entered from sleep mode, RXD is pulled low to indicate a wake event. When
entering standby mode from normal or standby init modes, a wake event on the LIN bus causes the RXD pin to
be pulled low.
During power up, if EN is low the device goes into standby mode, and if EN is high, the device goes into normal
mode. EN has an internal pull-down resistor ensuring EN is pulled low if the pin is left floating in the system.
9.4.4 Wake-Up Events
There are two ways to wake-up from sleep mode:
• Remote wake-up initiated by the falling edge of a recessive (high) to dominant (low) state transition on the
LIN bus where the dominant state is held for the tLINBUS filter time. After this tLINBUS filter time has been met
and a rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake-up
event eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
• Local wake-up through EN being set high for longer than tEN
.
9.4.4.1 Wake-Up Request (RXD)
When the TLIN1028-Q1 encounters a wake-up event from the LIN bus, RXD goes low and the device transitions
to standby mode until EN is reasserted high and the device enters normal mode. Once the device enters normal
mode, the RXD pin releases the wake-up request signal and the RXD pin then reflects the receiver output from
the LIN bus.
9.4.5 Mode Transitions
When the device is transitioning between modes, the device needs the time tMODE_CHANGE and tNOMINT to allow
the change to fully propagate from the EN pin through the device into the new state.
9.4.6 Voltage Regulator
The device has an integrated high-voltage LDO that operates over a 5.5 V to 28 V input voltage range for both
3.3 V and 5 V VCC. The device has an output current capability of 70 mA and 125 mA depending upon package
and support fixed output voltages of 3.3 V (TLIN10283-Q1) or 5 V (TLIN10285-Q1). It features thermal shutdown
and short-circuit protection to prevent damage during over-temperature and over-current conditions
9.4.6.1 VCC
The VCC pin is the regulated output based on the required voltage. The regulated voltage accuracy is ± 2%. The
output is current limited. In the event that the regulator drops out of regulation, the output tracks the input minus
a drop based on the load current. When the input voltage drops below the UVSUP threshold, the regulator shuts
down until the input voltage returns above the UVSUPR level. The device monitors situations where VCC may drop
below the UVCC level thus causing the nRST pin to be pulled low.
9.4.6.2 Output Capacitance Selection
For stable operation over the full temperature range and with load currents up to 125 mA on VCC a certain
capacitance is expected and depends upon the minimum load current. To support no load to full load a value of
10 µF and ESR smaller than 2 Ω is needed. For 20 µA to full load an 1.5 µF capacitance can be used. The low
ESR recommendation is to improve the load transient performance.
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9.4.6.3 Low-Voltage Tracking
At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage
based on the load current (IL) and power-switch resistor. This tracking allows for a smaller input capacitance and
can possibly eliminate the need for a boost converter during cold-crank conditions.
9.4.6.4 Power Supply Recommendation
The device is designed to operate from an input-voltage supply range between 5.5 V and 28 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the device. The recommended
minimum capacitance at the pin is 100 nF . The max voltage range is for the LIN functionality. Exceeding 24V for
the LDO reduces the effective current sourcing capability due to thermal considerations.
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
10.1 Application Information
The TLIN1028-Q1 can be used as both a responder device and a commander device in a LIN network. The
device comes with the ability to support a remote wake-up requests. It can provide the power to the local
processor.
10.2 Typical Application
The device comes with an integrated 45 kΩ pull-up resistor and series diode for responder node applications.
For commander node applications, an external 1 kΩ pull-up resistor with series blocking diode can be used. 图
10-1 shows the device being used in both commander and responder node applications.
Commander
Node
10 µF
VSUP
Vcc
100 nF(4)
EN
I/O
2
8
1
VDD
Commander
Node
MCU w/o
pull-up(2)
Pull-up(3)
V
DD I/O
1 k
LIN
MCU
4
LIN Controller
Or
5
220 pF
RXD
TXD
SCI/UART(1)
6
GND
7
3
nRST
Responder
Node
10 µF
Vcc
VSUP
100 nF(4)
EN
I/O
2
8
1
VDD
MCU w/o
pull-up(2)
Responder Node(3)
V
DD I/O
LIN
MCU
4
LIN Controller
Or
5
6
7
220 pF
RXD
TXD
SCI/UART(1)
3
GND
nRST
(1) If RXD on MCU or LIN responder node has internal pullup; no external pull-up resistor is needed.
(2) If RXD on MCU or LIN responder node does not have an internal pull-up requires external pull-up resistor.
(3) Commander node applica ons require and external 1 k pull-up resistor and serial diode.
(4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 µF and ≥10 µF
图10-1. Typical LIN Bus
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10.2.1 Design Requirements
10.2.1.1 Normal Mode Application Note
When using the TLIN1028-Q1 in systems which are monitoring the RXD pin for a wake-up request, special care
should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period
between states as the receivers are switched. The application software should not look for an edge on the RXD
pin indicating a wake-up request until tMODE_CHANGE. This is shown in 图8-15 when transitioning to normal mode
there is an initialization period shown as tNOMINIT
.
10.2.1.2 TXD Dominant State Timeout Application Note
The maximum dominant TXD time allowed by the TXD dominant state time out limits the minimum possible data
rate of the device. The LIN protocol has different constraints for commander and responder node applications;
thus, there are different maximum consecutive dominant bits for each application case and thus different
minimum data rates.
10.2.1.3 Brownout
图 10-17 and 图 10-18 show the behavior of the LIN, nRST and VCC pins during a brownout condition. For the
TLIN10283-Q1, VSUP down to ~ 2.24 V has results as shown. For the TLIN10285-Q1, VSUP down to ~ 2.63 V
has results as shown. When VSUP drops below these levels the signals are indeterminate.
10.2.2 Detailed Design Procedures
For processors or LIN responder nodes with an internal pull-up on RXD, no external pull-up resistor is needed.
For processors or LIN responder nodes without internal pull-up on RXD, an external pull-up resistor is required.
Commander node applications require an external 1 kΩ pull-up resistor and serial diode.
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10.2.3 Application Curves
Characteristic curves below show the LDO performance ramping between 0 V and up to 7 V.
80
70
60
50
40
30
20
10
0
130
120
110
100
90
80
70
60
50
40
-40°C
25°C
85°C
105°C
115°C
125°C
-40°C
25°C
85°C
105°C
115°C
125°C
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
7
3
3.5
4
4.5
5
VSUP (V)
5.5
6
6.5
7
D012
D002
Package = DRB
ICC = 125 mA
VCC = 3.3 V
Temperature =
Ambient
Package = D
ICC = 70 mA
VCC = 3.3 V
Temperature =
Ambient
图10-3. ISUP vs VSUP vs Temperature
图10-2. ISUP vs VSUP vs Temperature
130
120
110
100
90
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
80
70
60
50
40
-40°C
25°C
85°C
105°C
115°C
125°C
-40°C
25°C
85°C
105°C
115°C
125°C
30
20
10
0
0
-5
0
0.5
1
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
7
0
0.5
1
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
7
D022
D007
Package = DDA
ICC = 125 mA
VCC = 3.3 V
Temperature =
Ambient
Package = D
ICC = 70 mA
VCC = 5 V
Temperature =
Ambient
图10-4. ISUP vs VSUP vs Temperature
图10-5. ISUP vs VSUP vs Temperature
130
120
110
100
90
130
120
110
100
90
80
80
70
70
60
60
50
50
40
40
30
-40°C
25°C
85°C
-40°C
25°C
85°C
30
20
105°C
115°C
125°C
105°C
115°C
125°C
20
10
10
0
0
-10
0
0.5
1
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
7
0
0.5
1
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
7
D017
D027
Package = DRB
ICC = 125 mA
VCC = 5 V
Temperature =
Ambient
Package = DDA
ICC = 125 mA
VCC = 5 V
Temperature =
Ambient
图10-6. ISUP vs VSUP vs Temperature
图10-7. ISUP vs VSUP vs Temperature
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16
14
12
10
8
18
16
14
12
10
8
6
6
-40°C
25°C
85°C
-40°C
25°C
85°C
4
4
105°C
115°C
125°C
105°C
115°C
125°C
2
2
0
0
0
0.5
1
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
D004
0
0.5
1
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
D014
Package = D
Mode = Sleep
3.3 V VCC = Off
Temperature =
Ambient
Package = DRB
Mode = Sleep
3.3 V VCC = Off
Temperature =
Ambient
图10-8. ISUP vs VSUP vs Temperature Ramp-down 图10-9. ISUP vs VSUP vs Temperature Ramp-down
16
14
12
10
8
16
14
12
10
8
6
6
-40°C
25°C
85°C
-40°C
25°C
85°C
4
4
105°C
115°C
125°C
105°C
115°C
125°C
2
2
0
0
0
0.5
1
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
D024
0
0.5
1
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
D009
Package = DDA
Mode = Sleep
3.3 V VCC = Off
Temperature =
Ambient
Package = D
Mode = Sleep
5 V VCC = Off
Temperature =
Ambient
图10-10. ISUP vs VSUP vs Temperature Ramp-down 图10-11. ISUP vs VSUP vs Temperature Ramp-down
18
16
14
12
10
8
16
14
12
10
8
6
6
-40°C
25°C
85°C
-40°C
25°C
85°C
4
4
105°C
115°C
125°C
105°C
115°C
125°C
2
2
0
0
0
0.5
1
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
D019
0
0.5
1
1.5
2
2.5
3
3.5
VSUP (V)
4
4.5
5
5.5
6
6.5
D029
Package = DRB
Mode = Sleep
5 V VCC = Off
Temperature =
Ambient
Package = DDA
Mode = Sleep
5 V VCC = Off
Temperature =
Ambient
图10-12. ISUP vs VSUP vs Temperature Ramp-down 图10-13. ISUP vs VSUP vs Temperature Ramp-down
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图10-14. LIN Bus Performance
图10-15. Dominant to Recessive Propagation
Delay
图10-16. Recessive to Dominant Propagation
图10-17. TLIN10283-Q1 Brownout
Delay
图10-18. TLIN10285-Q1 Brownout
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11 Power Supply Recommendations
The TLIN1028-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 5.5 V
to 28 V . A 100 nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible.For
applications where the device goes from no load to full load, a minimum decoupling capacitance to ground of 10
μF is recommended when the LDO turns on. If the device is going from 20 µA to full load then a minimum of 1.5
µF capacitance is recommended.
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12 Layout
PCB design should start with understanding that frequency bandwidth from approximately 3 MHz to 3 GHz is
needed thus high frequency layout techniques must be applied during PCB design. Placement at the connector
also prevents these noisy events from propagating further into the PCB and system.
12.1 Layout Guidelines
• Pin 1 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close
to the device as possible.
• Pin 2 (EN): EN is an input pin that is used to place the device in a low power sleep mode. If this feature is not
used, the pin should be pulled high to the regulated voltage supply of the microprocessor through a series
resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pin to limit
current on the digital lines in the event of an over-voltage fault.
• Pin 3 (GND): This is the ground connection for the device. This pin should be tied to the ground plane
through a short trace with the use of two vias to limit total return inductance.
• Pin 4 (LIN): This pin connects to the LIN bus. For responder node applications, a 220 pF capacitor to ground
is implemented. For commander node applications, an additional series resistor and blocking diode should be
placed between the LIN pin and the VSUP pin. See 图10-1
• Pin 5 (RXD): The pin is an open-drain output and requires and external pull-up resistor in the range of 1 kΩ
to 10 kΩ to function properly. If the microprocessor paired with the transceiver does not have an integrated
pull-up, an external pull-up resistor should be placed on RXD. If RXD is connected to the VCC pin a higher
pull-up resistor value can be used to reduce standby current.
• Pin 6 (TXD): The TXD pin is the transmit input signal to the device from the processors. A series resistor can
be placed to limit the input current to the device in the event of an over voltage on this pin. A capacitor to
ground can be placed close to the input pin of the device to filter noise.
• Pin 7 (nRST): This pin connects to the processors as a reset out.
• Pin 8 (VCC): Output source, either 3.3 V or 5 V depending upon the version of the device.
备注
All ground and power connections should be made as short as possible and use at least two vias to
minimize the total loop inductance.
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12.2 Layout Example
VSUP
C2
VSUP
1
2
VCC
8
U1
Only needed for
the Commander
node
VCC
GND
GND
R2
EN
EN
nRST
7
LIN
GND
GND
3
4
GND
6
5
R4
TXD
TXD
GND
VCC
GND
LIN
RXD
RXD
图12-1. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• LIN Standards:
– ISO/DIS 17987-1: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and
use case definition
– ISO/DIS 17987-4: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer
(EPL) specification 12V/24V
– SAE J2602-1: LIN Network for Vehicle Applications
– LIN2.0, LIN2.1, LIN2.2 and LIN2.2A specification
• EMC requirements:
– SAE J2962-2: TBD
– HW Requirements for CAN, LIN, FR V1.3: German OEM requirements for LIN
– ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
– ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband
radiated electromagnetic energy - Part 4: Harness excitation methods
– ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1:
Definitions and general considerations
– ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical
transient transmission by capacitive and inductive coupling via lines other than supply lines
– IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz -
Part 4: Direct RF power injection method
– IEC 61967-4
– CISPR25
• Conformance Test requirements:
– ISO/DIS 17987-7: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer
(EPL) conformance test specification
– SAE J2602-2: LIN Network for Vehicle Applications Conformance Test
TLINx441 LDO Performance, SLLA427
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
13.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
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13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLIN10283DDARQ1
TLIN10283DRBRQ1
TLIN10283DRQ1
ACTIVE SO PowerPAD
DDA
DRB
D
8
8
8
8
8
8
2500 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TLN83
ACTIVE
ACTIVE
SON
NIPDAU
NIPDAU
TLN83
TLN83
TLN85
TLN85
TLN85
SOIC
TLIN10285DDARQ1
TLIN10285DRBRQ1
TLIN10285DRQ1
ACTIVE SO PowerPAD
DDA
DRB
D
NIPDAUAG
NIPDAU
ACTIVE
ACTIVE
SON
SOIC
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Mar-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLIN10283DDARQ1
SO
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
PowerPAD
TLIN10283DRBRQ1
TLIN10283DRQ1
SON
DRB
D
8
8
8
3000
2500
2500
330.0
330.0
330.0
12.4
12.4
12.8
3.3
6.4
6.4
3.3
5.2
5.2
1.1
2.1
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
SOIC
TLIN10285DDARQ1
SO
DDA
PowerPAD
TLIN10285DRBRQ1
TLIN10285DRQ1
SON
DRB
D
8
8
3000
2500
330.0
330.0
12.4
12.4
3.3
6.4
3.3
5.2
1.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLIN10283DDARQ1
TLIN10283DRBRQ1
TLIN10283DRQ1
SO PowerPAD
SON
DDA
DRB
D
8
8
8
8
8
8
2500
3000
2500
2500
3000
2500
366.0
367.0
356.0
366.0
367.0
356.0
364.0
367.0
356.0
364.0
367.0
356.0
50.0
35.0
35.0
50.0
35.0
35.0
SOIC
TLIN10285DDARQ1
TLIN10285DRBRQ1
TLIN10285DRQ1
SO PowerPAD
SON
DDA
DRB
D
SOIC
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
1.75
1.55
(0.2) TYP
6X 0.65
(0.19)
4
5
SYMM
9
2.5
2.3
1.95
1
8
0.36
0.26
8X
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A B
C
SYMM
0.5
0.3
8X
4225036/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
(1.65)
8X (0.6)
8X (0.31)
SYMM
1
8
6X (0.65)
SYMM
9
(1.95) (2.4)
(0.95)
(R0.05) TYP
4
5
(Ø 0.2) VIA
TYP
(0.575)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225036/A 06/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
2X
(1.51)
8X (0.6)
8X (0.31)
SYMM
1
8
2X
(1.06)
6X (0.65)
SYMM
(1.95)
(0.63)
9
(R0.05) TYP
4
5
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED COVERAGE BY AREA
SCALE: 20X
4225036/A 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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