TLC59482 [TI]
具有 6 位全局亮度控制功能的 16 通道、16 位 PWM LED 驱动器;
| 型号： | TLC59482 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 6 位全局亮度控制功能的 16 通道、16 位 PWM LED 驱动器 驱动 驱动器 |
| 文件： | 总34页 (文件大小：825K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
具有
6 位全局亮度控制的 16 通道，16 位，脉宽调制 (PWM) 发光二级管 (LED)
驱动器
查询样品: TLC59482
1
特性
应用范围
2
•
16 个恒定流入电流源输出通道
具有最大亮度控制 (BC) 数据的灌电流能力：
•
•
LED 视频显示屏
LED 信号板
•
–
–
1mA 至 35mA (VCC≤ 3.6V)
1mA 至 45mA (VCC> 3.6V)
说明
TLC59482 是一款 16 通道，恒定灌电流驱动器。 每个
通道有一个步长为 65,536 的独立可调节、脉宽调制
(PWM) 灰度 (GS) 亮度控制。 所有通道具有一个 64
步长的全局亮度控制 (BC)。 BC 调节与其它 LED 驱动
器的亮度偏差。 可通过一个串行接口访问 GS，和 BC
数据。
•
全局亮度控制 (BC)：
–
范围为 0% 至 100% 的 6 位（64 步长）（缺省
值为 50%）
•
•
•
LED 电源电压：高达 10V
VCC：3.0V 至 5.5V
恒定电流精度：
–
通道到通道：±1%（典型值），±2.5%（最大
值）
–
器件到器件：±2%（典型值），±4%（最大值）
•
•
•
•
•
•
•
数据传输速率：30MHz
灰度控制时钟：33MHz
自动重复显示功能
自动数据刷新
显示计时复位
用来防止涌入电流的 4 通道成组延迟开关
工作温度范围：-40°C 至 +85°C
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
English Data Sheet: SBVS218
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
VLED
¼
¼
¼
¼
¼
¼
¼
¼
OUT0
SIN
OUT15
SOUT
OUT0
SIN
OUT15
SOUT
DATA
SCLK
LAT
VCC
VCC
SCLK
LAT
SCLK
LAT
Device 1
Device n
VCC
GND
VCC
GND
GSCLK
GSCLK
IREF
GSCLK
IREF
Controller
RIREF
RIREF
3
Data Read
典型应用电路（多菊花链 TLC59482）
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
TLC59482DBQR
TLC59482DBQ
TLC59482RGER
TLC59482RGET
Tape and Reel, 2500
Tube, 50
DBQ
TLC59482
Tape and Reel, 3000
Tape and Reel, 250
RGE(2)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Product preview device.
2
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
MIN
MAX
+6
UNIT
V
VCC
–0.3
–0.3
–0.3
–0.3
SIN, SCLK, LAT, GSCLK, IREF
VCC + 0.3
VCC + 0.3
+11
V
Voltage(2)
SOUT
V
OUT0 to OUT15
V
Current
IOUT (dc), OUT0 to OUT15
Operating junction, TJ (max)
Storage, Tstg
+55
mA
°C
°C
V
+150
Temperature
–55
+150
Human body model (HBM)
Charged device model (CDM)
3000
Electrostatic discharge (ESD)
ratings
2000
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to device ground terminal.
THERMAL INFORMATION
TLC59482
DBQ
(SSOP, QSOP)
RGE
(QFN)
THERMAL METRIC(1)
UNITS
24 PINS
86.7
24 PINS
35.5
44
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
50.4
10.0
14.7
0.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
13.0
ψJB
39.7
14.8
2.9
θJCbot
N/A
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
Copyright © 2012, Texas Instruments Incorporated
3
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
RECOMMENDED OPERATING CONDITIONS
At TA = –40°C to +85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS (VCC = 3 V to 5.5 V)
VCC
VO
Supply voltage
3.0
5.5
V
V
Voltage applied to output
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
OUT0 to OUT15
10
VIH
VIL
IOH
IOL
SIN, SCLK, LAT, GSCLK
SIN, SCLK, LAT, GSCLK
SOUT
0.7 × VCC
GND
VCC
V
0.3 × VCC
V
–2
2
mA
mA
SOUT
OUT0 to OUT15,
3 V ≤ VCC ≤ 3.6 V
35
45
mA
mA
IOLC
Constant output sink current
OUT0 to OUT15,
3.6 V < VCC ≤ 5.5 V
TA
TJ
Operating free-air temperature range
Operating junction temperature range
–40
–40
+85
°C
°C
+125
AC CHARACTERISTICS (VCC = 3 V to 5.5 V)
VCC
Supply voltage
3.0
5.5
25
30
33
V
MHz
MHz
MHz
ns
SCLK, 3.0 V ≤ VCC ≤ 3.6 V
SCLK, 3.6 V < VCC ≤ 5.5 V
GSCLK
fCLK (SCLK)
Data shift clock frequency
Grayscale control clock frequency
fCLK (GSCLK)
tWH0
tWL0
tWH1
tWL1
tWH2
tSU0
tSU1
tSU2
tH0
SCLK
10
10
10
10
10
4
SCLK
ns
Pulse duration
GSCLK
ns
GSCLK
ns
LAT
ns
SIN to SCLK↑
LAT↑ to SCLK↑
LAT↓ to SCLK↑(1)
SCLK↑ to SIN
SCLK↑ to LAT↑
SCLK↑ to LAT↓
LAT↓ to GSCLK↑
ns
Setup time
Hold time
2
ns
5
ns
4
ns
tH1
7
ns
tH2
14
30
ns
tH3
ns
(1) Refer to the tD1 parameter in the Switching Characteristics table for the FC data read time.
4
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C and VCC = 3 V to 5.5 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
VOL
High-level output voltage (SOUT)
Low-level output voltage (SOUT)
Reference voltage output
IOH = –2 mA
IOL = 2 mA
VCC – 0.4
VCC
V
V
V
0.4
VIREF
RIREF = 1.5 kΩ
1.175
–1
1.200
1.225
Input current
(SIN, SCLK, GSCLK)
IIN
VIN = VCC or GND
1
3
μA
SIN, SCLK, LAT, GSCLK = GND, GSn = 0000h,
BC = 3Fh, VOUTn = 0.8 V, RIREF = open
ICC0
1.5
3
mA
SIN, SCLK, LAT, GSCLK = GND, GSn = 0000h,
BC = 3Fh, VOUTn = 0.8 V, RIREF = 3 kΩ
(IOUTn = 15.9-mA target)
ICC1
5
mA
mA
Supply current (VCC
)
SIN, SCLK, LAT = GND, GSCLK = 33 MHz,
GSn = FFFFh, BC = 3Fh, VOUTn = 0.8 V, RIREF = 3 kΩ
(IOUT = 15.9-mA target)
ICC2
8
10
SIN, SCLK, LAT = GND, GSCLK = 33 MHz,
GSn = FFFFh, BC = 3Fh, VOUTn = 0.8 V, RIREF = 1.5 kΩ
(IOUT = 31.8-mA target)
ICC3
9
13.5
33.8
mA
mA
Constant output sink current
(OUT0 to OUT15)
All OUTn = on, BC = 3Fh, VOUTn = VOUTfix = 0.8 V,
RIREF = 1.5 kΩ, TA = +25°C (IOLCn = 31.8-mA target)
IOLC
29.8
31.8
IOLKG0
IOLKG1
IOLKG2
TJ = +25°C
0.1
0.2
0.8
μA
μA
μA
All OUTn = off, GSn = 0000h,
VOUTn = VOUTfix = 10 V,
RIREF = 1.5 kΩ
Output leakage current
(OUT0 to OUT15)
TJ = +85°C(1)
TJ = +125°C(1)
(IOLCn = 31.8-mA target)
0.3
Constant-current error,
channel-to-channel
(OUT0 to OUT15)(2)
All OUTn = on, BC = 3Fh, VOUTn = VOUTfix = 0.8 V,
RIREF = 1.5 kΩ, TA = +25°C
(IOUTn = 31.8-mA target)
ΔIOLC0
ΔIOLC1
ΔIOLC2
±1%
±2.5%
±4%
±3
Constant-current error,
device-to-device
All OUTn = on, BC = 3Fh, VOUTn = VOUTfix = 0.8 V,
RIREF = 1.5 kΩ, TA = +25°C
(IOUTn = 31.8-mA target)
±2%
±1
(OUT0 to OUT15)(3)
VCC = 3.0 V to 5.5 V, all OUTn = on, BC = 3Fh,
VOUTn = VOUTfix = 0.8 V, RIREF = 1.5 kΩ
(IOUTn = 31.8-mA target)
Line regulation
%/V
(OUT0 to OUT15)(4)
All OUTn = on, BC = 3Fh, VOUTn = 0.8 V to 3.0 V,
VOUTfix = 0.8 V, RIREF = 1.5 kΩ
(IOUTn = 31.8-mA target)
Load regulation
ΔIOLC3
±1
±3
%/V
(OUT0 to OUT15)(5)
RPDWN
Pull-down resistor
LAT
250
500
750
kΩ
(1) Not tested; specified by design.
(2) The deviation of each output from the average of OUT0 to OUT15 constant-current. Deviation is calculated by the formula:
IOLCn
- 1
IOLC0 + IOLC1 + ... + IOLC14 + IOLC15
16
D (%) =
´ 100
where n = 0 to 15.
(3) The deviation of the OUTn output current value from the ideal constant-current value. Deviation is calculated by the formula:
(IOLC0 + IOLC1 + ... IOLC14 + IOLC15
)
- Ideal Output Current
D (%) =
´ 100
16
Ideal Output Current
Ideal current is calculated by the formula:
1.20
IOLCn(IDEAL) (mA) = 39.8 ´
RIREF (W)
where n = 0 to 15.
(4) Line regulation is calculated by the formula:
(IOLCn at VCC = 5.5 V) - (IOLCn at VCC = 3.0 V)
D (%/V) =
100
´
IOLCn at VCC = 3.0 V
5.5 V - 3 V
where n = 0 to 15.
(5) Load regulation is calculated by the equation:
(IOLCn at VOUTn = 3 V) - (IOLCn at VOUTn = 0.8 V)
D (%/V) =
100
´
IOLCn at VOUTn = 0.8 V
3 V - 0.8 V
where n = 0 to 15.
Copyright © 2012, Texas Instruments Incorporated
5
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
SWITCHING CHARACTERISTICS
At TA = –40°C to +85°C, VCC = 3 V to 5.5 V, CL = 15 pF, RL = 110 Ω, RIREF = 1.5 kΩ, and VLED = 5.0 V, unless otherwise
noted. Typical values are at TA = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
1.5
30
MAX UNIT
tR0
tR1
tF0
tF1
tD0
tD1
SOUT
5
ns
ns
ns
ns
ns
ns
Rise time
OUTn, BC = 7Fh, TA = +25°C
SOUT
1.5
30
5
Fall time
OUTn, BC = 7Fh, TA = +25°C
SCLK↑ to SOUT↑↓
LAT↓ to SOUT↑↓
23
35
42
27
GSCLK↑ to OUT0, OUT7, OUT8, OUT15 on/off with
BC = 7Fh, TA = +25°C
tD2
50
55
60
65
ns
ns
ns
ns
ns
GSCLK↑ to OUT1, OUT6, OUT9, OUT14 on/off with
BC = 7Fh, TA = +25°C
Propagation delay
tD3
GSCLK↑ to OUT2, OUT5, OUT10, OUT13 on/off with
BC = 7Fh, TA = +25°C
tD4
GSCLK↑ to OUT3, OUT4, OUT11, OUT12 on/off with
BC = 7Fh, TA = +25°C
tD5
tOUTON – tGSCLK, GSn = 0001h, GSCLK = 20 MHz,
BC = 3Fh, VCC = 3.3 V, TA = +25°C
tON_ERR
Output on-time error(1)
–35
10
(1) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR = tOUT_ON – tGSCLK. tOUT_ON is the actual on-time of the constant-
current driver. tGSCLK is the GSCLK period.
6
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
PARAMETER MEASUREMENT INFORMATION
PIN-EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
LAT
GND
GND
Figure 1. SIN, SCLK, and GSCLK
Figure 2. LAT
VCC
SOUT
GND
Figure 3. SOUT
(1)
OUTn
GND
(1) n = 0 to 15.
Figure 4. OUT0 Through OUT15
Copyright © 2012, Texas Instruments Incorporated
7
TLC59482
ZHCSAM5 –DECEMBER 2012
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TEST CIRCUITS
RL
CL
VCC
GND
VCC
(1)
IREF
OUTn
VLED
(2)
RIREF
(1) n = 0 to 15.
(2) CL includes measurement probe and jig capacitance.
Figure 5. Rise Time and Fall Time Test Circuit for OUTn
VCC
SOUT
VCC
(1)
CL
GND
(1) CL includes measurement probe and jig capacitance.
Figure 6. Rise Time and Fall Time Test Circuit for SOUT
VCC
OUT0
VCC
(1)
IREF
OUTn
RIREF
GND OUT15
VOUTn
VOUTfix
(1) n = 0 to 15.
Figure 7. Constant-Current Test Circuit for OUTn
8
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
TIMING DIAGRAMS
tWH0, tWH1, tWH2, tWL0, tWL1
:
VCC
Input(1) 50%
GND
tWH
tWL
tSU0, tSU1, tSU2, tH0, tH1, tH2, tH3
:
VCC
Clock Input(1)
50%
GND
VCC
tSU
tH
Data and Control
Clock(1)
50%
GND
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5
:
VCC
Input(1)
50%
GND
tD
VOH or VOUTnH
90%
50%
10%
Output
VOL or VOUTnL
tR or tF
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 9. Output Timing
Copyright © 2012, Texas Instruments Incorporated
9
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
GS1 GS1 GS1 GS1 GS1 GS1 GS1 GS1
5A
GS1
0A
GS0 GS0 GS0
14A
15A 13A
GS0
1A
GS0
0A
SIN
8A
7A
6A
4A
3A
2A
1A
tH0
tSU0
tWH0
SCLK
LAT
8
9
10
11
tWL0
12
13
14
tH1
15
16
1
2
--- 14
tSU1
15
16
tWH2
tSU2
tH2
tH3
tWH1
GSCLK
tD1
tWL1
GS Second Data
Latch (Internal)
Old Data
GS data are updated at the same time as the second
GS data when auto data refresh is disabled (XFRESH = 1).
New Data (GS15-15A to GS0-0A)
GS Third Data
Latch (Internal)
Old Data
New Data (GS15-15A to GS0-0A)
FC data are loaded into the common shift register
when the READFC command is input.
tD0
GS2 GS2 GS2 GS2 GS2 GS2 GS2 GS2
7A 4A 2A 1A
6A 5A 3A 0A
GS1
15A
GS1 GS1
14A 13A
GS1 GS1 GS0
1A
0A 15A
SOUT
tR0, tF0
GS data are one case.
tR1
tF1
OFF
OUT0, OUT7,
OUT8, OUT15
ON
tD2
tOUTON
OFF
ON
OUT1, OUT6,
OUT9, OUT14
tOUTON
tD3
OFF
ON
OUT2, OUT5,
OUT10, OUT13
tOUTON
tD4
OFF
ON
OUT3, OUT4,
OUT11, OUT12
tOUTON
tD5
tON_ERR = tOUTON - tGSCLK
(1) NV = Not valid; these data are not used for any function.
Figure 10. Timing Diagram
10
Copyright © 2012, Texas Instruments Incorporated
TLC59482
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ZHCSAM5 –DECEMBER 2012
PIN CONFIGURATIONS
DBQ PACKAGE
SSOP-24, QSOP-24
(Top View)
GND
SIN
1
2
3
4
5
6
7
8
9
24 VCC
23 IREF
SCLK
LAT
22 SOUT
21 GSCLK
20 OUT15
19 OUT14
18 OUT13
17 OUT12
16 OUT11
15 OUT10
14 OUT9
13 OUT8
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5 10
OUT6 11
OUT7 12
RGE PACKAGE
QFN-24
(Top View)
1
2
3
4
5
6
18 GSCLK
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
17 OUT15
16 OUT14
15 OUT13
14 OUT12
13 OUT11
Thermal Pad
(Bottom Side)
NOTE: The thermal pad is not internally connected to GND. The thermal pad must be connected to GND via the printed board circuit (PCB)
pattern.
Copyright © 2012, Texas Instruments Incorporated
11
TLC59482
ZHCSAM5 –DECEMBER 2012
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PIN DESCRIPTIONS
PIN
NO.
NAME
DBQ
RGE
I/O
DESCRIPTION
GND
1
22
—
Power ground
Grayscale (GS) pulse width modulation (PWM) reference clock control for OUTn.
Each GSCLK rising edge increments the GS counter for PWM control.
When the TMGRST command is input with the TMRSTEN bit (equal to '1') in the function
control data latch, all constant-current outputs (OUT0 to OUT15) are forced off and the GS
counter is reset to '0'. Furthermore, all constant-current outputs are forced off and the GS
counter is reset to '0' when the LATGS command is input with the XRFRESH bit (equal to '1')
in the function control data latch.
GSCLK
21
18
I
Reference current terminal.
IREF
LAT
23
4
20
1
I/O A resistor connected between IREF to GND sets the maximum current for all constant-current
outputs.
The LAT falling edge latches the data from the 16-bit common shift register into the first GS
data latch for the OUTn that are selected by either the GS data address down counter, global
I
brightness control (BC) data latch, or function control (FC) data latch. The data latch is
selected by the number of input SCLK rising edges while LAT is high. This pin is internally
pulled down to GND with a 500-kΩ (typ) resistor.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
5
2
3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
6
7
4
8
5
9
6
10
11
12
13
14
15
16
17
18
19
20
7
8
Constant-current outputs.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output.
9
10
11
12
13
14
15
16
17
Serial data shift clock.
Data present on SIN are shifted to the LSB of the 16-bit common shift register with the SCLK
rising edge. Data in the shift register are shifted towards the MSB at each SCLK rising edge.
The MSB of the common shift register appears on SOUT.
SCLK
SIN
3
2
24
23
19
21
I
I
Serial data input for the 16-bit common shift register
Serial data output of the 16-bit common shift register.
SOUT is connected to the 16-bit common shift register MSB. Data are clocked out at the
SCLK rising edge. Data in the function data latch can be read from SOUT during the READFC
command.
SOUT
VCC
22
24
O
—
Power-supply voltage
12
Copyright © 2012, Texas Instruments Incorporated
TLC59482
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ZHCSAM5 –DECEMBER 2012
FUNCTIONAL BLOCK DIAGRAM
VCC
SIN
LSB
MSB
16-Bit
Common
Shift Register
SOUT
SCLKB
SCLK
0
15
16
16
ADR[15:0]
1
1
1
1
16
16
16
16
Grayscale (GS)
Data Latch
Address Counter
LSB
MSB
XRST
GS First
Data Latch
for OUT0
GS First
Data Latch
for OUT15
GS First
Data Latch
for OUT1
GS First
Data Latch
for OU14
0
15 16
31 32
223 224
239 240
16
255
LAT16B
LOAD
16
16
16
LAT256B
LAT3RD
LATFC
LSB
MSB
GS Second
Data Latch
for OUT1
GS Second
Data Latch
for OUT0
GS Second
Data Latch
for OUT15
GS Second
Data Latch
for OUT14
LAT
Command
Decoder
0
15 16
31 32
223 224
239 240
255
16
16
16
16
XRST
MSB
SCLK
LSB
GS Third
DataLatch
for OUT0
GS Third
DataLatch
for OUT1
GS Third
DataLatch
for OUT14
GS Third
DataLatch
for OUT15
SCLKB
0
15 16
31 32
223 224
239 240
255
LAT
16
16
MSB
LSB
XRST
Power-On
Reset
Function Control (FC) Data Latch
16
XRFRESH
LATMODE
0
15
256
2
1
PRIODEND
XTMGRST
16-Bit
GS Counter
16-Bit PWM Timing Control
GSCLK
16
4-Grouped Switching Delay
16
6
BC
Reference
Current
Constant Sink Current Driver with 6-Bit BC
IREF
GND
Control
OUT0
OUT1
OUT14 OUT15
Copyright © 2012, Texas Instruments Incorporated
13
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
TYPICAL CHARACTERISTICS
At TA = +25°C, unless otherwise noted.
100
10
1
60
VCC = 5 V, BC = 3Fh,TA = +25°C
50
40
30
20
10
0
IOLCMax = 45 mA
IOLCMax = 35 mA
IOLCMax = 20 mA
IOLCMax = 10 mA
IOLCMax = 1 mA
0
10
20
30
40
50
0
0.5
1
1.5
2
2.5
3
Output Current (mA)
Output Voltage (V)
G000
G001
Figure 11. REFERENCE RESISTOR
vs OUTPUT CURRENT
Figure 12. OUTPUT CURRENT
vs OUTPUT VOLTAGE
39
38
37
36
35
34
33
32
31
3
2
VCC = 5 V, BC = 3Fh,IOLCMax = 35 mA
VCC = 5 V, BC = 3Fh,VOUTn = 0.8 V,TA = +25°C
1
0
−1
−2
−3
TA = −40°C
TA = +25°C
TA = +85°C
0
0.5
1
1.5
2
2.5
3
0
10
20
30
40
50
Output Voltage (V)
Output Current (mA)
G002
G003
Figure 13. OUTPUT CURRENT
vs OUTPUT VOLTAGE
Figure 14. CONSTANT-CURRENT ERROR vs
OUTPUT CURRENT SET BY EXTERNAL RESISTOR
3
2
50
VCC = 5 V, BC = 3Fh,VOUTn = 0.8 V,IOLCMax = 35 mA
VCC = 5 V,VOUTn = 0.8 V,TA = +25°C
IOLCMax = 45 mA
40
30
20
10
0
IOLCMax = 35 mA
IOLCMax = 20 mA
IOLCMax = 10 mA
1
0
−1
−2
−3
IOLCMax = 1 mA
48 56 63
−40
−20
0
20
40
60
80
100
0
8
16
24
32
40
Ambient Temperature (°C)
BC Data (Decimal)
G004
G005
Figure 15. CONSTANT-CURRENT ERROR
vs AMBIENT TEMPERATURE
Figure 16. GLOBAL BRIGHTNESS
CONTROL LINEARITY
14
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, unless otherwise noted.
20
18
16
14
12
10
8
VCC = 5.0 V
VCC = 3.3 V
6
TA = +25°C, SIN = 17.5 MHz, SCLK = 25 MHz,
GSCLK = 33 MHz, All GS data = FFFFh,
BC = 3Fh, VOUTn = 0.8 V
4
2
0
0
10
20
30
40
50
Output Current (mA)
G006
Figure 17. SUPPLY CURRENT
vs OUTPUT CURRENT
Copyright © 2012, Texas Instruments Incorporated
15
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
DETAILED DESCRIPTION
MAXIMUM CONSTANT SINK CURRENT VALUE
The maximum output current value of each channel (IOLCMax) is programmed by a single resistor (RIREF) that is
placed between the IREF and GND pins. The current value can be calculated by Equation 1:
VIREF (V)
RIREF (kW) =
´ 39.8
IOLCMax (mA)
Where:
VIREF = the internal reference voltage on IREF (typically 1.20 V when the global BC data are at maximum)
IOLCMax = 1 mA to 35 mA (3 V ≤ VCC ≤ 3.6 V) or 1 mA to 45 mA (3.6 V < VCC ≤ 5.5 V) at OUTn and BC =
63
(1)
IOLCMax is the highest current for each output. Each output sinks IOLCMax current when it is turned on and the
global brightness control (BC) data are set to the maximum value of 3Fh (64). Each output sink current can be
reduced by lowering the BC value.
RIREF must be between 1.06 kΩ and 47.8 kΩ in order to hold IOLCMax between 45 mA (typ) and 1 mA (typ).
Otherwise, the output may be unstable. Output currents lower than 1 mA can be achieved by setting IOLCMax to
1 mA or higher and then using global BC to lower the output current.
Table 1 shows the characteristics of the constant-current sink versus the external resistor, RIREF
.
Table 1. Maximum Constant-Current Output versus External Resistor Value
IOLC FOLLOWING POWER-UP (mA, BC =
IOLCMax (mA)
RIREF (kΩ, typ)
32)
22.5
20
45 (VCC > 3.6 V only)
1.06
1.19
1.37
1.59
1.91
2.39
3.18
4.78
9.55
47.8
40 (VCC > 3.6 V only)
35
30
25
20
15
10
5
17.5
15
12.5
10
7.5
5
2.5
0.5
1
GLOBAL BRIGHTNESS CONTROL (BC) FUNCTION
The TLC59482 can simultaneously adjust the output current of all constant-current outputs. This function is
called global brightness control (BC). The global BC for all outputs (OUT0 to OUT15) is programmed with a 6-bit
word. The global BC adjusts all output currents in 64 steps from 0% to 100%, where 100% corresponds to the
maximum output current set by RIREF. Equation 2 calculates the actual output current as a function of RIREF and
global BC value. BC data can be set via the serial interface. When the device is powered on, the BC data in the
function control (FC) data latch is set to 32 as the initial value.
The output current value controlled by BC can be calculated by Equation 2.
BCn
63
IOUTn (mA) = IOLCMax (mA) ´
Where:
IOLCMax = the maximum constant-current value for each output determined by RIREF
BC = the global brightness control value in the brightness control data latch (0 to 63)
(2)
16
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
Table 2 summarizes the BC data versus the set current value.
Table 2. BC Data versus Constant-Current Ratio and Set Current Value
BC DATA
RATIO OF OUTPUT
CURRENT TO
IOLCMax(%)
IOUT (mA)
(IOLCMax= 45 mA,
typ)
IOUT (mA)
BINARY
00 0000
00 0001
00 0010
—
DECIMAL
HEX
(IOLCMax= 1 mA, typ)
0
00
0
0
0
1
01
1.6
0.71
1.43
—
0.02
0.03
—
2
02
3.2
—
—
—
01 1111
10 0000 (default)
10 0001
—
31
1F
49.2
50.8
52.4
—
22.14
22.86
23.57
—
0.49
0.51
0.52
—
32 (default)
20 (default)
33
—
61
62
63
21
—
11 1101
11 1110
11 1111
3D
3E
3F
96.8
98.4
100.0
43.57
44.29
45.00
0.97
0.98
1.00
GRAYSCALE (GS) FUNCTION (PWM CONTROL)
The TLC59482 can adjust the brightness of each output channel using a pulse width modulation (PWM) control
scheme. The architecture of 16 bits per channel results in 65,536 brightness steps, from 0% up to 100%
brightness.
The PWM operation is controlled by the grayscale (GS) counter based on the GS data in the third GS data latch.
The GS counter increments on each rising edge of the grayscale reference clock (GSCLK). When the TMGRST
command is input with the TMRSTEN bit (equal to '1') of the function control data latch, or when the LATGS
command is input with the XRFRESH bit (equal to '1') of the function control data latch, all constant-current
outputs (OUT0 to OUT15) are forced off, the GS counter is reset to ‘0’, and the GS PWM timing controller is
initialized.
The on-time (tOUT_ON) of each output (OUTn) can be calculated by Equation 3.
tOUT_ON (ns) = tGSCLK × GSn
where:
tGSCLK is on GS clock period
GSn is the programmed GS value for OUTn (0 to 65535)
(3)
Copyright © 2012, Texas Instruments Incorporated
17
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
Table 3 summarizes the GS data values versus the output on-time duty cycle in a 16-bit length PWM. When the
device powers up, all outputs are forced off and do not turn on until the 256-bit GS data are written to the third
data latch even if GSCLK is input.
Table 3. Output Duty Cycle and On-Time versus GS Data (16-Bit PWM Bit Length)
GS DATA
GS DATA
ON-TIME RATE vs
MAX GS (%)
ON-TIME RATE vs
MAX GS (%)
DECIMAL
0
HEX
0
DECIMAL
32768
32769
32770
32771
—
HEX
8000
8001
8002
8003
—
0
50.001
50.002
50.004
50.005
—
1
1
0.002
0.003
0.005
—
2
2
3
3
—
—
8191
8192
8193
—
1FFF
2000
2001
—
12.499
12.500
12.502
—
40959
40960
40961
—
9FFF
A000
A001
—
62.499
62.501
62.502
—
16383
16384
16385
—
3FFF
4000
4001
—
24.999
25.000
25.002
—
49151
49152
49153
—
BFFF
C000
C001
—
75.000
75.001
75.003
—
24575
24576
24577
—
5FFF
6000
6001
—
37.499
37.501
37.502
—
57343
57344
57345
—
DFFF
E000
E001
—
87.500
87.501
87.503
—
32765
32766
32767
7FFD
7FFE
7FFF
49.996
49.998
49.999
65533
65534
65535
FFFD
FFFE
FFFF
99.997
99.998
100.000
Enhanced Spectrum (ES) PWM Control
In this PWM control, the entire display period is divided into 128 display segments. The total display period is the
time from the first grayscale clock (GSCLK) to the 65,536th GS clock input for the 16-bit length PWM. Each
display segment has a maximum of 512 grayscale clocks (maximum). The OUTn on-time changes, depending on
the 16-bit grayscale data. Refer to Table 4 for the sequence of information and to Figure 18 for the timing
information.
18
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
Table 4. ES PWM Drive Turn On-Time Length
GS DATA
DECIMAL
HEX
OUTn DRIVER OPERATION
Does not turn on
0
1
2
3
4
5
6
0000h
0001h
0002h
0003h
0004h
0005h
0006h
Turns on for one GSCLK period in the first display segment
Turns on for one GSCLK period in the first and 65th display segments
Turns on for one GSCLK period in the first, 65th, and 33th display segments
Turns on for one GSCLK period in the first, 65th, 33th, and 97th display segments
Turns on for one GSCLK period in the first, 65th, 33th, 97th, and 17th display segments
Turns on for one GSCLK period in the first, 65th, 33th, 97th, 17th, and 81th display segments
The number of display segments where OUTn is turned on for one GSCLK is incremented by
increasing the GS data in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 >
101 > 21 > 85 > 53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83
> 51 > 115 > 11 > 75 > 43 > 107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 >
15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 > 2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42
> 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86 > 54 > 118 > 14 > 78 > 46 > 110 > 30 >
94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44 > 108 > 28 > 92 > 60 >
124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 > 128.
—
—
Turns on for one GSCLK period in the first to 127th display segments, but does not turn on in the
128th display segment
127
128
129
007Fh
0080h
0081h
Turns on for one GSCLK period in all display segments (first to 128th)
Turns on for two GSCLK periods in the first display period and for one GSCLK period in all other
display periods
The number of display segments where OUTn is turned on for one GSCLK is incremented by
increasing the GS data in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 >
101 > 21 > 85 > 53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83
> 51 > 115 > 11 > 75 > 43 > 107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 >
15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 > 2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42
> 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86 > 54 > 118 > 14 > 78 > 46 > 110 > 30 >
94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44 > 108 > 28 > 92 > 60 >
124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 > 128.
—
—
Turns on for two GSCLK periods in the first to 127th display segments and turns on one GSCLK
period in the 128th display segment
255
256
257
00FFh
0100h
0101h
Turns on for two GSCLK periods in all display segments (first to 128th)
Turns on for three GSCLK periods in the first display segments and for two GSCLK periods in all
other display segments
The number of display segments where OUTn is turned on for one GSCLK is incremented by
increasing the GS data in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 >
101 > 21 > 85 > 53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83
> 51 > 115 > 11 > 75 > 43 > 107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 >
15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 > 2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42
> 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86 > 54 > 118 > 14 > 78 > 46 > 110 > 30 >
94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44 > 108 > 28 > 92 > 60 >
124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 > 128.
—
—
Turns on for 511 GSCLK periods in the first to 127th display segments, but only turns on 510
GSCLK periods in the 128th display segment
65407
65408
65409
—
FF7Fh
FF80h
FF81h
—
Turns on for 511 GSCLK periods in all display segments (first to 128th)
Turns on for 512 GSCLK periods in the first display period and for 511 GSCLK periods in the
second to 128th display segments
—
Turns on for 512 GSCLK periods in the first to 63th and 65th to 127th display segments; also turns
on 511 GSCLK periods in 64th and 128th display segments
65534
FFFEh
Turns on for 512 GSCLK periods in the first to 127th display segments but only turns on 511
GSCLK periods in the 128th display segment
65535
FFFFh
Copyright © 2012, Texas Instruments Incorporated
19
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
16382
16383
16384
16385
32766
32767
32768
32769
32770
¼
49150
49151
49152
49153
65023
65024
65025
65026
65536
65534
¼
511
513
514
16386
49154
¼
¼
¼
49155
¼
1
2
3
512
16387
32771
65535
GSCLK
32nd 33rd
Period Period
2nd
Period
64th 65th
Period Period
96th
Period Period
97th 127th
¼
128th
Period
1st
Period
¼
¼
¼
1st Period
(Voltage Level = High)
OFF
Period
OUTn
(GS Data = 0000h)
(Voltage Level = Low)
ON
t = GSCLK ´ 1d
OFF
ON
OUTn
(GS Data = 0001h)
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
OFF
ON
OUTn
(GS Data = 0002h)
t = GSCLK
t = GSCLK
OFF
ON
OUTn
(GS Data = 0003h)
t = GSCLK
t = GSCLK
OFF
ON
OUTn
(GS Data = 0004h)
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
OFF
ON
OUTn
(GS Data = 0041h)
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
OFF
ON
OUTn
(GS Data = 0080h)
t = GSCLK
t = GSCLK
t = GSCLK ´ 2
t = GSCLK ´ 1
OFF
ON
OUTn
(GS Data = 0081h)
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK ´ 2
t = GSCLK ´ 2
OFF
ON
OUTn
(GS Data = 0082h)
t = GSCLK
t = GSCLK
t =
GSCLK ´ 511
t = GSCLK ´ 511 in 2nd to 128th Period
OFF
ON
OUTn
(GS Data = FF80h)
t = GSCLK ´ 512
t = GSCLK ´ 511 in 2nd to 128th Period
OFF
ON
OUTn
(GS Data = FF81h)
t = GSCLK ´ 512 in 2nd to 63rd and 65th to 127th Periods,
t = GSCLK ´ 511 in 64th Period
t =
GSCLK ´ 511
t = GSCLK ´ 512
t = GSCLK ´ 512
OFF
ON
OUTn
(GS Data = FFFEh)
t =
GSCLK ´ 511
t = GSCLK ´ 512 in 2nd to 127th Period
OFF
ON
OUTn
(GS Data = FFFFh)
Figure 18. ES PWM Operation
20
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
Auto Display Repeat Function
This function can repeat the total display period as long as GSCLK is present, as shown in Figure 19. This
function is always enabled. OUTn turn on at the 513th GSCLK after the first LATGS command is input.
3V~5.5V
VCC
0V
SIN
SCLK
256 SCLK for 16-bit
* 16-word writing
2 SCLK for
“LATGS”
Command
LAT
First
“LATGS”
Command
16 LAT for
16 “WRTGS”
Command
GS Third Data
Latch (Internal)
Unknown
Written Data by 16 “WRTGS” Command
65534
65535
65536
1
1
65534
65535
65536
1
1
2
2
2
2
3
3
3
512
GSCLK
Third Entire
Display Period
First Entire
Display Period
Second Entire
Display Period
OUTn is turned on
at 513th GSCLK after first
“LATGS” command is input.
Display period is repeated
by auto display repeat
function.
OFF
ON
OFF
OFF
OUT
(GS Data = FFFFh)
Figure 19. Auto Display Repeat Function
Auto Data Refresh Function
This function allows users to input grayscale (GS) data at any time without synchronizing the input to the display
timing. When the LATGS command is input with the auto data refresh function enabled (XRFRESH bit = 0), the
256-bit data in the first GS data latch are copied only to the second GS data latch. The data in the second GS
data latch are copied to the third data latch when the 65,536th GSCLK occurs. The third latch data are used for
constant-current output (OUT0-OUT15) for the next display period.
When the LATGS command is input with the auto data refresh function disabled (XRFRESH bit = 1), the 256-bit
data in the first GS data latch are copied to the second and third GS data latches at the same time and the GS
data in the third data latch are used for OUT0-OUT15 on/off control from the next input GSCLK rising edge.
Furthermore, the GS counter is set to '0' and all constant-current outputs (OUTn) are forced off. Refer to
Figure 20 for a timing diagram of the auto data refresh function.
Copyright © 2012, Texas Instruments Incorporated
21
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
GS1
0B
GS0
15B
GS0 GS0 GS0 GS0
4B 2B 1B
3B
GS0
0B
GS15 GS15 GS15 GS15 GS15 GS15
10C
SIN
15C 14C 13C
12C 11C
Dotted line LAT
timing is accepted.
SCLK
LAT
1
12
Dotted line LAT timing
is accepted.
13
14
15
16
The LATGS command executes.
- - - -
2 or 3 rising edge of SCLK is needed
to be input while LAT is high level.
65535
1
3
- - - -
65534
65536
2
GSCLK
Shift Register
LSB Data
(Internal)
GS1
0B
GS0
15B
GS0 GS0 GS0 GS0 GS0
4B
GS0
0B
GS15 GS15 GS15 GS15 GS15 GS15
15C 14C 13C 12C 11C 10C
5B
3B
2B
1B
Shift Register
LSB+1 Data
(Internal)
GS1
1B
GS1
0B
GS0 GS0 GS0 GS0 GS0
3B
GS0
1B
GS0 GS15 GS15 GS15 GS15 GS15
0B 15C 14C 13C 12C 11C
6B
5B
4B
2B
Shift Register
MSB-1 Data
(Internal)
GS1
14B
GS1 GS1 GS1
3B 2B 1B
GS0 GS0 GS0 GS0 GS0 GS0
13B 12B 11B 10B 9B 8B
GS1
13B
GS1
0B
GS0
15B
GS0
14B
GS1
15B
GS1 GS1 GS1 GS1
14B 4B 3B 2B
GS0
15B
GS0 GS0 GS0 GS0 GS0 GS0
14B 13B 12B 11B 10B 9B
GS1
1B
GS1
0B
SOUT
OUT1
OUT0
GS Data Latch
Address Counter
(Internal)
OUT15
OUT0
OUT15 GS First
Data Latch
(Internal)
The all data in 16-bit common shift
register are copied to GS0 first data
latch at falling edge of LAT.
OUT0 GS First
Data Latch
(Internal)
Old 16-bit GS Data
New 16-bit GS Data
New 256-bit GS Data
The all data in GS first data
latch are copied to GS
second data latch.
GS Second Data
Latch (Internal)
Old 256-bit GS Data
When Auto data refresh mode is enabled,
the all data in GS second data latch are copied
to GS third data latch at 65536th GSCLK.
GS Third Data
Latch (Internal)
Old 256-bit GS Data
New 256-bit GS Data
OFF
ON
OUT
(GS data = FFFFh)
Figure 20. Auto Data Refresh Function (XRFRESH = 0, LATMODE = 0)
22
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
REGISTER AND DATA LATCH CONFIGURATION
The TLC59482 has one common shift register, one function control (FC) data latch, and a set of three data
latches: the first, second, and third grayscale (GS) data latches. The common shift register and FC data latch are
16 bits long and the GS data latches are 256 bits long. Figure 21 shows the common shift register and the data
latches configuration.
LSB
MSB
SIN
16-bit
Common
Shift Register
SOUT
SCLK
LOAD
0
15
16
OUT15 GS Data Latch (Internal)
OUT14 GS Data Latch (Internal)
OUT13~2 GS Data Latch (Internal)
OUT1 GS Data Latch (Internal)
OUT0 GS Data Latch (Internal)
12
16
16
16
GS
First Latch
for OUT0
16
GS
First Latch
for OUT1
16
GS
First Latch
for OU14
LSB
MSB
GS
First Latch
for OUT15
0
15 16
31 32
223 224
239 240
16
255
16
16
16
Latch Signal for GS Second
Data Latch (Internal)
LSB
MSB
GS
Second Latch
for OUT1
GS
Second Latch
for OUT0
GS
Second Latch
for OUT15
GS
Second Latch
for OUT14
0
15 16
31 32
223 224
239 240
16
255
Latch Signal for GS Third
Data Latch (Internal)
16
16
16
MSB
LSB
GS
Third Latch
for OUT0
GS
Third Latch
for OUT1
GS
Third Latch
for OUT14
GS
Third Latch
for OUT15
0
15 16
31 32
223 224
239 240
255
Latch Signal for FC
Data Latch (Internal)
16
DIN
LSB
MSB
LAT
16
Function Control (FC) Data Latch
0
15
16
256
To Constant Current Output/
To PWM Timing
Control Circuit
PWM Timing Control/Data Latch
Control Circuit
Figure 21. Shift Register and Data Latch Configuration
Copyright © 2012, Texas Instruments Incorporated
23
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
16-Bit Common Shift Register
The 16-bit common shift register is used to shift data from the SIN pin into the TLC59482. The data shifted into
the register are used for GS and FC data. The LSB of the common shift register is connected to SIN and the
MSB is connected to SOUT. On each SCLK rising edge, the data on SIN are shifted into the LSB and all 16 bits
are shifted towards the MSB. The register MSB is always connected to SOUT. When the device is powered up,
the data in the 16-bit common shift register are set to '0'.
First, Second, and Third Grayscale Data Latch
The first, second, and third grayscale (GS) data latches are each 256 bits long, and set the PWM timing for each
constant-current output. The on-time of all constant-current outputs is controlled by the data in the third GS data
latch. The 16-bit data are copied to the first GS data latch indicated by the GS data latch address counter when
the WRTGS command is input. The 256-bit GS data for OUTn in the first data latch are copied to the second GS
data latch when the LATGS command is input. The 256-bit data in the second data latch are copied to the third
GS data latch when the 65,536th GSCLK occurs with the XRFRESH bit in the FC data latch set to ‘0’. When the
XRFRESH bit is '1', the 256-bit data in the first data latch are copied to the second and third data latch at the
same time. When the device powers up, all constant-current outputs are forced off until GS data are written to
the third data latch. The GS data write sequence is shown in Figure 22 and Figure 23.
GS14 GS14
14B 13B
GS0
0A
GS14
15B
GS15 GS15 GS15
1B
GS15
0B
GS15 GS15 GS15 GS15 GS15
15B 14B 13B 12B 11B
GS15 GS15 GS15
6B 5B 4B
SIN
3B
2B
SCLK
LAT
1
2
3
1
2
3
4
5
10
11
12
13
14
15
16
Dashed LAT
timing is accepted.
0 or 1 SCLK rising edge must
be input while LAT is high.
Shift Register
LSB Data
(Internal)
GS0
0A
GS15 GS15 GS15 GS15
15B 14B 13B 12B
GS15 GS15 GS15
4B
GS15
0B
GS15 GS15 GS15
3B 2B 1B
GS14 GS14
15B 14B
6B
5B
Shift Register
LSB+1 Data
(Internal)
GS0
1A
GS0 GS15 GS15 GS15
0A 15B 14B 13B
GS15 GS15 GS15
5B
GS15 GS15 GS15
4B 3B 2B
GS15
1B
GS15 GS14
15B
7B
6B
0B
Shift Register
MSB-1 Data
(Internal)
GS0
14A
GS0 GS0 GS0 GS0
13A 12A 11A 10A
GS0 GS0 GS0
4A 3A 2A
GS0 GS0 GS15
1A 0A 15B
GS15 GS15
13B 12B
GS15
14B
GS0
15A
GS0 GS0 GS0 GS0
14A 13A 12A 11A
GS0 GS0 GS0
5A 4A 3A
GS0 GS0 GS0
0A
GS15
15B
GS15 GS15
14B 13B
SOUT
2A
1A
The GS data latch address counter value is decreased by 1
for every WRTGS command input.When the counter value is
‘0’, if the command is input, then the value becomes ‘15’.
GS Data Latch
Address Counter
(Internal)
OUT14
OUT15
The data in the 16-bit common shift register are
copied to the first data latch of OUTn shown
by the GS data latch address counter.
OUT15 GS First
Data Latch
(Internal)
Old 16-bit GS Data
New 16-bit GS Data
OUT0 GS First
Data Latch
(Internal)
GS Second Data
Latch (Internal)
GS Third Data
Latch (Internal)
Figure 22. 16-Bit GS Data Write (WRTGS) Command
24
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
GS1
0B
GS0 GS0 GS0 GS0 GS0
15B 14B 13B
12B 11B
GS0
6B
GS0 GS0 GS0 GS0 GS0
5B 4B 2B 1B
3B
GS0
0B
GS15 GS15 GS15
15C 14C 13C
SIN
Dotted line LAT
timing is accepted.
SCLK
LAT
1
2
3
1
2
3
4
5
10
11
12
13
14
15
16
Dashed LAT timing
is accepted.
2 or 3 SCLK rising edges must
be input while LAT is high.
Shift Register
LSB Data
(Internal)
GS1
0B
GS0 GS0 GS0 GS0
15B 14B 13B 12B
GS0 GS0 GS0
6B 5B 4B
GS0
0B
GS0 GS0 GS0
3B 2B 1B
GS15 GS15
15C 14C
Shift Register
LSB+1 Data
(Internal)
GS1
1B
GS1 GS0 GS0 GS0
0A 15B 14B 13B
GS0 GS0 GS0
7B 6B 5B
GS0 GS15
15C
GS0 GS0 GS0
4B 3B 2B
GS0
1B
0B
Shift Register
MSB-1 Data
(Internal)
GS1
14B
GS1 GS1 GS1 GS1
13A 12A 11A 10A
GS1 GS1 GS1
4A 3A 2A
GS1 GS1 GS0
1A 0A 15B
GS0 GS0
13B 12B
GS0
14B
GS1
15B
GS1 GS1 GS1 GS1
14A 13A 12A 11A
GS1 GS1 GS1
3A
GS1 GS1 GS1
2A 1A 0A
GS0
15B
GS0 GS0
14B 13B
SOUT
5A
4A
OUT1
OUT0
GS Data Latch
Address Counter
(Internal)
OUT15
OUT0
OUT15 GS First
Data Latch
(Internal)
All data in the 16-bit common shift
register are copied to the first GS0 data latch.
OUT0 GS First
Data Latch
(Internal)
Old 16-Bit GS Data
Old 256-Bit GS Data
New 16-Bit GS Data
All data in the first GS data latch are copied
to the second GS data latch.
GS Second Data
Latch ( Internal)
New 256-Bit GS Data
When the auto data refresh mode is disabled,
all data in the first GS data latch are copied
to both the second and third GS data latches.
GS Third Data
Latch (Internal)
New 256-Bit GS Data
Old 256-Bit GS Data
Figure 23. 256-Bit GS Data Latch (LATGS) Command (LATMODE = 0)
Copyright © 2012, Texas Instruments Incorporated
25
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
Function Control (FC) Data Latch
The function control (FC) data latch is 16 bits long. This latch sets the brightness control (BC) data, auto data
refresh, enables or disables the display timing reset, and selects the data latch mode. When the device is
powered on, the data in the FC data latch are set to the default values, as shown in Table 5.
Table 5. Function Control Data Latch Bit Description
DEFAULT
BIT
BIT
VALUE
NUMBER
NAME
(Binary)
DESCRIPTION
0 (LSB) to 3
N/A
0000
No applicable bit
Global brightness (BC) control bit (000000-111111).
This 6-bit data controls all output current with 64 steps between 0% and 100%
of the maximum current determined by a external resistor. When all bits are ‘0’,
all outputs are off. When the device is powered on, all output current are set to
approximately 50%.
4-9
BC
100000
Auto data refresh mode bit (0 = enabled, 1 = disabled).
If the LATGS command is input while this bit is '1', all data in the first grayscale
(GS) data latch are copied to both the second and third GS data latches. All
OUTn are forced off and the GS counter is also reset to '0'.
10
XRFRESH
0
If the LATGS command is input while this bit is '0', all data in the first GS data
latch are only copied to the second GS data latch. All data in the second GS
data latch are copied to the third GS data latch when the GS counter reaches
the maximum count value of 65,535. No OUTn are forced off and the GS
counter continues counting.
Display timing reset enable bit (0 = disabled, 1 = enabled).
If the TMGRST command is input while this bit is '1', the GS counter is reset to
'0'. When this occurs, all OUTn are forced off. When this bit is '0', even if the
TMGRST command is input, the GS counter is not reset to '0'.
11
TMRSTEN
N/A
0
12-14
000
No applicable bit
Latch mode select bit (0 = 15 WRTGS + 1 LATGS mode, 1 = 16 WRTGS + 1
LATGS mode).
When this bit is '1', The commands for all GS data writes are (16 × WRTGS + 1
LATGS). The 16th WRTGS command is required to latch the last GS input 16-
bit data to the first GS data latch.
15 (MSB)
LATMODE
0
When this bit is '0', the commands for all GS data writes are (15 × WRTGS + 1
LATGS). The 16th WRTGS command is not required to latch the last GS input
16-bit data to the first GS data latch.
26
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
Display Timing Reset Function
This function allows users to reset the GS counter using the TMGRST command described in Table 6. This
function is enabled when the TMRSTEN bit in the FC control data latch is ‘1’. The grayscale counter is reset to '0'
when the TMGRST command is input. All OUTn are forced off. Refer to Figure 26 for a display timing reset
functional timing diagram
Table 6. Function Commands Description
SCLK RISING
EDGES
COMMAND NAME
WHILE LAT IS HIGH
DESCRIPTION
The 16-bit data in the 16-bit common shift register are copied to the 16-bit GS latch in the
first latch selected by the GS data latch address counter. Refer to Figure 22 for a timing
diagram of this command operation.
WRTGS
(16-bit GS data write)
0 or 1
All data in the first GS data latch are only copied to the second GS data latch when the
XRFRESH bit in the FC data latch is ‘0’, All data in the first GS data latch are copied to both
the second and third GS data latches when the XRFRESH bit in the FC data latch is '1'. The
GS data latch address counter is initialized to OUT15 at the same timing. Refer to Figure 23
for a timing diagram of this command operation.
LATGS
(256-bit GS data
latch)
2 or 3
The 16-bit data in the FC data latch are copied to the 16-bit shift register. The loaded data
can be read from SOUT synchronized with the SCLK rising edge. Refer to Figure 24 for a
timing diagram of this command operation.
READFC
(FC data read)
4 or 5
WRTFC
(FC data write)
The 16-bit data in the 16-bit common shift register are copied to the FC data latch. Refer to
Figure 25 for a timing diagram of this command operation.
10 or 11
12 or 13
14 or 15
The GS counter is reset to '0' and all constant-current outputs (OUTn) are forced off when
the TMRSTEN bit in the FC data latch is ‘1’. However, the GS data in the third data latch
are not updated. Refer to Figure 26 for a timing diagram of this command operation.
TMGRST
(display timing reset)
FCWRTEN
(FC write enable)
FC writes are enabled by this command. This command must always be input before the
FC data write occurs. Refer to Figure 25 for a timing diagram of this command operation.
Function Commands
The TLC59482 has six commands that can be input with SCLK and LAT signals: WRTGS. LATGS, READFC,
WRTFC, TMGRST, and FCWRTEN. Refer to Figure 21 to Figure 26 for detailed command input timing diagrams
for each command. Each command function is described in Table 6.
(1)
*1
1
1
1
1
1
1
1
1
1
1
SIN
1
Dashed LAT
timing is accepted.
SCLK
LAT
1
2
3
4
5
10
11
12
13
14
15
16
1
2
3
4
Dashed LAT timing
is also accepted.
4 or 5 SCLK rising edges must
be input while LAT is high.
16-bit FC data are loaded to the 16-bit
common shift register at the LAT signal falling edge.
FC
12
FC
14
FC
13
FC
15
SOUT
Figure 24. FC Data Read (READFC) Command Timing Diagram
Copyright © 2012, Texas Instruments Incorporated
27
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
*1
*1
*1
*1
*1
FC
15
FC
14
FC
13
FC
12
FC
11
FC
10
FC
9
FC
1
FC
0
*1: Dont’ Care
SIN
Dotted line LAT
timing is accepted.
Dotted line LAT
timing is accepted.
SCLK
1
2
3
15
16
1
2
3
4
5
6
7
15
16
LAT
14 or 15 rising edge of SCLK is needed
to be input while LAT is high level for
FC write enable.
10 or 11 rising edge of SCLK is needed
to be input while LAT is high level for
FC write enable.
Dotted line LAT timing
is accepted too.
16-bit FC
Data Latch
(Internal)
Old 16-bit FC Data New 16-bit FC Data
The data in 16-bit common shift register are loaded to
FC data latch at LAT signal falling edge.
FC
15
SOUT
Figure 25. FC Data Write Enable (FCWRTEN) and FC Data Write (WRTFC) Command Timing Diagram
(1)
1
1
1
1
1
1
1
1
1
1
1
SIN
1
Dashed LAT
timing is accepted.
SCLK
LAT
1
2
3
1
2
3
4
5
10
11
12
13
14
15
16
Dashed LAT timing
is also accepted.
12 or 13 SCLK rising edges are required
to be input while LAT is high.
RSTENA in
FC Data Latch
(Internal)
1
GS counter is reset at the LAT
signal falling edge.
GS Counter
(Internal)
0
1
2
GSCLK
All OUTn are forced off at
the LAT signal falling edge.
OFF
OFF
OUT
ON
Figure 26. Display Timing Reset (TMGRST) Command Timing Diagram
28
Copyright © 2012, Texas Instruments Incorporated
TLC59482
www.ti.com.cn
ZHCSAM5 –DECEMBER 2012
GS0
0A
GS1
0A
GS0
15A
GS0
0
GS14 GS13 GS1 GS1
15A 15A 14A
GS1
1A
GS0
3A
GS0
1A
GS0
2A
GS15 GS15
15A 14A
GS15 GS15
1A
GS14 GS14
15A 14A
GS14
1A
SIN
SCLK
LAT
0A
0A
241
253
254
255
256
1
2
15
16
17
18
31
32
225
226
239
240
Dashed LAT timing is also accepted.
1st WRTGS
Command
2nd WRTGS
Command
15th WRTGS
Command
LATGS
Command
16-Bit Common
Shift Register
(Internal)
GS0
15
GS0
14
GS0 GS0
0
GS15
15A
GS15
14A
GS15 GS15 GS14
0A
GS2
14A
GS2 GS2
0A
GS1
15A
GS1 GS1 GS1
2A 0A
GS0
15A
SOUT
1A
1
15A
1A
1A
LATMODE Bit
in FC Data Latch
(Internal)
0
The counter is decreased when
“WRTGS” command is input.
The counter is set to OUT15 when
“LATGS” command is input.
OUT13
OUT1
GS Data Latch
Address Counter
(Internal)
OUT15
OUT15
OUT14
OUT14
OUT0
OUT15
OUT1
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 1’st “WRTGS” command
New 16bit GS data
OUT0
OUT15 GS First
Data Latch
(Internal)
Old 16-bit GS data
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 2’nd “WRTGS” command.
OUT14 GS First
Data Latch
(Internal)
Old 16-bit GS data
New 16-bit GS data
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 15’th “WRTGS” command
OUT1 GS First
Data Latch
(Internal)
New 16-bit
GS data
Old 16-bit GS data
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 16’th “LATGS” command.
OUT0 GS First
Data Latch
(Internal)
Old 16-bit
GS data
The all data in GS first data latch
are copied to GS second data latch.
New 16-bit
GS Data
GS Second
Data Latch
(Internal)
Old 256-bit
GS data
The all data in GS first data latch are copied
to both GS second and third data latch
when Auto data refresh mode is disabled.
New 256-bit
GS Data
GS Third
Data Latch
(Internal)
Figure 27. 256-Bit GS Data Write Sequence Timing Diagram
(15 × WRTGS + 1 LATGS, LATMODE = 0)
Copyright © 2012, Texas Instruments Incorporated
29
TLC59482
ZHCSAM5 –DECEMBER 2012
www.ti.com.cn
GS13 GS0
3A
GS0
0A
(1)
GS15
15A
GS15 GS15
1A
0A
GS14
15A
GS14
1A
GS14
0A
GS0 GS0
1A
GS0
0
1
1
SIN
SCLK
LAT
1
1
1
15A
2A
257
269
270
271
272
1
15
16
17
31
32
253
254 255
256
Dotted line LAT timing is also accepted.
1st WRTGS
Command
2nd WRTGS
Command
16th WRTGS
Command
LATGS
Command
16-Bit Common
Shift Register
(Internal)
GS15
14A
GS0
15A
GS1
14A
GS15
15A
GS15 GS15
0A
GS0
15
GS0
14
GS0
0
GS14
15A
GS1
0A
GS0
0A
GS0
1
GS1
14A
GS0 GS0 GS0
2A
GS1
1A
SOUT
1A
3A
1A
LATMODE Bit
in FC Data Latch
(Internal)
1
The counter is decreased when
the WRTGS command is input.
The counter is set to OUT15 when
the LATGS command is input.
OUT13
OUT0
GS Data Latch
Address Counter
(Internal)
OUT15
OUT15
OUT15
OUT14
OUT15
OUT14
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 1’st “WRTGS” command
OUT15 GS First
Data Latch
(Internal)
Old 16-bit GS Data
New 16-Bit GS Data
All data in the 16-bit common shift
register are copied to the first GS1 data
latch at the 2nd WRTGS command.
OUT15 GS First
Data Latch
(Internal)
Old 16-Bit GS Data
New 16-Bit GS Data
All data in the16-bit common shift
register are copied to the first GS0 data
latch at the 16th WRTGS command.
OUT0 GS First
Data Latch
(Internal)
Old 16-Bit GS Data
New 16-Bit GS Data
The all data in GS first data latch
are copied to GS second data latch.
GS Second
Data Latch
(Internal)
Old 256-bitGS Data
All data in the first GS data latch are copied to both the second and
third GS data latches when the auto data refresh mode is disabled.
New 256-Bit
GS Data
GS Third
Data Latch
(Internal)
.
Old 256-Bit GS Data
Figure 28. 256-Bit GS Data Write Sequence Timing Diagram
(16 × WRTGS + 1 LATGS, LATMODE = 1)
NOISE REDUCTION
Large surge currents may flow through the device and the board on which the device is mounted if all 16 outputs
turn on or off simultaneously. These large current surges can introduce detrimental noise and electromagnetic
interference (EMI) into other circuits.
The TLC59482 turns the outputs on with a series delay for each group independently to provide a soft-start
feature. The output current sinks are grouped into four groups. The first output group that is turned on/off are
OUT0, OUT7, OUT8, and OUT15; the second output group is OUT1, OUT6, OUT9, and OUT14; the third output
group is OUT2, OUT5, OUT10, and OUT13; and the fourth output group is OUT3, OUT4, OUT11, and OUT12.
Each output group is turned on and off sequentially with a 5-ns (typical) delay between the groups. However,
each output on/off is controlled by the GS clock.
30
Copyright © 2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC59482DBQ
ACTIVE
ACTIVE
SSOP
SSOP
DBQ
DBQ
24
24
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
TLC59482
TLC59482
TLC59482DBQR
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
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