TLC5923RHB [TI]
IC LED DISPLAY DRIVER, PQCC32, 5 X 5 MM, PLASTIC, QFN-32, Display Driver;
| 型号： | TLC5923RHB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC LED DISPLAY DRIVER, PQCC32, 5 X 5 MM, PLASTIC, QFN-32, Display Driver 驱动 接口集成电路 |
| 文件： | 总28页 (文件大小：1126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5923
DAP
RHB
www.ti.com
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
16-CHANNEL LED DRIVER WITH DOT CORRECTION
Check for Samples: TLC5923
1
FEATURES
– TEF: Thermal Error Flag
2
•
•
16 Channels
APPLICATIONS
Drive Capability
•
•
•
•
Monocolor, Multicolor, Fullcolor LED Display
Monocolor, Multicolor LED Signboard
Display Backlighting
–
0 to 80 mA (Constant-Current Sink)
•
•
•
•
•
•
•
•
•
Constant Current Accuracy: ±1% (typical)
Serial Data Interface
Multicolor LED lighting applications
Fast Switching Output: Tr / Tf = 10ns (typical)
CMOS Level Input/Output
DESCRIPTION
30 MHz Data Transfer Rate
The TLC5923 is a 16 channel constant-current sink
driver. Each channel has a On/Off state and a 128-
step adjustable constant current sink (dot correction).
The dot correction adjusts the brightness variations
between LED, LED channels and other LED drivers.
Both dot correction and On/Off state are accessible
via a serial data interface. A single external resistor
sets the maximum current of all 16 channels.
VCC = 3.0 V to 5.5 V
Operating Temperature = –40°C to 85°C
LED Supply Voltage up to 17 V
32-pin HTSSOP( PowerPAD™) and QFN
Packages
•
Dot Correction
The TLC5923 features two error information circuits.
The LED open detection (LOD) indicates a broken or
disconnected LED at an output terminal. The thermal
error flag (TEF) indicates an overtemperature
condition.
–
–
7 bit (128 Steps)
individual adjustable for each channel
•
•
Controlled In-Rush Current
Error Information
–
LOD: LED Open Detection
FUNCTIONAL BLOCK DIAGRAM
VCC GND PGND SCLK
SIN
MODE
XLAT
BLANK
MODE
Constant Current
Driver
0
0
LOD
0
1
1
0
OUT0
Delay
x0
On/Off Register
0
Max. OUTn
Current
IREF
0
7−bit DC Register
6
On/Off
Input
BLANK
Shift
Register
1
16
Constant Current
Driver
LOD
OUT1
16
Delay
x1
1
15
On/Off Register
112
0
7
7−bit DC Register
13
LED Open
Detection
(LOD)
DC Input
Shift
Register
BLANK
Temperature
Error Flag
(TEF)
BLANK
Constant Current
Driver
15
1
0
LOD
OUT15
Delay
x15
15
111
On/Off Register
XERR
105
7−bit DC Register
111
0
1
MODE
SOUT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
TLC5923
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TA
Package
Part Number(1)
TLC5923DAP
TLC5923RHB
32-pin, HTSSOP, PowerPAD™
32-pin, 5 mm x 5 mm QFN
–40°C to 85°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
(1) (2)
ABSOLUTE MAXIMUM RATINGS
TLC5923
–0.3 to 6
90
UNIT
VCC Supply voltage(2)
V
mA
V
IO
VI
Output current (dc)
Input voltage range(2)
I(OUT0) to I(OUT15)
V(BLANK), V(XLAT), V(SCLK), V(SIN), V(MODE), V(IREF)
V(SOUT), V(XERR)
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
-0.3 to 18
2
V
VO
Output voltage range(2)
V(OUT0) to V(OUT15)
V
HBM (JEDEC JESD22-A114, Human Body Model)
CDM (JEDEC JESD22-C101, Charged Device Model)
kV
ESD rating
500
V
Tstg
Storage temperature range
–40 to 150
42.54
°C
HTSSOP (DAP)
QFN (RHB)
mW/°C
mW/°C
Power dissipation rating at (or
above) TA = 25°C(3)
27.86
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) See SLMA002 for more information about PowerPAD™
RECOMMENDED OPERATING CONDITIONS—DC Characteristics
MIN
NOM
MAX
5.5
UNIT
V
VCC Supply voltage
3
VO
VIH
VIL
IOH
IOL
Voltage applied to output, (Out0 - Out15)
17
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
0.8 VCC
GND
VCC
0.2 VCC
–1
V
V
VCC = 5 V at SOUT
VCC = 5 V at SOUT, XERR
OUT0 to OUT15
mA
mA
mA
°C
1
IOLC Constant output current
TA
80
Operating free-air temperature range
-40
85
2
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: TLC5923
TLC5923
www.ti.com
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
RECOMMENDED OPERATING CONDITIONS—AC Characteristics
VCC = 3 V to 5.5 V, TA = -40°C to 85°C (unless otherwise noted)
MIN TYP
MAX
UNIT
MHz
ns
fSCLK
Clock frequency
SCLK
30
twh0, twl0 CLK pulse duration
SCLK=H/L
16
20
10
10
10
10
10
10
10
10
10
10
twh1
tsu0
tsu1
tsu1a
tsu2
tsu3
th0
XLAT pulse duration
Setup time
XLAT=H
SIN to SCLK↑(1)
ns
SLCK↑ to XLAT↓(dot correction data)
SCLK↑to XLAT↑ (ON/OFF data)
MODE↑↓ to SCLK↑
MODE↑↓ to XLAT↑
ns
ns
SCLK↑ to SIN
th1
XLAT ↓ to SCLK↑ (dot correction data)
XLAT↑ to SCLK↑ (ON/OFF data)
SCLK↑to MODE↑↓
th1a
th2
Hold time
th3
XLAT↓ to MODE↑↓
(1) "↑" and "↓" indicates a rising edge, and a falling edge respectively.
ELECTRICAL CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
High-level output voltage
Low-level output voltage
Input current
TEST CONDITIONS
MIN TYP
MAX UNIT
VOH
VOL
II
IOH = –1 mA, SOUT
VCC –0.5
V
IOL = 1 mA, SOUT
0.5
1
V
VI = VCC or GND, BLANK, XLAT, SCLK, SIN, MODE
No data transfer, All output OFF, VO = 1 V, R(IREF) = 10 kΩ
–1
μA
6
No data transfer, All output OFF, VO = 1 V, R(IREF) = 1.3
kΩ
15
32
ICC
Supply current
mA
Data transfer 30 MHz, All output ON, VO = 1 V,
R(IREF) = 1.3 kΩ
Data transfer 30 MHz, All output ON, VO = 1 V,
R(IREF) = 600 Ω
36
80
65(1)
90
IOLC
ILO0
ILO1
Constant sink current
Leakage output current
All output ON, VO = 1 V, R(IREF) = 600 Ω
70
mA
μA
μA
All output OFF, VO = 15 V, R(IREF) = 600 Ω, OUT0 to
OUT15
0.1
VXERR = 5.5 V, No TEF and LOD
10
ΔIOLC0 Constant sink current error
All output ON, VO = 1 V, R(IREF) = 600 Ω, OUT0 to OUT15
±1%
±4%
±4%
device to device, averaged current from OUT0 to OUT15,
R(IREF) = 600 Ω
ΔIOLC1 Constant sink current error
±8.5%
±4
All output ON, VO = 1 V, R(IREF) = 600 Ω,
OUT0 to OUT15, VCC = 3 V to 5.5 V
ΔIOLC2 Line regulation
ΔIOLC3 Load regulation
±1
±2
%/V
%/V
All output ON, VO = 1 V to 3 V, R(IREF) = 600 Ω,
OUT0 to OUT15
±6
T(TEF) Thermal error flag threshold
V(LOD) LED open detection threshold
V(IREF) Reference voltage output
Junction temperature, rising temperature(2)
150
160
0.3
180
0.4
°C
V
R(IREF) = 600 Ω
1.20 1.24
1.28
V
(1) Measured at device start-up temperature. Once the IC is operating (self heating), lower ICC values will be seen. See Figure 18.
(2) Not tested. Specified by design.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: TLC5923
TLC5923
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
www.ti.com
DISSIPATION RATINGS
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
PACKAGE
TA < 25°C
32-pin HTSSOP with PowerPAD(1)
soldered
32-pin HTSSOP with PowerPAD(1)
unsoldered
5318 mW
42.54 mW/°C
22.56 mW/°C
27.86 mW/°C
3403 mW
1805 mW
2228 mW
2765 mW
1466 mW
1811 mW
2820 mW
3482 mW
32-pin QFN
(1) The PowerPAD is soldered to the PCB with a 2 oz. copper trace. See SLMA002 for further information.
SWITCHING CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
(1)
tr0
SOUT(see
)
16
ns
Rise time
(2)
tr1
OUTn, VCC = 5 V, TA = 60°C, DCx = 7F (see
)
10
10
30
16
(1)
tf0
SOUT (see
)
Fall time
ns
(2)
tf1
OUTn, VCC = 5 V, TA = 60°C, DCx = 7F (see
)
30
(3) (4)
tpd0
tpd1
tpd2
tpd3
tpd4
tpd5
td
SCLK↑ to SOUT↑ ↓ (see
)
30
(3)
MODE↑↓ to SOUT↑↓ (see
)
30
BLANK ↑↓ to OUT0↑↓ (see (5)), Sink current On/Off
60
Propagation delay time
Output delay time
ns
ns
(5)
XLAT↑ to OUT0↑↓ (see
OUTn↑↓ to XERR↑↓ (see
)
60
(6)
)
1000
1000
30
(7)
XLAT↑ to IOUT(dot-correction) (see
)
(5)
OUTn↑ to OUT(n+1)↑, OUTn ↓ to OUT(n+1)↓ (see
)
14
22
(1) See Figure 4. Defined as from 10% to 90%
(2) See Figure 5. Defined as from 10% to 90%
(3) See Figure 4, Figure 14
(4) "↑" and "↓" indicates a rising edge, and a falling edge respectively.
(5) See Figure 5 and Figure 14
(6) See Figure 5, Figure 6, and Figure 14
(7) See Figure 5
RHB PACKAGE
(TOP VIEW)
DAP PACKAGE
(TOP VIEW)
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
BLANK
XLAT
SCLK
SIN
PGND
OUT0
OUT1
PGND
OUT2
OUT3
OUT4
OUT5
PGND
OUT6
OUT7
VCC
IREF
2
3
MODE
XERR
SOUT
PGND
OUT15
OUT14
PGND
OUT13
OUT12
OUT11
OUT10
PGND
OUT9
OUT8
XERR 25
MODE 26
IREF 27
VCC 28
16 OUT10
15 PGND
14 OUT9
13 OUT8
12 OUT7
11 OUT6
10 PGND
4
5
6
THERMAL
PAD
7
8
GND 29
BLANK 30
XLAT 31
SCLK 32
9
(QFN)
10
11
12
13
14
15
16
9
OUT5
4
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: TLC5923
TLC5923
www.ti.com
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
TSSOP
QFN
Blank (Light OFF). When BLANK=H, All OUTn outputs are forced OFF. When BLANK=L,
ON/OFF of OUTn outputs are controlled by input data.
BLANK
2
30
I
GND
IREF
1
29
27
Ground
31
I/O Reference current terminal
Mode select. When MODE=L, SIN, SOUT, SCLK, XLAT are connected to ON/OFF control
logic. When MODE=H, SIN, SOUT, SCLK, XLAT are connected to dot-correction logic.
MODE
30
26
I
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
7
8
3
4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
10
6
11
7
12
8
13
9
15
11
12
13
14
16
17
18
19
21
22
2, 5, 10,
16
17
18
20
21
22
23
25
26
6, 9, 14,
19, 24, 27 15, 20, 23
PGND
SCLK
Power ground
Data shift clock. Note that the internal connections are switched by MODE (pin #30). At
SCLK↑, the shift-registers selected by MODE shift the data.
4
32
I
SIN
5
1
I
Data input of serial I/F
Data output of serial I/F
Power supply voltage
SOUT
VCC
28
32
24
28
O
Error output. XERR is open drain terminal. XERR transistions from H to L when LOD or TEF
detected.
XERR
29
25
O
I
Data latch signal. When MODE = L (ON/OFF data mode), XLAT is an edge-triggered latch
signal of ON/OFF registers. The serial data in ON/OFF input shift registers is latched into the
ON/OFF registers at the rising edge of XLAT. When MODE = H (DC data mode), XLAT is a
level-triggered latch signal of dot correction registers. The serial data in DC input shift
registers is written into dot correction registers when XLAT = H. The data in dot correction
registers is held constant when XLAT = L.
XLAT
3
31
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: TLC5923
TLC5923
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
www.ti.com
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
(Note: Resistor values are equivalent resistance and not tested).
VCC
400 W
INPUT
GND
Figure 1. Input Equivalent Circuit (BLANK, XLAT, SCLK, SIN, MODE)
10 W
SOUT
GND
Figure 2. Output Equivalent Circuit
20 W
XERR
GND
Figure 3. Output Equivalent Circuit (XERR)
PARAMETER MEASUREMENT INFORMATION
SOUT
15 pF
Figure 4. Test Circuit for tr0, tf0, tpd0, tpd1
51 Ω
OUTn
15 pF
Figure 5. Test Circuit for tr1, tf1, tpd2, tpd3, tpd5, td
6
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: TLC5923
TLC5923
www.ti.com
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
PARAMETER MEASUREMENT INFORMATION (continued)
470 kΩ
XERR
Figure 6. Test Circuit for tpd4
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: TLC5923
TLC5923
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
www.ti.com
PRINCIPLES OF OPERATION
Setting Maximum Channel Current
The maximum output current per channel is set by a single external resistor, R(IREF), which is placed between
IREF and GND. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of 1.24V. The
maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of 40. The
maximum output current per channel can be calculated by Equation 1:
V
IREF
I
+
40
MAX
R
IREF
(1)
where:
VIREF = 1.24V typ.
RIREF = User selected external resistor (RIREF should not be smaller than 600 Ω)
Figure 15 shows the maximum output current, IOLC, versus R(IREF) . In Figure 15, R(IREF) is the value of the
resistor between IREF terminal to ground, and IOLC is the constant output current of OUT0,.....OUT15. A variable
power supply may be connected to the IREF pin through a resistor to change the maximum output current per
channel. The maximum output per channel is 40 times the current flowing out of the IREF pin. The maximum
current from IREF equals 1.24V/600Ω.
Setting Dot-Correction
The TLC5923 has the capability to fine adjust the current of each channel, OUT0 to OUT15 independently. This
is also called dot correction. This feature is used to adjust the brightness deviations of LED connected to the
output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 7-bit word. The channel
output can be adjusted in 128 steps from 0% to 100% of the maximum output current IMAX. Dot correction for all
channels must be entered at the same time. Equation 2 determines the output current for each OUTn:
I
DC
n
MAX
+
I
Outn
where:
127
(2)
IMax = the maximum programmable current of each output
DCn = the programmed dot-correction value for output n (DCn = 0, 1, 2 ...127)
n = 0, 1, 2 ... 15
Dot correction data are entered for all channels at the same time. The complete dot correction data format
consists of 16 x 7-bit words, which forms a 112-bit wide serial data packet. The channel data is put one after
another. All data is clocked in with MSB first. Figure 7 shows the DC data format. The DC15.6 in Figure 7 stands
for the 6th most significant bit for output 15.
MSB
111
LSB
0
105
104
7
6
DC 15.6
DC 15.0
DC 14.6
DC 1.0
DC 0.6
DC 0.0
DC OUT15
DC OUT0
DC OUT14 − DC OUT1
Figure 7. DC Data Format
To input data into dot correction register, MODE must be set to high. The internal input shift register is then set to
112 bit width. After all serial data is clocked in, a high level pulse of XLAT signal connects the serial data to the
dot correction register. The dot correction registers are level-triggered latches of XLAT signal. The serial data is
latched into the dot correction registers when XLAT goes low. The data in dot correction registers is held
constant when XLAT is low. BLANK signal does not need to be high to latch in new data. Since XLAT is a level-
triggered signal when MODE is high, SCLK and SIN must not be changed while XLAT is high. (Figure 14).
8
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: TLC5923
TLC5923
www.ti.com
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
Output Enable
All OUTn channels of TLC5923 can switched off with one signal. When BLANK signal is set to high, all OUTn are
disabled, regardless of On/Off status of each OUTn. When BLANK is set to low, all OUTn work under normal
conditions.
Table 1. BLANK Signal Truth Table
BLANK
LOW
OUT0 - OUT15
Normal condition
Disabled
HIGH
Setting Channel On/Off Status
All OUTn channels of TLC5923 can be switched on or off independently. Each of the channels can be
programmed with a 1-bit word. On/Off data are entered for all channels at the same time. The complete On/Off
data format consists of 16 x 1-bit words, which form a 16-bit wide data packet. The channel data is put one after
another. All data is clocked in with MSB first. Figure 8 shows the On/Off data format.
MSB
15
LSB
0
On/Off On/Off On/Off
OUT15 OUT14 OUT13
On/Off On/Off On/Off
OUT0
OUT2
OUT1
On/Off Data
Figure 8. On/Off Data Format
To input On/Off data into On/Off register MODE must be set to low. The internal input shift register is then set to
16 bit width. After all serial data is clocked in, a rising edge of XLAT is used to latch data into the On/Off register.
The ON/OFF register is an edge-triggered latch of XLAT signal. BLANK signal does not need to be high to latch
in new data. Figure 14 shows the On/Off data input timing chart.
Delay Between Outputs
The TLC5923 has graduated delay circuits between outputs. These delay circuits can be found in the constant
current block of the device (see Functional Block Diagram). The fixed delay time is 20 ns (typical), OUT0 has no
delay, OUT1 has 20 ns delay, OUT2 has 40 ns delay, etc. This delay prevents large inrush currents, which
reduce power supply bypass capacitor requirements when the outputs turn on. The delay works during switch on
and switch off of each output channel. LEDs that have not turned on before BLANK is pulled high will still turn on
and off at the determined delayed time regardless of the state of BLANK. Therefore, every LED will be
illuminated for the amount of time BLANK is low.
Serial Interface Data Transfer Rate
The TLC5923 includes a flexible serial interface, which can be connected to microcontroller or digital signal
processor. Only 3 pins are in required to input data into the device. The rising edge of SCLK signal shifts the
data from SIN pin to internal shift register. After all data is clocked in, a rising edge of XLAT latches the serial
data to the internal registers. All data is clocked in with MSB first. Multiple TLC5923 devices can be cascaded by
connecting SOUT pin of one device with SIN pin of following device. The SOUT pin can also be connected to
controller to receive LOD information from TLC5923.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: TLC5923
TLC5923
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
www.ti.com
V
V
V
V
V
(LED)
CC
(LED)
(LED)
(LED)
100 k
OUT0
OUT15
SOUT
OUT0
OUT15
SIN
SIN
SIN
XERR
SCLK
XLAT
SOUT
V
XERR
SCLK
XLAT
MODE
BLANK
XERR
SCLK
XLAT
V
CC
CC
100 nF
100 nF
IREF
TLC5923
IC 0
TLC5923
IC n
Controller
MODE
BLANK
MODE
BLANK
IREF
SOUT
5
Figure 9. Cascading Devices
Figure 9 shows a example application with n cascaded TLC5923 devices connected to a controller. The
maximum number of cascaded TLC5923 devices depends on application system and data transfer rate.
Equation 3 calculates the minimum data input frequency needed.
f_(SCLK) + 112 f_(update) n
(3)
where:
f_(SCLK): The minimum data input frequency for SCLK and SIN.
f_(update): The update rate of the whole cascaded system.
n: The number of cascaded TLC5923 devices.
Operating Modes
The TLC5923 has different operating modes depending on MODE signal. Table 2 shows the available operating
modes. The values in the input shift registers, DC register and On/Off register are unknown just after power on.
The DC and On/Off register values should be properly stored through the serial interface before starting the
operation.
Table 2. TLC5923 Operating Modes Truth Table
MODE SIGNAL
LOW
INPUT SHIFT REGISTER
MODE
16 bit
On/Off Mode
HIGH
112 bit
Dot Correction Data Input Mode
10
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: TLC5923
TLC5923
www.ti.com
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
Error Information Output
The open-drain output XERR is used to report both of the TLC5923 error flags, TEF and LOD. During normal
operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is
pulled up to VCC through a external pullup resistor. If TEF or LOD is detected, the internal transistor is turned on,
and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and pulled
up to VCC with a single pullup resistor. This reduces the number of signals needed to report a system error.
To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.
Table 3. XERR Truth Table
CONDITION
BLANK
ERROR INFORMATION
XERR
TEMPERATURE
TJ < T(TEF)
OUTn VOLTAGE
TEF
L
LODn
H
Don't Care
L
High-Z(1)
TJ > T(TEF)
H
L
TJ < T(TEF)
L
OUTn > V(LOD)
OUTn < V(LOD)
OUTn > V(LOD)
OUTn < V(LOD)
L
L
H
L
High-Z
L
L
L
TJ > T(TEF)
H
H
(1) Note: High-Z indicates high impedance
TEF: Thermal Error Flag
The TLC5923 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If
the junction temperature exceeds the threshold temperature T(TEF) (160°C typical), TEF becomes H and XERR
pin goes to low level. When the junction temperature becomes lower than the threshold temperature, TEF
becomes L and XERR pin becomes high impedance.
LOD: LED-Open Detection
The TLC5923 has an LED-open detector to detect broken or disconnected LEDs, which should be connected to
the output. The LED-open detector pulls the XERR pin down to GND when the LED open is detected. An open
LED is detected when the following three conditions are met:
1. BLANK is low
2. On/Off data is high
3. The voltage of OUTn is less than 0.3 V (typical)
The LOD status of each output can also be read out from the SOUT pin. Figure 10 shows the LOD data format.
Table 4 shows the LOD truth table.
MSB
15
LSB
0
LOD
OUT15 OUT14 OUT13
LOD
LOD
LOD
OUT2
LOD
OUT1
LOD
OUT0
LOD Data
Figure 10. LOD Data Format
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: TLC5923
TLC5923
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
www.ti.com
Table 4. LOD Data Truth Table
LED
Good
Good
Bad
ON/OFF
On
LOD BIT
0
0
1
0
Off
On
Bad
Off
Key Timing Requirements to Reading LOD
•
LOD status flag
The LOD status flag becomes active if the output voltage is <0.3 V (typical) when the output sink current turns
on. There is a 1-µs time delay from the time the output sink current turns on until the time the LOD status flag
becomes valid. The timing for each channel’s LOD status to become valid is shifted by the 30 ns channel-to-
channel turn-on time. After BLANK goes low, OUT0 LOD status is valid when tpd2 + tpd4 = 60 ns + 1 µs =
1.06 µs. OUT1 LOD status is valid when tpd2 + tpd4 + td = 60 ns + 1 µs + 30 ns = 1.09 µs. OUT3 LOD status
is valid when tpd2 + tpd4 + 2*td = 1.12 µs, and so on.
•
•
LOD internal latch
The TLC5923 has an internal latch to hold each channel’s LOD status flag information, as shown in
Figure 11. When MODE is low, the LOD status information is latched into this latch on the rising edge of
XLAT. This is an edge-triggered latch. To ensure that a valid LOD status flag is latched, BLANK must be low
when XLAT goes high. After the rising edge of XLAT, changes in the status flags do not affect the values in
the LOD latch.
Loading LOD data to the input shift register
The LOD data must be transferred to the input shift register before it is available to be clocked out of SOUT.
The internal shift register has a set/reset function that is controlled by the LOD internal latch. While XLAT is
high, the LOD internal latch holds the input shift register in either set or reset, depending on the value in the
latch. This effectively puts the LOD data into the input shift register where it remains as long as XLAT is high.
The values in the input shift register are unaffected by any other signals, including SIN and SCLK while XLAT
is high. During this time, the status of OUT15 is present on SOUT.
•
•
Latching LOD data into the internal shift register
While XLAT is high, the status of OUT15 is present on SOUT. When XLAT transitions low, all data is latched
into the Input shift register, and the LOD internal latch is disconnected from the internal shift register.
Clocking LOD data out of SOUT
While XLAT is low and SCLK is low, the status of OUT15 is on SOUT. On the next rising edge of SCLK, the
status of OUT14 shifts to SOUT. Each subsequent rising edge of SCLK shifts the LOD data out of SOUT.
XLAT must stay low until all LOD data is clocked out of SOUT. See Shifting the LOD Data Out section for
more details.
12
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: TLC5923
TLC5923
www.ti.com
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
16bit LOD Status Flags
16bit LOD Internal Latch
SOUT
SIN
Input Shift Register
(FIFO Register)
GS Register
Figure 11. LOD Flags and Latches
Shifting the LOD Data Out
SOUT outputs the LOD data as shown in Figure 12, where:
•
XLAT rising edge
Holds the LOD status flag. SOUT outputs LOD OUT15 data. BLANK must be low.
XLAT = H
•
Sets or resets the input shift register depending on each LOD data.
Set/Reset function is higher priority than shifting the register value. If XLAT is high and the SCLK pin is
pulsed, all LOD data are kept in the shift register and SOUT keeps the LOD OUT15 data.
•
•
XLAT = L
Ready to shift out LOD data by SCLK. SOUT contains LOD OUT15 data at this time. BLANK can be high or
low during this time.
SCLK rising edge
SOUT outputs LOD OUT14 at the first SCLK rising edge. SOUT outputs LOD OUT13 at the second SCLK
rising edge, and continues to output the next LOD data at each SCLK rising edge.
XLAT
SCLK
LOD
LOD
LOD
LOD
SOUT
OUT15
OUT14
OUT13
OUT12
Figure 12. The LOD Data of SOUT
Figure 13 shows the timing chart of reading LOD data.
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: TLC5923
TLC5923
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
www.ti.com
At the rising edge of XLAT while BLANK=L, LOD status is latched into
the internal edge-triggered register.
MODE
When XLAT=H, the internal edge-triggered register
sets or resets the input shift registe. r
XLAT
SCLK
SIN
SOUT
1510ns max
1510ns max
BLANK
tpd2: 60ns max
tpd2: 60ns max
OUT0
LED open
OUT15
td x 15 = 450ns max
td x 15 = 450ns max
XERR
tpd4: 1000ns max
>1000ns
tpd4: 1000ns max
>1000ns
Figure 13. Timing Chart of Reading LOD Data
14
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: TLC5923
TLC5923
www.ti.com
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
Figure 14. Timing Chart Example for ON/OFF Setting to Dot-Correction
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: TLC5923
TLC5923
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
www.ti.com
TYPICAL CHARACTERISTICS
REFERENCE RESISTOR
vs
OUTPUT CURRENT
OUTPUT CURRENT
vs
REQUIRED OUTPUTn VOLTAGE
100 k
10 k
1 k
100
90
49.6 k
V
= 1 V
Outn
DC = 127
80
70
60
9.92 k
4.96 k
I
I
= 60 mA
MAX
50
40
30
20
10
0
2.48 k
= 40 mA
= 20 mA
MAX
1.65 k
1.24 k
992
827
709
I
MAX
100
0
0.50
1
1.50
2
2.50
3
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
I
− Output Current − A
V
O
− Required Output Voltage − V
OLC
Figure 15.
Figure 16.
POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
6 k
5 k
4 k
3 k
2 k
1 k
0
70
60
50
40
30
20
TLC5923DAP
PowerPAD Soldered
TLC5923RHB
TLC5923DAP
PowerPAD Unsoldered
10
0
−40
−20
0
20
40
60
80
100
−50 −30 −10 10 30 50 70 90 110 130 150
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
A. Data Transfer = 30 MHz / All Outputs, ON/VO = 1 V / RIREF = 600
Ω / AVDD = 5 V
Figure 17.
Figure 18.
Power Rating – Free-Air Temperature
Figure 17 shows total power dissipation. Figure 18 shows supply current versus free-air temperature.
16
Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: TLC5923
TLC5923
www.ti.com
SLVS550B –DECEMBER 2004–REVISED JANUARY 2013
REVISION HISTORY
NOTE: Page numbers of previous versions may differ from current version.
Changes from Revision A (November 2005) to Revision B
Page
•
Corrected device number from "TLC4923RHB" to "TLC5923RHB" in Ordering Info table. ................................................. 2
Copyright © 2004–2013, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: TLC5923
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2013
PACKAGING INFORMATION
Orderable Device
TLC5923DAP
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
VQFN
DAP
32
32
32
32
32
32
32
32
46
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TLC5923
TLC5923DAPG4
TLC5923DAPR
TLC5923DAPRG4
TLC5923RHBR
TLC5923RHBRG4
TLC5923RHBT
TLC5923RHBTG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DAP
DAP
DAP
RHB
RHB
RHB
RHB
46
Green (RoHS
& no Sb/Br)
TLC5923
TLC5923
TLC5923
2000
2000
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TLC
5923
VQFN
Green (RoHS
& no Sb/Br)
TLC
5923
VQFN
Green (RoHS
& no Sb/Br)
TLC
5923
VQFN
250
Green (RoHS
& no Sb/Br)
TLC
5923
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jul-2013
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC5923RHBR
TLC5923RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC5923RHBR
TLC5923RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
TLC5923RHBR
16-channel LED driver with 20Mhz data transfer rate with dot correctionn and full diagnose 32-VQFN -40 to 85
TI
TLC5923RHBT
16-channel LED driver with 20Mhz data transfer rate with dot correctionn and full diagnose 32-VQFN -40 to 85
TI
©2020 ICPDF网 联系我们和版权申明