TLC320AD50IPT [TI]
SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION; 采用主从功能Σ-Δ模拟接口电路
| 型号： | TLC320AD50IPT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| 文件： | 总53页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Manual
2000
Mixed Signal Products
SLAS131D
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
Contents
Section
1
Title
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Definitions and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Register Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
2
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2.1 Device Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
2.1.10
2.1.11
Operating Frequencies and Filter Control . . . . . . . . . . . . . . 2–1
ADC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
DAC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Sigma-Delta DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Analog and Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
FIR Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2.2
Reset and Power-Down Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2.2.1
2.2.2
Software and Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Software and Hardware Power Down . . . . . . . . . . . . . . . . . . 2–6
2.3
2.4
Master Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Data Out (DOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
2.4.1
2.4.2
Data Out, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Data Out, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
2.5
2.6
2.7
Data In (DIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
FC (Hardware Secondary Communication Request) . . . . . . . . . . . . . 2–7
Frame-Sync Function for TLC320AD50C . . . . . . . . . . . . . . . . . . . . . . . 2–7
2.7.1
2.7.2
2.7.3
2.7.4
Frame Sync (FS) Function, Master Mode . . . . . . . . . . . . . . 2–8
Frame Sync (FS) Function,Slave Mode . . . . . . . . . . . . . . . . 2–8
Frame-Sync Delayed (FSD) Function, Master Mode . . . . . 2–9
Frame-Sync Delayed (FSD), Slave Mode . . . . . . . . . . . . . . 2–9
2.8
2.9
Frame-Sync Function for TLC320AD52C . . . . . . . . . . . . . . . . . . . . . . . 2–11
Multiplexed Analog Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
iii
2.9.1
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
3
Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3.1
3.2
Primary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Secondary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3.2.1
3.2.2
Hardware Secondary Serial Communication Request . . . . 3–3
Software Secondary Serial Communication Request . . . . 3–3
3.3
3.4
3.5
Conversion Rate Versus Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Phone Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
DIN and DOUT Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
3.5.1
Primary Serial Communication DIN and DOUT
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
3.5.2
Secondary Serial Communication DIN and DOUT
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
4
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.1
Absolute Maximum Ratings Over Operating Free-Air
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4.2.1
4.2.2
Recommended Operating Conditions, DV
Recommended Operating Conditions, DV
= 5 V . . . . . . 4–1
= 3 V . . . . . . 4–1
DD
DD
4.3
Electrical Characteristics Over Recommended Operating
Free-Air Temperature Range, DV = 5 V, R = 600 Ω . . . . . . . . . . . 4–2
DD
L
4.3.1
Digital Inputs and Outputs, MCLK = 8.192 MHz,
f = 8 kHz, DV = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
s
DD
4.3.2
Digital Inputs and Outputs, MCLK = 8.192 MHz,
f = 8 kHz, DV = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
s
DD
4.3.3
4.3.4
ADC Channel, MCLK = 8.192 MHz, f = 8 kHz . . . . . . . . . . 4–2
s
ADC Dynamic Performance, MCLK = 8.192 MHz,
f = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
s
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
ADC Channel Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 4–3
DAC Path Filter, MCLK = 8.192 MHz, f = 8 kHz . . . . . . . . 4–3
s
DAC Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
DAC Channel Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Power Supply, AV
= DV
= 5 V, No Load . . . . . . . . . . . 4–5
DD
DD
Power-Supply Rejection, AV
= DV
= 5 V . . . . . . . . . . 4–5
DD
DD
4.4
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
Master Mode Timing Requirements . . . . . . . . . . . . . . . . . . . 4–5
Slave Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . 4–6
Master Mode Switching Characteristics . . . . . . . . . . . . . . . . 4–6
Slave Mode Switching Characteristics . . . . . . . . . . . . . . . . . 4–6
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
5
6
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6.1
6.2
Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
iv
6.3
6.4
Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
7
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
Appendix A – Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
v
List of Illustrations
Figure
Title
Page
2–1 Timing Sequence of ADC Channel (Primary Communication Only) . . . . . . 2–2
2–2 Timing Sequence of ADC Channel (Primary and Secondary
Communication) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2–3 Timing Sequence of DAC Channel (Primary Communication Only) . . . . . . 2–3
2–4 Timing Sequence of DAC Channel (Primary and Secondary
Communication) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
2–5 Register 1 Read Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2–6 Register 1 Write Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2–7 Internal Power-Down Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2–8 Master Device Frame-Sync Signal With Primary and Secondary
Communications (No Slaves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
2–9 Master Device Frame-Sync Signal With Primary and Secondary
Communications (With 1 Slave Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
2–10 Master Device FS and FSD Output When FSD Register (D0–D5,
Control 3 Register) is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2–11 Master Device FS and FSD Output After Control 3 Register Is
Programmed (One Slave Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2–12 Master With Slaves (To DSP Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
2–13 Master-Slave Frame-Sync Timing After A Delay Has Been
Programmed Into The FSD Register (D0–D5 of Control 3 Register) . . . 2–10
2–14 Master Device FS and FSD Output After Control 3 Register
Is Programmed With 49H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2–15 RC Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2–16 INP and INM Internal Self-Biased (2.5 V) Circuit . . . . . . . . . . . . . . . . . . . . . 2–12
2–17 Differential Output Drive (Ground Referenced) . . . . . . . . . . . . . . . . . . . . . . . 2–12
2–18 Digital Input Code vs Analog Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . 2–12
3–1 Primary Serial Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3–2 Hardware and Software Methods to Make a Secondary Request . . . . . . . . . 3–2
3–3 FS Output When Hardware Secondary Serial Communication Is Requested
Only Once (No Slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3–4 FS Output When Hardware Secondary Serial Communication Is Requested
Only Once (Three Slaves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3–5 FS Output During Software Secondary Serial Communication Request
(No Slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3–6 Phone Mode Timing When Phone Mode Is Enabled . . . . . . . . . . . . . . . . . . . 3–4
vi
3–7 Primary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . . . . 3–4
3–8 Secondary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . . 3–5
5–1 Master FS and FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5–2 Slave FS to FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5–3 Master/Slave SCLK to FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5–4 Serial Communication Timing (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
5–5 Serial Communication Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
5–6 ADC Channel Filter Response (MCLK = 8.192 MHz, f = 8 kHz) . . . . . . . . 5–3
s
5–7 ADC Channel Filter Passband Ripple (MCLK = 8.192 MHz, f = 8 kHz) . . 5–3
s
5–8 DAC Channel Filter Response (MCLK = 8.192 MHz, f = 8 kHz) . . . . . . . . 5–4
s
5–9 DAC Channel Filter Passband Ripple (MCLK = 8.192 MHz, f = 8 kHz) . . 5–4
s
7–1 Master Device and Slave Device Connections (to DSP Interface) . . . . . . . 7–1
7–2 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2
List of Tables
Table
Title
Page
3–1 Least Significant Bit Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
6–1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6–2 Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6–3 Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
6–4 Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
6–5 Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
vii
viii
1 Introduction
The TLC320AD50C, TLC320AD50I, and TLC320AD52C provide high-resolution signal conversion from
digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology. This device
consists of a pair of 16-bit synchronous serial conversion paths (one for each direction) and includes an interpolation
filter before the DAC and a decimation filter after the ADC. Other overhead functions on the chip include timing
(sample rate, FSD delay) and control (programmable gain amplifier, PLL, communication protocol, etc.). The
sigma-delta architecture produces high resolution A/D and D/A conversion at a low system cost.
Programmable functions of this device can be selected through the serial interface. Options include reset, power
down, communications protocol, signal sampling rate, gain control, and system test modes (see section 6). The
TLC320AD50C and TLC320AD52C are characterized for operation from 0°C to 70°C, and the TLC320AD50I is
characterized for operation from –40°C to 85°C.
1.1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
General-purpose analog interface circuit for V.34+ modem and business audio applications
16-bit oversampling sigma-delta ADC and DAC
Serial port interface
Typical 89-dB SNR (signal-to-noise ratio) for ADC and DAC
Typical 90-dB THD (signal to total harmonic distortion) for ADC and DAC
Typical 88-dB dynamic range
Test mode that includes a digital loopback test and analog loopback test
Programmable A/D and D/A conversion rate
Programmable input and output gain control
Maximum conversion rate: 22.05 kHz
Single 5-V power supply voltage or 5-V analog and 3-V digital power supply voltage
Power dissipation (P ) of 120 mW rms typical in the operating mode
D
Hardware power-down mode to 7.5 mW
Internal reference voltage (V
)
ref
Differential architecture throughout device
TLC320AD50C/I can support up to three slave devices; TLC320AD52C can support one slave
2s complement data format
ALTDATA terminal provides data monitoring
Monitor amplifier to monitor input signals
On-chip phase locked loop (PLL)
1–1
1.2 Functional Block Diagram
5
INP
6
27
11
MONOUT
DOUT
INM
MUX
PGA
Sigma
-Delta
ADC
Decimation
Filter
Buffer
PGA
3
AUXP
MUX
4
Digital
Loopback
AUXM
1
REFP
REFM
Analog
Loopback
V
ref
2
23
12
OUTP
Low
Pass
Filter
Sigma
-Delta
DAC
DIN
Interpolation
Filter
22
21
14
M/S
FSD
24
OUTM
PGA
Buffer
ALTDATA
FC
FS
17
20
19
13
16
PWRDWN
15
SCLK
RESET
28
FLAG
FILT
Internal
Clock Circuit
I/O
Control
18
÷N
MCLK
PLL (x4)
26
25
10
9
7
8
DV
DV
AV
DD(PLL)
AV
AV
AV
DD
SS
NOTE: Pin numbers shown are for the DW package.
DD
SS(PLL)
SS
1–2
1.3 Terminal Assignments
DW PACKAGE
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REFP
REFM
AUXP
AUXM
INP
FILT
2
MONOUT
3
AV
AV
SS
DD
4
5
OUTM
OUTP
M/S
6
INM
7
AV
DD(PLL)
8
AV
FSD
SS(PLL)
9
DV
FS
DD
10
11
12
13
14
DV
SCLK
MCLK
FC
SS
DOUT
DIN
FLAG
PWRDWN
RESET
ALTDATA
PT PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
OUTM
OUTP
NC
NC
NC
1
INP
INM
NC
2
3
4
NC
5
AV
DD(PLL)
NC
NC
NC
6
7
AV
SS(PLL)
NC
M/S
FSD
FS
SCLK
MCLK
8
9
NC
NC
10
11
12
DV
DD
DV
SS
13 14 15 16 17 18 19 20 21 22 23 24
NC – No internal connection
1–3
1.4 Ordering Information
PACKAGE
SMALL OUTLINE
PLASTIC DIP
(DW)
T
A
QUAD FLAT PACK
(PT)
TLC320AD50CDW
TLC320AD52CDW
TLC320AD50CPT
TLC320AD52CPT
0°C to 70°C
–40°C to 85°C
TLC320AD50IDW
1.5 Terminal Functions
TERMINAL
I/O
DESCRIPTION
NO. NO.
NAME
PT
DW
ALTDATA
AUXM
17
14
I
I
I
Alternate data. ALTDATA signals are routed to DOUT during secondary communication if the phone mode
is enabled using control 2 register.
48
47
4
3
Invertinginputtoauxiliaryanaloginput. AUXMrequiresanexternalsingle-poleantialiasfilterwithalowoutput
impedance and should be tied to AV
SS
if not used.
AUXP
Noninverting input to auxiliary analog input. AUXP requires an external single-pole antialias filter with a low
output impedance and should be tied to AV if not used.
SS
AV
AV
AV
AV
37
5
25
7
I
I
I
I
I
Analog ADC power supply (5 V only) (see Note 1)
Analog power supply for the internal PLL (5 V only) (see Note 1)
Analog ground (see Note 1)
DD
DD(PLL)
SS
39
7
26
8
Analog ground for the internal PLL (see Note 1)
SS(PLL)
DIN
15
12
Datainput. DIN receives the DAC input data and register data from the external DSP (digital signal processor)
and is synchronized to SCLK and FS. Data is latched at the falling edge of SCLK when FS is low. DIN is at
high impedance when FS is not active.
DOUT
14
11
O
Data output. DOUT transmits the ADC output bits and register data, and is synchronized to SCLK. Data is
sent out at the rising edge of SCLK when FS is low. DOUT is at high impedance when FS is not activated.
When configured as a master, DOUT is active only during the appropriate time slot. DOUT is in high
impedance during the frame syncs for the slaves.
DV
DV
FC
11
12
23
9
I
I
I
Digital power supply (5 V or 3 V) (see Note 1)
Digital ground (see Note 1)
DD
SS
10
17
Hardware secondary communication request. When FC is set to high, a secondary communication, followed
by the primary communication, will occur to transfer data between this device and the external controller. FC
is sampled and latched on the rising edge of FS at the end of the primary serial communication. See section
3 for details.
FILT
43
28
O
O
Bandgap filter. FILT is provided for decoupling of the bandgap reference, and provides 3.2 V. The optimal
capacitor value is 0.1 µF (ceramic). This voltage node should be loaded only with a high-impedance dc load.
FLAG
FS
16
27
13
20
Output flag. During phone mode, FLAG contains the value set in control 2 register.
I/O Framesync. FSisanoutputwhenthedeviceisconfiguredasamaster(M/Spintiedhigh). FSisaninput when
the device is configured as a slave (M/S pin tied low). When configured as a slave, data will transfer when
FS goes low. FS is internally generated in the master mode for the master device and all slave devices. In
the master mode FS is low during data transfer.
FSD
28
21
O
Frame sync delayed output. The FSD (active-low) output synchronizes a slave device to the frame sync of
the master device. FSD is applied to the slave FS input and is the same duration as the master FS signal but
is delayed in time by the number of shift clocks programmed in the control 3 register.
INM
INP
2
1
6
5
I
I
Inverting input to analog modulator. INM requires an external single-pole antialias filter with a low output
impedance.
Noninverting input to analog modulator. INP requires an external single-pole antialias filter with a low output
impedance.
NOTES: 1. Separateanaloganddigitalpowerandgroundpinsaresuppliedonthisdevice.Forbestoperationandresults,thePCboarddesigner
should utilize separate analog and digital power supplies as well as separate analog and digital ground planes.
2. All digital inputs and outputs are TTL compatible, unless otherwise noted (for DV
DD
= 5 V).
1–4
1.5 Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NO. NO.
NAME
PT
29
25
40
DW
M/S
22
I
I
Master/slave select input. When M/S is high, the device is the master. When M/S is low, the device is a slave.
Master clock. MCLK derives the internal clocks of the sigma–delta analog interface circuit.
MCLK
18
MONOUT
27
O
Monitor output. MONOUT allows for monitoring of the analog input and is a high-impedance output. The gain
or mute is selected using control 1 register.
OUTM
36
24
O
Inverting output of the DAC. The OUTM output can be loaded with 600 Ω. OUTM is functionally identical with
and complementary to OUTP. OUTM can also be used alone for single-ended operation.
OUTP
35
22
23
16
O
I
Noninverting output of the DAC. The OUTP output can be loaded with 600 Ω. OUTP can also be used alone
for single-ended operation.
PWRDWN
Power down. When PWRDWN is pulled low, the device goes into a power-down mode, the serial interface
isdisabled.However,alltheregistervaluesaresustainedandthedeviceresumesfullpoweroperationwithout
reinitialization when PWRDWN is pulled high again. PWRDWN resets the counters only and preserves the
programmed register contents (see paragraph 2.2.2 for more information).
REFM
REFP
46
45
2
1
O
O
I
Voltage reference filter output. REFM is provided for low-pass filtering of the internal bandgap reference. The
optimal ceramic capacitor value is 0.1 µF and should be connected between REFM and REFP. DC voltage
at REFM is 0 V.
Voltage reference filter positive output. REFP is provided for low-pass filtering of the internal bandgap
reference.Theoptimalceramiccapacitorvalueis0.1µFandshouldbeconnectedbetweenREFPandREFM.
DC voltage at REFP is 3.2 V.
RESET
SCLK
21
26
15
19
Reset. RESET initializes all of the internal registers to their default values. The serial port can be configured
to the default state accordingly. See section 6 and paragraph 2.2.1 for more information.
I/O Shift clock. The SCLK signal clocks serial data in through DIN and out through DOUT during the frame-sync
interval.Whenconfiguredasanoutput(M/Shigh), SCLKisgeneratedinternallybymultiplyingtheframe-sync
signal frequency by 256. When configured as an input (M/S low), SCLK is generated externally and must be
synchronous with the master clock and frame sync.
NOTES: 1. Separateanaloganddigitalpowerandgroundpinsaresuppliedonthisdevice.Forbestoperationandresults,thePCboarddesigner
should utilize separate analog and digital power supplies as well as separate analog and digital ground planes.
2. All digital inputs and outputs are TTL compatible, unless otherwise noted (for DV
= 5 V).
DD
1–5
1.6 Definitions and Terminology
ADC Channel
Channel Delay
d
The ADC channel refers to all signal processing circuits between the analog input and the digital
conversion results at DOUT.
The delay for the analog signal at the ADC input to appear on the digital output. The delay for
the digital value at the DAC input to appear on the analog output.
The alpha character d represents valid programmed or default data in the control register format
(see Section 3.2) when discussing other data bit portions of the register.
Dxx
Dxx is the bit position in the primary data word (xx is the bit number).
DSxx is the bit position in the secondary data word (xx is the bit number).
DSxx
DAC Channel
DAC channel refers to all signal processing circuits between the digital data word applied to DIN
and the differential output analog signal available at OUTP and OUTM.
Data Transfer
Interval
The time during which data is transferred from DOUT and to DIN. The interval is 16 shift clocks
and the data transfer is initiated by the falling edge of the frame-sync signal.
FIR
Finite duration impulse response
The sampling frequency
f
s
Frame Sync and Frame sync and sampling period is the time between falling edges of successive primary
Sampling Period frame-sync signals. It is always equal to 256 SCLK.
Frame Sync
Frame sync refers only to the falling edge of the signal that initiates the data transfer interval.
The primary frame sync starts the primary communications, and the secondary frame sync
starts the secondary communications.
Frame-Sync
Interval
The frame-sync interval is the time period occupied by 16 shift clocks. The frame-sync signal
goes high on the seventeenth rising edge of SCLK.
Host
A host is any processing system that interfaces to DIN, DOUT, SCLK, FS, and/or MCLK.
Programmable gain amplifier
PGA
Primary
Primary communications refers to the digital data transfer interval. Since the device is
Communications synchronous, the signal data words from the ADC channel and to the DAC channel occur
simultaneously.
Secondary
Secondary communications refers to the digital control and configuration data transfer interval
Communications into DIN and the register read data cycle from DOUT. The data transfer interval occurs when
requested by hardware or software.
Signal Data
This refers to the input signal and all of the converted representations through the ADC channel
and the signal through the DAC channel to the analog output. This is contrasted with the purely
digital software control data.
X
The alpha character X represents a don’t care bit-position within the control register format.
1–6
1.7 Register Functional Summary
There are seven control registers that are used as follows:
Register 0 The No-Op register. Addressing register 0 allows secondary communications requests without altering
any other register.
Register 1 Control register 1. The data in this register controls:
•
•
•
•
•
•
•
Software reset
Software power down
Normal or auxiliary analog inputs enabling
Normal or auxiliary analog inputs monitoring
Selection of monitor amplifier output gain
Selection of digital loopback
Selection of16-bit or (15+1)-bit mode of DAC operation
Register 2 Control register 2. The data in this register:
•
•
•
•
•
Contains the output value of FLAG
Selects phone mode
Contains the output flag indicating a decimator FIR filter overflow
Selects either 16-bit mode or (15+1)-bit mode of ADC operation
Enables analog loopback
Register 3 Control register 3. The data in this register:
•
•
Sets the number of SCLK delays between FS and FSD
Informs the master device of how many slaves are connected in the chain
Register 4 Control register 4. The data in this register:
•
•
Selects the amplifier gain for the input and output amplifiers
Sets the sample rate by choosing the value of N from 1 to 8 where f = MCLK/(128
N) or
s
MCLK/(512
Selects the PLL. If the PLL is selected, the sampling rate is set to MCLK/(128
bypassed, the sampling rate can be set to MCLK/(512 N).
N)
•
N). If the PLL is
Register 5 Reserved for factory test. Do not write to this register.
Register 6 Reserved for factory test. Do not write to this register.
1–7
1–8
2 Detailed Description
2.1 Device Functions
2.1.1 Operating Frequencies and Filter Control
The sampling frequency is controlled by control register 4. When the internal PLL is enabled (D7=0), the sampling
frequency is derived from the following equation:
MCLK
128
(1)
f
Sampling (conversion) frequency
s
N
When the internal PLL is disabled (D7=1), the sampling frequency is derived from the following equation:
MCLK
512
(2)
f
Sampling (conversion) frequency
s
N
If the sampling frequency is lower than 7 kHz, the sampling frequency is derived from the master clock (MCLK) using
equation 2. The internal PLL must be bypassed. The PLL input clock for sampling frequencies lower than 7 kHz is
outside the working range for the PLL input clock.
The frequency of SCLK is derived from sampling frequency (fs) instead of MCLK. The equation is as follows:
(3)
SCLK
256
f
s
The cutoff frequency of the filter can not be controlled by register programming. The filter response is shown in the
specification for an 8 kHz sample rate. This pass band scales linearly with the sample rate.
2.1.2 ADC Signal Channel
The input signal is amplified and applied to the ADC input. The ADC converts the signal into discrete output digital
words in 2s-complement data format, corresponding to the instantaneous analog-signal value at the sampling time.
These 16-bit (or 15-bit) digital words, representing sampled values of the analog input signal after the PGA, are
clocked out of the serial port (DOUT) at the positive edge of SCLK during the frame-sync interval, one bit for each
SCLK and one word for each primary communication interval (256 SCLKs). The 16-bit or (15 + 1)-bit ADC mode is
programmed into the device using control register 2. The default setting is the (15 + 1)-bit mode after power-up.
During secondary communication, the data previously programmed into the registers can be read out. This read
operation is accomplished by sending the appropriate register address (DS12 – DS8) with the read bit (DS13) set
to 1 in through DIN during present secondary communication. If a register read is not requested, all 16 bits are cleared
to 0 in the secondary communication. The timing sequence is shown in Figure 2–1 and Figure 2–2.
2–1
1
2
15
16
17
SCLK
FS
16 SCLKs
DOUT
(16-Bit)
D15
MSB
D15
D14
D14
D1
D0
LSB
M/S
DOUT
(15+1-Bit)
D1
MSB
LSB
NOTES: A. The 16-bit or (15 + 1)-bit mode is programmed via control register 2.
B. M/S is used to indicate whether the 15-bit data comes from master device or slave device. (Master: M/S = 1, Slave M/S = 0)
C. The MSB (D15) is stable (the host can latch the data in at this time) at the falling edging of SCLK #1, the last bit (D0,M/S) is stable
at the falling edging of SCLK #16.
Figure 2–1. Timing Sequence of ADC Channel (Primary Communication Only)
Primary
Secondary
16 SCLKs
Primary
16 SCLKs
FS
DOUT
(16-Bit)
16-Bit ADC Data
M/S + Register Address +
Register Data/
M/S + Register Address +
All 0s (see Note A)
DOUT
(15 +1-Bit)
15-Bit ADC Data
+ M/S
M/S + Register Data/
M/S + All 0 (see Note A)
128 SCLKs
256 SCLKs
NOTE A: M/S bit (DS15) in the secondary communication is used to indicate whether the register data (address and content) comes from the
master device or the slave device if the read bit is set. During register read operations, bits DS7 – DS0 are the contents of the specified
register. In register write operations, bits DS7 – DS0 are all 0s.
Figure 2–2. Timing Sequence of ADC Channel (Primary and Secondary Communication)
2.1.3 DAC Signal Channel
DIN receives the 16-bit serial data word (2’s complement) from the host during the primary communications interval.
These 16-bit digital words, representing the analog output signal before PGA, are clocked into the serial port (DIN)
at the falling edge of SCLK during the frame-sync interval, one bit for each SCLK and one word for each primary
communication interval (256 SCLKs). The data are converted to a pulse train by the sigma-delta DAC, which consists
of a digital interpolation filter and a digital modulator. The output of the modulator is then passed to an internal
low-pass filter to complete the analog signal reconstruction. Finally, the resulting analog signal is applied to the input
of a programmable-gain amplifier, which is capable of driving a 600-Ω load differentially at OUTP and OUTM. The
timing sequence is shown in Figure 2–3.
2–2
1
2
15
16
17
SCLK
FS
16 SCLKs
DIN
(16-Bit)
D15
MSB
d15
D14
d14
D1
D0
LSB
d0=0
DIN
(15+1-Bit)
d1
MSB
LSB
see Note B
NOTES: A. The 16-bit or (15 + 1)-bit mode is programmed via control register 1.
B. d0 = 0 means no secondary communication request (software secondary communication request control — paragraph 3.2)
Figure 2–3. Timing Sequence of DAC Channel (Primary Communication Only)
During secondary communication, the digital control and configuration data (together with the register address), are
clocked in through DIN. These 16-bits of data are used either to initialize the register, or to read the register content
through DOUT. If a register initialization is not required, a no-operation word (DS15–DS8 are all set to 0) can be used.
If DS13 is set to 1, the content of the control register, specified by DS12–DS8, will be sent out through DOUT during
the same secondary communication (see section 2.1.5). The timing sequence is shown in Figure 2–4.
Primary
Secondary
16 SCLKs
Primary
16 SCLKs
FS
DIN (16-Bit)
(see Note A)
16-Bit DAC Data
Register Read/Write
Register Read/Write
DIN
(15 +1-Bit)
15-Bit DAC
Data + D0=1
(see Note B)
128 SCLKs
256 SCLKs
NOTES: A. FC has to be set high for a secondary communication request when 16–bit DAC data format is used (paragraph 3.2).
B. D0 = 1 means secondary communication request (software secondary communication request control — paragraph 3.2).
Figure 2–4. Timing Sequence of DAC Channel (Primary and Secondary Communication)
2.1.4 Serial Interface
The digital serial interface consists of the shift clock (SCLK), the frame-sync signal (FS), the ADC-channel data output
(DOUT), and the DAC-channel data input (DIN). During the primary frame synchronization interval, SCLK clocks the
ADC channel results out through DOUT and clocks 16-bit/(15+1)-bit DAC data in through DIN.
Duringthesecondaryframe-syncinterval, SCLKclockstheregisterreaddataoutthroughDOUTifthereadbit(DS13)
is set to 1 and transfers control and device parameter in through DIN. The timing sequence is shown in Figures 2–2
and 2–4.
2.1.5 Register Programming
All register programming occurs during secondary communications through DIN, and data is latched and valid on the
falling edge of SCLK during the frame-sync signal. If the default value for a particular register is desired, that register
2–3
does not need to be addressed during the secondary communications interval. The no-op command (DS15 – DS8
all set to 0) addresses the pseudo-register (register 0), and no register programming takes place during the
communications.
In addition, each register can be read back through DOUT during secondary communications by setting the read bit
(DS13) to 1. When the register is in the read mode, no data can be written to the register during this cycle. DS13 must
be cleared to write to the register.
For example, if the contents of control register 1 is desired to be read out from DOUT, the following procedure must
be performed through DIN:
1. Request secondary communication by setting either D0 = 1 (software request) or FC = high (hardware
request) during the primary communication interval.
2. At the secondary communication interval (FS), send data in the following format in through DIN:
read
1
control register 1
0
0
0
0
0
0
1
x
x
x
x
x
x
x
x
DS15
DS0
3. Then the following data will be read from DOUT, the last 8 bits of DOUT will contain the register 1 data.
read
1
control register 1
data
M/S
0
0
0
0
0
1
d
d
d
d
d
d
d
d
DS15
DS0
Figure 2–5 is a timing diagram of this procedure.
P
S
FS
Register 1 Read
DIN
DOUT
Low 8 Bits (DS0–DS7) are the
Content of Register 1
Figure 2–5. Register 1 Read Operation Timing Diagram
If control register 1 needs to be programmed, the following procedure must be performed through DIN:
1. Request secondary communication by setting either D0 = 1 (software request) or FC = high (hardware
request) during the primary communication interval.
2. At the secondary communication interval (FS), send data in the following format in through DIN:
write
0
control register 1
data
0
0
0
0
0
0
1
d
d
d
d
d
d
d
d
DS15
DS0
3. Then the following data is generated from DOUT:
write
0
control register 1
M/S
0
0
0
0
0
1
0
0
0
0
0
0
0
0
DS15
DS0
2–4
Figure 2–6 is a timing diagram of this procedure.
P
S
FS
Register Write
DIN
DOUT
Low 8 Bits (DS0–DS7) are all 0
Figure 2–6. Register 1 Write Operation Timing Diagram
2.1.6 Sigma-Delta ADC
The sigma-delta analog-to-digital converter in the device is a sigma-delta modulator with 64-× oversampling. The
ADC provides high-resolution, low-noise performance using oversampling techniques. Due to the oversampling
employed, only single-pole antialiasing filters are required on the analog inputs.
2.1.7 Decimation Filter
The decimation filters reduce the digital data rate to the sampling rate. This is accomplished by decimating with a ratio
of 1:64. The output of the decimation filter is a 16-bit 2s-complement data word clocking at the sample rate selected
for that particular data channel. The bandwidth of the filter is 0.439 × f
and scales linearly with the sample rate.
sample
2.1.8 Sigma-Delta DAC
The sigma-delta digital-to-analog converter in the device is a sigma-delta modulator with 256-× oversampling. The
DAC provides high-resolution, low-noise performance using oversampling techniques.
2.1.9 Interpolation Filter
The interpolation filter resamples the digital data at a rate of 256 times the incoming sample rate. The high-speed
data output from the interpolation filter is then used in the sigma-delta DAC. The bandwidth of the filter is 0.439 ×
f
and scales linearly with the sample rate.
sample
2.1.10 Analog and Digital Loopback
The analog and digital loopbacks provide a means of testing the modem data ADC/DAC channels and can be used
forin-circuitsystem-leveltests. TheanalogloopbackroutestheDAClow-passfilteroutputintotheanaloginputwhere
it is then converted by the ADC into a digital word. The digital loopback, enabled by setting bit D1 in control 1 register
to 1, routes the ADC output to the DAC input on the device. Analog loopback is enabled by setting bit D3 in control
2 register to 1 (see section 6).
2.1.11 FIR Overflow Flag
The decimator FIR filter sets an overflow flag (bit D5) of control 2 register to indicate that the input analog signal has
exceeded the range of the internal decimation filter calculations. Once the FIR overflow flag has been set in the
register, it remains set until the register is read by the user. Reading this value resets the overflow flag.
If FIR overflow occurs, the input signal must be attenuated either by the PGA or some other method.
2–5
2.2 Reset and Power-Down Functions
2.2.1 Software and Hardware Reset
The TLC320AD50C and TLC320AD52C reset the internal counters and registers in response to either of two events:
1. A low-going reset pulse is applied to terminal RESET.
2. A 1 is written to the programmable software reset bit (D7 of control register 1).
Either event resets the control registers and clears all the sequential circuits in the device. Reset signals should be
at least 6 master clock periods long.
After hardware reset, the default contents of all registers is 0.
After a hardware or software reset, the AD50 and AD52 require a finite amount of time for the internal PLL to stabilize.
During this time, no control words or D/A data should be written to the device.
The reset sequence should be as follows:
1. Assert reset (pulse width encompassing at least 6 MCLK periods)
2. De-activate reset
3. Wait for SCLKS to be generated by the master device. This will take approximately 100 µs.
4. Wait for 18 frame syncs to occur
5. Write control and configuration data
6. Collect conversion data
2.2.2 Software and Hardware Power Down
Except for the digital interface, most of the device enters the power-down mode when D6 in control 1 register is set
to 1. When PWRDWN is taken low, the entire device is powered down. In either case, the register contents are
preserved and the output of the monitor amplifier is held at the midpoint voltage to minimize pops and clicks.
The amount of power drawn during software power down is higher than it is during a hardware power down because
of the current required to keep the digital interface active. Additional differences between software and hardware
power-down modes are detailed in the following paragraphs. Figure 2–7 represents the internal power-down logic.
PWRDWN
D6 is Programmed
Through a Secondary
Write Operation
Software Power Down
(Control Register 1, D6)
Internal TLC320AD50C
Figure 2–7. Internal Power-Down Logic
2.2.2.1 Software Power Down
When D6 of control 1 register is set to 1, the device enters the software power-down mode. In this state, the digital
interface circuit is still active while the internal ADC and DAC channels and differential outputs OUTP and OUTM are
disabled, and DOUT and FSD are inactive. Register data in the secondary serial communications is still accepted,
but data in the primary serial communications is ignored. The device returns to normal operation when D6 of control
1 register is reset to 0.
2–6
2.2.2.2 Hardware Power Down
WhenPWRDWNisheldlow, thedeviceentersthehardwarepower-downmode. Inthisstate, theinternalclockcontrol
circuit and the differential outputs OUTP and OUTM are disabled. All other digital I/Os either are disabled or remain
in the state they were in immediately before power down. DIN cannot accept any data input. The device can only be
returned to normal operation by taking and holding PWRDWN high. When not holding the device in the hardware
power-down mode, PWRDWN should be tied high.
2.3 Master Clock Circuit
MCLK is the external master clock input. The internal clock circuit generates and distributes necessary clocks
throughout the device. An internal PLL circuit is used for upsampling to provide the appropriate clocks for the digital
filters and modulators.
When the device is in the master mode, SCLK and FS are derived from MCLK in order to provide clocking of the serial
communications between the device and its controller. When in the slave mode, SCLK and FS are both inputs.
2.4 Data Out (DOUT)
DOUT is placed in the high-impedance state on the rising edge of the frame sync. In the primary communication, the
data word is the ADC conversion result. In the secondary communication, the data is the register-read results when
requested by the read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are
all zeroes. The state of the master/slave (M/S) terminal is reflected by the MSB in secondary communication (DOUT,
bit DS15) and the LSB in the primary communication (DOUT, bit D0) while in 15 + 1 mode. When the device is in the
slave mode, DOUT remains in a high-impedance state until a nonzero value is written as a number of slaves in control
register 3 (bits D7 and D6).
2.4.1 Data Out, Master Mode
In the master mode, DOUT is taken from the high-impedance state by the falling edge of the frame sync (FS) that
is assigned to DOUT. The most significant data bit then appears first on DOUT.
2.4.2 Data Out, Slave Mode
In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the input frame sync (FS).
The most significant data bit then appears on DOUT. When in the slave mode, DOUT is not enabled until the control
3 register is programmed with the number of slaves. This must be done even if there is only one slave device.
2.5 Data In (DIN)
In a primary communication, the data word is the input digital signal to the DAC channel. If the (15+1)-bit data format
is used, the LSB (D0) is used to request a secondary communication. In a secondary communication, the data is the
control and configuration data that sets the device for a particular function (see Section 3, Secondary Serial
Communication for details).
2.6 FC (Hardware Secondary Communication Request)
The FC input provides for hardware requests for secondary communications. FC works in conjunction with the LSB
of the primary data word. The signal on FC is latched on the rising edge of the primary frame sync (FS). FC should
be tied low if not used.
2.7 Frame-Sync Function for TLC320AD50C
The frame-sync signal (FS) indicates the device is ready to send and receive data. The data transfer out of DOUT
and into DIN begins on the falling edge of the frame-sync signal.
2–7
2.7.1 Frame Sync (FS) Function, Master Mode
The frame sync is generated internally and goes low on the rising edge of SCLK and remains low during a 16-bit data
transfer. In addition to generating its own frame-sync signal, the master also outputs a frame sync for each slave that
is being used (see Figures 2–8 and 2–9).
SCLK
Primary
Secondary
16 SCLKs
Primary
Primary
16 SCLKs
FS
(see Note A)
Primary
FS
(see Note B)
DIN/DOUT
128 SCLKs
256 SCLKs
NOTES: A. Primary and secondary serial communication
B. Primary serial communication, only
Figure 2–8. Master Device Frame-Sync Signal With Primary and Secondary Communications
(No Slaves)
SCLK
MP
MP
SP
SP
MS
SS
MP
MP
FS
(see Note A)
FS
(see Note B)
Delay is m Shift Clocks
(see Note C)
128 SCLKs
256 SCLKs
Legend:
MP:Master Primary (master device data is transferred in this period, DOUT of the slave device is in high impedance state).
SP: Slave Primary (slave device data is transferred in this period, DOUT of master device is in high impedance state).
MS:MasterSecondary(masterdevicecontrolregisterinformationistransferredinthisperiod,DOUToftheslavedeviceisinhighimpedancestate).
SS: Slave Secondary(slave device control register information is transferred in this period, DOUT of the master device is in high impedance state).
NOTES: A. Primary and secondary serial communications
B. Primary serial communication only
C. m is the value programmed into the FSD register (control register 3: D0–D5)
Figure 2–9. Master Device Frame-Sync Signal With Primary and Secondary Communications
(With 1 Slave Device)
2.7.2 Frame Sync (FS) Function,Slave Mode
Frame-sync timing is generated externally by the master FSD (or the previous slave in a multi-slave configuration)
and is applied to FS of the slave to control the ADC and DAC timing.
2–8
2.7.3 Frame-Sync Delayed (FSD) Function, Master Mode
The timing relationships are as follows:
•
When the FSD register (control 3 register) data is 0 (default state at power up), thenFSDgoes low 1/4 SCLK
prior to the rising edge of SCLK when FS goes low (Figure 2–10).
•
When the FSD register data is greater than 17, then FSD goes low on the rising edge of SCLK that is the
FSD register number of SCLKs after the falling edge of FS (Figure 2–11).
Register data values from 1 to 17 result in a default register value of zero and should not be used.
SCLK
MP and SP
See Note A
MS and SS
See Note A
FS
(P and S)
See Note B
FSD
(P and S)
See Note B
FS (P)
See Note B
FSD (P)
See Note B
NOTES: A. The DIN of master and slave devices share the same DIN bus during first initialization. The DOUT is occupied by the Master device
only until the control 3 register of master and slave device is programmed with slave devices number and number of SCLKs between
FS and FSD (m>17).
B. P&S: Primary and secondary communications P: Primary communication only
Figure 2–10. Master Device FS and FSD Output When FSD Register (D0–D5, Control 3 Register) is 0
MP
SP
MS
SS
MP
FS
FSD
Delay is m
SCLKs (m > 17)
128 SCLKs
256 SCLKs
NOTES: A. Since master and slave share the same DIN bus during first initialization, they share the same input data word. Only one write cycle
is needed to program control 3 register of master device and slave device(s).
B. After the control 3 register is programmed, the DIN or DOUT bus of master and slave(s) are separated by time, although they still
physically connect to each other.
Figure 2–11. Master Device FS and FSD Output After Control 3 Register Is Programmed
(One Slave Device)
2.7.4 Frame-Sync Delayed (FSD), Slave Mode
The master FSD is output to the first slave device and the first slave FSD is output to the second slave device and
so on (see Figure 2–12). The FSD output of each device is input to the FS terminal of the succeeding device. The
FSD timing sequence in the slave mode is as follows:
•
•
When the FSD register data is 0, then FSD goes low 1/4 SCLK cycle before FS goes low.
When the FSD register data is greater than 17, then FSD goes low on the rising edge of the SCLK that is
equal to the FSD register number of SCLKs after the falling edge of FS (see Figure 2–13).
2–9
Data values from 1 to 17 should not be used.
CLKOUT
DX
DR
DV
DD
MCLK
DIN
MCLK
DIN
MCLK
DIN
MCLK
DIN
M/S
FS
FSX
FSR
DOUT
DOUT
DOUT
DOUT
FSD
FS
FSD
FS
FSD
FS
M/S
SCLK
M/S
SCLK
M/S
SCLK
CLKX
CLKR
SCLK
Master
Slave 1
Slave 2
Slave 3
TMS320C5X
TMS320C2X
TMS320C54X
Figure 2–12. Master With Slaves (To DSP Interface)
S
S
P
P
P
P
S
S1
M
S1
S2
S3
M
Master FS
Master FSD
Slave 1 FS
Delay 1
Delay 2
Delay 3
Delay 4
Slave 1 FSD
Slave 2 FS
Slave 2 FSD
Slave 3 FS
Slave 3 FSD
(see Note A)
128 SCLKs
NOTE A: Slave 3 FSD cannot be used.
Figure 2–13. Master-Slave Frame-Sync Timing After A Delay Has Been Programmed Into The FSD
Register (D0–D5 of Control 3 Register)
2–10
2.8 Frame-Sync Function for TLC320AD52C
The frame-sync function for TLC320AD52C is very similar to that of the TLC320AD50C except the following:
1. TLC320AD52C can support only one slave.
2. The FSD terminal function can be disabled for TLC320AD52C by programming bit D2 in control 2 register.
3. The FSD value loaded into control 3 register must be multiplied by 2 to obtain the actual number of SCLKs
for the delay.
For example, if FSD register (control register 3) is programmed with 49H, it means that the TLC320AD52C has one
slave and the FSD terminal has 18 SCLKs delay after master primary FS output. See Figure 2–14.
MP
SP
MS
SS
MP
FS
FSD
Delay is ≥18
SCLKs
(See Note A)
128 SCLKs
256 SCLKs
NOTE A: Minimum SCLK delay number in FSD register is 9. This means that a delay of at least 18 SCLKs is required for proper operation of the
TLC320AD52C.
Figure 2–14. Master Device FS and FSD Output After Control 3 Register
Is Programmed With 49H
2.9 Multiplexed Analog Input and Output
The two differential analog inputs (INP and INM or AUXP and AUXM) are multiplexed into the sigma-delta modulator.
The performance of the AUX channel is similar to the normal input channel. A single-pole antialias filter must be
connected to INP and INM (also AUXP and AUXM, if used). If an RC is used for the single-pole filter (Figure 2–15)
the value of R should not be greater that 1 kΩ. The gain of the input amplifiers is set through the control register 4.
R
INP
IN +
C
C
R
INM
IN –
NOTES: A. The bandwidth of this RC antialias is determined by: (f = 1/(2π RC))
0
B. AUXP and AUXM need to be connected to AV
if not used.
SS
C. Bandwidth of the antialias filter can be 4 × f .
s
D. The input signal must have AV /2 dc or it must be ac coupled.
DD
Figure 2–15. RC Antialias Filter
To produce the best possible common-mode rejection of unwanted signal performance, the analog signal is
processed differentially until it is converted to digital data. The signal applied to the terminals INM and INP should
be differential to preserve the device specifications. As much as 6 dB of signal level will be lost if the single-ended
input is used directly. The signal source driving the analog inputs (INP and INM or AUXP and AUXM) should have
a low source impedance for best low-noise performance and accuracy.
To obtain maximum dynamic range, the signal should be ac coupled to the input terminal. The analog input signal
is self-biased to the midsupply voltage if the monitor-amplifier input source is selected as the same source for the
2–11
ADC input. These input sources are selected by bits D4 and D5 of control register 1. The default condition self biases
the input since the register default value selects INP and INM as the source for both the ADC and monitor amplifier
input (see Figure 2–16). A simple single-pole antialias filter with low output impedance must be connected to INP and
INM (also AUXP and AUXM, if used).
INP
V
INP
35 kΩ
2.5 V
35 kΩ
INM
V
INM
Figure 2–16. INP and INM Internal Self-Biased (2.5 V) Circuit
2.9.1 Analog Output
TheOUTPandOUTMaredifferentialoutputsandcandriveatypical600Ω loaddirectly. Figure2–17showsthecircuit
when load is ground referenced.
10 kΩ
5 V
10 kΩ
OUTM
OUTP
+
_
TLE2062
10 kΩ
10 kΩ
Load
–5 V
Figure 2–17. Differential Output Drive (Ground Referenced)
OUTP (Solid Line)
4 V
(Virtual 0) 2.5 V
1 V
OUTM (Dashed Line)
Digital Input Code
Analog Output Voltage
OUT +
4 V
2.5 V
1 V
OUT –
1 V
2.5 V
4 V
(+FS) 0111 1111 1111 1111
(Virtual 0) 0000 0000 0000 0000
(–FS) 1000 0000 0000 0000
Figure 2–18. Digital Input Code vs. Analog Output Voltage
2–12
3 Serial Communications
DOUT, DIN, SCLK, FS, and FC are the serial communication signals. The digital output data from the ADC is taken
from DOUT. The digital input data for the DAC is applied to DIN. The synchronizing clock for the serial communication
data and the frame sync is taken from SCLK. The frame-sync pulse that encloses the ADC and DAC data transfer
interval is taken from FS. For signal data transmitted from the ADC or to the DAC, primary serial communication is
used. To read or write words that control both the options and the circuit configurations of the device, secondary
communication is used.
The purpose of the primary and secondary communications is to allow conversion data and control data to be
transferred across the same serial port. A primary transfer is always dedicated to conversion data. A secondary
transfer is used to set up and/or read the register values. A primary transfer occurs for every conversion period. A
secondary transfer occurs only when requested. Secondary serial communication can be requested either by
hardware (FC terminal) or by software (D0 of primary data input to DIN).
3.1 Primary Serial Communication
Primary serial communication is used both to transmit and receive conversion signal data. The DAC word length
depends on the state of bit D0 in control 1 register. After power up or reset, the device defaults to the 15-bit mode.
When the DAC word length is 15 bits, the last bit of the primary 16-bit serial communication word is a control bit used
to request secondary serial communication. In the 16-bit mode, all 16 bits of the primary communication word are
used as data for the DAC and the hardware terminal FC must be used to request secondary communication.
Figure 3–1 shows the timing relationship for SCLK, FS, DOUT and DIN in a primary communication. The timing
sequence for this operation is as follows:
1. FS is brought low by the TLC320AD50C, TLC320AD50I, or TLC320AD52C.
2. A 16-bit word is transmitted from the ADC (DOUT) and a 16-bit word is received from the DAC (DIN).
3. FS is brought high by the TLC320AD50C, TLC320AD50I, or TLC320AD52C, signaling the end of the data
transfer.
SCLK
FS
DIN
D15 D14 D13 D12 D11 D10
D15 D14 D13 D12 D11 D10
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
DOUT
NOTE: DIN is latched at the falling edge of SCLK. DOUT is sent out at the rising edge of SCLK
Figure 3–1. Primary Serial Communication Timing
3–1
3.2 Secondary Serial Communication
Secondary serial communication is used to read or write 16-bit words that program both the options and the circuit
configurations of the device. Register programming always occurs during secondary communication. Four primary
and secondary communication cycles are required to program the four registers. If the default value for a particular
register is desired, then the register addressing can be omitted during secondary communications. The NOOP
command addresses a pseudo-register, register 0, and no register programming takes place during this secondary
communication. If secondary communication is desired for any device (either master or slave), then a secondary
communication must be requested for all devices, starting with the master. This results in a secondary frame sync
(FS) for all devices. The NOOP command can be used for devices that do not need a secondary operation.
During secondary communication, a register may be written to or read from. When writing a value to a register, DIN
contains the value to be written. When reading the value in a register, the data is stepped out on DOUT.
There are two methods for initiating secondary communications:
1. By asserting a high level on FC
2. By asserting the LSB of the DIN 16-bit serial communication high while in the15-bit mode
Both methods are illustrated in Figure 3–2.
FC
Secondary
(Hardware)
Request
(LSB of DIN)
16-Bit Mode
(Control 1 Register, Bit 0)
Internal TLC320AD50C
Figure 3–2. Hardware and Software Methods to Make a Secondary Request
FC should be pulled high before the rising edge of the frame sync (FS). This causes the start of the secondary
communication, 128 SCLKs after the start of the primary communication frame. If slaves are present, FC should
remain high until the rising edge of the frame sync for the last slave.
The second method for secondary communication is by asserting the LSB high. The least significant bit (D0) can be
used for the secondary requests as shown in Table 3–1. The request is made by placing the device in the 15-bit DAC
mode and making the LSB of DIN equal to 1. All devices should be in the 15-bit DAC mode and secondary
communication should be requested for all devices.
Table 3–1. Least Significant Bit Control Function
CONTROL BIT D0
CONTROL BIT FUNCTION
No operation (NOOP)
Secondary communication request
0
1
Ifasecondarycommunicationrequestismade, FSgoeslowafter128SCLKsafterthebeginningoftheprimaryframe.
3–2
3.2.1 Hardware Secondary Serial Communication Request
The FC requests a secondary communication when it is asserted. The FC terminal is latched at the rising edge of
FS (primary communication), so FC should be pulled high before the rising edge of the primary frame sync (FS).
Figures 3–3 and 3–4 show the FS output from a master device.
P
S
P
FS
Secondary
Request
No Secondary
Request
FC
Register
ADC Data Out
DAC Data In
ADC Data Out
DAC Data In
DOUT
Read/Write
Register
Read/Write
DIN
Figure 3–3. FS Output When Hardware Secondary Serial Communication Is Requested Only Once
(No Slave)
P
P
P
P
S
S
S
S
P
FS
(Master)
M
S1
S2
S3
M
S1
S2
S3
M
FC
(See Note)
NOTE: FC of master device and slave devices should connect together.
Figure 3–4. FS Output When Hardware Secondary Serial Communication Is Requested Only Once
(Three Slaves)
3.2.2 Software Secondary Serial Communication Request
The LSB of the DAC data within a primary transfer can request a secondary communication when the device is in
the 15-bit mode.
Forallserialcommunications, themostsignificantbitistransferredfirst. Fora16-bitADCwordanda16-bitDACword,
D15 is the most significant bit and D0 is the least significant bit. For a 15-bit DAC data word in a primary
communication, D15 is the most significant bit and D1 is the least significant bit. Bit D0 is then used for the secondary
communication request control. All digital data values are in 2s complement data format (Figure 3–5).
If the data format is set to the 16-bit word mode, all 16 bits are either ADC or DAC data and secondary communication
can then be requested only by hardware (FC terminal).
P
S
P
FS
Register
Read/Write
Data (D0 = 1)
Data (D0 = 0)
DIN
Secondary Communication Request
No Secondary Communication Request
NOTE: See Figure 3–8 for secondary communication DIN data format.
Figure 3–5. FS Output During Software Secondary Serial Communication Request (No Slave)
3–3
3.3 Conversion Rate Versus Serial Port
The SCLK frequency is set equal to the frequency of the frame-sync signal (FS) multiplied by 256. The conversion
rate or sample rate is equal to the frequency of FS.
3.4 Phone Mode Control
Phone mode control is provided for applications that need hardware control and monitoring of external events. By
allowing the device to drive the FLAG terminal (set through control 2 register), the host DSP is capable of system
control through the same serial port that connects the device. Along with this control is the capability of monitoring
the value of the ALTDATA terminal during a secondary communication cycle. One application for this function is in
monitoring RING DETECT or OFFHOOK DETECT from a phone answering system. FLAG allows response to these
incoming control signals. Figure 3–6 shows the timing associated with this operating mode.
P
S
FS
Register Data
(8-Bits)
DOUT
(see Note A)
8-Bits
DOUT
(see Note B)
16-Bits
ALTDATA
NOTES: A. When DIN performs a read operation (set D13 to 1) during secondary communication.
B. When DIN perform a write operation (set D13 to 0) during secondary communication.
Figure 3–6. Phone Mode Timing When Phone Mode Is Enabled
3.5 DIN and DOUT Data Format
3.5.1 Primary Serial Communication DIN and DOUT Data Format (Figure 3–7)
DIN
D15 – D1
D0
(15+1) Bit Mode
Secondary
Communication Request
A/D and D/A Data
D15 – D1
DOUT
(15+1) Bit Mode
D0
DIN
16-Bit Mode
M/S Bit
D15 – D0
A/D and D/A Data
D15 – D0
DOUT
16-Bit Mode
Figure 3–7. Primary Communication DIN and DOUT Data Format
3–4
3.5.2 Secondary Serial Communication DIN and DOUT Data Format (Figure 3–8)
Don’t Care
DS13=1
DS15 DS14 DS13 DS12 DS11 DS10 DS9 DS8
DIN (Read)
DIN (Write)
DS7 – DS0
Data to the
Register
R/W
Register Address
DS15 DS14 DS13 DS12 DS11 DS10 DS9 DS8
DS13=0
DS7 – DS0
Register Data
DS13=1
DOUT (Read)
(Phone Mode Disabled)
DS15 DS14 DS13 DS12 DS11 DS10 DS9
DS8
DS7 – DS0
Register Address
M/S
All 0
DOUT (Write)
(Phone Mode Disabled)
DS15 DS14 DS13 DS12 DS11 DS10 DS9 DS8
DS13=0
DS7 – DS0
DOUT (Read)
(Phone Mode Enabled)
DS7 – DS0: Register Data
DS15 – DS8: ALTDATA
DOUT (Write)
(Phone Mode Enabled)
DS15 – DS0: ALTDATA
Figure 3–8. Second Communication DIN and DOUT Data Format
3–5
3–6
4 Specifications
4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
†
(Unless Otherwise Noted)
Supply voltage range, DV
AV
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
DD,
DD
Output voltage range, DOUT, FS, SCLK, FLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV
Output voltage range, OUTP, OUTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Input voltage range, DIN, PWRDWN, RESET, ALTDATA, MCLK, FC . . . . . . . . . . . . –0.3 V to DV
Input voltage range, INP, INM, AUXP, AUXM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
DD
DD
DD
DD
Case temperature for 10 seconds: DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Operating free-air temperature range, TLC320AD50C/52C, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Operating free-air temperature range, TLC320AD50I, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
4.2 Recommended Operating Conditions
MIN NOM
MAX
5.5
6
UNIT
V
Supply voltage, AV
DD
(see Note 2)
4.75
Analog signal input voltage, V
I(analog)
Differential (INP–INM) peak, for full scale operation
L
V
Differential output load resistance, OUTP, OUTM, R
600
Ω
L
Differential output load capacitance, OUTP, OUTM, C
ADC or DAC conversion rate
15
22.05
70
pF
kHz
°C
8
Operating free-air temperature, T
0
A
NOTE 2: Voltages at analog inputs and outputs and AV
DD
are with respect to the AV
terminal.
terminal.
terminal.
SS
SS
SS
4.2.1 Recommended Operating Conditions, DV
= 5 V
DD
MIN NOM
MAX
UNIT
V
Supply voltage, DV
DD
(see Note 3)
4.5
2
5.5
High-level input voltage, V
IH
V
Low-level input voltage, V
MCLK frequency
0.8
V
IL
8.192 11.290
MHz
NOTE 3: Voltages at digital inputs and outputs and DV
DD
are with respect to the DV
4.2.2 Recommended Operating Conditions, DV
= 3 V
DD
MIN NOM
MAX
UNIT
V
Supply voltage, DV
DD
(see Note 3)
2.7
1.8
3
3.3
High-level input voltage, V
IH
V
Low-level input voltage, V
MCLK frequency
0.6
V
IL
8.192 11.290
MHz
NOTE 3: Voltages at digital inputs and outputs and DV
DD
are with respect to the DV
4–1
4.3 Electrical Characteristics Over Recommended Operating Free-Air Temperature
Range, DV = 5 V, R = 600 Ω (Unless Otherwise Noted)
DD
L
4.3.1 Digital Inputs and Outputs, MCLK = 8.192 MHz, f = 8 kHz, DV
= 5 V
DD
s
PARAMETER
High-level output voltage, DOUT
TEST CONDITIONS
MIN
TYP
5
MAX
UNIT
V
V
V
I
I
= 360 µA
4
OH
O
Low-level output voltage, DOUT
High-level input current, any digital input
Low-level input current, any digital input
Input capacitance
= –2 mA
0.2
0.4
10
10
V
OL
O
I
I
V
V
= 5 V
µA
µA
pF
pF
IH
IH
= 0.8 V
IL
IL
C
C
5
5
i
Output capacitance
o
4.3.2 Digital Inputs and Outputs, MCLK = 8.192 MHz, f = 8 kHz, DV
= 3 V
DD
s
PARAMETER
High-level output voltage, DOUT
TEST CONDITIONS
MIN
TYP
3
MAX
UNIT
V
V
V
I
I
= 360 µA
2.4
OH
O
Low-level output voltage, DOUT
High-level input current, any digital input
Low-level input current, any digital input
Input capacitance
= –2 mA
0.2
0.4
10
10
V
OL
O
I
I
V
= 3 V
µA
µA
pF
pF
IH
IH
IL
V
= 0.6 V
IL
C
C
5
5
i
Output capacitance
o
4.3.3 ADC Channel, MCLK = 8.192 MHz, f = 8 kHz (see Note 4, Figures 5-6 and 5-7)
s
PARAMETER
TEST CONDITIONS
0 to 300 Hz
300 Hz to 3 kHz
3.3 kHz
MIN
–0.5
TYP
MAX
0.2
UNIT
–0.25
–0.35
0.25
0.3
Filter gain relative to gain at 1020 Hz
dB
3.6 kHz
–3
4 kHz
–40
–74
≥ 4.4 kHz
NOTE 4: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The analog input test signal is a sine wave with
0 dB = 4 V as the reference level for the analog input signal. The passband is 0 to 3600 Hz for an 8-kHz sample rate. This passband
PP
scales linearly with the sample rate.
4.3.4 ADC Dynamic Performance, MCLK = 8.192 MHz, f = 8 kHz
s
4.3.4.1 ADC Signal-to-Noise (see Note 5 and Figure 5-10)
TLC320AD50C/52C
TLC320AD50I
PARAMETER
TEST CONDITIONS
V = –1 dB (5.35 V)
UNIT
MIN
85
TYP
89
MAX
MIN
TYP
87
MAX
83
75
44
19
75
I
V = –9 dB (2.13 V)
I
77
81
79
Signal-to-noise ratio (SNR)
V = –40 dB (60 mV)
I
46
50
48
dB
V = –65 dB (3 mV)
I
21
25
23
V
AUX
= –9 dB
77
81
79
NOTE 5: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referenced to AV
DD
/2.
4–2
4.3.4.2 ADC Signal-to-Distortion (see Note 5 and Figure 5-11)
TLC320AD50C/52C
TLC320AD50I
PARAMETER
TEST CONDITIONS
V = –3 dB (4.25 V)
UNIT
MIN
80
TYP
85
MAX
MIN
TYP
84
MAX
79
78
66
42
78
I
V = –9 dB (2.13 V)
I
79
90
89
Signal-to-total harmonic distortion (THD)
V = –40 dB (60 mV)
I
67
72
71
dB
V = –65 dB (3 mV)
I
43
48
47
V
AUX
= –9 dB
79
90
89
NOTE 5. The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referenced to V
/2.
DD
4.3.4.3 ADC Signal-to-Distortion + Noise (see Note 5 and Figure 5-12)
TLC320AD50C/52C
TLC320AD50I
PARAMETER
TEST CONDITIONS
V = –3 dB (4.25 V)
UNIT
MIN
78
TYP
82
MAX
MIN
TYP
80
MAX
76
74
43
19
74
I
V = –9 dB (2.13 V)
I
76
80
78
Signal-to-total harmonic distortion + noise (THD + N) V = –40 dB (60 mV)
45
49
47
dB
I
V = –65 dB (3 mV)
I
20
24
22
V
AUX
= –9 dB
76
80
78
NOTE 5. The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referenced to V
/2.
DD
4.3.5 ADC Channel Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Peak-to-peak input voltage
(differential (INP–INM) peak, for full
scale operation)
V
I(PP)
6
V
Dynamic range
V = –1 dB (5.35 V)
88
100
± 0.3
5
dB
dB
dB
mV
dB
I
Interchannel isolation
Gain error
E
E
V = –1 dB at 1020 Hz
I
G
ADC converter offset error
O(ADC)
CMRR
Common-mode rejection ratio at INM, INP or AUXM, AUXP
Idle channel noise (on-chip reference)
Input resistance
V = –1 dB at 1020 Hz
I
74
V
= 2.5 V
75 µV rms
INP, INM
= 25°C
A
R
T
35
kΩ
i
Channel delay
17/f
s
s
4.3.6 DAC Path Filter, MCLK = 8.192 MHz, f = 8 kHz (see Note 6, Figures 5-8 and 5-9)
s
PARAMETER
TEST CONDITIONS
0 to 300 Hz
300 Hz to 3 kHz
3.3 kHz
MIN
–0.5
TYP
MAX
UNIT
0.2
0.25
0.3
–0.25
–0.35
Filter gain relative to gain at 1020 Hz
dB
3.6 kHz
–3
4 kHz
–40
–74
≥ 4.4 kHz
NOTE 6: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the digital equivalent of a
sine wave (digital full scale = 0 dB). The nominal differential DAC channel output with this input condition is 6 V
is 0 to 3600 Hz for an 8-kHz sample rate. This pass band scales linearly with the conversion rate.
. The pass band
I(PP)
4–3
4.3.7 DAC Dynamic Performance
4.3.7.1 DAC Signal-to-Noise When Load is 600 Ω (see Note 7 and Figure 5-13)
TLC320AD50C/52C
TLC320AD50I
PARAMETER
TEST CONDITIONS
V = 0 dB
UNIT
MIN
85
TYP
89
MAX
MIN
TYP
87
MAX
83
74
43
18
I
V = –9 dB
I
76
80
78
Signal-to-noise ratio (SNR)
dB
V = –40 dB
I
45
49
47
V = –65 dB
I
20
24
22
NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test is measured at output of
application schematic low-pass filter. The test is conducted in 16-bit mode.
4.3.7.2 DAC Signal-to-Noise When Load is 10 kΩ (see Note 7)
PARAMETER
TEST CONDITIONS
V = 0 dB
MIN
TYP
89
MAX
UNIT
I
V = –9 dB
80
I
Signal-to-noise ratio (SNR)
dB
V = –40 dB
I
50
V = –65 dB
I
25
NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test is measured at output of
application schematic low-pass filter. The test is conducted in 16-bit mode.
4.3.7.3 DAC Signal-to-Distortion When Load is 600 Ω (see Note 7, Figure 5-14)
TLC320AD50C/52C
TLC320AD50I
PARAMETER
TEST CONDITIONS
V = –3 dB
UNIT
MIN
76
TYP
80
MAX
MIN
TYP
78
MAX
74
82
62
40
I
V = –9 dB
I
84
90
88
Signal-to-total harmonic distortion (THD)
dB
V = –40 dB
I
64
72
70
V = –65 dB
I
42
48
46
NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test is measured at output of
application schematic low-pass filter. The test is conducted in 16-bit mode.
4.3.7.4 DAC Signal-to-Distortion When Load is 10 kΩ (see Note 7)
PARAMETER
TEST CONDITIONS
V = –3 dB
MIN
TYP
82
MAX
UNIT
I
V = –9 dB
91
I
Signal-to-total harmonic distortion (THD)
dB
V = –40 dB
I
77
V = –65 dB
I
49
NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test is measured at output of
application schematic low-pass filter. The test is conducted in 16-bit mode.
4.3.7.5 DAC Signal-to-Distortion+Noise When Load is 600 Ω (see Note 7, Figure 5-15)
TLC320AD50C/52C
TLC320AD50I
PARAMETER
TEST CONDITIONS
V = –3 dB
UNIT
MIN
75
TYP
79
MAX
MIN
TYP
76
MAX
72
72
42
17
I
V = –9 dB
I
75
79
76
Signal-to-total harmonic distortion + noise (THD + N)
dB
V = –40 dB
I
45
49
46
V = –65 dB
I
20
24
21
NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test is measured at output of
application schematic low-pass filter. The test is conducted in 16-bit mode.
4–4
4.3.8 DAC Channel Characteristics
PARAMETER
Dynamic range
TEST CONDITIONS
MIN
TYP
88
MAX
UNIT
dB
Interchannel isolation
100
±0.3
dB
E
G
Gain error, 0 dB
V
O
= 0 dB at 1020 Hz
dB
Idle channel narrow band noise
Output offset voltage at OUT (differential)
0 – 4 kHz, See Note 8
DIN = All 0s
125 µV rms
V
V
30
mV
OO
R
= 600 Ω typ (see Figure 2–17) with internal
L
Analog output voltage, OUTP–OUTM
reference and full-scale digital input,
See Note 9, differential
6
V
PP
O
Total out of band energy (0.55 f to 3 MHz)
s
–45
dB
Channel delay
18/f
s
NOTES: 8. The conversion rate is 8 kHz; the-out-of-band measurement is made from 4400 Hz to 3 MHz.
9. The digital input to the DAC channel at DIN is in 2s complement format. The TLC320AD50C/52C DAC is of the voltage-type and
requires a load resistor for current to voltage conversion.
4.3.9 Power Supply, AV
= DV
= 5 V, No Load
DD
DD
PARAMETER
TEST CONDITIONS
Operating
MIN
TYP
18
1
MAX
UNIT
24
I
I
I
I
(analog) Power supply current, ADC
mA
DD
DD
DD
DD
Power down
Operating
2
4
6
(PLL)
Power supply current, PLL
mA
Power down
Operating
0.5
4
mA
µA
(digital 1) Power supply current, digital
Power down
Operating
10
4
mA
µA
(digital 2) Power supply current, digital, DV
Power dissipation
= 3 V
DD
Power down
Operating
10
120
7.5
170
20
P
D
mW
H/W-power down
4.3.10 Power-Supply Rejection, AV
= DV
= 5 V (see Note 10)
DD
DD
PARAMETER
TEST CONDITIONS
f = 0 to f /2
MIN
TYP
50
MAX
UNIT
AV
DD
Supply voltage rejection ratio, analog supply
i
s
DV
DV
Supply voltage rejection ratio, DAC channel
Supply voltage rejection ratio, ADC channel
f = 0 to 30 kHz
40
dB
DD
i
f = 0 to 30 kHz
i
50
DD
NOTE 10: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV peak-to-peak signal
applied to the appropriate supply.
4.4 Timing Characteristics (see Parameter Measurement Information)
4.4.1 Master Mode Timing Requirements
MIN NOM
MAX
UNIT
t
t
t
t
Delay time, SCLK↑ to FS↓
0
d1
Setup time, DIN, before SCLK low
Hold time, DIN, after SCLK low
25
su1
20
50
h1
ns
Delay time, SCLK high to FSD low (see Figure 5–1)
d(CH–FDL)
t
Pulse duration, MCLK high
Pulse duration, MCLK low
32
20
wH
wL
t
4–5
4.4.2 Slave Mode Timing Requirements
MIN NOM
MAX
UNIT
t
t
t
t
Delay time, SCLK↑ to FS↓
0
d4
Setup time, DIN, before SCLK low
Hold time, DIN, after SCLK low
20
su2
20
40
50
h2
Delay time, FS low to FSD low, (see Figure 5–2)
d(FL–FDL)
ns
t
t
t
Delay time, SCLK high to FSD low, slave mode (see Figure 5–3)
Pulse duration, MCLK high
d(CH–FDL)
32
20
wH
wL
Pulse duration, MCLK low
4.4.3 Master Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
20
UNIT
t
t
t
Delay time, SCLK↑ to DOUT
Enable time, FS↓ to DOUT
Disable time, FS↑ to DOUT Hi-Z
d2
C
= 20 pF
L
25
ns
en1
dis1
20
4.4.4 Slave Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
20
UNIT
t
t
t
Delay time, SCLK↑ to DOUT
Enable time, FS↓ to DOUT
Disable time, FS↑ to DOUT Hi-Z
d5
C
= 20 pF
L
25
ns
en2
dis2
20
4.4.5 Reset Timing
PARAMETER
PARAMETER
MIN
TYP
TYP
MAX
MAX
UNIT
t
Reset pulsewidth
6 MCLKs
ns
PW
4.4.6 Other
MIN
10
UNIT
ns
t
t
Setup time, FC before FS↑
Hold time, FC after FS↑
su3
10
ns
h3
4–6
5 Parameter Measurement Information
2.4 V
SCLK
SCLK Period/4
FSD
0.8 V
t
d(CH-FDL)
FS
0.8 V
NOTE A: Timing shown is for the TLC320AD50C/52C operating as the master device. The programmed data value in the FSD register is 0. D0
through D5 of control 3 register are all 0.
Figure 5–1. Master FS and FSD Timing
FS
0.8 V
t
d(FL-FDL)
FSD
0.8 V
NOTE A: Timing shown is for the TLC320AD50C/52C operating in the slave mode (FS and SCLK signals are generated externally). The
programmed data value in the FSD register is 0.
Figure 5–2. Slave FS to FSD Timing
SCLK
0.8 V
t
d(CH-FDL)
FSD
0.8 V
NOTE A: Timing shown is for the TLC320AD50C/52C operating in the slave mode (FS and SCLK signals are generated externally). There is a
data value in the FSD register greater than 18 decimal. D0 through D5 of control 3 register are greater than 17.
Figure 5–3. Master/Slave SCLK to FSD Timing
5–1
t
wH
MCLK
SCLK
t
wL
t
d1
t
d2
FS
t
t
dis1
en1
DOUT
D15
D14
t
su1
DIN
D15
D14
t
h1
NOTE A: The master mode and D0 through D5 of control 3 register are greater than 17.
Figure 5–4. Serial Communication Timing (Master Mode)
t
wH
MCLK
SCLK
t
wL
t
d4
t
d5
FS
t
dis2
t
en2
D15
D14
DOUT
t
su2
D15
D14
DIN
t
h2
Figure 5–5. Serial Communication Timing (Slave Mode)
5–2
– 16
– 32
– 48
– 64
– 80
– 96
– 112
– 128
– 144
0
0.8
1.6
2.4
3.2
4
4.8
5.6
6.4
7.2
8
f – Input Frequency – kHz
I
Figure 5–6. ADC Channel Filter Response (MCLK = 8.192 MHz, f = 8 kHz)
s
0.5
0.4
0.3
0.2
0.1
0
– 0.1
– 0.2
– 0.3
– 0.4
– 0.5
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
f – Input Frequency – kHz
I
Figure 5–7. ADC Channel Filter Passband Ripple (MCLK = 8.192 MHz, f = 8 kHz)
s
5–3
– 16
– 32
– 48
– 64
– 80
– 96
– 112
– 128
– 144
0
0.8
1.6
2.4
3.2
4
4.8
5.6
6.4
7.2
8
f – Input Frequency – kHz
I
Figure 5–8. DAC Channel Filter Response (MCLK = 8.192 MHz, f = 8 kHz)
s
0.5
0.4
0.3
0.2
0.1
0
– 0.1
– 0.2
– .03
– 0.4
– 0.5
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
f – Input Frequency – kHz
I
Figure 5–9. DAC Channel Filter Passband Ripple (MCLK = 8.192 MHz, f = 8 kHz)
s
5–4
ADC SIGNAL-TO-NOISE RATIO
ADC SIGNAL-TO-DISTORTION RATIO
vs
vs
INPUT SIGNAL
INPUT SIGNAL
90
80
100
90
80
70
60
50
40
30
20
70
60
50
40
30
20
8 kHz Conversion Rate
MCLK = 8.192 MHz
8 kHz Conversion Rate
MCLK = 8.192 MHz
10
0
10
0
–65
–40
–9
–3
–2
–1
0
–65
–40
–9
–3
–2
–1
0
Input Signal – dB
Input Signal – dB
Figure 5–10
Figure 5–11
ADC SIGNAL-TO-(NOISE AND DISTORTION) RATIO
DAC SIGNAL-TO-NOISE RATIO
vs
vs
INPUT SIGNAL
INPUT SIGNAL
90
80
90
80
70
60
70
60
50
40
30
20
50
40
30
20
8 kHz Conversion Rate
MCLK = 8.192 MHz
8 kHz Conversion Rate
MCLK = 8.192 MHz
10
0
10
0
–65
–40
–9
–3
–2
–1
0
–65
–40
–9
–3
–2
–1
0
Input Signal – dB
Input Signal – dB
Figure 5–12
Figure 5–13
5–5
DAC SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL
100
90
80
70
60
50
40
30
20
8 kHz Conversion Rate
MCLK = 8.192 MHz
10
0
–65
–40
–9
–3
–2
–1
0
Input Signal – dB
Figure 5–14
DAC SIGNAL-TO-(NOISE AND DISTORTION) RATIO
vs
INPUT SIGNAL
90
80
70
60
50
40
30
20
8 kHz Conversion Rate
MCLK = 8.192 MHz
10
0
–65
–40
–9
–3
–2
–1
0
Input Signal – dB
Figure 5–15
5–6
6 Register Set
Bits D12 through D8 in a secondary serial communication comprise the address of the register that is written with
data carried in D7 through D0. D13 determines a read or write cycle to the addressed register. When low, a write cycle
is selected.
The following table shows the register map.
Table 6–1. Register Map
REGISTER NO. D15 D14 D13 D12 D11 D10 D9
D8
0
REGISTER NAME
No operation
Control 1
0
1
2
3
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
Control 2
1
Control 3
0
Control 4
6.1 Control Register 1
Table 6–2. Control Register 1
D7
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
D6
–
–
1
0
–
–
–
–
–
–
–
–
–
–
–
–
D5
–
–
–
–
1
0
–
–
–
–
–
–
–
–
–
–
D4
–
–
–
–
–
–
0
1
–
–
–
–
–
–
–
–
D3
–
–
–
–
–
–
–
–
1
1
0
0
–
–
–
–
D2
–
–
–
–
–
–
–
–
1
0
1
0
–
–
–
–
D1
–
–
–
–
–
–
–
–
–
–
–
–
1
0
–
–
D0
DESCRIPTION
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
0
Software reset
Software reset not asserted
Software power down (analog and filters)
Software power down (not asserted)
Select AUXP and AUXM for ADC
Select INP and INM for ADC
Select INP and INM for monitor
Select AUXP and AUXM for monitor
Monitor amplifier gain = –18 dB (see Note 1)
Monitor amplifier gain = –8 dB (see Note 1)
Monitor amplifier gain = 0 dB (see Note 1)
Monitor amp mute
Digital loopback asserted
Digital loopback not asserted
16-bit DAC mode (hardware secondary requests)
Not 16-bit DAC mode (software secondary requests) [(15+1)– bit mode]
Default value: 0 0 0 0 0 0 0 0
NOTE 1: These gains are for a single-ended input. The gain is 6 dB lower with a differential input.
A software reset is a one-shot operation and this bit is cleared to 0 after reset. It is not necessary to write a 0 to end
the master reset operation. Writing 0s to the reserved bits is suggested.
6–1
6.2 Control Register 2
Table 6–3. Control Register 2
D7
X
–
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
DESCRIPTION
–
–
–
–
–
FLAG output value
Phone mode enable
Phone mode disable
1
–
–
–
–
–
–
0
–
–
–
–
–
–
–
X
–
–
–
–
–
Decimator FIR overflow flag (valid only during read cycle)
16-bit ADC mode
–
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
1
0
–
X
0
1
–
–
–
0
0
–
–
–
–
0
0
–
–
–
Not-16-bit ADC mode [(15+1)– bit mode]
Reserved (TLC320AD50C only)
FSD enable (TLC320AD52C only)
FSD disable (TLC320AD52C only)
Analog loopback enabled
Analog loopback disabled
Default value: 00000000
Writing 0s to the reserved bits is suggested.
6.3 Control Register 3
The following command contains the frame-sync delay (FSD) register address and loads D7 (MSB)–D0 into the FSD
register. The data byte (D5–D0) determines the number of SCLKs between FS and the delayed frame-sync signal,
FSD. The minimum data value for this portion of the register, bits D5 – D0, is decimal 18.
Table 6–4. Control Register 3
D7
–
D6
–
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
DESCRIPTION
Number of SCLKs between FS and FSD
X
X
–
–
–
–
–
–
Binary number of slave devices (3 maximum for TLC320AC50C, 1 maximum for
TLC320AC52C)
Default value: 00000000
Writing 0s to the reserved bits is suggested.
6.4 Control Register 4
Table 6–5. Control Register 4
D7
–
D6
–
D5
–
D4
–
D3
1
D2
1
D1
–
D0
DESCRIPTION
–
–
–
–
1
0
1
0
–
–
–
Analog input gain = mute
Analog input gain = 12 dB
Analog input gain = 6 dB
Analog input gain = 0 dB
Analog output gain = mute
Analog output gain = – 12 dB
Analog output gain = – 6 dB
Analog output gain = 0 dB
–
–
–
–
1
0
–
–
–
–
–
0
1
–
–
–
–
–
0
0
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
X
–
X
–
X
–
–
–
–
Sample frequency select (N): f = MCLK/(128
s
N) or MCLK/(512
N)
1
–
–
–
Bypass internal DPLL
Enable internal DPLL
0
–
–
–
–
–
–
Default value: 00000000
The value of the sample frequency divisor, N, is determined by the octal respresentation of bits D4 – D6. Hence, 001
= 1, 010 = 2, etc. By setting D4 – D6 to 000, N = 8 is selected.
6–2
7 Application Information
TMS320C2x/3x/5x/2xx/54x
TLC320AD50C
XF
FC
CLKOUT
MCLK
DX
DR
DIN
DOUT
FS
Master Mode
FSX
FSR
FSD
SCLK
CLKX
CLKR
DV
DD
M/S
TLC320AD50C
FC
MCLK
DIN
DOUT
FS
Slave Mode
FSD
SCLK
M/S
Figure 7–1. Master Device and Slave Device Connections (to DSP Interface)
When multiple AD50’s or AD52’s are attached to a single DSP serial interface in a master/slave configuration, the
control registers should be programmed in the following order during device initialization:
Control register 1
Control register 2
Control register 4
Control register 3
All AD50 or AD52 devices will be configured the same with a single global initialization being written to registers 1,
2, and 4. Once register 3 is programmed (setting the number of SCLKS between FS and FSD), each device will begin
communicating in its designated time slot.
7–1
TLC320AD50
REFP
INP
INM
0.1 µF
REFM
FILT
5 V
0.1 µF
AV (PLL)
DD
0.1 µF
AV (PLL)
SS
AV
DD
5 V
0.1 µF
AV
OUTP
OUTM
SS
3 V or 5 V
DV
DV
DD
0.1 µF
SS
DGND
AGND
Figure 7–2. Power Supply Decoupling
7–2
Appendix A
Mechanical Data
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
28
0.710
DIM
0.410
0.510
0.610
A MAX
A MIN
(10,41) (12,95) (15,49) (18,03)
0.400
0.500
0.600
0.700
(10,16) (12,70) (15,24) (17,78)
4040000/C 07/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
A–1
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
M
0,08
0,50
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
Gage Plane
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,45
1,35
0,75
0,45
Seating Plane
0,10
1,60 MAX
4040052/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
A–2
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
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Copyright 2000, Texas Instruments Incorporated
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