TLC2543CN [TI]
12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS; 12位模拟数字转换器带串行控制和11个模拟输入
| 型号： | TLC2543CN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS |
| 文件： | 总27页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
12-Bit-Resolution A/D Converter
DB, DW, J, OR N PACKAGE
(TOP VIEW)
10-µs Conversion Time Over Operating
Temperature
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
V
CC
EOC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
11 Analog Input Channels
3 Built-In Self-Test Modes
Inherent Sample-and-Hold Function
Linearity Error . . . ±1 LSB Max
On-Chip System Clock
I/O CLOCK
DATA INPUT
DATA OUT
CS
14 REF+
End-of-Conversion Output
13
12
11
REF–
AIN10
AIN9
Unipolar or Bipolar Output Operation
(Signed Binary With Respect to 1/2 the
Applied Voltage Reference)
Programmable MSB or LSB First
Programmable Power Down
Programmable Output Data Length
CMOS Technology
FK OR FN PACKAGE
(TOP VIEW)
†
Application Report Available
3
2
1
20 19
18
AIN3
AIN4
AIN5
AIN6
AIN7
I/O CLOCK
DATA INPUT
DATA OUT
CS
4
5
6
7
8
description
17
16
15
The TLC2543C and TLC2543I are 12-bit, switched-
capacitor, successive-approximation, analog-to-
digital converters. Each device has three control
inputs [chip select (CS), the input-output clock (I/O
CLOCK), and the address input (DATA INPUT)] and
is designed for communication with the serial port of
a host processor or peripheral through a serial 3-state
output. The device allows high-speed data transfers
from the host.
14 REF+
9 10 11 12 13
In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel
multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages. The
sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high
to indicate that conversion is complete. The converter incorporated in the device features differential
high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry
from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating
temperature range.
The TLC2543C is characterized for operation from T = 0°C to 70°C. The TLC2543I is characterized for
A
operation from T = –40°C to 85°C. The TLC2543M is characterized for operation from T = –55°C to 125°C.
A
A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Microcontroller Based Data Acquisition Using the TLC2543 12-bit Serial-Out ADC (SLAA012)
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
AVAILABLE OPTIONS
PACKAGE
PLASTIC CHIP
CARRIER
PLASTIC CHIP
CARRIER
SMALL OUTLINE
PLASTIC DIP
PLASTIC DIP
T
A
†
†
†
(FN)
(DB)
(DW)
(FK)
(J)
(N)
0°C to 70°C
–40°C to 85°C
–55°C to 125°C
TLC2543CDB
TLC2543CDW
TLC2543IDW
—
—
—
TLC2543CFN
TLC2543IFN
—
—
—
TLC2543CN
TLC2543IN
—
—
—
TLC2543MFK
TLC2543MJ
†
Available in tape and reel and ordered as the TLC2543CDBLE, TLC2543CDWR, TLC2543IDWR, TLC2543CFNR, or TLC2543IFNR.
functional block diagram
REF+
14
REF–
13
12-Bit
Analog-to-Digital
Converter
1
2
3
4
5
6
7
8
Sample-and-
Hold
Function
AIN0
AIN1
AIN2
AIN3
(Switched Capacitors)
AIN4
14-Channel
Analog
Multiplexer
12
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
12
Output
Data
Register
12-to-1 Data
Selector and
Driver
9
11
12
16
DATA
OUT
4
Input Address
Register
4
3
Control Logic
and I/O
Counters
Self-Test
Reference
19
EOC
17
DATA
INPUT
18
15
I/O CLOCK
CS
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
AIN0 – AIN10
1–9,
11, 12
I
Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should
be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and be capable of slewing the analog input
voltage into a capacitance of 60 pF.
CS
15
17
16
I
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT,
DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup
time.
DATA INPUT
DATA OUT
Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next.
The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK.
After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order.
O
The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS
is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state
†
and is driven to the logic level corresponding to the MSB/LSB value of the previous conversion result. The
next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB, and
the remaining bits are shifted out in order.
EOC
19
10
18
O
I
End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and
remains low until the conversion is complete and the data is ready for transfer.
GND
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage
measurements are with respect to GND.
I/O CLOCK
Input/output clock. I/O CLOCK receives the serial input and performs the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK
with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input
begins charging the capacitor array and continues to do so until the last falling edge of the I/O
CLOCK.
3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on
the falling edge of I/O CLOCK.
4. It transfers control of the conversion to the internal state controller on the falling edge of the last
I/O CLOCK.
REF+
REF–
14
I
I
Positive reference voltage The upper reference voltage value (nominally V ) is applied to REF+. The
CC
maximuminput voltage range is determined by the difference between the voltage applied to this terminal and
the voltage applied to the REF– terminal.
13
20
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF–.
Positive supply voltage
V
CC
†
MSB/LSB = Most significant bit /least significant bit
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise
†
noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
+ 0.3 V
+ 0.1 V
I
CC
CC
CC
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
O
Positive reference voltage, V
Negative reference voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
ref+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 V
ref–
Peak input current, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
I
Peak total input current, I (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA
I
Operating free-air temperature range, T : TLC2543C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLC2543I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
TLC2543M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted).
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
4.5
5
5.5
CC
Positive reference voltage, V
(see Note 2)
(see Note 2)
– V (see Note 2)
V
V
V
ref+
Negative reference voltage, V
CC
0
V
ref–
Differential reference voltage, V
2.5
0
V +0.1
CC
V
ref+
ref–
CC
Analog input voltage (see Note 2)
High-level control input voltage, V
V
CC
V
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
2
V
IH
CC
Low-level control input voltage, V
Clock frequency at I/O CLOCK
0.8
4.1
V
IL
CC
0
100
0
MHz
ns
ns
ns
µs
ns
ns
µs
µs
Setup time, address bits at DATA INPUT before I/O CLOCK↑, t
(see Figure 4)
su(A)
Hold time, address bits after I/O CLOCK↑, t
(see Figure 4)
h(A)
Hold time, CS low after last I/O CLOCK↓, t
(see Figure 5)
0
h(CS)
Setup time, CS low before clocking in first address bit, t
(see Note 3 and Figure 5)
1.425
120
120
su(CS)
Pulse duration, I/O CLOCK high, t
wH(I/O)
Pulse duration, I/O CLOCK low, t
wL(I/O)
Transition time, I/O CLOCK high to low, t
t(I/O)
(see Note 4 and Figure 6)
1
10
70
85
Transition time, DATA INPUT and CS, t
t(CS)
TLC2543C
TLC2543I
TLC2543M
0
–40
–55
Operating free-air temperature, T
°C
A
125
NOTES: 2. AnaloginputvoltagesgreaterthanthatappliedtoREF+convertasallones(111111111111),whileinputvoltageslessthanthatapplied
to REF– convert as all zeros (000000000000).
3. To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS↓ before responding to control
input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed.
4. This is the time required for the clock input signal to fall from V min to V max or to rise from V max to V min. In the vicinity of
IH
IL
IL
IH
normalroomtemperature, thedevicesfunctionwithinputclocktransitiontimeasslowas1µsforremotedataacquisitionapplications
where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range,
= V = 4.5 V to 5.5 V, f = 4.1 MHz (unless otherwise noted)
V
CC
ref+
(I/O CLOCK)
TLC2543C, TLC2543I
PARAMETER
TEST CONDITIONS
UNIT
V
†
TYP
MIN
MAX
V
V
V
V
V
V
= 4.5 V,
I
I
I
I
= –1.6 mA
= –20 µA
= 1.6 mA
= 20 µA
2.4
CC
CC
CC
CC
OH
OH
OL
OL
V
OH
High-level output voltage
Low-level output voltage
= 4.5 V to 5.5 V,
= 4.5 V,
V
–0.1
CC
0.4
0.1
V
OL
V
= 4.5 V to 5.5 V,
= V
CC
= 0,
,
CS at V
1
1
1
1
1
2.5
High-impedance off-state output
current
O
O
CC
CC
I
µA
OZ
CS at V
–2.5
2.5
I
I
I
High-level input current
Low-level input current
Operating supply current
V = V
I CC
µA
µA
IH
V = 0
I
–2.5
2.5
IL
CS at 0 V
For all digital inputs,
0 ≤ V ≤ 0.5 V or V ≥ V – 0.5 V
CC
mA
CC
I
Power-down current
4
25
1
µA
CC(PD)
I
I
Selected channel at V
CC
,
Unselected channel at 0 V
Selected channel leakage
current
µA
Selected channel at 0 V,
Unselected channel at V
–1
CC
Maximum static analog
reference current into REF+
V
ref+
= V
,
V = GND
ref–
1
2.5
µA
CC
Analog inputs
Control inputs
30
5
60
15
Input
capacitance
C
pF
i
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
electrical characteristics over recommended operating free-air temperature range,
V
= V
= 4.5 V to 5.5 V, f = 4.1 MHz (unless otherwise noted)
CC
ref+
(I/O CLOCK)
TLC2543M
PARAMETER
TEST CONDITIONS
MIN
UNIT
V
†
TYP
MAX
V
V
V
V
V
V
= 4.5 V,
I
I
I
I
= –1.6 mA
= –20 µA
= 1.6 mA
= 20 µA
2.4
–0.1
CC
CC
CC
CC
OH
OH
OL
OL
V
OH
High-level output voltage
Low-level output voltage
= 4.5 V to 5.5 V,
= 4.5 V,
V
CC
0.4
0.1
V
OL
V
= 4.5 V to 5.5 V,
= V
CC
= 0,
,
CS at V
1
1
1
1
1
2.5
High-impedance off-state output
current
O
O
CC
CC
I
µA
OZ
CS at V
–2.5
10
I
I
I
High-level input current
Low-level input current
Operating supply current
V = V
I CC
µA
µA
IH
V = 0
I
–10
10
IL
CS at 0 V
For all digital inputs,
0 ≤ V ≤ 0.5 V or V ≥ V – 0.5 V
CC
mA
CC
I
Power-down current
4
25
10
µA
CC(PD)
I
I
Selected channel at V
CC
,
Unselected channel at 0 V
Selected channel leakage
current
µA
Selected channel at 0 V,
Unselected channel at V
–10
CC
Maximum static analog
reference current into REF+
V
ref+
= V
,
V = GND
ref–
1
2.5
µA
CC
Analog inputs
Control inputs
30
5
60
15
Input
capacitance
C
pF
i
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
operating characteristics over recommended operating free-air temperature range,
V
= V
= 4.5 V to 5.5 V, f
= 4.1 MHz
CC
ref+
(I/O CLOCK)
†
PARAMETER
Linearity error (see Note 5)
Differential linearity error
TEST CONDITIONS
See Figure 2
MIN TYP
MAX
±1
UNIT
LSB
LSB
E
L
E
D
See Figure 2
±1
See Note 2 and
Figure 2
E
O
Offset error (see Note 6)
±1.5
LSB
See Note 2 and
Figure 2
E
E
Gain error (see Note 6)
±1
LSB
LSB
G
Total unadjusted error (see Note 7)
±1.75
T
DATA INPUT = 1011
DATA INPUT = 1100
DATA INPUT = 1101
See Figures 9–14
2048
0
Self-test output code (see Table 3 and Note 8)
Conversion time
4095
8
t
t
10
µs
µs
conv
10 + total
I/O CLOCK
periods +
See Figures 9–14
and Note 9
Total cycle time (access, sample, and conversion)
c
t
d(I/O-EOC)
I/O
CLOCK
periods
See Figures 9–14
and Note 9
t
Channel acquisition time (sample)
4
12
acq
t
t
t
t
t
t
t
t
t
t
Valid time, DATA OUT remains valid after I/O CLOCK↓
Delay time, I/O CLOCK↓ to DATA OUT valid
Delay time, last I/O CLOCK↓ to EOC↓
Delay time, EOC↑ to DATA OUT (MSB/LSB)
Enable time, CS↓ to DATA OUT (MSB/LSB driven)
Disable time, CS↑ to DATA OUT (high impedance)
Rise time, EOC
See Figure 6
See Figure 6
See Figure 7
See Figure 8
See Figure 3
See Figure 3
See Figure 8
See Figure 7
See Figure 6
See Figure 6
10
ns
ns
µs
ns
µs
ns
ns
ns
ns
ns
v
150
2.2
100
1.3
150
50
d(I/O-DATA)
d(I/O-EOC)
1.5
d(EOC-DATA)
, t
PZH PZL
0.7
70
15
15
15
15
, t
PHZ PLZ
r(EOC)
f(EOC)
r(bus)
f(bus)
Fall time, EOC
50
Rise time, data bus
50
Fall time, data bus
50
Delay time, last I/O CLOCK↓ to CS↓ to abort conversion
(see Note 10)
t
5
µs
d(I/O-CS)
†
All typical values are at T = 25°C.
A
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that
applied to REF– convert as all zeros (000000000000).
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified
gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the
nominal midstep value at the offset point.
7. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic.
9. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 7).
10. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ≤ 5 µs
of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 µs and 10 µs, the result is uncertain as to whether
the conversion is aborted or the conversion results are valid.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
15 V
50 Ω
C1
10 µF
C2
0.1 µF
C3
470 pF
TLC2543
_
U1
+
10 Ω
AIN0–AIN10
V
I
C1
10 µF
C3
470 pF
C2
0.1 µF
50 Ω
–15 V
LOCATION
DESCRIPTION
PART NUMBER
U1
C1
C2
C3
OP27
—
—
10-µF 35-V tantalum capacitor
0.1-µF ceramic NPO SMD capacitor
AVX 12105C104KA105 or equivalent
470-pF porcelain Hi-Q SMD capacitor
Johanson 201S420471JG4L or equivalent
Figure 1. Analog Input Buffer to Analog Inputs AIN0–AIN10
V
CC
V
CC
Test Point
Test Point
R
= 2.18 kΩ
R
= 2.18 kΩ
L
L
EOC
DATA OUT
12 kΩ
12 kΩ
C
= 50 pF
C = 100 pF
L
L
Figure 2. Load Circuits
Data
Valid
2 V
2 V
0.8 V
DATA INPUT
CS
t
0.8 V
, t
PZH PZL
t
h(A)
t
, t
t
PHZ PLZ
su(A)
2.4 V
0.4 V
90%
10%
I/O CLOCK
DATA
OUT
0.8 V
Figure 4. DATA INPUT and I/O CLOCK
Voltage Waveforms
Figure 3. DATA OUT to Hi-Z Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
2 V
CS
0.8 V
t
su(CS)
t
h(CS)
I/O CLOCK
Last
Clock
0.8 V
0.8 V
NOTE A: To ensure full conversion accuracy, it is recommended that no input signal change
occurs while a conversion is ongoing.
Figure 5. CS and I/O CLOCK Voltage Waveforms
t
t(I/O)
t
t(I/O)
2 V
2 V
0.8 V
I/O CLOCK
0.8 V
0.8 V
I/O CLOCK Period
t
d(I/O-DATA)
t
v
2.4 V
0.4 V
2.4 V
0.4 V
DATA OUT
t
, t
r(bus) f(bus)
Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms
I/O CLOCK
Last
0.8 V
Clock
t
d(I/O-EOC)
2.4 V
EOC
0.4 V
t
f(EOC)
Figure 7. I/O CLOCK and EOC Voltage Waveforms
t
r(EOC)
EOC
2.4 V
0.4 V
t
d(EOC-DATA)
2.4 V
0.4 V
DATA OUT
Valid MSB
Figure 8. EOC and DATA OUT Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
11
12
1
Access Cycle B
Sample Cycle B
Hi-Z State
DATA
OUT
A11
A10
A9
A8
A7
A6
A5
A4
A1
A0
B11
Previous Conversion Data
MSB
LSB
DATA
INPUT
C7
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC
t
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
conv
A/D Conversion
Interval
Initialize
Initialize
NOTE A: TominimizeerrorscausedbynoiseatCS, theinternalcircuitrywaitsforasetuptimeafterCS↓ beforerespondingtocontrolinputsignals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 9. Timing for 12-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
11
12
1
Access Cycle B
Sample Cycle B
DATA
OUT
A11
A10
A9
A8
A7
A6
A5
A4
A1
A0
B11
Low Level
Previous Conversion Data
MSB
LSB
DATA
INPUT
B7
B6
B5
B4
C7
B3
B2
B1
B0
MSB
LSB
EOC
t
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
conv
A/D Conversion
Interval
Initialize
Initialize
NOTE A: TominimizeerrorscausedbynoiseatCS, theinternalcircuitrywaitsforasetuptimeafterCS↓ beforerespondingtocontrolinputsignals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
1
2
3
4
5
6
7
8
1
I/O CLOCK
DATA OUT
Access Cycle B
Sample Cycle B
Hi-Z
A7
A6
A5
A4
A3
A2
A1
A0
B7
Previous Conversion Data
MSB
LSB
B0
DATA INPUT
B3
B2
B1
B7
B6
B5
B4
C7
MSB
LSB
EOC
t
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
conv
A/D Conversion
Interval
Initialize
Initialize
NOTE A: TominimizeerrorscausedbynoiseatCS, theinternalcircuitrywaitsforasetuptimeafterCS↓ beforerespondingtocontrolinputsignals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 11. Timing for 8-Clock Transfer Using CS With MSB First
CS
(see Note A)
1
2
3
4
5
6
7
8
1
I/O CLOCK
DATA OUT
Access Cycle B
Sample Cycle B
A7
A6
A5
A4
A3
A2
A1
A0
B7
Low Level
Previous Conversion Data
MSB
LSB
B0
DATA INPUT
EOC
B7
B6
B5
B4
C7
B3
B2
B1
MSB
LSB
t
Shift in New Multiplexer Address,
conv
Simultaneously Shift Out Previous
Conversion Value
A/D Conversion
Interval
Initialize
Initialize
NOTE A: TominimizeerrorscausedbynoiseatCS, theinternalcircuitrywaitsforasetuptimeafterCS↓ beforerespondingtocontrolinputsignals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
15
16
1
Access Cycle B
Sample Cycle B
Hi-Z State
DATA
OUT
A15
A14
A13
A12
A11
A10
A9
A8
B0
A1
A0
B15
Previous Conversion Data
MSB
LSB
DATA
INPUT
B7
B6
B5
B4
B3
B2
B1
C7
MSB
LSB
EOC
t
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
conv
A/D Conversion
Interval
Initialize
Initialize
NOTE A: TominimizeerrorscausedbynoiseatCS, theinternalcircuitrywaitsforasetuptimeafterCS↓ beforerespondingtocontrolinputsignals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 13. Timing for 16-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1
2
3
4
5
6
7
8
15
16
1
Access Cycle B
Sample Cycle B
DATA
OUT
Low Level
A15
A14
A13
A12
A11
A10
A9
A8
A1
A0
B15
Previous Conversion Data
MSB
LSB
DATA
INPUT
B3
B2
B1
B0
B7
B6
B5
B4
C7
MSB
LSB
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
t
conv
A/D Conversion
Interval
Initialize
NOTE A: TominimizeerrorscausedbynoiseatCS, theinternalcircuitrywaitsforasetuptimeafterCS↓ beforerespondingtocontrolinputsignals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 14. Timing for 16-Clock Transfer Not Using CS With MSB First
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PRINCIPLES OF OPERATION
Initially, with chip select (CS) high, I/O CLOCK and DATA INPUT are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATAINPUT
and removes DATA OUT from the high-impedance state.
The input data is an 8-bit data stream consisting of a 4-bit analog channel address (D7–D4), a 2-bit data length
select (D3–D2), an output MSB or LSB first bit (D1), and a unipolar or bipolar output select bit (D0) that are
applied to DATA INPUT. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the
input data register.
During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output data
register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles long depending on
the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge
of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The last
falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.
converter operation
The operation of the converter is organized as a succession of two distinct cycles: 1) the I/O cycle and 2) the
actual conversion cycle.
I/O cycle
The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods, depending
on the selected output data length.
During the I/O cycle, the following two operations take place simultaneously.
An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data is
shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after the first
eight clocks during 12- or 16-clock I/O transfers.
The data output, with a length of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the
first output data bit occurs on the rising edge of EOC. When CS is negated between conversions, the first output
data bit occurs on the falling edge of CS. This data is the result of the previous conversion period, and after the
first output data bit, each succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK.
conversion cycle
The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to
I/O CLOCK. During the conversion period, the device performs a successive-approximation conversion on the
analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when
conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O
cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PRINCIPLES OF OPERATION
power up and initialization
After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data
register is set to all zeroes. The contents of the output data register are random, and the first conversion result
should be ignored. To initialize during operation, CS is taken high and is then returned low to begin the next I/O
cycle. The first conversion after the device has returned from the power-down state may not read accurately
due to internal device settling.
Table 1. Operational Terminology
Current (N) I/O cycle
The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion from DATA OUT
Current (N) conversion cycle
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the
last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the output
register when conversion is complete.
Current (N) conversion result
The current conversion result is serially shifted out on the next I/O cycle.
Previous (N–1) conversion cycle The conversion cycle just prior to the current I/O cycle
Next (N+1) I/O cycle The I/O period that follows the current conversion cycle
Example: Inthe12-bitmode, theresultofthecurrentconversioncycleisa12-bitserial-datastreamclockedoutduring
the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even
when this corrupts the output data from the previous conversion. The current conversion is begun
immediately after the twelfth falling edge of the current I/O cycle.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PRINCIPLES OF OPERATION
data input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the data word with the MSB first.
Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data input-register
format).
Table 2. Input-Register Format
INPUT DATA BYTE
ADDRESS BITS
L1
D3
L0
D2
LSBF
D1
BIP
FUNCTION SELECT
D7
D6
D5
D4
D0
(MSB)
(LSB)
Select input channel
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Select test voltage
(V
ref+
– V )/2
ref–
1
1
1
0
1
1
1
0
0
1
0
1
V
ref–
V
ref+
Software power down
1
1
1
0
Output data length
8 bits
0
X
1
1
0
1
†
12 bits
16 bits
Output data format
MSB first
0
1
LSB first (LSBF)
Unipolar (binary)
0
1
Bipolar (BIP) 2s complement
X represents a do not care condition.
†
data input address bits
The four MSBs (D7 – D4) of the data register address one of the 11 input channels, a reference-test voltage,
or the power-down mode. The address bits affect the current conversion, which is the conversion that
immediately follows the current I/O cycle. The reference voltage is nominally equal to V
– V
.
ref+
ref–
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PRINCIPLES OF OPERATION
data output length
The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is
valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the
current I/O cycle, allows device startup without losing I/O synchronization. A data length of 8, 12, or 16 bits can
be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversionisoutputasa12-bitserialdatastreamduringthenextI/Ocycle. ThecurrentI/Ocyclemustbeexactly
12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion
result are truncated and discarded. The current conversion is started immediately after the eighth falling edge
of the current I/O cycle.
Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict
with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when
the data format is selected to be least significant bit first, since at the time the data length change becomes
effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out.
Inactualoperation, whendifferentdatalengthsarerequiredwithinanapplicationandthedatalengthischanged
between two conversions, no more than one conversion result can be corrupted and only when it is shifted out
in LSB-first format.
sampling period
During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after
the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge
of the I/O CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK
falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has
begun. After EOC goes low, the analog input can be changed without affecting the conversion result. Since the
delay from the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be
digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty.
After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC
goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the
influence of external digital noise.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PRINCIPLES OF OPERATION
data register, LSB first
D1 in the input data register (LSB first) controls the direction of the output binary data transfer. When D1 is reset
to 0, the conversion result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of
MSB first or LSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one
data direction to another, the current I/O cycle is never disrupted.
data register, bipolar format
D0 (BIP) in the input data register controls the binary data format used to represent the conversion result. When
D0 is cleared to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the
conversion result of an input voltage equal to V
is a code of all zeros (000 . . . 0), the conversion result of
ref–
an input voltage equal to V
is a code of all ones (111 . . . 1), and the conversion result of (V
+ V
)/2
ref+
ref +
ref–
is a code of a one followed by zeros (100 . . . 0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to V is a code of a one followed by zeros (100 . . . 0), conversion of an input voltage
ref–
equal to V
is a code of a zero followed by all ones (011 . . . 1), and the conversion of (V
+ V
)/2 is a
ref+
ref+
ref–
code of all zeros (000 . . . 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the
unipolar format in that the MSBs are always each other’s complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
EOC output
TheEOCsignalindicatesthebeginningandtheendofconversion. Intheresetstate, EOCisalwayshigh. During
the sampling period (beginning after the fourth falling edge of the I/O CLOCK sequence), EOC remains high
until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs
after the eighth, twelfth, or sixteenth I/O CLOCK falling edge, depending on the data-length selection in the input
data register. After the EOC signal goes low, the analog input signal can be changed without affecting the
conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the
falling edge of CS.
data format and pad bits
D3 and D2 of the input data register determine the number of significant bits in the digital output that represent
the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines
the arithmetic conversion. The numerical data is always justified toward the MSB in any output format.
The internal conversion result is always 12 bits long. When an 8-bit data transfer is selected, the four LSBs of
the internal result are discarded to provide a faster one-byte transfer. When a 12-bit transfer is used, all bits are
transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion
result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are
zeros.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PRINCIPLES OF OPERATION
data format and pad bits (continued)
When CS is held low continuously, the first data bit of the newly completed conversion occurs on DATA OUT
on the rising edge of EOC. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes
low and the serial output is forced to a setting of 0 until EOC goes high again.
When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS.
On each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next
bit in the serial conversion result until the required number of bits has been output.
chip-select input (CS)
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing
its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK
is inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next I/O cycle.
power-down features
When a binary address of 1110 is clocked into the input data register during the first four I/O CLOCK cycles,
the power-down mode is selected. Power down is activated on the falling edge of the fourth I/O CLOCK pulse.
During power down, all internal circuitry is put in a low-current standby mode. No conversions are performed,
and the internal output buffer keeps the previous conversion cycle data results provided that all digital inputs
are held above V
– 0.5 V or below 0.5 V. The I/O logic remains active so the current I/O cycle must be
CC
completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle,
the converter normally begins in the power-down mode. The device remains in the power-down mode until a
valid input address (other than 1110) is clocked in. Upon completion of that I/O cycle, a normal conversion is
performed with the results being shifted out during the next I/O cycle.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PRINCIPLES OF OPERATION
analog input, test, and power-down mode
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Tables 2, 3, and 4. The input multiplexer is a break-before-make type
to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on
the falling edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held
on the falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
Table 3. Analog-Channel-Select Address
VALUE SHIFTED INTO
ANALOG INPUT
DATA INPUT
SELECTED
BINARY
0000
0001
0010
0011
0100
0101
0110
0111
HEX
0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
1
2
3
4
5
6
7
1000
1001
1010
8
9
A
Table 4. Test-Mode-Select Address
INTERNAL
SELF-TEST
VOLTAGE
VALUE SHIFTED INTO
UNIPOLAR OUTPUT
RESULT (HEX)
DATA INPUT
‡
†
BINARY HEX
SELECTED
V
ref+
– V
2
ref–
1011
B
800
V
1100
1101
C
D
000
FFF
ref–
V
ref+
†
‡
V
is the voltage applied to REF+, and V
is the voltage applied to REF–.
ref+
ref–
The output results shown are the ideal values and may vary with the reference stability
and with internal offsets.
Table 5. Power-Down-Select Address
VALUE SHIFTED INTO
DATA INPUT
BINARY HEX
1110
INPUT COMMAND
RESULT
Power down
E
I
≤ 25 µA
CC
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
PRINCIPLES OF OPERATION
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the S switch and all S switches simultaneously.
C
T
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all S and S switches are opened and the threshold detector
T
C
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)
voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF–. When the voltage at the
summing node is greater than the trip point of the threshold detector (approximately 1/2 V ), a bit 0 is placed
CC
intheoutputregisterandthe4096-weightcapacitorisswitchedtoREF–. Whenthevoltageatthesummingnode
is less than the trip point of the threshold detector, a bit 1 is placed in the register and this 4096-weight capacitor
remains connected to REF+ through the remainder of the successive-approximation process. The process is
repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down the line until all bits are
determined. With each step of the successive-approximation process, the initial charge is redistributed among
the capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.
reference voltage inputs
The two reference inputs used with the device are the voltages applied to the REF+ and REF– terminals. These
voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero-scale
reading respectively. These voltages and the analog input should not exceed the positive supply or be lower
than ground consistent with the specified absolute maximum ratings. The digital output is at full scale when the
input signal is equal to or higher than REF+ terminal voltage and at zero when the input signal is equal to or lower
than REF– terminal voltage.
S
C
Threshold
Detector
To Output
Latches
4096
Node 4096
2048
1024
16
8
4
2
1
1
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF–
REF–
REF–
REF–
REF–
REF–
REF–
REF–
REF–
T
S
S
S
S
S
S
S
S
S
T
T
T
T
T
T
T
T
V
I
Figure 15. Simplified Model of the Successive-Approximation System
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
APPLICATION INFORMATION
4095
4094
4093
111111111111
111111111110
111111111101
V
FS
See Notes A and B
V
FSnom
V
FT
= V
– 1/2 LSB
FS
2049
2048
100000000001
100000000000
V
ZT
= V
+ 1/2 LSB
ZS
2047
011111111111
V
ZS
2
1
0
000000000010
000000000001
000000000000
0
0.0012 0.0024
2.4564 2.4576 2.4588
V – Analog Input Voltage – V
4.9128
4.9140 4.9152
I
NOTES: A. This curve is based on the assumption that V
ref+
and V have been adjusted so that the voltage at the transition from digital 0
ref–
to 1 (V ) is 0.0006 V and the transition to full scale (V ) is 4.9134 V. 1 LSB = 1.2 mV.
ZT FT
B. The full-scale value (V ) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (V ) is
FS
ZS
the step whose nominal midstep value equals zero.
Figure 16. Ideal Conversion Characteristics
TLC2543
15
1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
CS
18
17
2
I/O CLOCK
3
DATA INPUT
Control
Circuit
4
Processor
5
16
19
DATA OUT
EOC
6
Analog
Inputs
7
8
9
14
13
5-V DC Regulated
REF+
REF–
11
12
GND
10
To Source
Ground
Figure 17. Serial Interface
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
APPLICATION INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 18, the time required to charge the analog input capacitance from 0 V to
V within 1/2 LSB can be derived as follows:
S
The capacitance charging voltage is given by
–t R C
(1)
(2)
c
t
i
V
V
1–e
C
S
where
R = R + r
t
s
i
The final voltage to 1/2 LSB is given by
V (1/2 LSB) = V – (V /8192)
C
S
S
Equating equation 1 to equation 2 and solving for time t gives
c
–t R C
c
t
i
V
V
8192
V
1–e
(3)
(4)
S
S
S
and
t (1/2 LSB) = R × C × ln(8192)
c
t
i
Therefore, with the values given, the time for the analog input signal to settle is
t (1/2 LSB) = (R + 1 kΩ) × 60 pF × ln(8192)
(5)
c
s
This time must be less than the converter sample time shown in the timing diagrams.
†
Driving Source
TLC2543
R
r
i
s
V
I
V
S
V
C
1 kΩ Max
C
i
60 pF Max
V
V
= Input Voltage at AIN
= External Driving Source Voltage
I
S
s
R = Source Resistance
r
= Input Resistance
i
C = Input Capacitance
i
C
V
= Capacitance Charging Voltage
†
Driving source requirements:
•
Noise and distortion for the source must be equivalent to the
resolution of the converter.
•
R must be real at the input frequency.
s
Figure 18. Equivalent Input Circuit Including the Driving Source
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
MECHANICAL INFORMATION
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–8°
1,03
0,63
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
DIM
3,30
2,70
6,50
5,90
6,50
5,90
7,50
6,90
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
9,90
12,30
4040065 /C 10/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
MECHANICAL INFORMATION
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
PINS **
0.050 (1,27)
16
20
24
28
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
0.410
0.510
0.610
0.710
A MAX
(10,41) (12,95) (15,49) (18,03)
16
9
0.400
0.500
0.600
0.700
A MIN
(10,16) (12,70) (15,24) (17,78)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
4040000/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
MECHANICAL INFORMATION
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
14 PIN SHOWN
PINS **
14
16
18
20
DIM
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
A MAX
B
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
A MIN
B MAX
B MIN
C MAX
C MIN
14
8
0.785
(19,94)
0.785
(19,94)
0.910
(23,10)
0.975
(24,77)
C
0.755
(19,18)
0.755
(19,18)
0.930
(23,62)
0.280
(7,11)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
1
7
0.065 (1,65)
0.045 (1,14)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.100 (2,54)
0.070 (1,78)
0.020 (0,51) MIN
A
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040083/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, and GDIP1-T20
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2543C, TLC2543I, TLC2543M
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079D – DECEMBER 1993 – REVISED MAY 1997
MECHANICAL INFORMATION
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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